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usb: dwc3: core: simplify suspend/resume operations
[linux/fpc-iii.git] / drivers / usb / dwc3 / core.c
blob80e9affd3d779c896f7d882531ef4536bbb3046a
1 /**
2 * core.c - DesignWare USB3 DRD Controller Core file
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include <linux/version.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/io.h>
32 #include <linux/list.h>
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/of.h>
36 #include <linux/acpi.h>
37 #include <linux/pinctrl/consumer.h>
38
39 #include <linux/usb/ch9.h>
40 #include <linux/usb/gadget.h>
41 #include <linux/usb/of.h>
42 #include <linux/usb/otg.h>
43
44 #include "platform_data.h"
45 #include "core.h"
46 #include "gadget.h"
47 #include "io.h"
48
49 #include "debug.h"
50
51 /* -------------------------------------------------------------------------- */
52
53 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
54 {
55 u32 reg;
56
57 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
58 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
59 reg |= DWC3_GCTL_PRTCAPDIR(mode);
60 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
61 }
62
63 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
64 {
65 struct dwc3 *dwc = dep->dwc;
66 u32 reg;
67
68 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
69 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
70 DWC3_GDBGFIFOSPACE_TYPE(type));
71
72 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
73
74 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
75 }
76
77 /**
78 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
79 * @dwc: pointer to our context structure
80 */
81 static int dwc3_core_soft_reset(struct dwc3 *dwc)
82 {
83 u32 reg;
84 int retries = 1000;
85 int ret;
86
87 usb_phy_init(dwc->usb2_phy);
88 usb_phy_init(dwc->usb3_phy);
89 ret = phy_init(dwc->usb2_generic_phy);
90 if (ret < 0)
91 return ret;
92
93 ret = phy_init(dwc->usb3_generic_phy);
94 if (ret < 0) {
95 phy_exit(dwc->usb2_generic_phy);
96 return ret;
97 }
98
99 /*
100 * We're resetting only the device side because, if we're in host mode,
101 * XHCI driver will reset the host block. If dwc3 was configured for
102 * host-only mode, then we can return early.
103 */
104 if (dwc->dr_mode == USB_DR_MODE_HOST)
105 return 0;
106
107 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
108 reg |= DWC3_DCTL_CSFTRST;
109 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
110
111 do {
112 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
113 if (!(reg & DWC3_DCTL_CSFTRST))
114 return 0;
115
116 udelay(1);
117 } while (--retries);
118
119 return -ETIMEDOUT;
120 }
121
122 /**
123 * dwc3_soft_reset - Issue soft reset
124 * @dwc: Pointer to our controller context structure
125 */
126 static int dwc3_soft_reset(struct dwc3 *dwc)
127 {
128 unsigned long timeout;
129 u32 reg;
130
131 timeout = jiffies + msecs_to_jiffies(500);
132 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
133 do {
134 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
135 if (!(reg & DWC3_DCTL_CSFTRST))
136 break;
137
138 if (time_after(jiffies, timeout)) {
139 dev_err(dwc->dev, "Reset Timed Out\n");
140 return -ETIMEDOUT;
141 }
142
143 cpu_relax();
144 } while (true);
145
146 return 0;
147 }
148
149 /*
150 * dwc3_frame_length_adjustment - Adjusts frame length if required
151 * @dwc3: Pointer to our controller context structure
152 */
153 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
154 {
155 u32 reg;
156 u32 dft;
157
158 if (dwc->revision < DWC3_REVISION_250A)
159 return;
160
161 if (dwc->fladj == 0)
162 return;
163
164 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
165 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
166 if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
167 "request value same as default, ignoring\n")) {
168 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
169 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
170 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
171 }
172 }
173
174 /**
175 * dwc3_free_one_event_buffer - Frees one event buffer
176 * @dwc: Pointer to our controller context structure
177 * @evt: Pointer to event buffer to be freed
178 */
179 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
180 struct dwc3_event_buffer *evt)
181 {
182 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
183 }
184
185 /**
186 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
187 * @dwc: Pointer to our controller context structure
188 * @length: size of the event buffer
189 *
190 * Returns a pointer to the allocated event buffer structure on success
191 * otherwise ERR_PTR(errno).
192 */
193 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
194 unsigned length)
195 {
196 struct dwc3_event_buffer *evt;
197
198 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
199 if (!evt)
200 return ERR_PTR(-ENOMEM);
201
202 evt->dwc = dwc;
203 evt->length = length;
204 evt->buf = dma_alloc_coherent(dwc->dev, length,
205 &evt->dma, GFP_KERNEL);
206 if (!evt->buf)
207 return ERR_PTR(-ENOMEM);
208
209 return evt;
210 }
211
212 /**
213 * dwc3_free_event_buffers - frees all allocated event buffers
214 * @dwc: Pointer to our controller context structure
215 */
216 static void dwc3_free_event_buffers(struct dwc3 *dwc)
217 {
218 struct dwc3_event_buffer *evt;
219
220 evt = dwc->ev_buf;
221 if (evt)
222 dwc3_free_one_event_buffer(dwc, evt);
223 }
224
225 /**
226 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
227 * @dwc: pointer to our controller context structure
228 * @length: size of event buffer
229 *
230 * Returns 0 on success otherwise negative errno. In the error case, dwc
231 * may contain some buffers allocated but not all which were requested.
232 */
233 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
234 {
235 struct dwc3_event_buffer *evt;
236
237 evt = dwc3_alloc_one_event_buffer(dwc, length);
238 if (IS_ERR(evt)) {
239 dev_err(dwc->dev, "can't allocate event buffer\n");
240 return PTR_ERR(evt);
241 }
242 dwc->ev_buf = evt;
243
244 return 0;
245 }
246
247 /**
248 * dwc3_event_buffers_setup - setup our allocated event buffers
249 * @dwc: pointer to our controller context structure
250 *
251 * Returns 0 on success otherwise negative errno.
252 */
253 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
254 {
255 struct dwc3_event_buffer *evt;
256
257 evt = dwc->ev_buf;
258 dwc3_trace(trace_dwc3_core,
259 "Event buf %p dma %08llx length %d\n",
260 evt->buf, (unsigned long long) evt->dma,
261 evt->length);
262
263 evt->lpos = 0;
264
265 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
266 lower_32_bits(evt->dma));
267 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
268 upper_32_bits(evt->dma));
269 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
270 DWC3_GEVNTSIZ_SIZE(evt->length));
271 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
272
273 return 0;
274 }
275
276 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
277 {
278 struct dwc3_event_buffer *evt;
279
280 evt = dwc->ev_buf;
281
282 evt->lpos = 0;
283
284 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
285 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
286 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
287 | DWC3_GEVNTSIZ_SIZE(0));
288 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
289 }
290
291 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
292 {
293 if (!dwc->has_hibernation)
294 return 0;
295
296 if (!dwc->nr_scratch)
297 return 0;
298
299 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
300 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
301 if (!dwc->scratchbuf)
302 return -ENOMEM;
303
304 return 0;
305 }
306
307 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
308 {
309 dma_addr_t scratch_addr;
310 u32 param;
311 int ret;
312
313 if (!dwc->has_hibernation)
314 return 0;
315
316 if (!dwc->nr_scratch)
317 return 0;
318
319 /* should never fall here */
320 if (!WARN_ON(dwc->scratchbuf))
321 return 0;
322
323 scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
324 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
325 DMA_BIDIRECTIONAL);
326 if (dma_mapping_error(dwc->dev, scratch_addr)) {
327 dev_err(dwc->dev, "failed to map scratch buffer\n");
328 ret = -EFAULT;
329 goto err0;
330 }
331
332 dwc->scratch_addr = scratch_addr;
333
334 param = lower_32_bits(scratch_addr);
335
336 ret = dwc3_send_gadget_generic_command(dwc,
337 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
338 if (ret < 0)
339 goto err1;
340
341 param = upper_32_bits(scratch_addr);
342
343 ret = dwc3_send_gadget_generic_command(dwc,
344 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
345 if (ret < 0)
346 goto err1;
347
348 return 0;
349
350 err1:
351 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
352 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
353
354 err0:
355 return ret;
356 }
357
358 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
359 {
360 if (!dwc->has_hibernation)
361 return;
362
363 if (!dwc->nr_scratch)
364 return;
365
366 /* should never fall here */
367 if (!WARN_ON(dwc->scratchbuf))
368 return;
369
370 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
371 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
372 kfree(dwc->scratchbuf);
373 }
374
375 static void dwc3_core_num_eps(struct dwc3 *dwc)
376 {
377 struct dwc3_hwparams *parms = &dwc->hwparams;
378
379 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
380 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
381
382 dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
383 dwc->num_in_eps, dwc->num_out_eps);
384 }
385
386 static void dwc3_cache_hwparams(struct dwc3 *dwc)
387 {
388 struct dwc3_hwparams *parms = &dwc->hwparams;
389
390 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
391 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
392 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
393 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
394 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
395 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
396 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
397 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
398 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
399 }
400
401 /**
402 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
403 * @dwc: Pointer to our controller context structure
404 *
405 * Returns 0 on success. The USB PHY interfaces are configured but not
406 * initialized. The PHY interfaces and the PHYs get initialized together with
407 * the core in dwc3_core_init.
408 */
409 static int dwc3_phy_setup(struct dwc3 *dwc)
410 {
411 u32 reg;
412 int ret;
413
414 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
415
416 /*
417 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
418 * to '0' during coreConsultant configuration. So default value
419 * will be '0' when the core is reset. Application needs to set it
420 * to '1' after the core initialization is completed.
421 */
422 if (dwc->revision > DWC3_REVISION_194A)
423 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
424
425 if (dwc->u2ss_inp3_quirk)
426 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
427
428 if (dwc->dis_rxdet_inp3_quirk)
429 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
430
431 if (dwc->req_p1p2p3_quirk)
432 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
433
434 if (dwc->del_p1p2p3_quirk)
435 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
436
437 if (dwc->del_phy_power_chg_quirk)
438 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
439
440 if (dwc->lfps_filter_quirk)
441 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
442
443 if (dwc->rx_detect_poll_quirk)
444 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
445
446 if (dwc->tx_de_emphasis_quirk)
447 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
448
449 if (dwc->dis_u3_susphy_quirk)
450 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
451
452 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
453
454 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
455
456 /* Select the HS PHY interface */
457 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
458 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
459 if (dwc->hsphy_interface &&
460 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
461 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
462 break;
463 } else if (dwc->hsphy_interface &&
464 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
465 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
466 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
467 } else {
468 /* Relying on default value. */
469 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
470 break;
471 }
472 /* FALLTHROUGH */
473 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
474 /* Making sure the interface and PHY are operational */
475 ret = dwc3_soft_reset(dwc);
476 if (ret)
477 return ret;
478
479 udelay(1);
480
481 ret = dwc3_ulpi_init(dwc);
482 if (ret)
483 return ret;
484 /* FALLTHROUGH */
485 default:
486 break;
487 }
488
489 /*
490 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
491 * '0' during coreConsultant configuration. So default value will
492 * be '0' when the core is reset. Application needs to set it to
493 * '1' after the core initialization is completed.
494 */
495 if (dwc->revision > DWC3_REVISION_194A)
496 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
497
498 if (dwc->dis_u2_susphy_quirk)
499 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
500
501 if (dwc->dis_enblslpm_quirk)
502 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
503
504 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
505
506 return 0;
507 }
508
509 static void dwc3_core_exit(struct dwc3 *dwc)
510 {
511 dwc3_event_buffers_cleanup(dwc);
512
513 usb_phy_shutdown(dwc->usb2_phy);
514 usb_phy_shutdown(dwc->usb3_phy);
515 phy_exit(dwc->usb2_generic_phy);
516 phy_exit(dwc->usb3_generic_phy);
517
518 usb_phy_set_suspend(dwc->usb2_phy, 1);
519 usb_phy_set_suspend(dwc->usb3_phy, 1);
520 phy_power_off(dwc->usb2_generic_phy);
521 phy_power_off(dwc->usb3_generic_phy);
522 }
523
524 /**
525 * dwc3_core_init - Low-level initialization of DWC3 Core
526 * @dwc: Pointer to our controller context structure
527 *
528 * Returns 0 on success otherwise negative errno.
529 */
530 static int dwc3_core_init(struct dwc3 *dwc)
531 {
532 u32 hwparams4 = dwc->hwparams.hwparams4;
533 u32 reg;
534 int ret;
535
536 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
537 /* This should read as U3 followed by revision number */
538 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
539 /* Detected DWC_usb3 IP */
540 dwc->revision = reg;
541 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
542 /* Detected DWC_usb31 IP */
543 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
544 dwc->revision |= DWC3_REVISION_IS_DWC31;
545 } else {
546 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
547 ret = -ENODEV;
548 goto err0;
549 }
550
551 /*
552 * Write Linux Version Code to our GUID register so it's easy to figure
553 * out which kernel version a bug was found.
554 */
555 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
556
557 /* Handle USB2.0-only core configuration */
558 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
559 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
560 if (dwc->maximum_speed == USB_SPEED_SUPER)
561 dwc->maximum_speed = USB_SPEED_HIGH;
562 }
563
564 /* issue device SoftReset too */
565 ret = dwc3_soft_reset(dwc);
566 if (ret)
567 goto err0;
568
569 ret = dwc3_core_soft_reset(dwc);
570 if (ret)
571 goto err0;
572
573 ret = dwc3_phy_setup(dwc);
574 if (ret)
575 goto err0;
576
577 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
578 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
579
580 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
581 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
582 /**
583 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
584 * issue which would cause xHCI compliance tests to fail.
585 *
586 * Because of that we cannot enable clock gating on such
587 * configurations.
588 *
589 * Refers to:
590 *
591 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
592 * SOF/ITP Mode Used
593 */
594 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
595 dwc->dr_mode == USB_DR_MODE_OTG) &&
596 (dwc->revision >= DWC3_REVISION_210A &&
597 dwc->revision <= DWC3_REVISION_250A))
598 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
599 else
600 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
601 break;
602 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
603 /* enable hibernation here */
604 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
605
606 /*
607 * REVISIT Enabling this bit so that host-mode hibernation
608 * will work. Device-mode hibernation is not yet implemented.
609 */
610 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
611 break;
612 default:
613 dwc3_trace(trace_dwc3_core, "No power optimization available\n");
614 }
615
616 /* check if current dwc3 is on simulation board */
617 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
618 dwc3_trace(trace_dwc3_core,
619 "running on FPGA platform\n");
620 dwc->is_fpga = true;
621 }
622
623 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
624 "disable_scramble cannot be used on non-FPGA builds\n");
625
626 if (dwc->disable_scramble_quirk && dwc->is_fpga)
627 reg |= DWC3_GCTL_DISSCRAMBLE;
628 else
629 reg &= ~DWC3_GCTL_DISSCRAMBLE;
630
631 if (dwc->u2exit_lfps_quirk)
632 reg |= DWC3_GCTL_U2EXIT_LFPS;
633
634 /*
635 * WORKAROUND: DWC3 revisions <1.90a have a bug
636 * where the device can fail to connect at SuperSpeed
637 * and falls back to high-speed mode which causes
638 * the device to enter a Connect/Disconnect loop
639 */
640 if (dwc->revision < DWC3_REVISION_190A)
641 reg |= DWC3_GCTL_U2RSTECN;
642
643 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
644
645 dwc3_core_num_eps(dwc);
646
647 ret = dwc3_setup_scratch_buffers(dwc);
648 if (ret)
649 goto err1;
650
651 /* Adjust Frame Length */
652 dwc3_frame_length_adjustment(dwc);
653
654 usb_phy_set_suspend(dwc->usb2_phy, 0);
655 usb_phy_set_suspend(dwc->usb3_phy, 0);
656 ret = phy_power_on(dwc->usb2_generic_phy);
657 if (ret < 0)
658 goto err2;
659
660 ret = phy_power_on(dwc->usb3_generic_phy);
661 if (ret < 0)
662 goto err3;
663
664 ret = dwc3_event_buffers_setup(dwc);
665 if (ret) {
666 dev_err(dwc->dev, "failed to setup event buffers\n");
667 goto err4;
668 }
669
670 return 0;
671
672 err4:
673 phy_power_off(dwc->usb2_generic_phy);
674
675 err3:
676 phy_power_off(dwc->usb3_generic_phy);
677
678 err2:
679 usb_phy_set_suspend(dwc->usb2_phy, 1);
680 usb_phy_set_suspend(dwc->usb3_phy, 1);
681 dwc3_core_exit(dwc);
682
683 err1:
684 usb_phy_shutdown(dwc->usb2_phy);
685 usb_phy_shutdown(dwc->usb3_phy);
686 phy_exit(dwc->usb2_generic_phy);
687 phy_exit(dwc->usb3_generic_phy);
688
689 err0:
690 return ret;
691 }
692
693 static int dwc3_core_get_phy(struct dwc3 *dwc)
694 {
695 struct device *dev = dwc->dev;
696 struct device_node *node = dev->of_node;
697 int ret;
698
699 if (node) {
700 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
701 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
702 } else {
703 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
704 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
705 }
706
707 if (IS_ERR(dwc->usb2_phy)) {
708 ret = PTR_ERR(dwc->usb2_phy);
709 if (ret == -ENXIO || ret == -ENODEV) {
710 dwc->usb2_phy = NULL;
711 } else if (ret == -EPROBE_DEFER) {
712 return ret;
713 } else {
714 dev_err(dev, "no usb2 phy configured\n");
715 return ret;
716 }
717 }
718
719 if (IS_ERR(dwc->usb3_phy)) {
720 ret = PTR_ERR(dwc->usb3_phy);
721 if (ret == -ENXIO || ret == -ENODEV) {
722 dwc->usb3_phy = NULL;
723 } else if (ret == -EPROBE_DEFER) {
724 return ret;
725 } else {
726 dev_err(dev, "no usb3 phy configured\n");
727 return ret;
728 }
729 }
730
731 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
732 if (IS_ERR(dwc->usb2_generic_phy)) {
733 ret = PTR_ERR(dwc->usb2_generic_phy);
734 if (ret == -ENOSYS || ret == -ENODEV) {
735 dwc->usb2_generic_phy = NULL;
736 } else if (ret == -EPROBE_DEFER) {
737 return ret;
738 } else {
739 dev_err(dev, "no usb2 phy configured\n");
740 return ret;
741 }
742 }
743
744 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
745 if (IS_ERR(dwc->usb3_generic_phy)) {
746 ret = PTR_ERR(dwc->usb3_generic_phy);
747 if (ret == -ENOSYS || ret == -ENODEV) {
748 dwc->usb3_generic_phy = NULL;
749 } else if (ret == -EPROBE_DEFER) {
750 return ret;
751 } else {
752 dev_err(dev, "no usb3 phy configured\n");
753 return ret;
754 }
755 }
756
757 return 0;
758 }
759
760 static int dwc3_core_init_mode(struct dwc3 *dwc)
761 {
762 struct device *dev = dwc->dev;
763 int ret;
764
765 switch (dwc->dr_mode) {
766 case USB_DR_MODE_PERIPHERAL:
767 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
768 ret = dwc3_gadget_init(dwc);
769 if (ret) {
770 dev_err(dev, "failed to initialize gadget\n");
771 return ret;
772 }
773 break;
774 case USB_DR_MODE_HOST:
775 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
776 ret = dwc3_host_init(dwc);
777 if (ret) {
778 dev_err(dev, "failed to initialize host\n");
779 return ret;
780 }
781 break;
782 case USB_DR_MODE_OTG:
783 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
784 ret = dwc3_host_init(dwc);
785 if (ret) {
786 dev_err(dev, "failed to initialize host\n");
787 return ret;
788 }
789
790 ret = dwc3_gadget_init(dwc);
791 if (ret) {
792 dev_err(dev, "failed to initialize gadget\n");
793 return ret;
794 }
795 break;
796 default:
797 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
798 return -EINVAL;
799 }
800
801 return 0;
802 }
803
804 static void dwc3_core_exit_mode(struct dwc3 *dwc)
805 {
806 switch (dwc->dr_mode) {
807 case USB_DR_MODE_PERIPHERAL:
808 dwc3_gadget_exit(dwc);
809 break;
810 case USB_DR_MODE_HOST:
811 dwc3_host_exit(dwc);
812 break;
813 case USB_DR_MODE_OTG:
814 dwc3_host_exit(dwc);
815 dwc3_gadget_exit(dwc);
816 break;
817 default:
818 /* do nothing */
819 break;
820 }
821 }
822
823 #define DWC3_ALIGN_MASK (16 - 1)
824
825 static int dwc3_probe(struct platform_device *pdev)
826 {
827 struct device *dev = &pdev->dev;
828 struct dwc3_platform_data *pdata = dev_get_platdata(dev);
829 struct resource *res;
830 struct dwc3 *dwc;
831 u8 lpm_nyet_threshold;
832 u8 tx_de_emphasis;
833 u8 hird_threshold;
834
835 int ret;
836
837 void __iomem *regs;
838 void *mem;
839
840 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
841 if (!mem)
842 return -ENOMEM;
843
844 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
845 dwc->mem = mem;
846 dwc->dev = dev;
847
848 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
849 if (!res) {
850 dev_err(dev, "missing IRQ\n");
851 return -ENODEV;
852 }
853 dwc->xhci_resources[1].start = res->start;
854 dwc->xhci_resources[1].end = res->end;
855 dwc->xhci_resources[1].flags = res->flags;
856 dwc->xhci_resources[1].name = res->name;
857
858 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
859 if (!res) {
860 dev_err(dev, "missing memory resource\n");
861 return -ENODEV;
862 }
863
864 dwc->xhci_resources[0].start = res->start;
865 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
866 DWC3_XHCI_REGS_END;
867 dwc->xhci_resources[0].flags = res->flags;
868 dwc->xhci_resources[0].name = res->name;
869
870 res->start += DWC3_GLOBALS_REGS_START;
871
872 /*
873 * Request memory region but exclude xHCI regs,
874 * since it will be requested by the xhci-plat driver.
875 */
876 regs = devm_ioremap_resource(dev, res);
877 if (IS_ERR(regs)) {
878 ret = PTR_ERR(regs);
879 goto err0;
880 }
881
882 dwc->regs = regs;
883 dwc->regs_size = resource_size(res);
884
885 /* default to highest possible threshold */
886 lpm_nyet_threshold = 0xff;
887
888 /* default to -3.5dB de-emphasis */
889 tx_de_emphasis = 1;
890
891 /*
892 * default to assert utmi_sleep_n and use maximum allowed HIRD
893 * threshold value of 0b1100
894 */
895 hird_threshold = 12;
896
897 dwc->maximum_speed = usb_get_maximum_speed(dev);
898 dwc->dr_mode = usb_get_dr_mode(dev);
899
900 dwc->has_lpm_erratum = device_property_read_bool(dev,
901 "snps,has-lpm-erratum");
902 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
903 &lpm_nyet_threshold);
904 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
905 "snps,is-utmi-l1-suspend");
906 device_property_read_u8(dev, "snps,hird-threshold",
907 &hird_threshold);
908 dwc->usb3_lpm_capable = device_property_read_bool(dev,
909 "snps,usb3_lpm_capable");
910
911 dwc->disable_scramble_quirk = device_property_read_bool(dev,
912 "snps,disable_scramble_quirk");
913 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
914 "snps,u2exit_lfps_quirk");
915 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
916 "snps,u2ss_inp3_quirk");
917 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
918 "snps,req_p1p2p3_quirk");
919 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
920 "snps,del_p1p2p3_quirk");
921 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
922 "snps,del_phy_power_chg_quirk");
923 dwc->lfps_filter_quirk = device_property_read_bool(dev,
924 "snps,lfps_filter_quirk");
925 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
926 "snps,rx_detect_poll_quirk");
927 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
928 "snps,dis_u3_susphy_quirk");
929 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
930 "snps,dis_u2_susphy_quirk");
931 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
932 "snps,dis_enblslpm_quirk");
933 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
934 "snps,dis_rxdet_inp3_quirk");
935
936 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
937 "snps,tx_de_emphasis_quirk");
938 device_property_read_u8(dev, "snps,tx_de_emphasis",
939 &tx_de_emphasis);
940 device_property_read_string(dev, "snps,hsphy_interface",
941 &dwc->hsphy_interface);
942 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
943 &dwc->fladj);
944
945 if (pdata) {
946 dwc->maximum_speed = pdata->maximum_speed;
947 dwc->has_lpm_erratum = pdata->has_lpm_erratum;
948 if (pdata->lpm_nyet_threshold)
949 lpm_nyet_threshold = pdata->lpm_nyet_threshold;
950 dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend;
951 if (pdata->hird_threshold)
952 hird_threshold = pdata->hird_threshold;
953
954 dwc->usb3_lpm_capable = pdata->usb3_lpm_capable;
955 dwc->dr_mode = pdata->dr_mode;
956
957 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
958 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
959 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
960 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
961 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
962 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
963 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
964 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
965 dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk;
966 dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk;
967 dwc->dis_enblslpm_quirk = pdata->dis_enblslpm_quirk;
968 dwc->dis_rxdet_inp3_quirk = pdata->dis_rxdet_inp3_quirk;
969
970 dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk;
971 if (pdata->tx_de_emphasis)
972 tx_de_emphasis = pdata->tx_de_emphasis;
973
974 dwc->hsphy_interface = pdata->hsphy_interface;
975 dwc->fladj = pdata->fladj_value;
976 }
977
978 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
979 dwc->tx_de_emphasis = tx_de_emphasis;
980
981 dwc->hird_threshold = hird_threshold
982 | (dwc->is_utmi_l1_suspend << 4);
983
984 platform_set_drvdata(pdev, dwc);
985 dwc3_cache_hwparams(dwc);
986
987 ret = dwc3_core_get_phy(dwc);
988 if (ret)
989 goto err0;
990
991 spin_lock_init(&dwc->lock);
992
993 if (!dev->dma_mask) {
994 dev->dma_mask = dev->parent->dma_mask;
995 dev->dma_parms = dev->parent->dma_parms;
996 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
997 }
998
999 pm_runtime_enable(dev);
1000 pm_runtime_get_sync(dev);
1001 pm_runtime_forbid(dev);
1002
1003 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1004 if (ret) {
1005 dev_err(dwc->dev, "failed to allocate event buffers\n");
1006 ret = -ENOMEM;
1007 goto err0;
1008 }
1009
1010 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
1011 dwc->dr_mode = USB_DR_MODE_HOST;
1012 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
1013 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
1014
1015 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
1016 dwc->dr_mode = USB_DR_MODE_OTG;
1017
1018 ret = dwc3_alloc_scratch_buffers(dwc);
1019 if (ret)
1020 goto err1;
1021
1022 ret = dwc3_core_init(dwc);
1023 if (ret) {
1024 dev_err(dev, "failed to initialize core\n");
1025 goto err2;
1026 }
1027
1028 /* Check the maximum_speed parameter */
1029 switch (dwc->maximum_speed) {
1030 case USB_SPEED_LOW:
1031 case USB_SPEED_FULL:
1032 case USB_SPEED_HIGH:
1033 case USB_SPEED_SUPER:
1034 case USB_SPEED_SUPER_PLUS:
1035 break;
1036 default:
1037 dev_err(dev, "invalid maximum_speed parameter %d\n",
1038 dwc->maximum_speed);
1039 /* fall through */
1040 case USB_SPEED_UNKNOWN:
1041 /* default to superspeed */
1042 dwc->maximum_speed = USB_SPEED_SUPER;
1043
1044 /*
1045 * default to superspeed plus if we are capable.
1046 */
1047 if (dwc3_is_usb31(dwc) &&
1048 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1049 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1050 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1051
1052 break;
1053 }
1054
1055 ret = dwc3_core_init_mode(dwc);
1056 if (ret)
1057 goto err3;
1058
1059 dwc3_debugfs_init(dwc);
1060 pm_runtime_allow(dev);
1061
1062 return 0;
1063
1064 err3:
1065 dwc3_event_buffers_cleanup(dwc);
1066
1067 err2:
1068 dwc3_free_scratch_buffers(dwc);
1069
1070 err1:
1071 dwc3_free_event_buffers(dwc);
1072 dwc3_ulpi_exit(dwc);
1073
1074 err0:
1075 /*
1076 * restore res->start back to its original value so that, in case the
1077 * probe is deferred, we don't end up getting error in request the
1078 * memory region the next time probe is called.
1079 */
1080 res->start -= DWC3_GLOBALS_REGS_START;
1081
1082 return ret;
1083 }
1084
1085 static int dwc3_remove(struct platform_device *pdev)
1086 {
1087 struct dwc3 *dwc = platform_get_drvdata(pdev);
1088 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1089
1090 /*
1091 * restore res->start back to its original value so that, in case the
1092 * probe is deferred, we don't end up getting error in request the
1093 * memory region the next time probe is called.
1094 */
1095 res->start -= DWC3_GLOBALS_REGS_START;
1096
1097 dwc3_debugfs_exit(dwc);
1098 dwc3_core_exit_mode(dwc);
1099
1100 dwc3_core_exit(dwc);
1101 dwc3_ulpi_exit(dwc);
1102
1103 dwc3_free_event_buffers(dwc);
1104 dwc3_free_scratch_buffers(dwc);
1105
1106 pm_runtime_put_sync(&pdev->dev);
1107 pm_runtime_disable(&pdev->dev);
1108
1109 return 0;
1110 }
1111
1112 #ifdef CONFIG_PM_SLEEP
1113 static int dwc3_suspend(struct device *dev)
1114 {
1115 struct dwc3 *dwc = dev_get_drvdata(dev);
1116
1117 switch (dwc->dr_mode) {
1118 case USB_DR_MODE_PERIPHERAL:
1119 case USB_DR_MODE_OTG:
1120 dwc3_gadget_suspend(dwc);
1121 break;
1122 case USB_DR_MODE_HOST:
1123 default:
1124 /* do nothing */
1125 break;
1126 }
1127
1128 dwc3_core_exit(dwc);
1129
1130 pinctrl_pm_select_sleep_state(dev);
1131
1132 return 0;
1133 }
1134
1135 static int dwc3_resume(struct device *dev)
1136 {
1137 struct dwc3 *dwc = dev_get_drvdata(dev);
1138 int ret;
1139
1140 pinctrl_pm_select_default_state(dev);
1141
1142 ret = dwc3_core_init(dwc);
1143 if (ret)
1144 return ret;
1145
1146 switch (dwc->dr_mode) {
1147 case USB_DR_MODE_PERIPHERAL:
1148 case USB_DR_MODE_OTG:
1149 dwc3_gadget_resume(dwc);
1150 /* FALLTHROUGH */
1151 case USB_DR_MODE_HOST:
1152 default:
1153 /* do nothing */
1154 break;
1155 }
1156
1157 pm_runtime_disable(dev);
1158 pm_runtime_set_active(dev);
1159 pm_runtime_enable(dev);
1160
1161 return 0;
1162 }
1163 #endif /* CONFIG_PM_SLEEP */
1164
1165 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1166 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1167 };
1168
1169 #ifdef CONFIG_OF
1170 static const struct of_device_id of_dwc3_match[] = {
1171 {
1172 .compatible = "snps,dwc3"
1173 },
1174 {
1175 .compatible = "synopsys,dwc3"
1176 },
1177 { },
1178 };
1179 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1180 #endif
1181
1182 #ifdef CONFIG_ACPI
1183
1184 #define ACPI_ID_INTEL_BSW "808622B7"
1185
1186 static const struct acpi_device_id dwc3_acpi_match[] = {
1187 { ACPI_ID_INTEL_BSW, 0 },
1188 { },
1189 };
1190 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1191 #endif
1192
1193 static struct platform_driver dwc3_driver = {
1194 .probe = dwc3_probe,
1195 .remove = dwc3_remove,
1196 .driver = {
1197 .name = "dwc3",
1198 .of_match_table = of_match_ptr(of_dwc3_match),
1199 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1200 .pm = &dwc3_dev_pm_ops,
1201 },
1202 };
1203
1204 module_platform_driver(dwc3_driver);
1205
1206 MODULE_ALIAS("platform:dwc3");
1207 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1208 MODULE_LICENSE("GPL v2");
1209 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
Linux with added FPC-III support