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qlcnic: Fix mailbox completion handling during spurious interrupt
[linux/fpc-iii.git] / sound / pci / hda / patch_ca0132.c
blob0374bd5b61c82e42064d5020dc0879bb8588fda5
1 /*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/mutex.h>
28 #include <linux/module.h>
29 #include <linux/firmware.h>
30 #include <sound/core.h>
31 #include "hda_codec.h"
32 #include "hda_local.h"
33 #include "hda_auto_parser.h"
34 #include "hda_jack.h"
35
36 #include "ca0132_regs.h"
37
38 /* Enable this to see controls for tuning purpose. */
39 /*#define ENABLE_TUNING_CONTROLS*/
40
41 #define FLOAT_ZERO 0x00000000
42 #define FLOAT_ONE 0x3f800000
43 #define FLOAT_TWO 0x40000000
44 #define FLOAT_MINUS_5 0xc0a00000
45
46 #define UNSOL_TAG_HP 0x10
47 #define UNSOL_TAG_AMIC1 0x12
48 #define UNSOL_TAG_DSP 0x16
49
50 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
51 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
52
53 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
54 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
55 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
56
57 #define MASTERCONTROL 0x80
58 #define MASTERCONTROL_ALLOC_DMA_CHAN 10
59 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
60
61 #define WIDGET_CHIP_CTRL 0x15
62 #define WIDGET_DSP_CTRL 0x16
63
64 #define MEM_CONNID_MICIN1 3
65 #define MEM_CONNID_MICIN2 5
66 #define MEM_CONNID_MICOUT1 12
67 #define MEM_CONNID_MICOUT2 14
68 #define MEM_CONNID_WUH 10
69 #define MEM_CONNID_DSP 16
70 #define MEM_CONNID_DMIC 100
71
72 #define SCP_SET 0
73 #define SCP_GET 1
74
75 #define EFX_FILE "ctefx.bin"
76
77 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
78 MODULE_FIRMWARE(EFX_FILE);
79 #endif
80
81 static char *dirstr[2] = { "Playback", "Capture" };
82
83 enum {
84 SPEAKER_OUT,
85 HEADPHONE_OUT
86 };
87
88 enum {
89 DIGITAL_MIC,
90 LINE_MIC_IN
91 };
92
93 enum {
94 #define VNODE_START_NID 0x80
95 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
96 VNID_MIC,
97 VNID_HP_SEL,
98 VNID_AMIC1_SEL,
99 VNID_HP_ASEL,
100 VNID_AMIC1_ASEL,
101 VNODE_END_NID,
102 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
103
104 #define EFFECT_START_NID 0x90
105 #define OUT_EFFECT_START_NID EFFECT_START_NID
106 SURROUND = OUT_EFFECT_START_NID,
107 CRYSTALIZER,
108 DIALOG_PLUS,
109 SMART_VOLUME,
110 X_BASS,
111 EQUALIZER,
112 OUT_EFFECT_END_NID,
113 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
114
115 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID
116 ECHO_CANCELLATION = IN_EFFECT_START_NID,
117 VOICE_FOCUS,
118 MIC_SVM,
119 NOISE_REDUCTION,
120 IN_EFFECT_END_NID,
121 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
122
123 VOICEFX = IN_EFFECT_END_NID,
124 PLAY_ENHANCEMENT,
125 CRYSTAL_VOICE,
126 EFFECT_END_NID
127 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
128 };
129
130 /* Effects values size*/
131 #define EFFECT_VALS_MAX_COUNT 12
132
133 /* Latency introduced by DSP blocks in milliseconds. */
134 #define DSP_CAPTURE_INIT_LATENCY 0
135 #define DSP_CRYSTAL_VOICE_LATENCY 124
136 #define DSP_PLAYBACK_INIT_LATENCY 13
137 #define DSP_PLAY_ENHANCEMENT_LATENCY 30
138 #define DSP_SPEAKER_OUT_LATENCY 7
139
140 struct ct_effect {
141 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
142 hda_nid_t nid;
143 int mid; /*effect module ID*/
144 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
145 int direct; /* 0:output; 1:input*/
146 int params; /* number of default non-on/off params */
147 /*effect default values, 1st is on/off. */
148 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
149 };
150
151 #define EFX_DIR_OUT 0
152 #define EFX_DIR_IN 1
153
154 static struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
155 { .name = "Surround",
156 .nid = SURROUND,
157 .mid = 0x96,
158 .reqs = {0, 1},
159 .direct = EFX_DIR_OUT,
160 .params = 1,
161 .def_vals = {0x3F800000, 0x3F2B851F}
162 },
163 { .name = "Crystalizer",
164 .nid = CRYSTALIZER,
165 .mid = 0x96,
166 .reqs = {7, 8},
167 .direct = EFX_DIR_OUT,
168 .params = 1,
169 .def_vals = {0x3F800000, 0x3F266666}
170 },
171 { .name = "Dialog Plus",
172 .nid = DIALOG_PLUS,
173 .mid = 0x96,
174 .reqs = {2, 3},
175 .direct = EFX_DIR_OUT,
176 .params = 1,
177 .def_vals = {0x00000000, 0x3F000000}
178 },
179 { .name = "Smart Volume",
180 .nid = SMART_VOLUME,
181 .mid = 0x96,
182 .reqs = {4, 5, 6},
183 .direct = EFX_DIR_OUT,
184 .params = 2,
185 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
186 },
187 { .name = "X-Bass",
188 .nid = X_BASS,
189 .mid = 0x96,
190 .reqs = {24, 23, 25},
191 .direct = EFX_DIR_OUT,
192 .params = 2,
193 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
194 },
195 { .name = "Equalizer",
196 .nid = EQUALIZER,
197 .mid = 0x96,
198 .reqs = {9, 10, 11, 12, 13, 14,
199 15, 16, 17, 18, 19, 20},
200 .direct = EFX_DIR_OUT,
201 .params = 11,
202 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
203 0x00000000, 0x00000000, 0x00000000, 0x00000000,
204 0x00000000, 0x00000000, 0x00000000, 0x00000000}
205 },
206 { .name = "Echo Cancellation",
207 .nid = ECHO_CANCELLATION,
208 .mid = 0x95,
209 .reqs = {0, 1, 2, 3},
210 .direct = EFX_DIR_IN,
211 .params = 3,
212 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
213 },
214 { .name = "Voice Focus",
215 .nid = VOICE_FOCUS,
216 .mid = 0x95,
217 .reqs = {6, 7, 8, 9},
218 .direct = EFX_DIR_IN,
219 .params = 3,
220 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
221 },
222 { .name = "Mic SVM",
223 .nid = MIC_SVM,
224 .mid = 0x95,
225 .reqs = {44, 45},
226 .direct = EFX_DIR_IN,
227 .params = 1,
228 .def_vals = {0x00000000, 0x3F3D70A4}
229 },
230 { .name = "Noise Reduction",
231 .nid = NOISE_REDUCTION,
232 .mid = 0x95,
233 .reqs = {4, 5},
234 .direct = EFX_DIR_IN,
235 .params = 1,
236 .def_vals = {0x3F800000, 0x3F000000}
237 },
238 { .name = "VoiceFX",
239 .nid = VOICEFX,
240 .mid = 0x95,
241 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
242 .direct = EFX_DIR_IN,
243 .params = 8,
244 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
245 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
246 0x00000000}
247 }
248 };
249
250 /* Tuning controls */
251 #ifdef ENABLE_TUNING_CONTROLS
252
253 enum {
254 #define TUNING_CTL_START_NID 0xC0
255 WEDGE_ANGLE = TUNING_CTL_START_NID,
256 SVM_LEVEL,
257 EQUALIZER_BAND_0,
258 EQUALIZER_BAND_1,
259 EQUALIZER_BAND_2,
260 EQUALIZER_BAND_3,
261 EQUALIZER_BAND_4,
262 EQUALIZER_BAND_5,
263 EQUALIZER_BAND_6,
264 EQUALIZER_BAND_7,
265 EQUALIZER_BAND_8,
266 EQUALIZER_BAND_9,
267 TUNING_CTL_END_NID
268 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
269 };
270
271 struct ct_tuning_ctl {
272 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
273 hda_nid_t parent_nid;
274 hda_nid_t nid;
275 int mid; /*effect module ID*/
276 int req; /*effect module request*/
277 int direct; /* 0:output; 1:input*/
278 unsigned int def_val;/*effect default values*/
279 };
280
281 static struct ct_tuning_ctl ca0132_tuning_ctls[] = {
282 { .name = "Wedge Angle",
283 .parent_nid = VOICE_FOCUS,
284 .nid = WEDGE_ANGLE,
285 .mid = 0x95,
286 .req = 8,
287 .direct = EFX_DIR_IN,
288 .def_val = 0x41F00000
289 },
290 { .name = "SVM Level",
291 .parent_nid = MIC_SVM,
292 .nid = SVM_LEVEL,
293 .mid = 0x95,
294 .req = 45,
295 .direct = EFX_DIR_IN,
296 .def_val = 0x3F3D70A4
297 },
298 { .name = "EQ Band0",
299 .parent_nid = EQUALIZER,
300 .nid = EQUALIZER_BAND_0,
301 .mid = 0x96,
302 .req = 11,
303 .direct = EFX_DIR_OUT,
304 .def_val = 0x00000000
305 },
306 { .name = "EQ Band1",
307 .parent_nid = EQUALIZER,
308 .nid = EQUALIZER_BAND_1,
309 .mid = 0x96,
310 .req = 12,
311 .direct = EFX_DIR_OUT,
312 .def_val = 0x00000000
313 },
314 { .name = "EQ Band2",
315 .parent_nid = EQUALIZER,
316 .nid = EQUALIZER_BAND_2,
317 .mid = 0x96,
318 .req = 13,
319 .direct = EFX_DIR_OUT,
320 .def_val = 0x00000000
321 },
322 { .name = "EQ Band3",
323 .parent_nid = EQUALIZER,
324 .nid = EQUALIZER_BAND_3,
325 .mid = 0x96,
326 .req = 14,
327 .direct = EFX_DIR_OUT,
328 .def_val = 0x00000000
329 },
330 { .name = "EQ Band4",
331 .parent_nid = EQUALIZER,
332 .nid = EQUALIZER_BAND_4,
333 .mid = 0x96,
334 .req = 15,
335 .direct = EFX_DIR_OUT,
336 .def_val = 0x00000000
337 },
338 { .name = "EQ Band5",
339 .parent_nid = EQUALIZER,
340 .nid = EQUALIZER_BAND_5,
341 .mid = 0x96,
342 .req = 16,
343 .direct = EFX_DIR_OUT,
344 .def_val = 0x00000000
345 },
346 { .name = "EQ Band6",
347 .parent_nid = EQUALIZER,
348 .nid = EQUALIZER_BAND_6,
349 .mid = 0x96,
350 .req = 17,
351 .direct = EFX_DIR_OUT,
352 .def_val = 0x00000000
353 },
354 { .name = "EQ Band7",
355 .parent_nid = EQUALIZER,
356 .nid = EQUALIZER_BAND_7,
357 .mid = 0x96,
358 .req = 18,
359 .direct = EFX_DIR_OUT,
360 .def_val = 0x00000000
361 },
362 { .name = "EQ Band8",
363 .parent_nid = EQUALIZER,
364 .nid = EQUALIZER_BAND_8,
365 .mid = 0x96,
366 .req = 19,
367 .direct = EFX_DIR_OUT,
368 .def_val = 0x00000000
369 },
370 { .name = "EQ Band9",
371 .parent_nid = EQUALIZER,
372 .nid = EQUALIZER_BAND_9,
373 .mid = 0x96,
374 .req = 20,
375 .direct = EFX_DIR_OUT,
376 .def_val = 0x00000000
377 }
378 };
379 #endif
380
381 /* Voice FX Presets */
382 #define VOICEFX_MAX_PARAM_COUNT 9
383
384 struct ct_voicefx {
385 char *name;
386 hda_nid_t nid;
387 int mid;
388 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
389 };
390
391 struct ct_voicefx_preset {
392 char *name; /*preset name*/
393 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
394 };
395
396 static struct ct_voicefx ca0132_voicefx = {
397 .name = "VoiceFX Capture Switch",
398 .nid = VOICEFX,
399 .mid = 0x95,
400 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
401 };
402
403 static struct ct_voicefx_preset ca0132_voicefx_presets[] = {
404 { .name = "Neutral",
405 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
406 0x44FA0000, 0x3F800000, 0x3F800000,
407 0x3F800000, 0x00000000, 0x00000000 }
408 },
409 { .name = "Female2Male",
410 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
411 0x44FA0000, 0x3F19999A, 0x3F866666,
412 0x3F800000, 0x00000000, 0x00000000 }
413 },
414 { .name = "Male2Female",
415 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
416 0x450AC000, 0x4017AE14, 0x3F6B851F,
417 0x3F800000, 0x00000000, 0x00000000 }
418 },
419 { .name = "ScrappyKid",
420 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
421 0x44FA0000, 0x40400000, 0x3F28F5C3,
422 0x3F800000, 0x00000000, 0x00000000 }
423 },
424 { .name = "Elderly",
425 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
426 0x44E10000, 0x3FB33333, 0x3FB9999A,
427 0x3F800000, 0x3E3A2E43, 0x00000000 }
428 },
429 { .name = "Orc",
430 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
431 0x45098000, 0x3F266666, 0x3FC00000,
432 0x3F800000, 0x00000000, 0x00000000 }
433 },
434 { .name = "Elf",
435 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
436 0x45193000, 0x3F8E147B, 0x3F75C28F,
437 0x3F800000, 0x00000000, 0x00000000 }
438 },
439 { .name = "Dwarf",
440 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
441 0x45007000, 0x3F451EB8, 0x3F7851EC,
442 0x3F800000, 0x00000000, 0x00000000 }
443 },
444 { .name = "AlienBrute",
445 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
446 0x451F6000, 0x3F266666, 0x3FA7D945,
447 0x3F800000, 0x3CF5C28F, 0x00000000 }
448 },
449 { .name = "Robot",
450 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
451 0x44FA0000, 0x3FB2718B, 0x3F800000,
452 0xBC07010E, 0x00000000, 0x00000000 }
453 },
454 { .name = "Marine",
455 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
456 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
457 0x3F0A3D71, 0x00000000, 0x00000000 }
458 },
459 { .name = "Emo",
460 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
461 0x44FA0000, 0x3F800000, 0x3F800000,
462 0x3E4CCCCD, 0x00000000, 0x00000000 }
463 },
464 { .name = "DeepVoice",
465 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
466 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
467 0x3F800000, 0x00000000, 0x00000000 }
468 },
469 { .name = "Munchkin",
470 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
471 0x44FA0000, 0x3F800000, 0x3F1A043C,
472 0x3F800000, 0x00000000, 0x00000000 }
473 }
474 };
475
476 enum hda_cmd_vendor_io {
477 /* for DspIO node */
478 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
479 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
480
481 VENDOR_DSPIO_STATUS = 0xF01,
482 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
483 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
484 VENDOR_DSPIO_DSP_INIT = 0x703,
485 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
486 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
487
488 /* for ChipIO node */
489 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
490 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
491 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
492 VENDOR_CHIPIO_DATA_LOW = 0x300,
493 VENDOR_CHIPIO_DATA_HIGH = 0x400,
494
495 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
496 VENDOR_CHIPIO_STATUS = 0xF01,
497 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
498 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
499
500 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
501 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
502
503 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
504 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
505
506 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
507 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
508 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
509 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
510 VENDOR_CHIPIO_FLAG_SET = 0x70F,
511 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
512 VENDOR_CHIPIO_PARAM_SET = 0x710,
513 VENDOR_CHIPIO_PARAM_GET = 0xF10,
514
515 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
516 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
517 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
518 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
519
520 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
521 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
522 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
523 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
524
525 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
526 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
527 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
528 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
529 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
530 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
531
532 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
533 };
534
535 /*
536 * Control flag IDs
537 */
538 enum control_flag_id {
539 /* Connection manager stream setup is bypassed/enabled */
540 CONTROL_FLAG_C_MGR = 0,
541 /* DSP DMA is bypassed/enabled */
542 CONTROL_FLAG_DMA = 1,
543 /* 8051 'idle' mode is disabled/enabled */
544 CONTROL_FLAG_IDLE_ENABLE = 2,
545 /* Tracker for the SPDIF-in path is bypassed/enabled */
546 CONTROL_FLAG_TRACKER = 3,
547 /* DigitalOut to Spdif2Out connection is disabled/enabled */
548 CONTROL_FLAG_SPDIF2OUT = 4,
549 /* Digital Microphone is disabled/enabled */
550 CONTROL_FLAG_DMIC = 5,
551 /* ADC_B rate is 48 kHz/96 kHz */
552 CONTROL_FLAG_ADC_B_96KHZ = 6,
553 /* ADC_C rate is 48 kHz/96 kHz */
554 CONTROL_FLAG_ADC_C_96KHZ = 7,
555 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
556 CONTROL_FLAG_DAC_96KHZ = 8,
557 /* DSP rate is 48 kHz/96 kHz */
558 CONTROL_FLAG_DSP_96KHZ = 9,
559 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
560 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
561 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
562 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
563 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
564 CONTROL_FLAG_DECODE_LOOP = 12,
565 /* De-emphasis filter on DAC-1 disabled/enabled */
566 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
567 /* De-emphasis filter on DAC-2 disabled/enabled */
568 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
569 /* De-emphasis filter on DAC-3 disabled/enabled */
570 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
571 /* High-pass filter on ADC_B disabled/enabled */
572 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
573 /* High-pass filter on ADC_C disabled/enabled */
574 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
575 /* Common mode on Port_A disabled/enabled */
576 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
577 /* Common mode on Port_D disabled/enabled */
578 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
579 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
580 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
581 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
582 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
583 /* ASI rate is 48kHz/96kHz */
584 CONTROL_FLAG_ASI_96KHZ = 22,
585 /* DAC power settings able to control attached ports no/yes */
586 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
587 /* Clock Stop OK reporting is disabled/enabled */
588 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
589 /* Number of control flags */
590 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
591 };
592
593 /*
594 * Control parameter IDs
595 */
596 enum control_param_id {
597 /* 0: None, 1: Mic1In*/
598 CONTROL_PARAM_VIP_SOURCE = 1,
599 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
600 CONTROL_PARAM_SPDIF1_SOURCE = 2,
601 /* Port A output stage gain setting to use when 16 Ohm output
602 * impedance is selected*/
603 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
604 /* Port D output stage gain setting to use when 16 Ohm output
605 * impedance is selected*/
606 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
607
608 /* Stream Control */
609
610 /* Select stream with the given ID */
611 CONTROL_PARAM_STREAM_ID = 24,
612 /* Source connection point for the selected stream */
613 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
614 /* Destination connection point for the selected stream */
615 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
616 /* Number of audio channels in the selected stream */
617 CONTROL_PARAM_STREAMS_CHANNELS = 27,
618 /*Enable control for the selected stream */
619 CONTROL_PARAM_STREAM_CONTROL = 28,
620
621 /* Connection Point Control */
622
623 /* Select connection point with the given ID */
624 CONTROL_PARAM_CONN_POINT_ID = 29,
625 /* Connection point sample rate */
626 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
627
628 /* Node Control */
629
630 /* Select HDA node with the given ID */
631 CONTROL_PARAM_NODE_ID = 31
632 };
633
634 /*
635 * Dsp Io Status codes
636 */
637 enum hda_vendor_status_dspio {
638 /* Success */
639 VENDOR_STATUS_DSPIO_OK = 0x00,
640 /* Busy, unable to accept new command, the host must retry */
641 VENDOR_STATUS_DSPIO_BUSY = 0x01,
642 /* SCP command queue is full */
643 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
644 /* SCP response queue is empty */
645 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
646 };
647
648 /*
649 * Chip Io Status codes
650 */
651 enum hda_vendor_status_chipio {
652 /* Success */
653 VENDOR_STATUS_CHIPIO_OK = 0x00,
654 /* Busy, unable to accept new command, the host must retry */
655 VENDOR_STATUS_CHIPIO_BUSY = 0x01
656 };
657
658 /*
659 * CA0132 sample rate
660 */
661 enum ca0132_sample_rate {
662 SR_6_000 = 0x00,
663 SR_8_000 = 0x01,
664 SR_9_600 = 0x02,
665 SR_11_025 = 0x03,
666 SR_16_000 = 0x04,
667 SR_22_050 = 0x05,
668 SR_24_000 = 0x06,
669 SR_32_000 = 0x07,
670 SR_44_100 = 0x08,
671 SR_48_000 = 0x09,
672 SR_88_200 = 0x0A,
673 SR_96_000 = 0x0B,
674 SR_144_000 = 0x0C,
675 SR_176_400 = 0x0D,
676 SR_192_000 = 0x0E,
677 SR_384_000 = 0x0F,
678
679 SR_COUNT = 0x10,
680
681 SR_RATE_UNKNOWN = 0x1F
682 };
683
684 enum dsp_download_state {
685 DSP_DOWNLOAD_FAILED = -1,
686 DSP_DOWNLOAD_INIT = 0,
687 DSP_DOWNLOADING = 1,
688 DSP_DOWNLOADED = 2
689 };
690
691 /* retrieve parameters from hda format */
692 #define get_hdafmt_chs(fmt) (fmt & 0xf)
693 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
694 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
695 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
696
697 /*
698 * CA0132 specific
699 */
700
701 struct ca0132_spec {
702 struct snd_kcontrol_new *mixers[5];
703 unsigned int num_mixers;
704 const struct hda_verb *base_init_verbs;
705 const struct hda_verb *base_exit_verbs;
706 const struct hda_verb *init_verbs[5];
707 unsigned int num_init_verbs; /* exclude base init verbs */
708 struct auto_pin_cfg autocfg;
709
710 /* Nodes configurations */
711 struct hda_multi_out multiout;
712 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
713 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
714 unsigned int num_outputs;
715 hda_nid_t input_pins[AUTO_PIN_LAST];
716 hda_nid_t adcs[AUTO_PIN_LAST];
717 hda_nid_t dig_out;
718 hda_nid_t dig_in;
719 unsigned int num_inputs;
720 hda_nid_t shared_mic_nid;
721 hda_nid_t shared_out_nid;
722
723 /* chip access */
724 struct mutex chipio_mutex; /* chip access mutex */
725 u32 curr_chip_addx;
726
727 /* DSP download related */
728 enum dsp_download_state dsp_state;
729 unsigned int dsp_stream_id;
730 unsigned int wait_scp;
731 unsigned int wait_scp_header;
732 unsigned int wait_num_data;
733 unsigned int scp_resp_header;
734 unsigned int scp_resp_data[4];
735 unsigned int scp_resp_count;
736
737 /* mixer and effects related */
738 unsigned char dmic_ctl;
739 int cur_out_type;
740 int cur_mic_type;
741 long vnode_lvol[VNODES_COUNT];
742 long vnode_rvol[VNODES_COUNT];
743 long vnode_lswitch[VNODES_COUNT];
744 long vnode_rswitch[VNODES_COUNT];
745 long effects_switch[EFFECTS_COUNT];
746 long voicefx_val;
747 long cur_mic_boost;
748
749 struct hda_codec *codec;
750 struct delayed_work unsol_hp_work;
751
752 #ifdef ENABLE_TUNING_CONTROLS
753 long cur_ctl_vals[TUNING_CTLS_COUNT];
754 #endif
755 };
756
757 /*
758 * CA0132 codec access
759 */
760 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
761 unsigned int verb, unsigned int parm, unsigned int *res)
762 {
763 unsigned int response;
764 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
765 *res = response;
766
767 return ((response == -1) ? -1 : 0);
768 }
769
770 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
771 unsigned short converter_format, unsigned int *res)
772 {
773 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
774 converter_format & 0xffff, res);
775 }
776
777 static int codec_set_converter_stream_channel(struct hda_codec *codec,
778 hda_nid_t nid, unsigned char stream,
779 unsigned char channel, unsigned int *res)
780 {
781 unsigned char converter_stream_channel = 0;
782
783 converter_stream_channel = (stream << 4) | (channel & 0x0f);
784 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
785 converter_stream_channel, res);
786 }
787
788 /* Chip access helper function */
789 static int chipio_send(struct hda_codec *codec,
790 unsigned int reg,
791 unsigned int data)
792 {
793 unsigned int res;
794 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
795
796 /* send bits of data specified by reg */
797 do {
798 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
799 reg, data);
800 if (res == VENDOR_STATUS_CHIPIO_OK)
801 return 0;
802 msleep(20);
803 } while (time_before(jiffies, timeout));
804
805 return -EIO;
806 }
807
808 /*
809 * Write chip address through the vendor widget -- NOT protected by the Mutex!
810 */
811 static int chipio_write_address(struct hda_codec *codec,
812 unsigned int chip_addx)
813 {
814 struct ca0132_spec *spec = codec->spec;
815 int res;
816
817 if (spec->curr_chip_addx == chip_addx)
818 return 0;
819
820 /* send low 16 bits of the address */
821 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
822 chip_addx & 0xffff);
823
824 if (res != -EIO) {
825 /* send high 16 bits of the address */
826 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
827 chip_addx >> 16);
828 }
829
830 spec->curr_chip_addx = (res < 0) ? ~0UL : chip_addx;
831
832 return res;
833 }
834
835 /*
836 * Write data through the vendor widget -- NOT protected by the Mutex!
837 */
838 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
839 {
840 struct ca0132_spec *spec = codec->spec;
841 int res;
842
843 /* send low 16 bits of the data */
844 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
845
846 if (res != -EIO) {
847 /* send high 16 bits of the data */
848 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
849 data >> 16);
850 }
851
852 /*If no error encountered, automatically increment the address
853 as per chip behaviour*/
854 spec->curr_chip_addx = (res != -EIO) ?
855 (spec->curr_chip_addx + 4) : ~0UL;
856 return res;
857 }
858
859 /*
860 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
861 */
862 static int chipio_write_data_multiple(struct hda_codec *codec,
863 const u32 *data,
864 unsigned int count)
865 {
866 int status = 0;
867
868 if (data == NULL) {
869 codec_dbg(codec, "chipio_write_data null ptr\n");
870 return -EINVAL;
871 }
872
873 while ((count-- != 0) && (status == 0))
874 status = chipio_write_data(codec, *data++);
875
876 return status;
877 }
878
879
880 /*
881 * Read data through the vendor widget -- NOT protected by the Mutex!
882 */
883 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
884 {
885 struct ca0132_spec *spec = codec->spec;
886 int res;
887
888 /* post read */
889 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
890
891 if (res != -EIO) {
892 /* read status */
893 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
894 }
895
896 if (res != -EIO) {
897 /* read data */
898 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
899 VENDOR_CHIPIO_HIC_READ_DATA,
900 0);
901 }
902
903 /*If no error encountered, automatically increment the address
904 as per chip behaviour*/
905 spec->curr_chip_addx = (res != -EIO) ?
906 (spec->curr_chip_addx + 4) : ~0UL;
907 return res;
908 }
909
910 /*
911 * Write given value to the given address through the chip I/O widget.
912 * protected by the Mutex
913 */
914 static int chipio_write(struct hda_codec *codec,
915 unsigned int chip_addx, const unsigned int data)
916 {
917 struct ca0132_spec *spec = codec->spec;
918 int err;
919
920 mutex_lock(&spec->chipio_mutex);
921
922 /* write the address, and if successful proceed to write data */
923 err = chipio_write_address(codec, chip_addx);
924 if (err < 0)
925 goto exit;
926
927 err = chipio_write_data(codec, data);
928 if (err < 0)
929 goto exit;
930
931 exit:
932 mutex_unlock(&spec->chipio_mutex);
933 return err;
934 }
935
936 /*
937 * Write multiple values to the given address through the chip I/O widget.
938 * protected by the Mutex
939 */
940 static int chipio_write_multiple(struct hda_codec *codec,
941 u32 chip_addx,
942 const u32 *data,
943 unsigned int count)
944 {
945 struct ca0132_spec *spec = codec->spec;
946 int status;
947
948 mutex_lock(&spec->chipio_mutex);
949 status = chipio_write_address(codec, chip_addx);
950 if (status < 0)
951 goto error;
952
953 status = chipio_write_data_multiple(codec, data, count);
954 error:
955 mutex_unlock(&spec->chipio_mutex);
956
957 return status;
958 }
959
960 /*
961 * Read the given address through the chip I/O widget
962 * protected by the Mutex
963 */
964 static int chipio_read(struct hda_codec *codec,
965 unsigned int chip_addx, unsigned int *data)
966 {
967 struct ca0132_spec *spec = codec->spec;
968 int err;
969
970 mutex_lock(&spec->chipio_mutex);
971
972 /* write the address, and if successful proceed to write data */
973 err = chipio_write_address(codec, chip_addx);
974 if (err < 0)
975 goto exit;
976
977 err = chipio_read_data(codec, data);
978 if (err < 0)
979 goto exit;
980
981 exit:
982 mutex_unlock(&spec->chipio_mutex);
983 return err;
984 }
985
986 /*
987 * Set chip control flags through the chip I/O widget.
988 */
989 static void chipio_set_control_flag(struct hda_codec *codec,
990 enum control_flag_id flag_id,
991 bool flag_state)
992 {
993 unsigned int val;
994 unsigned int flag_bit;
995
996 flag_bit = (flag_state ? 1 : 0);
997 val = (flag_bit << 7) | (flag_id);
998 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
999 VENDOR_CHIPIO_FLAG_SET, val);
1000 }
1001
1002 /*
1003 * Set chip parameters through the chip I/O widget.
1004 */
1005 static void chipio_set_control_param(struct hda_codec *codec,
1006 enum control_param_id param_id, int param_val)
1007 {
1008 struct ca0132_spec *spec = codec->spec;
1009 int val;
1010
1011 if ((param_id < 32) && (param_val < 8)) {
1012 val = (param_val << 5) | (param_id);
1013 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1014 VENDOR_CHIPIO_PARAM_SET, val);
1015 } else {
1016 mutex_lock(&spec->chipio_mutex);
1017 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1018 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1019 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1020 param_id);
1021 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1022 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1023 param_val);
1024 }
1025 mutex_unlock(&spec->chipio_mutex);
1026 }
1027 }
1028
1029 /*
1030 * Set sampling rate of the connection point.
1031 */
1032 static void chipio_set_conn_rate(struct hda_codec *codec,
1033 int connid, enum ca0132_sample_rate rate)
1034 {
1035 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1036 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1037 rate);
1038 }
1039
1040 /*
1041 * Enable clocks.
1042 */
1043 static void chipio_enable_clocks(struct hda_codec *codec)
1044 {
1045 struct ca0132_spec *spec = codec->spec;
1046
1047 mutex_lock(&spec->chipio_mutex);
1048 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1049 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1050 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1051 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1052 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1053 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1054 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1055 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1056 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1057 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1058 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1059 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1060 mutex_unlock(&spec->chipio_mutex);
1061 }
1062
1063 /*
1064 * CA0132 DSP IO stuffs
1065 */
1066 static int dspio_send(struct hda_codec *codec, unsigned int reg,
1067 unsigned int data)
1068 {
1069 int res;
1070 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1071
1072 /* send bits of data specified by reg to dsp */
1073 do {
1074 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1075 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1076 return res;
1077 msleep(20);
1078 } while (time_before(jiffies, timeout));
1079
1080 return -EIO;
1081 }
1082
1083 /*
1084 * Wait for DSP to be ready for commands
1085 */
1086 static void dspio_write_wait(struct hda_codec *codec)
1087 {
1088 int status;
1089 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1090
1091 do {
1092 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1093 VENDOR_DSPIO_STATUS, 0);
1094 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1095 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1096 break;
1097 msleep(1);
1098 } while (time_before(jiffies, timeout));
1099 }
1100
1101 /*
1102 * Write SCP data to DSP
1103 */
1104 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1105 {
1106 struct ca0132_spec *spec = codec->spec;
1107 int status;
1108
1109 dspio_write_wait(codec);
1110
1111 mutex_lock(&spec->chipio_mutex);
1112 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1113 scp_data & 0xffff);
1114 if (status < 0)
1115 goto error;
1116
1117 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1118 scp_data >> 16);
1119 if (status < 0)
1120 goto error;
1121
1122 /* OK, now check if the write itself has executed*/
1123 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1124 VENDOR_DSPIO_STATUS, 0);
1125 error:
1126 mutex_unlock(&spec->chipio_mutex);
1127
1128 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1129 -EIO : 0;
1130 }
1131
1132 /*
1133 * Write multiple SCP data to DSP
1134 */
1135 static int dspio_write_multiple(struct hda_codec *codec,
1136 unsigned int *buffer, unsigned int size)
1137 {
1138 int status = 0;
1139 unsigned int count;
1140
1141 if ((buffer == NULL))
1142 return -EINVAL;
1143
1144 count = 0;
1145 while (count < size) {
1146 status = dspio_write(codec, *buffer++);
1147 if (status != 0)
1148 break;
1149 count++;
1150 }
1151
1152 return status;
1153 }
1154
1155 static int dspio_read(struct hda_codec *codec, unsigned int *data)
1156 {
1157 int status;
1158
1159 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1160 if (status == -EIO)
1161 return status;
1162
1163 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1164 if (status == -EIO ||
1165 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1166 return -EIO;
1167
1168 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1169 VENDOR_DSPIO_SCP_READ_DATA, 0);
1170
1171 return 0;
1172 }
1173
1174 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1175 unsigned int *buf_size, unsigned int size_count)
1176 {
1177 int status = 0;
1178 unsigned int size = *buf_size;
1179 unsigned int count;
1180 unsigned int skip_count;
1181 unsigned int dummy;
1182
1183 if ((buffer == NULL))
1184 return -1;
1185
1186 count = 0;
1187 while (count < size && count < size_count) {
1188 status = dspio_read(codec, buffer++);
1189 if (status != 0)
1190 break;
1191 count++;
1192 }
1193
1194 skip_count = count;
1195 if (status == 0) {
1196 while (skip_count < size) {
1197 status = dspio_read(codec, &dummy);
1198 if (status != 0)
1199 break;
1200 skip_count++;
1201 }
1202 }
1203 *buf_size = count;
1204
1205 return status;
1206 }
1207
1208 /*
1209 * Construct the SCP header using corresponding fields
1210 */
1211 static inline unsigned int
1212 make_scp_header(unsigned int target_id, unsigned int source_id,
1213 unsigned int get_flag, unsigned int req,
1214 unsigned int device_flag, unsigned int resp_flag,
1215 unsigned int error_flag, unsigned int data_size)
1216 {
1217 unsigned int header = 0;
1218
1219 header = (data_size & 0x1f) << 27;
1220 header |= (error_flag & 0x01) << 26;
1221 header |= (resp_flag & 0x01) << 25;
1222 header |= (device_flag & 0x01) << 24;
1223 header |= (req & 0x7f) << 17;
1224 header |= (get_flag & 0x01) << 16;
1225 header |= (source_id & 0xff) << 8;
1226 header |= target_id & 0xff;
1227
1228 return header;
1229 }
1230
1231 /*
1232 * Extract corresponding fields from SCP header
1233 */
1234 static inline void
1235 extract_scp_header(unsigned int header,
1236 unsigned int *target_id, unsigned int *source_id,
1237 unsigned int *get_flag, unsigned int *req,
1238 unsigned int *device_flag, unsigned int *resp_flag,
1239 unsigned int *error_flag, unsigned int *data_size)
1240 {
1241 if (data_size)
1242 *data_size = (header >> 27) & 0x1f;
1243 if (error_flag)
1244 *error_flag = (header >> 26) & 0x01;
1245 if (resp_flag)
1246 *resp_flag = (header >> 25) & 0x01;
1247 if (device_flag)
1248 *device_flag = (header >> 24) & 0x01;
1249 if (req)
1250 *req = (header >> 17) & 0x7f;
1251 if (get_flag)
1252 *get_flag = (header >> 16) & 0x01;
1253 if (source_id)
1254 *source_id = (header >> 8) & 0xff;
1255 if (target_id)
1256 *target_id = header & 0xff;
1257 }
1258
1259 #define SCP_MAX_DATA_WORDS (16)
1260
1261 /* Structure to contain any SCP message */
1262 struct scp_msg {
1263 unsigned int hdr;
1264 unsigned int data[SCP_MAX_DATA_WORDS];
1265 };
1266
1267 static void dspio_clear_response_queue(struct hda_codec *codec)
1268 {
1269 unsigned int dummy = 0;
1270 int status = -1;
1271
1272 /* clear all from the response queue */
1273 do {
1274 status = dspio_read(codec, &dummy);
1275 } while (status == 0);
1276 }
1277
1278 static int dspio_get_response_data(struct hda_codec *codec)
1279 {
1280 struct ca0132_spec *spec = codec->spec;
1281 unsigned int data = 0;
1282 unsigned int count;
1283
1284 if (dspio_read(codec, &data) < 0)
1285 return -EIO;
1286
1287 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1288 spec->scp_resp_header = data;
1289 spec->scp_resp_count = data >> 27;
1290 count = spec->wait_num_data;
1291 dspio_read_multiple(codec, spec->scp_resp_data,
1292 &spec->scp_resp_count, count);
1293 return 0;
1294 }
1295
1296 return -EIO;
1297 }
1298
1299 /*
1300 * Send SCP message to DSP
1301 */
1302 static int dspio_send_scp_message(struct hda_codec *codec,
1303 unsigned char *send_buf,
1304 unsigned int send_buf_size,
1305 unsigned char *return_buf,
1306 unsigned int return_buf_size,
1307 unsigned int *bytes_returned)
1308 {
1309 struct ca0132_spec *spec = codec->spec;
1310 int status = -1;
1311 unsigned int scp_send_size = 0;
1312 unsigned int total_size;
1313 bool waiting_for_resp = false;
1314 unsigned int header;
1315 struct scp_msg *ret_msg;
1316 unsigned int resp_src_id, resp_target_id;
1317 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1318
1319 if (bytes_returned)
1320 *bytes_returned = 0;
1321
1322 /* get scp header from buffer */
1323 header = *((unsigned int *)send_buf);
1324 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1325 &device_flag, NULL, NULL, &data_size);
1326 scp_send_size = data_size + 1;
1327 total_size = (scp_send_size * 4);
1328
1329 if (send_buf_size < total_size)
1330 return -EINVAL;
1331
1332 if (get_flag || device_flag) {
1333 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1334 return -EINVAL;
1335
1336 spec->wait_scp_header = *((unsigned int *)send_buf);
1337
1338 /* swap source id with target id */
1339 resp_target_id = src_id;
1340 resp_src_id = target_id;
1341 spec->wait_scp_header &= 0xffff0000;
1342 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1343 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1344 spec->wait_scp = 1;
1345 waiting_for_resp = true;
1346 }
1347
1348 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1349 scp_send_size);
1350 if (status < 0) {
1351 spec->wait_scp = 0;
1352 return status;
1353 }
1354
1355 if (waiting_for_resp) {
1356 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1357 memset(return_buf, 0, return_buf_size);
1358 do {
1359 msleep(20);
1360 } while (spec->wait_scp && time_before(jiffies, timeout));
1361 waiting_for_resp = false;
1362 if (!spec->wait_scp) {
1363 ret_msg = (struct scp_msg *)return_buf;
1364 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1365 memcpy(&ret_msg->data, spec->scp_resp_data,
1366 spec->wait_num_data);
1367 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1368 status = 0;
1369 } else {
1370 status = -EIO;
1371 }
1372 spec->wait_scp = 0;
1373 }
1374
1375 return status;
1376 }
1377
1378 /**
1379 * Prepare and send the SCP message to DSP
1380 * @codec: the HDA codec
1381 * @mod_id: ID of the DSP module to send the command
1382 * @req: ID of request to send to the DSP module
1383 * @dir: SET or GET
1384 * @data: pointer to the data to send with the request, request specific
1385 * @len: length of the data, in bytes
1386 * @reply: point to the buffer to hold data returned for a reply
1387 * @reply_len: length of the reply buffer returned from GET
1388 *
1389 * Returns zero or a negative error code.
1390 */
1391 static int dspio_scp(struct hda_codec *codec,
1392 int mod_id, int req, int dir, void *data, unsigned int len,
1393 void *reply, unsigned int *reply_len)
1394 {
1395 int status = 0;
1396 struct scp_msg scp_send, scp_reply;
1397 unsigned int ret_bytes, send_size, ret_size;
1398 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1399 unsigned int reply_data_size;
1400
1401 memset(&scp_send, 0, sizeof(scp_send));
1402 memset(&scp_reply, 0, sizeof(scp_reply));
1403
1404 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1405 return -EINVAL;
1406
1407 if (dir == SCP_GET && reply == NULL) {
1408 codec_dbg(codec, "dspio_scp get but has no buffer\n");
1409 return -EINVAL;
1410 }
1411
1412 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
1413 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
1414 return -EINVAL;
1415 }
1416
1417 scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req,
1418 0, 0, 0, len/sizeof(unsigned int));
1419 if (data != NULL && len > 0) {
1420 len = min((unsigned int)(sizeof(scp_send.data)), len);
1421 memcpy(scp_send.data, data, len);
1422 }
1423
1424 ret_bytes = 0;
1425 send_size = sizeof(unsigned int) + len;
1426 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1427 send_size, (unsigned char *)&scp_reply,
1428 sizeof(scp_reply), &ret_bytes);
1429
1430 if (status < 0) {
1431 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
1432 return status;
1433 }
1434
1435 /* extract send and reply headers members */
1436 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1437 NULL, NULL, NULL, NULL, NULL);
1438 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1439 &reply_resp_flag, &reply_error_flag,
1440 &reply_data_size);
1441
1442 if (!send_get_flag)
1443 return 0;
1444
1445 if (reply_resp_flag && !reply_error_flag) {
1446 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1447 / sizeof(unsigned int);
1448
1449 if (*reply_len < ret_size*sizeof(unsigned int)) {
1450 codec_dbg(codec, "reply too long for buf\n");
1451 return -EINVAL;
1452 } else if (ret_size != reply_data_size) {
1453 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
1454 return -EINVAL;
1455 } else {
1456 *reply_len = ret_size*sizeof(unsigned int);
1457 memcpy(reply, scp_reply.data, *reply_len);
1458 }
1459 } else {
1460 codec_dbg(codec, "reply ill-formed or errflag set\n");
1461 return -EIO;
1462 }
1463
1464 return status;
1465 }
1466
1467 /*
1468 * Set DSP parameters
1469 */
1470 static int dspio_set_param(struct hda_codec *codec, int mod_id,
1471 int req, void *data, unsigned int len)
1472 {
1473 return dspio_scp(codec, mod_id, req, SCP_SET, data, len, NULL, NULL);
1474 }
1475
1476 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1477 int req, unsigned int data)
1478 {
1479 return dspio_set_param(codec, mod_id, req, &data, sizeof(unsigned int));
1480 }
1481
1482 /*
1483 * Allocate a DSP DMA channel via an SCP message
1484 */
1485 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1486 {
1487 int status = 0;
1488 unsigned int size = sizeof(dma_chan);
1489
1490 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
1491 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1492 SCP_GET, NULL, 0, dma_chan, &size);
1493
1494 if (status < 0) {
1495 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
1496 return status;
1497 }
1498
1499 if ((*dma_chan + 1) == 0) {
1500 codec_dbg(codec, "no free dma channels to allocate\n");
1501 return -EBUSY;
1502 }
1503
1504 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1505 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
1506
1507 return status;
1508 }
1509
1510 /*
1511 * Free a DSP DMA via an SCP message
1512 */
1513 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1514 {
1515 int status = 0;
1516 unsigned int dummy = 0;
1517
1518 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
1519 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
1520
1521 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1522 SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy);
1523
1524 if (status < 0) {
1525 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
1526 return status;
1527 }
1528
1529 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
1530
1531 return status;
1532 }
1533
1534 /*
1535 * (Re)start the DSP
1536 */
1537 static int dsp_set_run_state(struct hda_codec *codec)
1538 {
1539 unsigned int dbg_ctrl_reg;
1540 unsigned int halt_state;
1541 int err;
1542
1543 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1544 if (err < 0)
1545 return err;
1546
1547 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1548 DSP_DBGCNTL_STATE_LOBIT;
1549
1550 if (halt_state != 0) {
1551 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1552 DSP_DBGCNTL_SS_MASK);
1553 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1554 dbg_ctrl_reg);
1555 if (err < 0)
1556 return err;
1557
1558 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1559 DSP_DBGCNTL_EXEC_MASK;
1560 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1561 dbg_ctrl_reg);
1562 if (err < 0)
1563 return err;
1564 }
1565
1566 return 0;
1567 }
1568
1569 /*
1570 * Reset the DSP
1571 */
1572 static int dsp_reset(struct hda_codec *codec)
1573 {
1574 unsigned int res;
1575 int retry = 20;
1576
1577 codec_dbg(codec, "dsp_reset\n");
1578 do {
1579 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1580 retry--;
1581 } while (res == -EIO && retry);
1582
1583 if (!retry) {
1584 codec_dbg(codec, "dsp_reset timeout\n");
1585 return -EIO;
1586 }
1587
1588 return 0;
1589 }
1590
1591 /*
1592 * Convert chip address to DSP address
1593 */
1594 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
1595 bool *code, bool *yram)
1596 {
1597 *code = *yram = false;
1598
1599 if (UC_RANGE(chip_addx, 1)) {
1600 *code = true;
1601 return UC_OFF(chip_addx);
1602 } else if (X_RANGE_ALL(chip_addx, 1)) {
1603 return X_OFF(chip_addx);
1604 } else if (Y_RANGE_ALL(chip_addx, 1)) {
1605 *yram = true;
1606 return Y_OFF(chip_addx);
1607 }
1608
1609 return INVALID_CHIP_ADDRESS;
1610 }
1611
1612 /*
1613 * Check if the DSP DMA is active
1614 */
1615 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
1616 {
1617 unsigned int dma_chnlstart_reg;
1618
1619 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
1620
1621 return ((dma_chnlstart_reg & (1 <<
1622 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
1623 }
1624
1625 static int dsp_dma_setup_common(struct hda_codec *codec,
1626 unsigned int chip_addx,
1627 unsigned int dma_chan,
1628 unsigned int port_map_mask,
1629 bool ovly)
1630 {
1631 int status = 0;
1632 unsigned int chnl_prop;
1633 unsigned int dsp_addx;
1634 unsigned int active;
1635 bool code, yram;
1636
1637 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
1638
1639 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
1640 codec_dbg(codec, "dma chan num invalid\n");
1641 return -EINVAL;
1642 }
1643
1644 if (dsp_is_dma_active(codec, dma_chan)) {
1645 codec_dbg(codec, "dma already active\n");
1646 return -EBUSY;
1647 }
1648
1649 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1650
1651 if (dsp_addx == INVALID_CHIP_ADDRESS) {
1652 codec_dbg(codec, "invalid chip addr\n");
1653 return -ENXIO;
1654 }
1655
1656 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
1657 active = 0;
1658
1659 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
1660
1661 if (ovly) {
1662 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
1663 &chnl_prop);
1664
1665 if (status < 0) {
1666 codec_dbg(codec, "read CHNLPROP Reg fail\n");
1667 return status;
1668 }
1669 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
1670 }
1671
1672 if (!code)
1673 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1674 else
1675 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1676
1677 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
1678
1679 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
1680 if (status < 0) {
1681 codec_dbg(codec, "write CHNLPROP Reg fail\n");
1682 return status;
1683 }
1684 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
1685
1686 if (ovly) {
1687 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
1688 &active);
1689
1690 if (status < 0) {
1691 codec_dbg(codec, "read ACTIVE Reg fail\n");
1692 return status;
1693 }
1694 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
1695 }
1696
1697 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
1698 DSPDMAC_ACTIVE_AAR_MASK;
1699
1700 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
1701 if (status < 0) {
1702 codec_dbg(codec, "write ACTIVE Reg fail\n");
1703 return status;
1704 }
1705
1706 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
1707
1708 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
1709 port_map_mask);
1710 if (status < 0) {
1711 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
1712 return status;
1713 }
1714 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
1715
1716 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
1717 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
1718 if (status < 0) {
1719 codec_dbg(codec, "write IRQCNT Reg fail\n");
1720 return status;
1721 }
1722 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
1723
1724 codec_dbg(codec,
1725 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
1726 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
1727 chip_addx, dsp_addx, dma_chan,
1728 port_map_mask, chnl_prop, active);
1729
1730 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
1731
1732 return 0;
1733 }
1734
1735 /*
1736 * Setup the DSP DMA per-transfer-specific registers
1737 */
1738 static int dsp_dma_setup(struct hda_codec *codec,
1739 unsigned int chip_addx,
1740 unsigned int count,
1741 unsigned int dma_chan)
1742 {
1743 int status = 0;
1744 bool code, yram;
1745 unsigned int dsp_addx;
1746 unsigned int addr_field;
1747 unsigned int incr_field;
1748 unsigned int base_cnt;
1749 unsigned int cur_cnt;
1750 unsigned int dma_cfg = 0;
1751 unsigned int adr_ofs = 0;
1752 unsigned int xfr_cnt = 0;
1753 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
1754 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
1755
1756 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
1757
1758 if (count > max_dma_count) {
1759 codec_dbg(codec, "count too big\n");
1760 return -EINVAL;
1761 }
1762
1763 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1764 if (dsp_addx == INVALID_CHIP_ADDRESS) {
1765 codec_dbg(codec, "invalid chip addr\n");
1766 return -ENXIO;
1767 }
1768
1769 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
1770
1771 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
1772 incr_field = 0;
1773
1774 if (!code) {
1775 addr_field <<= 1;
1776 if (yram)
1777 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
1778
1779 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
1780 }
1781
1782 dma_cfg = addr_field + incr_field;
1783 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
1784 dma_cfg);
1785 if (status < 0) {
1786 codec_dbg(codec, "write DMACFG Reg fail\n");
1787 return status;
1788 }
1789 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
1790
1791 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
1792 (code ? 0 : 1));
1793
1794 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
1795 adr_ofs);
1796 if (status < 0) {
1797 codec_dbg(codec, "write DSPADROFS Reg fail\n");
1798 return status;
1799 }
1800 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
1801
1802 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
1803
1804 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
1805
1806 xfr_cnt = base_cnt | cur_cnt;
1807
1808 status = chipio_write(codec,
1809 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
1810 if (status < 0) {
1811 codec_dbg(codec, "write XFRCNT Reg fail\n");
1812 return status;
1813 }
1814 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
1815
1816 codec_dbg(codec,
1817 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
1818 "ADROFS=0x%x, XFRCNT=0x%x\n",
1819 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
1820
1821 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
1822
1823 return 0;
1824 }
1825
1826 /*
1827 * Start the DSP DMA
1828 */
1829 static int dsp_dma_start(struct hda_codec *codec,
1830 unsigned int dma_chan, bool ovly)
1831 {
1832 unsigned int reg = 0;
1833 int status = 0;
1834
1835 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
1836
1837 if (ovly) {
1838 status = chipio_read(codec,
1839 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1840
1841 if (status < 0) {
1842 codec_dbg(codec, "read CHNLSTART reg fail\n");
1843 return status;
1844 }
1845 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
1846
1847 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1848 DSPDMAC_CHNLSTART_DIS_MASK);
1849 }
1850
1851 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1852 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
1853 if (status < 0) {
1854 codec_dbg(codec, "write CHNLSTART reg fail\n");
1855 return status;
1856 }
1857 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
1858
1859 return status;
1860 }
1861
1862 /*
1863 * Stop the DSP DMA
1864 */
1865 static int dsp_dma_stop(struct hda_codec *codec,
1866 unsigned int dma_chan, bool ovly)
1867 {
1868 unsigned int reg = 0;
1869 int status = 0;
1870
1871 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
1872
1873 if (ovly) {
1874 status = chipio_read(codec,
1875 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1876
1877 if (status < 0) {
1878 codec_dbg(codec, "read CHNLSTART reg fail\n");
1879 return status;
1880 }
1881 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
1882 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1883 DSPDMAC_CHNLSTART_DIS_MASK);
1884 }
1885
1886 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1887 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
1888 if (status < 0) {
1889 codec_dbg(codec, "write CHNLSTART reg fail\n");
1890 return status;
1891 }
1892 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
1893
1894 return status;
1895 }
1896
1897 /**
1898 * Allocate router ports
1899 *
1900 * @codec: the HDA codec
1901 * @num_chans: number of channels in the stream
1902 * @ports_per_channel: number of ports per channel
1903 * @start_device: start device
1904 * @port_map: pointer to the port list to hold the allocated ports
1905 *
1906 * Returns zero or a negative error code.
1907 */
1908 static int dsp_allocate_router_ports(struct hda_codec *codec,
1909 unsigned int num_chans,
1910 unsigned int ports_per_channel,
1911 unsigned int start_device,
1912 unsigned int *port_map)
1913 {
1914 int status = 0;
1915 int res;
1916 u8 val;
1917
1918 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1919 if (status < 0)
1920 return status;
1921
1922 val = start_device << 6;
1923 val |= (ports_per_channel - 1) << 4;
1924 val |= num_chans - 1;
1925
1926 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1927 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
1928 val);
1929
1930 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1931 VENDOR_CHIPIO_PORT_ALLOC_SET,
1932 MEM_CONNID_DSP);
1933
1934 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1935 if (status < 0)
1936 return status;
1937
1938 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1939 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
1940
1941 *port_map = res;
1942
1943 return (res < 0) ? res : 0;
1944 }
1945
1946 /*
1947 * Free router ports
1948 */
1949 static int dsp_free_router_ports(struct hda_codec *codec)
1950 {
1951 int status = 0;
1952
1953 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1954 if (status < 0)
1955 return status;
1956
1957 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1958 VENDOR_CHIPIO_PORT_FREE_SET,
1959 MEM_CONNID_DSP);
1960
1961 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1962
1963 return status;
1964 }
1965
1966 /*
1967 * Allocate DSP ports for the download stream
1968 */
1969 static int dsp_allocate_ports(struct hda_codec *codec,
1970 unsigned int num_chans,
1971 unsigned int rate_multi, unsigned int *port_map)
1972 {
1973 int status;
1974
1975 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
1976
1977 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
1978 codec_dbg(codec, "bad rate multiple\n");
1979 return -EINVAL;
1980 }
1981
1982 status = dsp_allocate_router_ports(codec, num_chans,
1983 rate_multi, 0, port_map);
1984
1985 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
1986
1987 return status;
1988 }
1989
1990 static int dsp_allocate_ports_format(struct hda_codec *codec,
1991 const unsigned short fmt,
1992 unsigned int *port_map)
1993 {
1994 int status;
1995 unsigned int num_chans;
1996
1997 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
1998 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
1999 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2000
2001 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2002 codec_dbg(codec, "bad rate multiple\n");
2003 return -EINVAL;
2004 }
2005
2006 num_chans = get_hdafmt_chs(fmt) + 1;
2007
2008 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2009
2010 return status;
2011 }
2012
2013 /*
2014 * free DSP ports
2015 */
2016 static int dsp_free_ports(struct hda_codec *codec)
2017 {
2018 int status;
2019
2020 codec_dbg(codec, " dsp_free_ports() -- begin\n");
2021
2022 status = dsp_free_router_ports(codec);
2023 if (status < 0) {
2024 codec_dbg(codec, "free router ports fail\n");
2025 return status;
2026 }
2027 codec_dbg(codec, " dsp_free_ports() -- complete\n");
2028
2029 return status;
2030 }
2031
2032 /*
2033 * HDA DMA engine stuffs for DSP code download
2034 */
2035 struct dma_engine {
2036 struct hda_codec *codec;
2037 unsigned short m_converter_format;
2038 struct snd_dma_buffer *dmab;
2039 unsigned int buf_size;
2040 };
2041
2042
2043 enum dma_state {
2044 DMA_STATE_STOP = 0,
2045 DMA_STATE_RUN = 1
2046 };
2047
2048 static int dma_convert_to_hda_format(struct hda_codec *codec,
2049 unsigned int sample_rate,
2050 unsigned short channels,
2051 unsigned short *hda_format)
2052 {
2053 unsigned int format_val;
2054
2055 format_val = snd_hda_calc_stream_format(codec,
2056 sample_rate,
2057 channels,
2058 SNDRV_PCM_FORMAT_S32_LE,
2059 32, 0);
2060
2061 if (hda_format)
2062 *hda_format = (unsigned short)format_val;
2063
2064 return 0;
2065 }
2066
2067 /*
2068 * Reset DMA for DSP download
2069 */
2070 static int dma_reset(struct dma_engine *dma)
2071 {
2072 struct hda_codec *codec = dma->codec;
2073 struct ca0132_spec *spec = codec->spec;
2074 int status;
2075
2076 if (dma->dmab->area)
2077 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2078
2079 status = snd_hda_codec_load_dsp_prepare(codec,
2080 dma->m_converter_format,
2081 dma->buf_size,
2082 dma->dmab);
2083 if (status < 0)
2084 return status;
2085 spec->dsp_stream_id = status;
2086 return 0;
2087 }
2088
2089 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
2090 {
2091 bool cmd;
2092
2093 switch (state) {
2094 case DMA_STATE_STOP:
2095 cmd = false;
2096 break;
2097 case DMA_STATE_RUN:
2098 cmd = true;
2099 break;
2100 default:
2101 return 0;
2102 }
2103
2104 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2105 return 0;
2106 }
2107
2108 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2109 {
2110 return dma->dmab->bytes;
2111 }
2112
2113 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2114 {
2115 return dma->dmab->area;
2116 }
2117
2118 static int dma_xfer(struct dma_engine *dma,
2119 const unsigned int *data,
2120 unsigned int count)
2121 {
2122 memcpy(dma->dmab->area, data, count);
2123 return 0;
2124 }
2125
2126 static void dma_get_converter_format(
2127 struct dma_engine *dma,
2128 unsigned short *format)
2129 {
2130 if (format)
2131 *format = dma->m_converter_format;
2132 }
2133
2134 static unsigned int dma_get_stream_id(struct dma_engine *dma)
2135 {
2136 struct ca0132_spec *spec = dma->codec->spec;
2137
2138 return spec->dsp_stream_id;
2139 }
2140
2141 struct dsp_image_seg {
2142 u32 magic;
2143 u32 chip_addr;
2144 u32 count;
2145 u32 data[0];
2146 };
2147
2148 static const u32 g_magic_value = 0x4c46584d;
2149 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2150
2151 static bool is_valid(const struct dsp_image_seg *p)
2152 {
2153 return p->magic == g_magic_value;
2154 }
2155
2156 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2157 {
2158 return g_chip_addr_magic_value == p->chip_addr;
2159 }
2160
2161 static bool is_last(const struct dsp_image_seg *p)
2162 {
2163 return p->count == 0;
2164 }
2165
2166 static size_t dsp_sizeof(const struct dsp_image_seg *p)
2167 {
2168 return sizeof(*p) + p->count*sizeof(u32);
2169 }
2170
2171 static const struct dsp_image_seg *get_next_seg_ptr(
2172 const struct dsp_image_seg *p)
2173 {
2174 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
2175 }
2176
2177 /*
2178 * CA0132 chip DSP transfer stuffs. For DSP download.
2179 */
2180 #define INVALID_DMA_CHANNEL (~0U)
2181
2182 /*
2183 * Program a list of address/data pairs via the ChipIO widget.
2184 * The segment data is in the format of successive pairs of words.
2185 * These are repeated as indicated by the segment's count field.
2186 */
2187 static int dspxfr_hci_write(struct hda_codec *codec,
2188 const struct dsp_image_seg *fls)
2189 {
2190 int status;
2191 const u32 *data;
2192 unsigned int count;
2193
2194 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
2195 codec_dbg(codec, "hci_write invalid params\n");
2196 return -EINVAL;
2197 }
2198
2199 count = fls->count;
2200 data = (u32 *)(fls->data);
2201 while (count >= 2) {
2202 status = chipio_write(codec, data[0], data[1]);
2203 if (status < 0) {
2204 codec_dbg(codec, "hci_write chipio failed\n");
2205 return status;
2206 }
2207 count -= 2;
2208 data += 2;
2209 }
2210 return 0;
2211 }
2212
2213 /**
2214 * Write a block of data into DSP code or data RAM using pre-allocated
2215 * DMA engine.
2216 *
2217 * @codec: the HDA codec
2218 * @fls: pointer to a fast load image
2219 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2220 * no relocation
2221 * @dma_engine: pointer to DMA engine to be used for DSP download
2222 * @dma_chan: The number of DMA channels used for DSP download
2223 * @port_map_mask: port mapping
2224 * @ovly: TRUE if overlay format is required
2225 *
2226 * Returns zero or a negative error code.
2227 */
2228 static int dspxfr_one_seg(struct hda_codec *codec,
2229 const struct dsp_image_seg *fls,
2230 unsigned int reloc,
2231 struct dma_engine *dma_engine,
2232 unsigned int dma_chan,
2233 unsigned int port_map_mask,
2234 bool ovly)
2235 {
2236 int status = 0;
2237 bool comm_dma_setup_done = false;
2238 const unsigned int *data;
2239 unsigned int chip_addx;
2240 unsigned int words_to_write;
2241 unsigned int buffer_size_words;
2242 unsigned char *buffer_addx;
2243 unsigned short hda_format;
2244 unsigned int sample_rate_div;
2245 unsigned int sample_rate_mul;
2246 unsigned int num_chans;
2247 unsigned int hda_frame_size_words;
2248 unsigned int remainder_words;
2249 const u32 *data_remainder;
2250 u32 chip_addx_remainder;
2251 unsigned int run_size_words;
2252 const struct dsp_image_seg *hci_write = NULL;
2253 unsigned long timeout;
2254 bool dma_active;
2255
2256 if (fls == NULL)
2257 return -EINVAL;
2258 if (is_hci_prog_list_seg(fls)) {
2259 hci_write = fls;
2260 fls = get_next_seg_ptr(fls);
2261 }
2262
2263 if (hci_write && (!fls || is_last(fls))) {
2264 codec_dbg(codec, "hci_write\n");
2265 return dspxfr_hci_write(codec, hci_write);
2266 }
2267
2268 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
2269 codec_dbg(codec, "Invalid Params\n");
2270 return -EINVAL;
2271 }
2272
2273 data = fls->data;
2274 chip_addx = fls->chip_addr,
2275 words_to_write = fls->count;
2276
2277 if (!words_to_write)
2278 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2279 if (reloc)
2280 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2281
2282 if (!UC_RANGE(chip_addx, words_to_write) &&
2283 !X_RANGE_ALL(chip_addx, words_to_write) &&
2284 !Y_RANGE_ALL(chip_addx, words_to_write)) {
2285 codec_dbg(codec, "Invalid chip_addx Params\n");
2286 return -EINVAL;
2287 }
2288
2289 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2290 sizeof(u32);
2291
2292 buffer_addx = dma_get_buffer_addr(dma_engine);
2293
2294 if (buffer_addx == NULL) {
2295 codec_dbg(codec, "dma_engine buffer NULL\n");
2296 return -EINVAL;
2297 }
2298
2299 dma_get_converter_format(dma_engine, &hda_format);
2300 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2301 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2302 num_chans = get_hdafmt_chs(hda_format) + 1;
2303
2304 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2305 (num_chans * sample_rate_mul / sample_rate_div));
2306
2307 if (hda_frame_size_words == 0) {
2308 codec_dbg(codec, "frmsz zero\n");
2309 return -EINVAL;
2310 }
2311
2312 buffer_size_words = min(buffer_size_words,
2313 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2314 65536 : 32768));
2315 buffer_size_words -= buffer_size_words % hda_frame_size_words;
2316 codec_dbg(codec,
2317 "chpadr=0x%08x frmsz=%u nchan=%u "
2318 "rate_mul=%u div=%u bufsz=%u\n",
2319 chip_addx, hda_frame_size_words, num_chans,
2320 sample_rate_mul, sample_rate_div, buffer_size_words);
2321
2322 if (buffer_size_words < hda_frame_size_words) {
2323 codec_dbg(codec, "dspxfr_one_seg:failed\n");
2324 return -EINVAL;
2325 }
2326
2327 remainder_words = words_to_write % hda_frame_size_words;
2328 data_remainder = data;
2329 chip_addx_remainder = chip_addx;
2330
2331 data += remainder_words;
2332 chip_addx += remainder_words*sizeof(u32);
2333 words_to_write -= remainder_words;
2334
2335 while (words_to_write != 0) {
2336 run_size_words = min(buffer_size_words, words_to_write);
2337 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
2338 words_to_write, run_size_words, remainder_words);
2339 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2340 if (!comm_dma_setup_done) {
2341 status = dsp_dma_stop(codec, dma_chan, ovly);
2342 if (status < 0)
2343 return status;
2344 status = dsp_dma_setup_common(codec, chip_addx,
2345 dma_chan, port_map_mask, ovly);
2346 if (status < 0)
2347 return status;
2348 comm_dma_setup_done = true;
2349 }
2350
2351 status = dsp_dma_setup(codec, chip_addx,
2352 run_size_words, dma_chan);
2353 if (status < 0)
2354 return status;
2355 status = dsp_dma_start(codec, dma_chan, ovly);
2356 if (status < 0)
2357 return status;
2358 if (!dsp_is_dma_active(codec, dma_chan)) {
2359 codec_dbg(codec, "dspxfr:DMA did not start\n");
2360 return -EIO;
2361 }
2362 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2363 if (status < 0)
2364 return status;
2365 if (remainder_words != 0) {
2366 status = chipio_write_multiple(codec,
2367 chip_addx_remainder,
2368 data_remainder,
2369 remainder_words);
2370 if (status < 0)
2371 return status;
2372 remainder_words = 0;
2373 }
2374 if (hci_write) {
2375 status = dspxfr_hci_write(codec, hci_write);
2376 if (status < 0)
2377 return status;
2378 hci_write = NULL;
2379 }
2380
2381 timeout = jiffies + msecs_to_jiffies(2000);
2382 do {
2383 dma_active = dsp_is_dma_active(codec, dma_chan);
2384 if (!dma_active)
2385 break;
2386 msleep(20);
2387 } while (time_before(jiffies, timeout));
2388 if (dma_active)
2389 break;
2390
2391 codec_dbg(codec, "+++++ DMA complete\n");
2392 dma_set_state(dma_engine, DMA_STATE_STOP);
2393 status = dma_reset(dma_engine);
2394
2395 if (status < 0)
2396 return status;
2397
2398 data += run_size_words;
2399 chip_addx += run_size_words*sizeof(u32);
2400 words_to_write -= run_size_words;
2401 }
2402
2403 if (remainder_words != 0) {
2404 status = chipio_write_multiple(codec, chip_addx_remainder,
2405 data_remainder, remainder_words);
2406 }
2407
2408 return status;
2409 }
2410
2411 /**
2412 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2413 *
2414 * @codec: the HDA codec
2415 * @fls_data: pointer to a fast load image
2416 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2417 * no relocation
2418 * @sample_rate: sampling rate of the stream used for DSP download
2419 * @channels: channels of the stream used for DSP download
2420 * @ovly: TRUE if overlay format is required
2421 *
2422 * Returns zero or a negative error code.
2423 */
2424 static int dspxfr_image(struct hda_codec *codec,
2425 const struct dsp_image_seg *fls_data,
2426 unsigned int reloc,
2427 unsigned int sample_rate,
2428 unsigned short channels,
2429 bool ovly)
2430 {
2431 struct ca0132_spec *spec = codec->spec;
2432 int status;
2433 unsigned short hda_format = 0;
2434 unsigned int response;
2435 unsigned char stream_id = 0;
2436 struct dma_engine *dma_engine;
2437 unsigned int dma_chan;
2438 unsigned int port_map_mask;
2439
2440 if (fls_data == NULL)
2441 return -EINVAL;
2442
2443 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
2444 if (!dma_engine)
2445 return -ENOMEM;
2446
2447 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2448 if (!dma_engine->dmab) {
2449 kfree(dma_engine);
2450 return -ENOMEM;
2451 }
2452
2453 dma_engine->codec = codec;
2454 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
2455 dma_engine->m_converter_format = hda_format;
2456 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2457 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2458
2459 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
2460
2461 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2462 hda_format, &response);
2463
2464 if (status < 0) {
2465 codec_dbg(codec, "set converter format fail\n");
2466 goto exit;
2467 }
2468
2469 status = snd_hda_codec_load_dsp_prepare(codec,
2470 dma_engine->m_converter_format,
2471 dma_engine->buf_size,
2472 dma_engine->dmab);
2473 if (status < 0)
2474 goto exit;
2475 spec->dsp_stream_id = status;
2476
2477 if (ovly) {
2478 status = dspio_alloc_dma_chan(codec, &dma_chan);
2479 if (status < 0) {
2480 codec_dbg(codec, "alloc dmachan fail\n");
2481 dma_chan = INVALID_DMA_CHANNEL;
2482 goto exit;
2483 }
2484 }
2485
2486 port_map_mask = 0;
2487 status = dsp_allocate_ports_format(codec, hda_format,
2488 &port_map_mask);
2489 if (status < 0) {
2490 codec_dbg(codec, "alloc ports fail\n");
2491 goto exit;
2492 }
2493
2494 stream_id = dma_get_stream_id(dma_engine);
2495 status = codec_set_converter_stream_channel(codec,
2496 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2497 if (status < 0) {
2498 codec_dbg(codec, "set stream chan fail\n");
2499 goto exit;
2500 }
2501
2502 while ((fls_data != NULL) && !is_last(fls_data)) {
2503 if (!is_valid(fls_data)) {
2504 codec_dbg(codec, "FLS check fail\n");
2505 status = -EINVAL;
2506 goto exit;
2507 }
2508 status = dspxfr_one_seg(codec, fls_data, reloc,
2509 dma_engine, dma_chan,
2510 port_map_mask, ovly);
2511 if (status < 0)
2512 break;
2513
2514 if (is_hci_prog_list_seg(fls_data))
2515 fls_data = get_next_seg_ptr(fls_data);
2516
2517 if ((fls_data != NULL) && !is_last(fls_data))
2518 fls_data = get_next_seg_ptr(fls_data);
2519 }
2520
2521 if (port_map_mask != 0)
2522 status = dsp_free_ports(codec);
2523
2524 if (status < 0)
2525 goto exit;
2526
2527 status = codec_set_converter_stream_channel(codec,
2528 WIDGET_CHIP_CTRL, 0, 0, &response);
2529
2530 exit:
2531 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2532 dspio_free_dma_chan(codec, dma_chan);
2533
2534 if (dma_engine->dmab->area)
2535 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2536 kfree(dma_engine->dmab);
2537 kfree(dma_engine);
2538
2539 return status;
2540 }
2541
2542 /*
2543 * CA0132 DSP download stuffs.
2544 */
2545 static void dspload_post_setup(struct hda_codec *codec)
2546 {
2547 codec_dbg(codec, "---- dspload_post_setup ------\n");
2548
2549 /*set DSP speaker to 2.0 configuration*/
2550 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2551 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
2552
2553 /*update write pointer*/
2554 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2555 }
2556
2557 /**
2558 * dspload_image - Download DSP from a DSP Image Fast Load structure.
2559 *
2560 * @codec: the HDA codec
2561 * @fls: pointer to a fast load image
2562 * @ovly: TRUE if overlay format is required
2563 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2564 * no relocation
2565 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2566 * @router_chans: number of audio router channels to be allocated (0 means use
2567 * internal defaults; max is 32)
2568 *
2569 * Download DSP from a DSP Image Fast Load structure. This structure is a
2570 * linear, non-constant sized element array of structures, each of which
2571 * contain the count of the data to be loaded, the data itself, and the
2572 * corresponding starting chip address of the starting data location.
2573 * Returns zero or a negative error code.
2574 */
2575 static int dspload_image(struct hda_codec *codec,
2576 const struct dsp_image_seg *fls,
2577 bool ovly,
2578 unsigned int reloc,
2579 bool autostart,
2580 int router_chans)
2581 {
2582 int status = 0;
2583 unsigned int sample_rate;
2584 unsigned short channels;
2585
2586 codec_dbg(codec, "---- dspload_image begin ------\n");
2587 if (router_chans == 0) {
2588 if (!ovly)
2589 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
2590 else
2591 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
2592 }
2593
2594 sample_rate = 48000;
2595 channels = (unsigned short)router_chans;
2596
2597 while (channels > 16) {
2598 sample_rate *= 2;
2599 channels /= 2;
2600 }
2601
2602 do {
2603 codec_dbg(codec, "Ready to program DMA\n");
2604 if (!ovly)
2605 status = dsp_reset(codec);
2606
2607 if (status < 0)
2608 break;
2609
2610 codec_dbg(codec, "dsp_reset() complete\n");
2611 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
2612 ovly);
2613
2614 if (status < 0)
2615 break;
2616
2617 codec_dbg(codec, "dspxfr_image() complete\n");
2618 if (autostart && !ovly) {
2619 dspload_post_setup(codec);
2620 status = dsp_set_run_state(codec);
2621 }
2622
2623 codec_dbg(codec, "LOAD FINISHED\n");
2624 } while (0);
2625
2626 return status;
2627 }
2628
2629 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
2630 static bool dspload_is_loaded(struct hda_codec *codec)
2631 {
2632 unsigned int data = 0;
2633 int status = 0;
2634
2635 status = chipio_read(codec, 0x40004, &data);
2636 if ((status < 0) || (data != 1))
2637 return false;
2638
2639 return true;
2640 }
2641 #else
2642 #define dspload_is_loaded(codec) false
2643 #endif
2644
2645 static bool dspload_wait_loaded(struct hda_codec *codec)
2646 {
2647 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
2648
2649 do {
2650 if (dspload_is_loaded(codec)) {
2651 pr_info("ca0132 DOWNLOAD OK :-) DSP IS RUNNING.\n");
2652 return true;
2653 }
2654 msleep(20);
2655 } while (time_before(jiffies, timeout));
2656
2657 pr_err("ca0132 DOWNLOAD FAILED!!! DSP IS NOT RUNNING.\n");
2658 return false;
2659 }
2660
2661 /*
2662 * PCM callbacks
2663 */
2664 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2665 struct hda_codec *codec,
2666 unsigned int stream_tag,
2667 unsigned int format,
2668 struct snd_pcm_substream *substream)
2669 {
2670 struct ca0132_spec *spec = codec->spec;
2671
2672 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
2673
2674 return 0;
2675 }
2676
2677 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2678 struct hda_codec *codec,
2679 struct snd_pcm_substream *substream)
2680 {
2681 struct ca0132_spec *spec = codec->spec;
2682
2683 if (spec->dsp_state == DSP_DOWNLOADING)
2684 return 0;
2685
2686 /*If Playback effects are on, allow stream some time to flush
2687 *effects tail*/
2688 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
2689 msleep(50);
2690
2691 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
2692
2693 return 0;
2694 }
2695
2696 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
2697 struct hda_codec *codec,
2698 struct snd_pcm_substream *substream)
2699 {
2700 struct ca0132_spec *spec = codec->spec;
2701 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
2702 struct snd_pcm_runtime *runtime = substream->runtime;
2703
2704 if (spec->dsp_state != DSP_DOWNLOADED)
2705 return 0;
2706
2707 /* Add latency if playback enhancement and either effect is enabled. */
2708 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
2709 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
2710 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
2711 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
2712 }
2713
2714 /* Applying Speaker EQ adds latency as well. */
2715 if (spec->cur_out_type == SPEAKER_OUT)
2716 latency += DSP_SPEAKER_OUT_LATENCY;
2717
2718 return (latency * runtime->rate) / 1000;
2719 }
2720
2721 /*
2722 * Digital out
2723 */
2724 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
2725 struct hda_codec *codec,
2726 struct snd_pcm_substream *substream)
2727 {
2728 struct ca0132_spec *spec = codec->spec;
2729 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2730 }
2731
2732 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2733 struct hda_codec *codec,
2734 unsigned int stream_tag,
2735 unsigned int format,
2736 struct snd_pcm_substream *substream)
2737 {
2738 struct ca0132_spec *spec = codec->spec;
2739 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2740 stream_tag, format, substream);
2741 }
2742
2743 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2744 struct hda_codec *codec,
2745 struct snd_pcm_substream *substream)
2746 {
2747 struct ca0132_spec *spec = codec->spec;
2748 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
2749 }
2750
2751 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
2752 struct hda_codec *codec,
2753 struct snd_pcm_substream *substream)
2754 {
2755 struct ca0132_spec *spec = codec->spec;
2756 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2757 }
2758
2759 /*
2760 * Analog capture
2761 */
2762 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
2763 struct hda_codec *codec,
2764 unsigned int stream_tag,
2765 unsigned int format,
2766 struct snd_pcm_substream *substream)
2767 {
2768 snd_hda_codec_setup_stream(codec, hinfo->nid,
2769 stream_tag, 0, format);
2770
2771 return 0;
2772 }
2773
2774 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
2775 struct hda_codec *codec,
2776 struct snd_pcm_substream *substream)
2777 {
2778 struct ca0132_spec *spec = codec->spec;
2779
2780 if (spec->dsp_state == DSP_DOWNLOADING)
2781 return 0;
2782
2783 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
2784 return 0;
2785 }
2786
2787 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
2788 struct hda_codec *codec,
2789 struct snd_pcm_substream *substream)
2790 {
2791 struct ca0132_spec *spec = codec->spec;
2792 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
2793 struct snd_pcm_runtime *runtime = substream->runtime;
2794
2795 if (spec->dsp_state != DSP_DOWNLOADED)
2796 return 0;
2797
2798 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
2799 latency += DSP_CRYSTAL_VOICE_LATENCY;
2800
2801 return (latency * runtime->rate) / 1000;
2802 }
2803
2804 /*
2805 * Controls stuffs.
2806 */
2807
2808 /*
2809 * Mixer controls helpers.
2810 */
2811 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
2812 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2813 .name = xname, \
2814 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2815 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2816 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
2817 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
2818 .info = ca0132_volume_info, \
2819 .get = ca0132_volume_get, \
2820 .put = ca0132_volume_put, \
2821 .tlv = { .c = ca0132_volume_tlv }, \
2822 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2823
2824 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
2825 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2826 .name = xname, \
2827 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2828 .info = snd_hda_mixer_amp_switch_info, \
2829 .get = ca0132_switch_get, \
2830 .put = ca0132_switch_put, \
2831 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2832
2833 /* stereo */
2834 #define CA0132_CODEC_VOL(xname, nid, dir) \
2835 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
2836 #define CA0132_CODEC_MUTE(xname, nid, dir) \
2837 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
2838
2839 /* The followings are for tuning of products */
2840 #ifdef ENABLE_TUNING_CONTROLS
2841
2842 static unsigned int voice_focus_vals_lookup[] = {
2843 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
2844 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
2845 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
2846 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
2847 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
2848 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
2849 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
2850 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
2851 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
2852 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
2853 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
2854 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
2855 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
2856 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
2857 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
2858 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
2859 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
2860 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
2861 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
2862 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
2863 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
2864 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
2865 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
2866 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
2867 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
2868 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
2869 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
2870 };
2871
2872 static unsigned int mic_svm_vals_lookup[] = {
2873 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
2874 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
2875 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
2876 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
2877 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
2878 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
2879 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
2880 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
2881 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
2882 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
2883 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
2884 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
2885 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
2886 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
2887 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
2888 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
2889 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
2890 };
2891
2892 static unsigned int equalizer_vals_lookup[] = {
2893 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
2894 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
2895 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
2896 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
2897 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
2898 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
2899 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
2900 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
2901 0x41C00000
2902 };
2903
2904 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
2905 unsigned int *lookup, int idx)
2906 {
2907 int i = 0;
2908
2909 for (i = 0; i < TUNING_CTLS_COUNT; i++)
2910 if (nid == ca0132_tuning_ctls[i].nid)
2911 break;
2912
2913 snd_hda_power_up(codec);
2914 dspio_set_param(codec, ca0132_tuning_ctls[i].mid,
2915 ca0132_tuning_ctls[i].req,
2916 &(lookup[idx]), sizeof(unsigned int));
2917 snd_hda_power_down(codec);
2918
2919 return 1;
2920 }
2921
2922 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
2923 struct snd_ctl_elem_value *ucontrol)
2924 {
2925 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2926 struct ca0132_spec *spec = codec->spec;
2927 hda_nid_t nid = get_amp_nid(kcontrol);
2928 long *valp = ucontrol->value.integer.value;
2929 int idx = nid - TUNING_CTL_START_NID;
2930
2931 *valp = spec->cur_ctl_vals[idx];
2932 return 0;
2933 }
2934
2935 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
2936 struct snd_ctl_elem_info *uinfo)
2937 {
2938 int chs = get_amp_channels(kcontrol);
2939 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2940 uinfo->count = chs == 3 ? 2 : 1;
2941 uinfo->value.integer.min = 20;
2942 uinfo->value.integer.max = 180;
2943 uinfo->value.integer.step = 1;
2944
2945 return 0;
2946 }
2947
2948 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
2949 struct snd_ctl_elem_value *ucontrol)
2950 {
2951 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2952 struct ca0132_spec *spec = codec->spec;
2953 hda_nid_t nid = get_amp_nid(kcontrol);
2954 long *valp = ucontrol->value.integer.value;
2955 int idx;
2956
2957 idx = nid - TUNING_CTL_START_NID;
2958 /* any change? */
2959 if (spec->cur_ctl_vals[idx] == *valp)
2960 return 0;
2961
2962 spec->cur_ctl_vals[idx] = *valp;
2963
2964 idx = *valp - 20;
2965 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
2966
2967 return 1;
2968 }
2969
2970 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
2971 struct snd_ctl_elem_info *uinfo)
2972 {
2973 int chs = get_amp_channels(kcontrol);
2974 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2975 uinfo->count = chs == 3 ? 2 : 1;
2976 uinfo->value.integer.min = 0;
2977 uinfo->value.integer.max = 100;
2978 uinfo->value.integer.step = 1;
2979
2980 return 0;
2981 }
2982
2983 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
2984 struct snd_ctl_elem_value *ucontrol)
2985 {
2986 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2987 struct ca0132_spec *spec = codec->spec;
2988 hda_nid_t nid = get_amp_nid(kcontrol);
2989 long *valp = ucontrol->value.integer.value;
2990 int idx;
2991
2992 idx = nid - TUNING_CTL_START_NID;
2993 /* any change? */
2994 if (spec->cur_ctl_vals[idx] == *valp)
2995 return 0;
2996
2997 spec->cur_ctl_vals[idx] = *valp;
2998
2999 idx = *valp;
3000 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3001
3002 return 0;
3003 }
3004
3005 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3006 struct snd_ctl_elem_info *uinfo)
3007 {
3008 int chs = get_amp_channels(kcontrol);
3009 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3010 uinfo->count = chs == 3 ? 2 : 1;
3011 uinfo->value.integer.min = 0;
3012 uinfo->value.integer.max = 48;
3013 uinfo->value.integer.step = 1;
3014
3015 return 0;
3016 }
3017
3018 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3019 struct snd_ctl_elem_value *ucontrol)
3020 {
3021 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3022 struct ca0132_spec *spec = codec->spec;
3023 hda_nid_t nid = get_amp_nid(kcontrol);
3024 long *valp = ucontrol->value.integer.value;
3025 int idx;
3026
3027 idx = nid - TUNING_CTL_START_NID;
3028 /* any change? */
3029 if (spec->cur_ctl_vals[idx] == *valp)
3030 return 0;
3031
3032 spec->cur_ctl_vals[idx] = *valp;
3033
3034 idx = *valp;
3035 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3036
3037 return 1;
3038 }
3039
3040 static const DECLARE_TLV_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3041 static const DECLARE_TLV_DB_SCALE(eq_db_scale, -2400, 100, 0);
3042
3043 static int add_tuning_control(struct hda_codec *codec,
3044 hda_nid_t pnid, hda_nid_t nid,
3045 const char *name, int dir)
3046 {
3047 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3048 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3049 struct snd_kcontrol_new knew =
3050 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3051
3052 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3053 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3054 knew.tlv.c = 0;
3055 knew.tlv.p = 0;
3056 switch (pnid) {
3057 case VOICE_FOCUS:
3058 knew.info = voice_focus_ctl_info;
3059 knew.get = tuning_ctl_get;
3060 knew.put = voice_focus_ctl_put;
3061 knew.tlv.p = voice_focus_db_scale;
3062 break;
3063 case MIC_SVM:
3064 knew.info = mic_svm_ctl_info;
3065 knew.get = tuning_ctl_get;
3066 knew.put = mic_svm_ctl_put;
3067 break;
3068 case EQUALIZER:
3069 knew.info = equalizer_ctl_info;
3070 knew.get = tuning_ctl_get;
3071 knew.put = equalizer_ctl_put;
3072 knew.tlv.p = eq_db_scale;
3073 break;
3074 default:
3075 return 0;
3076 }
3077 knew.private_value =
3078 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3079 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3080 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3081 }
3082
3083 static int add_tuning_ctls(struct hda_codec *codec)
3084 {
3085 int i;
3086 int err;
3087
3088 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3089 err = add_tuning_control(codec,
3090 ca0132_tuning_ctls[i].parent_nid,
3091 ca0132_tuning_ctls[i].nid,
3092 ca0132_tuning_ctls[i].name,
3093 ca0132_tuning_ctls[i].direct);
3094 if (err < 0)
3095 return err;
3096 }
3097
3098 return 0;
3099 }
3100
3101 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3102 {
3103 struct ca0132_spec *spec = codec->spec;
3104 int i;
3105
3106 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
3107 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3108 /* SVM level defaults to 0.74. */
3109 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3110
3111 /* EQ defaults to 0dB. */
3112 for (i = 2; i < TUNING_CTLS_COUNT; i++)
3113 spec->cur_ctl_vals[i] = 24;
3114 }
3115 #endif /*ENABLE_TUNING_CONTROLS*/
3116
3117 /*
3118 * Select the active output.
3119 * If autodetect is enabled, output will be selected based on jack detection.
3120 * If jack inserted, headphone will be selected, else built-in speakers
3121 * If autodetect is disabled, output will be selected based on selection.
3122 */
3123 static int ca0132_select_out(struct hda_codec *codec)
3124 {
3125 struct ca0132_spec *spec = codec->spec;
3126 unsigned int pin_ctl;
3127 int jack_present;
3128 int auto_jack;
3129 unsigned int tmp;
3130 int err;
3131
3132 codec_dbg(codec, "ca0132_select_out\n");
3133
3134 snd_hda_power_up_pm(codec);
3135
3136 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3137
3138 if (auto_jack)
3139 jack_present = snd_hda_jack_detect(codec, spec->out_pins[1]);
3140 else
3141 jack_present =
3142 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3143
3144 if (jack_present)
3145 spec->cur_out_type = HEADPHONE_OUT;
3146 else
3147 spec->cur_out_type = SPEAKER_OUT;
3148
3149 if (spec->cur_out_type == SPEAKER_OUT) {
3150 codec_dbg(codec, "ca0132_select_out speaker\n");
3151 /*speaker out config*/
3152 tmp = FLOAT_ONE;
3153 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3154 if (err < 0)
3155 goto exit;
3156 /*enable speaker EQ*/
3157 tmp = FLOAT_ONE;
3158 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3159 if (err < 0)
3160 goto exit;
3161
3162 /* Setup EAPD */
3163 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3164 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3165 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3166 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3167 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3168 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3169 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3170 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3171
3172 /* disable headphone node */
3173 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3174 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3175 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3176 pin_ctl & ~PIN_HP);
3177 /* enable speaker node */
3178 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3179 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3180 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3181 pin_ctl | PIN_OUT);
3182 } else {
3183 codec_dbg(codec, "ca0132_select_out hp\n");
3184 /*headphone out config*/
3185 tmp = FLOAT_ZERO;
3186 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3187 if (err < 0)
3188 goto exit;
3189 /*disable speaker EQ*/
3190 tmp = FLOAT_ZERO;
3191 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3192 if (err < 0)
3193 goto exit;
3194
3195 /* Setup EAPD */
3196 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3197 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3198 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3199 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3200 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3201 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3202 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3203 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3204
3205 /* disable speaker*/
3206 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3207 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3208 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3209 pin_ctl & ~PIN_HP);
3210 /* enable headphone*/
3211 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3212 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3213 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3214 pin_ctl | PIN_HP);
3215 }
3216
3217 exit:
3218 snd_hda_power_down_pm(codec);
3219
3220 return err < 0 ? err : 0;
3221 }
3222
3223 static void ca0132_unsol_hp_delayed(struct work_struct *work)
3224 {
3225 struct ca0132_spec *spec = container_of(
3226 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
3227 struct hda_jack_tbl *jack;
3228
3229 ca0132_select_out(spec->codec);
3230 jack = snd_hda_jack_tbl_get(spec->codec, UNSOL_TAG_HP);
3231 if (jack) {
3232 jack->block_report = 0;
3233 snd_hda_jack_report_sync(spec->codec);
3234 }
3235 }
3236
3237 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
3238 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
3239 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
3240
3241 /*
3242 * Select the active VIP source
3243 */
3244 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
3245 {
3246 struct ca0132_spec *spec = codec->spec;
3247 unsigned int tmp;
3248
3249 if (spec->dsp_state != DSP_DOWNLOADED)
3250 return 0;
3251
3252 /* if CrystalVoice if off, vipsource should be 0 */
3253 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
3254 (val == 0)) {
3255 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
3256 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
3257 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
3258 if (spec->cur_mic_type == DIGITAL_MIC)
3259 tmp = FLOAT_TWO;
3260 else
3261 tmp = FLOAT_ONE;
3262 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3263 tmp = FLOAT_ZERO;
3264 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3265 } else {
3266 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
3267 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
3268 if (spec->cur_mic_type == DIGITAL_MIC)
3269 tmp = FLOAT_TWO;
3270 else
3271 tmp = FLOAT_ONE;
3272 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3273 tmp = FLOAT_ONE;
3274 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3275 msleep(20);
3276 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
3277 }
3278
3279 return 1;
3280 }
3281
3282 /*
3283 * Select the active microphone.
3284 * If autodetect is enabled, mic will be selected based on jack detection.
3285 * If jack inserted, ext.mic will be selected, else built-in mic
3286 * If autodetect is disabled, mic will be selected based on selection.
3287 */
3288 static int ca0132_select_mic(struct hda_codec *codec)
3289 {
3290 struct ca0132_spec *spec = codec->spec;
3291 int jack_present;
3292 int auto_jack;
3293
3294 codec_dbg(codec, "ca0132_select_mic\n");
3295
3296 snd_hda_power_up_pm(codec);
3297
3298 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3299
3300 if (auto_jack)
3301 jack_present = snd_hda_jack_detect(codec, spec->input_pins[0]);
3302 else
3303 jack_present =
3304 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
3305
3306 if (jack_present)
3307 spec->cur_mic_type = LINE_MIC_IN;
3308 else
3309 spec->cur_mic_type = DIGITAL_MIC;
3310
3311 if (spec->cur_mic_type == DIGITAL_MIC) {
3312 /* enable digital Mic */
3313 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
3314 ca0132_set_dmic(codec, 1);
3315 ca0132_mic_boost_set(codec, 0);
3316 /* set voice focus */
3317 ca0132_effects_set(codec, VOICE_FOCUS,
3318 spec->effects_switch
3319 [VOICE_FOCUS - EFFECT_START_NID]);
3320 } else {
3321 /* disable digital Mic */
3322 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
3323 ca0132_set_dmic(codec, 0);
3324 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
3325 /* disable voice focus */
3326 ca0132_effects_set(codec, VOICE_FOCUS, 0);
3327 }
3328
3329 snd_hda_power_down_pm(codec);
3330
3331 return 0;
3332 }
3333
3334 /*
3335 * Check if VNODE settings take effect immediately.
3336 */
3337 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
3338 hda_nid_t vnid,
3339 hda_nid_t *shared_nid)
3340 {
3341 struct ca0132_spec *spec = codec->spec;
3342 hda_nid_t nid;
3343
3344 switch (vnid) {
3345 case VNID_SPK:
3346 nid = spec->shared_out_nid;
3347 break;
3348 case VNID_MIC:
3349 nid = spec->shared_mic_nid;
3350 break;
3351 default:
3352 return false;
3353 }
3354
3355 if (shared_nid)
3356 *shared_nid = nid;
3357
3358 return true;
3359 }
3360
3361 /*
3362 * The following functions are control change helpers.
3363 * They return 0 if no changed. Return 1 if changed.
3364 */
3365 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
3366 {
3367 struct ca0132_spec *spec = codec->spec;
3368 unsigned int tmp;
3369
3370 /* based on CrystalVoice state to enable VoiceFX. */
3371 if (enable) {
3372 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
3373 FLOAT_ONE : FLOAT_ZERO;
3374 } else {
3375 tmp = FLOAT_ZERO;
3376 }
3377
3378 dspio_set_uint_param(codec, ca0132_voicefx.mid,
3379 ca0132_voicefx.reqs[0], tmp);
3380
3381 return 1;
3382 }
3383
3384 /*
3385 * Set the effects parameters
3386 */
3387 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
3388 {
3389 struct ca0132_spec *spec = codec->spec;
3390 unsigned int on;
3391 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3392 int err = 0;
3393 int idx = nid - EFFECT_START_NID;
3394
3395 if ((idx < 0) || (idx >= num_fx))
3396 return 0; /* no changed */
3397
3398 /* for out effect, qualify with PE */
3399 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
3400 /* if PE if off, turn off out effects. */
3401 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3402 val = 0;
3403 }
3404
3405 /* for in effect, qualify with CrystalVoice */
3406 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
3407 /* if CrystalVoice if off, turn off in effects. */
3408 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3409 val = 0;
3410
3411 /* Voice Focus applies to 2-ch Mic, Digital Mic */
3412 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
3413 val = 0;
3414 }
3415
3416 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
3417 nid, val);
3418
3419 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
3420 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
3421 ca0132_effects[idx].reqs[0], on);
3422
3423 if (err < 0)
3424 return 0; /* no changed */
3425
3426 return 1;
3427 }
3428
3429 /*
3430 * Turn on/off Playback Enhancements
3431 */
3432 static int ca0132_pe_switch_set(struct hda_codec *codec)
3433 {
3434 struct ca0132_spec *spec = codec->spec;
3435 hda_nid_t nid;
3436 int i, ret = 0;
3437
3438 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
3439 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
3440
3441 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
3442 nid = OUT_EFFECT_START_NID;
3443 /* PE affects all out effects */
3444 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
3445 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3446
3447 return ret;
3448 }
3449
3450 /* Check if Mic1 is streaming, if so, stop streaming */
3451 static int stop_mic1(struct hda_codec *codec)
3452 {
3453 struct ca0132_spec *spec = codec->spec;
3454 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
3455 AC_VERB_GET_CONV, 0);
3456 if (oldval != 0)
3457 snd_hda_codec_write(codec, spec->adcs[0], 0,
3458 AC_VERB_SET_CHANNEL_STREAMID,
3459 0);
3460 return oldval;
3461 }
3462
3463 /* Resume Mic1 streaming if it was stopped. */
3464 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
3465 {
3466 struct ca0132_spec *spec = codec->spec;
3467 /* Restore the previous stream and channel */
3468 if (oldval != 0)
3469 snd_hda_codec_write(codec, spec->adcs[0], 0,
3470 AC_VERB_SET_CHANNEL_STREAMID,
3471 oldval);
3472 }
3473
3474 /*
3475 * Turn on/off CrystalVoice
3476 */
3477 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
3478 {
3479 struct ca0132_spec *spec = codec->spec;
3480 hda_nid_t nid;
3481 int i, ret = 0;
3482 unsigned int oldval;
3483
3484 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
3485 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
3486
3487 i = IN_EFFECT_START_NID - EFFECT_START_NID;
3488 nid = IN_EFFECT_START_NID;
3489 /* CrystalVoice affects all in effects */
3490 for (; nid < IN_EFFECT_END_NID; nid++, i++)
3491 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3492
3493 /* including VoiceFX */
3494 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
3495
3496 /* set correct vipsource */
3497 oldval = stop_mic1(codec);
3498 ret |= ca0132_set_vipsource(codec, 1);
3499 resume_mic1(codec, oldval);
3500 return ret;
3501 }
3502
3503 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
3504 {
3505 struct ca0132_spec *spec = codec->spec;
3506 int ret = 0;
3507
3508 if (val) /* on */
3509 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3510 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
3511 else /* off */
3512 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3513 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
3514
3515 return ret;
3516 }
3517
3518 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
3519 struct snd_ctl_elem_value *ucontrol)
3520 {
3521 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3522 hda_nid_t nid = get_amp_nid(kcontrol);
3523 hda_nid_t shared_nid = 0;
3524 bool effective;
3525 int ret = 0;
3526 struct ca0132_spec *spec = codec->spec;
3527 int auto_jack;
3528
3529 if (nid == VNID_HP_SEL) {
3530 auto_jack =
3531 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3532 if (!auto_jack)
3533 ca0132_select_out(codec);
3534 return 1;
3535 }
3536
3537 if (nid == VNID_AMIC1_SEL) {
3538 auto_jack =
3539 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3540 if (!auto_jack)
3541 ca0132_select_mic(codec);
3542 return 1;
3543 }
3544
3545 if (nid == VNID_HP_ASEL) {
3546 ca0132_select_out(codec);
3547 return 1;
3548 }
3549
3550 if (nid == VNID_AMIC1_ASEL) {
3551 ca0132_select_mic(codec);
3552 return 1;
3553 }
3554
3555 /* if effective conditions, then update hw immediately. */
3556 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3557 if (effective) {
3558 int dir = get_amp_direction(kcontrol);
3559 int ch = get_amp_channels(kcontrol);
3560 unsigned long pval;
3561
3562 mutex_lock(&codec->control_mutex);
3563 pval = kcontrol->private_value;
3564 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3565 0, dir);
3566 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
3567 kcontrol->private_value = pval;
3568 mutex_unlock(&codec->control_mutex);
3569 }
3570
3571 return ret;
3572 }
3573 /* End of control change helpers. */
3574
3575 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
3576 struct snd_ctl_elem_info *uinfo)
3577 {
3578 unsigned int items = sizeof(ca0132_voicefx_presets)
3579 / sizeof(struct ct_voicefx_preset);
3580
3581 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3582 uinfo->count = 1;
3583 uinfo->value.enumerated.items = items;
3584 if (uinfo->value.enumerated.item >= items)
3585 uinfo->value.enumerated.item = items - 1;
3586 strcpy(uinfo->value.enumerated.name,
3587 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
3588 return 0;
3589 }
3590
3591 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
3592 struct snd_ctl_elem_value *ucontrol)
3593 {
3594 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3595 struct ca0132_spec *spec = codec->spec;
3596
3597 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
3598 return 0;
3599 }
3600
3601 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
3602 struct snd_ctl_elem_value *ucontrol)
3603 {
3604 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3605 struct ca0132_spec *spec = codec->spec;
3606 int i, err = 0;
3607 int sel = ucontrol->value.enumerated.item[0];
3608 unsigned int items = sizeof(ca0132_voicefx_presets)
3609 / sizeof(struct ct_voicefx_preset);
3610
3611 if (sel >= items)
3612 return 0;
3613
3614 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
3615 sel, ca0132_voicefx_presets[sel].name);
3616
3617 /*
3618 * Idx 0 is default.
3619 * Default needs to qualify with CrystalVoice state.
3620 */
3621 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
3622 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
3623 ca0132_voicefx.reqs[i],
3624 ca0132_voicefx_presets[sel].vals[i]);
3625 if (err < 0)
3626 break;
3627 }
3628
3629 if (err >= 0) {
3630 spec->voicefx_val = sel;
3631 /* enable voice fx */
3632 ca0132_voicefx_set(codec, (sel ? 1 : 0));
3633 }
3634
3635 return 1;
3636 }
3637
3638 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
3639 struct snd_ctl_elem_value *ucontrol)
3640 {
3641 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3642 struct ca0132_spec *spec = codec->spec;
3643 hda_nid_t nid = get_amp_nid(kcontrol);
3644 int ch = get_amp_channels(kcontrol);
3645 long *valp = ucontrol->value.integer.value;
3646
3647 /* vnode */
3648 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3649 if (ch & 1) {
3650 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
3651 valp++;
3652 }
3653 if (ch & 2) {
3654 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
3655 valp++;
3656 }
3657 return 0;
3658 }
3659
3660 /* effects, include PE and CrystalVoice */
3661 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
3662 *valp = spec->effects_switch[nid - EFFECT_START_NID];
3663 return 0;
3664 }
3665
3666 /* mic boost */
3667 if (nid == spec->input_pins[0]) {
3668 *valp = spec->cur_mic_boost;
3669 return 0;
3670 }
3671
3672 return 0;
3673 }
3674
3675 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
3676 struct snd_ctl_elem_value *ucontrol)
3677 {
3678 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3679 struct ca0132_spec *spec = codec->spec;
3680 hda_nid_t nid = get_amp_nid(kcontrol);
3681 int ch = get_amp_channels(kcontrol);
3682 long *valp = ucontrol->value.integer.value;
3683 int changed = 1;
3684
3685 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
3686 nid, *valp);
3687
3688 snd_hda_power_up(codec);
3689 /* vnode */
3690 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3691 if (ch & 1) {
3692 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
3693 valp++;
3694 }
3695 if (ch & 2) {
3696 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
3697 valp++;
3698 }
3699 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
3700 goto exit;
3701 }
3702
3703 /* PE */
3704 if (nid == PLAY_ENHANCEMENT) {
3705 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3706 changed = ca0132_pe_switch_set(codec);
3707 goto exit;
3708 }
3709
3710 /* CrystalVoice */
3711 if (nid == CRYSTAL_VOICE) {
3712 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3713 changed = ca0132_cvoice_switch_set(codec);
3714 goto exit;
3715 }
3716
3717 /* out and in effects */
3718 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
3719 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
3720 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3721 changed = ca0132_effects_set(codec, nid, *valp);
3722 goto exit;
3723 }
3724
3725 /* mic boost */
3726 if (nid == spec->input_pins[0]) {
3727 spec->cur_mic_boost = *valp;
3728
3729 /* Mic boost does not apply to Digital Mic */
3730 if (spec->cur_mic_type != DIGITAL_MIC)
3731 changed = ca0132_mic_boost_set(codec, *valp);
3732 goto exit;
3733 }
3734
3735 exit:
3736 snd_hda_power_down(codec);
3737 return changed;
3738 }
3739
3740 /*
3741 * Volume related
3742 */
3743 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
3744 struct snd_ctl_elem_info *uinfo)
3745 {
3746 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3747 struct ca0132_spec *spec = codec->spec;
3748 hda_nid_t nid = get_amp_nid(kcontrol);
3749 int ch = get_amp_channels(kcontrol);
3750 int dir = get_amp_direction(kcontrol);
3751 unsigned long pval;
3752 int err;
3753
3754 switch (nid) {
3755 case VNID_SPK:
3756 /* follow shared_out info */
3757 nid = spec->shared_out_nid;
3758 mutex_lock(&codec->control_mutex);
3759 pval = kcontrol->private_value;
3760 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3761 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3762 kcontrol->private_value = pval;
3763 mutex_unlock(&codec->control_mutex);
3764 break;
3765 case VNID_MIC:
3766 /* follow shared_mic info */
3767 nid = spec->shared_mic_nid;
3768 mutex_lock(&codec->control_mutex);
3769 pval = kcontrol->private_value;
3770 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3771 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3772 kcontrol->private_value = pval;
3773 mutex_unlock(&codec->control_mutex);
3774 break;
3775 default:
3776 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3777 }
3778 return err;
3779 }
3780
3781 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
3782 struct snd_ctl_elem_value *ucontrol)
3783 {
3784 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3785 struct ca0132_spec *spec = codec->spec;
3786 hda_nid_t nid = get_amp_nid(kcontrol);
3787 int ch = get_amp_channels(kcontrol);
3788 long *valp = ucontrol->value.integer.value;
3789
3790 /* store the left and right volume */
3791 if (ch & 1) {
3792 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
3793 valp++;
3794 }
3795 if (ch & 2) {
3796 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
3797 valp++;
3798 }
3799 return 0;
3800 }
3801
3802 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
3803 struct snd_ctl_elem_value *ucontrol)
3804 {
3805 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3806 struct ca0132_spec *spec = codec->spec;
3807 hda_nid_t nid = get_amp_nid(kcontrol);
3808 int ch = get_amp_channels(kcontrol);
3809 long *valp = ucontrol->value.integer.value;
3810 hda_nid_t shared_nid = 0;
3811 bool effective;
3812 int changed = 1;
3813
3814 /* store the left and right volume */
3815 if (ch & 1) {
3816 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
3817 valp++;
3818 }
3819 if (ch & 2) {
3820 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
3821 valp++;
3822 }
3823
3824 /* if effective conditions, then update hw immediately. */
3825 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3826 if (effective) {
3827 int dir = get_amp_direction(kcontrol);
3828 unsigned long pval;
3829
3830 snd_hda_power_up(codec);
3831 mutex_lock(&codec->control_mutex);
3832 pval = kcontrol->private_value;
3833 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3834 0, dir);
3835 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
3836 kcontrol->private_value = pval;
3837 mutex_unlock(&codec->control_mutex);
3838 snd_hda_power_down(codec);
3839 }
3840
3841 return changed;
3842 }
3843
3844 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
3845 unsigned int size, unsigned int __user *tlv)
3846 {
3847 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3848 struct ca0132_spec *spec = codec->spec;
3849 hda_nid_t nid = get_amp_nid(kcontrol);
3850 int ch = get_amp_channels(kcontrol);
3851 int dir = get_amp_direction(kcontrol);
3852 unsigned long pval;
3853 int err;
3854
3855 switch (nid) {
3856 case VNID_SPK:
3857 /* follow shared_out tlv */
3858 nid = spec->shared_out_nid;
3859 mutex_lock(&codec->control_mutex);
3860 pval = kcontrol->private_value;
3861 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3862 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3863 kcontrol->private_value = pval;
3864 mutex_unlock(&codec->control_mutex);
3865 break;
3866 case VNID_MIC:
3867 /* follow shared_mic tlv */
3868 nid = spec->shared_mic_nid;
3869 mutex_lock(&codec->control_mutex);
3870 pval = kcontrol->private_value;
3871 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3872 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3873 kcontrol->private_value = pval;
3874 mutex_unlock(&codec->control_mutex);
3875 break;
3876 default:
3877 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3878 }
3879 return err;
3880 }
3881
3882 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
3883 const char *pfx, int dir)
3884 {
3885 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3886 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3887 struct snd_kcontrol_new knew =
3888 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
3889 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
3890 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3891 }
3892
3893 static int add_voicefx(struct hda_codec *codec)
3894 {
3895 struct snd_kcontrol_new knew =
3896 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
3897 VOICEFX, 1, 0, HDA_INPUT);
3898 knew.info = ca0132_voicefx_info;
3899 knew.get = ca0132_voicefx_get;
3900 knew.put = ca0132_voicefx_put;
3901 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
3902 }
3903
3904 /*
3905 * When changing Node IDs for Mixer Controls below, make sure to update
3906 * Node IDs in ca0132_config() as well.
3907 */
3908 static struct snd_kcontrol_new ca0132_mixer[] = {
3909 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
3910 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
3911 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
3912 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
3913 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
3914 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
3915 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
3916 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
3917 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
3918 0x12, 1, HDA_INPUT),
3919 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
3920 VNID_HP_SEL, 1, HDA_OUTPUT),
3921 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
3922 VNID_AMIC1_SEL, 1, HDA_INPUT),
3923 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
3924 VNID_HP_ASEL, 1, HDA_OUTPUT),
3925 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
3926 VNID_AMIC1_ASEL, 1, HDA_INPUT),
3927 { } /* end */
3928 };
3929
3930 static int ca0132_build_controls(struct hda_codec *codec)
3931 {
3932 struct ca0132_spec *spec = codec->spec;
3933 int i, num_fx;
3934 int err = 0;
3935
3936 /* Add Mixer controls */
3937 for (i = 0; i < spec->num_mixers; i++) {
3938 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
3939 if (err < 0)
3940 return err;
3941 }
3942
3943 /* Add in and out effects controls.
3944 * VoiceFX, PE and CrystalVoice are added separately.
3945 */
3946 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3947 for (i = 0; i < num_fx; i++) {
3948 err = add_fx_switch(codec, ca0132_effects[i].nid,
3949 ca0132_effects[i].name,
3950 ca0132_effects[i].direct);
3951 if (err < 0)
3952 return err;
3953 }
3954
3955 err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0);
3956 if (err < 0)
3957 return err;
3958
3959 err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1);
3960 if (err < 0)
3961 return err;
3962
3963 add_voicefx(codec);
3964
3965 #ifdef ENABLE_TUNING_CONTROLS
3966 add_tuning_ctls(codec);
3967 #endif
3968
3969 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
3970 if (err < 0)
3971 return err;
3972
3973 if (spec->dig_out) {
3974 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
3975 spec->dig_out);
3976 if (err < 0)
3977 return err;
3978 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
3979 if (err < 0)
3980 return err;
3981 /* spec->multiout.share_spdif = 1; */
3982 }
3983
3984 if (spec->dig_in) {
3985 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
3986 if (err < 0)
3987 return err;
3988 }
3989 return 0;
3990 }
3991
3992 /*
3993 * PCM
3994 */
3995 static struct hda_pcm_stream ca0132_pcm_analog_playback = {
3996 .substreams = 1,
3997 .channels_min = 2,
3998 .channels_max = 6,
3999 .ops = {
4000 .prepare = ca0132_playback_pcm_prepare,
4001 .cleanup = ca0132_playback_pcm_cleanup,
4002 .get_delay = ca0132_playback_pcm_delay,
4003 },
4004 };
4005
4006 static struct hda_pcm_stream ca0132_pcm_analog_capture = {
4007 .substreams = 1,
4008 .channels_min = 2,
4009 .channels_max = 2,
4010 .ops = {
4011 .prepare = ca0132_capture_pcm_prepare,
4012 .cleanup = ca0132_capture_pcm_cleanup,
4013 .get_delay = ca0132_capture_pcm_delay,
4014 },
4015 };
4016
4017 static struct hda_pcm_stream ca0132_pcm_digital_playback = {
4018 .substreams = 1,
4019 .channels_min = 2,
4020 .channels_max = 2,
4021 .ops = {
4022 .open = ca0132_dig_playback_pcm_open,
4023 .close = ca0132_dig_playback_pcm_close,
4024 .prepare = ca0132_dig_playback_pcm_prepare,
4025 .cleanup = ca0132_dig_playback_pcm_cleanup
4026 },
4027 };
4028
4029 static struct hda_pcm_stream ca0132_pcm_digital_capture = {
4030 .substreams = 1,
4031 .channels_min = 2,
4032 .channels_max = 2,
4033 };
4034
4035 static int ca0132_build_pcms(struct hda_codec *codec)
4036 {
4037 struct ca0132_spec *spec = codec->spec;
4038 struct hda_pcm *info;
4039
4040 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
4041 if (!info)
4042 return -ENOMEM;
4043 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
4044 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
4045 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
4046 spec->multiout.max_channels;
4047 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4048 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4049 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
4050
4051 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
4052 if (!info)
4053 return -ENOMEM;
4054 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4055 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4056 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
4057
4058 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
4059 if (!info)
4060 return -ENOMEM;
4061 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4062 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4063 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
4064
4065 if (!spec->dig_out && !spec->dig_in)
4066 return 0;
4067
4068 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
4069 if (!info)
4070 return -ENOMEM;
4071 info->pcm_type = HDA_PCM_TYPE_SPDIF;
4072 if (spec->dig_out) {
4073 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
4074 ca0132_pcm_digital_playback;
4075 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
4076 }
4077 if (spec->dig_in) {
4078 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
4079 ca0132_pcm_digital_capture;
4080 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
4081 }
4082
4083 return 0;
4084 }
4085
4086 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
4087 {
4088 if (pin) {
4089 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
4090 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
4091 snd_hda_codec_write(codec, pin, 0,
4092 AC_VERB_SET_AMP_GAIN_MUTE,
4093 AMP_OUT_UNMUTE);
4094 }
4095 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
4096 snd_hda_codec_write(codec, dac, 0,
4097 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
4098 }
4099
4100 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
4101 {
4102 if (pin) {
4103 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
4104 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
4105 snd_hda_codec_write(codec, pin, 0,
4106 AC_VERB_SET_AMP_GAIN_MUTE,
4107 AMP_IN_UNMUTE(0));
4108 }
4109 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
4110 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
4111 AMP_IN_UNMUTE(0));
4112
4113 /* init to 0 dB and unmute. */
4114 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4115 HDA_AMP_VOLMASK, 0x5a);
4116 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4117 HDA_AMP_MUTE, 0);
4118 }
4119 }
4120
4121 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
4122 {
4123 unsigned int caps;
4124
4125 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
4126 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
4127 snd_hda_override_amp_caps(codec, nid, dir, caps);
4128 }
4129
4130 /*
4131 * Switch between Digital built-in mic and analog mic.
4132 */
4133 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
4134 {
4135 struct ca0132_spec *spec = codec->spec;
4136 unsigned int tmp;
4137 u8 val;
4138 unsigned int oldval;
4139
4140 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
4141
4142 oldval = stop_mic1(codec);
4143 ca0132_set_vipsource(codec, 0);
4144 if (enable) {
4145 /* set DMic input as 2-ch */
4146 tmp = FLOAT_TWO;
4147 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4148
4149 val = spec->dmic_ctl;
4150 val |= 0x80;
4151 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4152 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4153
4154 if (!(spec->dmic_ctl & 0x20))
4155 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
4156 } else {
4157 /* set AMic input as mono */
4158 tmp = FLOAT_ONE;
4159 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4160
4161 val = spec->dmic_ctl;
4162 /* clear bit7 and bit5 to disable dmic */
4163 val &= 0x5f;
4164 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4165 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4166
4167 if (!(spec->dmic_ctl & 0x20))
4168 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
4169 }
4170 ca0132_set_vipsource(codec, 1);
4171 resume_mic1(codec, oldval);
4172 }
4173
4174 /*
4175 * Initialization for Digital Mic.
4176 */
4177 static void ca0132_init_dmic(struct hda_codec *codec)
4178 {
4179 struct ca0132_spec *spec = codec->spec;
4180 u8 val;
4181
4182 /* Setup Digital Mic here, but don't enable.
4183 * Enable based on jack detect.
4184 */
4185
4186 /* MCLK uses MPIO1, set to enable.
4187 * Bit 2-0: MPIO select
4188 * Bit 3: set to disable
4189 * Bit 7-4: reserved
4190 */
4191 val = 0x01;
4192 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4193 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
4194
4195 /* Data1 uses MPIO3. Data2 not use
4196 * Bit 2-0: Data1 MPIO select
4197 * Bit 3: set disable Data1
4198 * Bit 6-4: Data2 MPIO select
4199 * Bit 7: set disable Data2
4200 */
4201 val = 0x83;
4202 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4203 VENDOR_CHIPIO_DMIC_PIN_SET, val);
4204
4205 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
4206 * Bit 3-0: Channel mask
4207 * Bit 4: set for 48KHz, clear for 32KHz
4208 * Bit 5: mode
4209 * Bit 6: set to select Data2, clear for Data1
4210 * Bit 7: set to enable DMic, clear for AMic
4211 */
4212 val = 0x23;
4213 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
4214 spec->dmic_ctl = val;
4215 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4216 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4217 }
4218
4219 /*
4220 * Initialization for Analog Mic 2
4221 */
4222 static void ca0132_init_analog_mic2(struct hda_codec *codec)
4223 {
4224 struct ca0132_spec *spec = codec->spec;
4225
4226 mutex_lock(&spec->chipio_mutex);
4227 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4228 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
4229 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4230 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4231 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4232 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4233 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4234 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
4235 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4236 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4237 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4238 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4239 mutex_unlock(&spec->chipio_mutex);
4240 }
4241
4242 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
4243 {
4244 struct ca0132_spec *spec = codec->spec;
4245 int i;
4246
4247 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
4248 snd_hda_codec_update_widgets(codec);
4249
4250 for (i = 0; i < spec->multiout.num_dacs; i++)
4251 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
4252
4253 for (i = 0; i < spec->num_outputs; i++)
4254 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
4255
4256 for (i = 0; i < spec->num_inputs; i++) {
4257 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
4258 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
4259 }
4260 }
4261
4262 /*
4263 * Setup default parameters for DSP
4264 */
4265 static void ca0132_setup_defaults(struct hda_codec *codec)
4266 {
4267 struct ca0132_spec *spec = codec->spec;
4268 unsigned int tmp;
4269 int num_fx;
4270 int idx, i;
4271
4272 if (spec->dsp_state != DSP_DOWNLOADED)
4273 return;
4274
4275 /* out, in effects + voicefx */
4276 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
4277 for (idx = 0; idx < num_fx; idx++) {
4278 for (i = 0; i <= ca0132_effects[idx].params; i++) {
4279 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4280 ca0132_effects[idx].reqs[i],
4281 ca0132_effects[idx].def_vals[i]);
4282 }
4283 }
4284
4285 /*remove DSP headroom*/
4286 tmp = FLOAT_ZERO;
4287 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
4288
4289 /*set speaker EQ bypass attenuation*/
4290 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
4291
4292 /* set AMic1 and AMic2 as mono mic */
4293 tmp = FLOAT_ONE;
4294 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4295 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
4296
4297 /* set AMic1 as CrystalVoice input */
4298 tmp = FLOAT_ONE;
4299 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4300
4301 /* set WUH source */
4302 tmp = FLOAT_TWO;
4303 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
4304 }
4305
4306 /*
4307 * Initialization of flags in chip
4308 */
4309 static void ca0132_init_flags(struct hda_codec *codec)
4310 {
4311 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
4312 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
4313 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
4314 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
4315 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
4316 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
4317 }
4318
4319 /*
4320 * Initialization of parameters in chip
4321 */
4322 static void ca0132_init_params(struct hda_codec *codec)
4323 {
4324 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
4325 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
4326 }
4327
4328 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
4329 {
4330 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
4331 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
4332 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
4333 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
4334 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
4335 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
4336
4337 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4338 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4339 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
4340 }
4341
4342 static bool ca0132_download_dsp_images(struct hda_codec *codec)
4343 {
4344 bool dsp_loaded = false;
4345 const struct dsp_image_seg *dsp_os_image;
4346 const struct firmware *fw_entry;
4347
4348 if (request_firmware(&fw_entry, EFX_FILE, codec->card->dev) != 0)
4349 return false;
4350
4351 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
4352 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
4353 pr_err("ca0132 dspload_image failed.\n");
4354 goto exit_download;
4355 }
4356
4357 dsp_loaded = dspload_wait_loaded(codec);
4358
4359 exit_download:
4360 release_firmware(fw_entry);
4361
4362 return dsp_loaded;
4363 }
4364
4365 static void ca0132_download_dsp(struct hda_codec *codec)
4366 {
4367 struct ca0132_spec *spec = codec->spec;
4368
4369 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
4370 return; /* NOP */
4371 #endif
4372
4373 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
4374 return; /* don't retry failures */
4375
4376 chipio_enable_clocks(codec);
4377 spec->dsp_state = DSP_DOWNLOADING;
4378 if (!ca0132_download_dsp_images(codec))
4379 spec->dsp_state = DSP_DOWNLOAD_FAILED;
4380 else
4381 spec->dsp_state = DSP_DOWNLOADED;
4382
4383 if (spec->dsp_state == DSP_DOWNLOADED)
4384 ca0132_set_dsp_msr(codec, true);
4385 }
4386
4387 static void ca0132_process_dsp_response(struct hda_codec *codec,
4388 struct hda_jack_callback *callback)
4389 {
4390 struct ca0132_spec *spec = codec->spec;
4391
4392 codec_dbg(codec, "ca0132_process_dsp_response\n");
4393 if (spec->wait_scp) {
4394 if (dspio_get_response_data(codec) >= 0)
4395 spec->wait_scp = 0;
4396 }
4397
4398 dspio_clear_response_queue(codec);
4399 }
4400
4401 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
4402 {
4403 struct ca0132_spec *spec = codec->spec;
4404 struct hda_jack_tbl *tbl;
4405
4406 /* Delay enabling the HP amp, to let the mic-detection
4407 * state machine run.
4408 */
4409 cancel_delayed_work_sync(&spec->unsol_hp_work);
4410 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
4411 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
4412 if (tbl)
4413 tbl->block_report = 1;
4414 }
4415
4416 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
4417 {
4418 ca0132_select_mic(codec);
4419 }
4420
4421 static void ca0132_init_unsol(struct hda_codec *codec)
4422 {
4423 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_HP, hp_callback);
4424 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_AMIC1,
4425 amic_callback);
4426 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
4427 ca0132_process_dsp_response);
4428 }
4429
4430 /*
4431 * Verbs tables.
4432 */
4433
4434 /* Sends before DSP download. */
4435 static struct hda_verb ca0132_base_init_verbs[] = {
4436 /*enable ct extension*/
4437 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
4438 {}
4439 };
4440
4441 /* Send at exit. */
4442 static struct hda_verb ca0132_base_exit_verbs[] = {
4443 /*set afg to D3*/
4444 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
4445 /*disable ct extension*/
4446 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
4447 {}
4448 };
4449
4450 /* Other verbs tables. Sends after DSP download. */
4451 static struct hda_verb ca0132_init_verbs0[] = {
4452 /* chip init verbs */
4453 {0x15, 0x70D, 0xF0},
4454 {0x15, 0x70E, 0xFE},
4455 {0x15, 0x707, 0x75},
4456 {0x15, 0x707, 0xD3},
4457 {0x15, 0x707, 0x09},
4458 {0x15, 0x707, 0x53},
4459 {0x15, 0x707, 0xD4},
4460 {0x15, 0x707, 0xEF},
4461 {0x15, 0x707, 0x75},
4462 {0x15, 0x707, 0xD3},
4463 {0x15, 0x707, 0x09},
4464 {0x15, 0x707, 0x02},
4465 {0x15, 0x707, 0x37},
4466 {0x15, 0x707, 0x78},
4467 {0x15, 0x53C, 0xCE},
4468 {0x15, 0x575, 0xC9},
4469 {0x15, 0x53D, 0xCE},
4470 {0x15, 0x5B7, 0xC9},
4471 {0x15, 0x70D, 0xE8},
4472 {0x15, 0x70E, 0xFE},
4473 {0x15, 0x707, 0x02},
4474 {0x15, 0x707, 0x68},
4475 {0x15, 0x707, 0x62},
4476 {0x15, 0x53A, 0xCE},
4477 {0x15, 0x546, 0xC9},
4478 {0x15, 0x53B, 0xCE},
4479 {0x15, 0x5E8, 0xC9},
4480 {0x15, 0x717, 0x0D},
4481 {0x15, 0x718, 0x20},
4482 {}
4483 };
4484
4485 static struct hda_verb ca0132_init_verbs1[] = {
4486 {0x10, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_HP},
4487 {0x12, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_AMIC1},
4488 /* config EAPD */
4489 {0x0b, 0x78D, 0x00},
4490 /*{0x0b, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/
4491 /*{0x10, 0x78D, 0x02},*/
4492 /*{0x10, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/
4493 {}
4494 };
4495
4496 static void ca0132_init_chip(struct hda_codec *codec)
4497 {
4498 struct ca0132_spec *spec = codec->spec;
4499 int num_fx;
4500 int i;
4501 unsigned int on;
4502
4503 mutex_init(&spec->chipio_mutex);
4504
4505 spec->cur_out_type = SPEAKER_OUT;
4506 spec->cur_mic_type = DIGITAL_MIC;
4507 spec->cur_mic_boost = 0;
4508
4509 for (i = 0; i < VNODES_COUNT; i++) {
4510 spec->vnode_lvol[i] = 0x5a;
4511 spec->vnode_rvol[i] = 0x5a;
4512 spec->vnode_lswitch[i] = 0;
4513 spec->vnode_rswitch[i] = 0;
4514 }
4515
4516 /*
4517 * Default states for effects are in ca0132_effects[].
4518 */
4519 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4520 for (i = 0; i < num_fx; i++) {
4521 on = (unsigned int)ca0132_effects[i].reqs[0];
4522 spec->effects_switch[i] = on ? 1 : 0;
4523 }
4524
4525 spec->voicefx_val = 0;
4526 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
4527 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
4528
4529 #ifdef ENABLE_TUNING_CONTROLS
4530 ca0132_init_tuning_defaults(codec);
4531 #endif
4532 }
4533
4534 static void ca0132_exit_chip(struct hda_codec *codec)
4535 {
4536 /* put any chip cleanup stuffs here. */
4537
4538 if (dspload_is_loaded(codec))
4539 dsp_reset(codec);
4540 }
4541
4542 static int ca0132_init(struct hda_codec *codec)
4543 {
4544 struct ca0132_spec *spec = codec->spec;
4545 struct auto_pin_cfg *cfg = &spec->autocfg;
4546 int i;
4547
4548 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
4549 spec->dsp_state = DSP_DOWNLOAD_INIT;
4550 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
4551
4552 snd_hda_power_up_pm(codec);
4553
4554 ca0132_init_unsol(codec);
4555
4556 ca0132_init_params(codec);
4557 ca0132_init_flags(codec);
4558 snd_hda_sequence_write(codec, spec->base_init_verbs);
4559 ca0132_download_dsp(codec);
4560 ca0132_refresh_widget_caps(codec);
4561 ca0132_setup_defaults(codec);
4562 ca0132_init_analog_mic2(codec);
4563 ca0132_init_dmic(codec);
4564
4565 for (i = 0; i < spec->num_outputs; i++)
4566 init_output(codec, spec->out_pins[i], spec->dacs[0]);
4567
4568 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
4569
4570 for (i = 0; i < spec->num_inputs; i++)
4571 init_input(codec, spec->input_pins[i], spec->adcs[i]);
4572
4573 init_input(codec, cfg->dig_in_pin, spec->dig_in);
4574
4575 for (i = 0; i < spec->num_init_verbs; i++)
4576 snd_hda_sequence_write(codec, spec->init_verbs[i]);
4577
4578 ca0132_select_out(codec);
4579 ca0132_select_mic(codec);
4580
4581 snd_hda_jack_report_sync(codec);
4582
4583 snd_hda_power_down_pm(codec);
4584
4585 return 0;
4586 }
4587
4588 static void ca0132_free(struct hda_codec *codec)
4589 {
4590 struct ca0132_spec *spec = codec->spec;
4591
4592 cancel_delayed_work_sync(&spec->unsol_hp_work);
4593 snd_hda_power_up(codec);
4594 snd_hda_sequence_write(codec, spec->base_exit_verbs);
4595 ca0132_exit_chip(codec);
4596 snd_hda_power_down(codec);
4597 kfree(codec->spec);
4598 }
4599
4600 static struct hda_codec_ops ca0132_patch_ops = {
4601 .build_controls = ca0132_build_controls,
4602 .build_pcms = ca0132_build_pcms,
4603 .init = ca0132_init,
4604 .free = ca0132_free,
4605 .unsol_event = snd_hda_jack_unsol_event,
4606 };
4607
4608 static void ca0132_config(struct hda_codec *codec)
4609 {
4610 struct ca0132_spec *spec = codec->spec;
4611 struct auto_pin_cfg *cfg = &spec->autocfg;
4612
4613 spec->dacs[0] = 0x2;
4614 spec->dacs[1] = 0x3;
4615 spec->dacs[2] = 0x4;
4616
4617 spec->multiout.dac_nids = spec->dacs;
4618 spec->multiout.num_dacs = 3;
4619 spec->multiout.max_channels = 2;
4620
4621 spec->num_outputs = 2;
4622 spec->out_pins[0] = 0x0b; /* speaker out */
4623 spec->out_pins[1] = 0x10; /* headphone out */
4624 spec->shared_out_nid = 0x2;
4625
4626 spec->num_inputs = 3;
4627 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4628 spec->adcs[1] = 0x8; /* analog mic2 */
4629 spec->adcs[2] = 0xa; /* what u hear */
4630 spec->shared_mic_nid = 0x7;
4631
4632 spec->input_pins[0] = 0x12;
4633 spec->input_pins[1] = 0x11;
4634 spec->input_pins[2] = 0x13;
4635
4636 /* SPDIF I/O */
4637 spec->dig_out = 0x05;
4638 spec->multiout.dig_out_nid = spec->dig_out;
4639 cfg->dig_out_pins[0] = 0x0c;
4640 cfg->dig_outs = 1;
4641 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
4642 spec->dig_in = 0x09;
4643 cfg->dig_in_pin = 0x0e;
4644 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
4645 }
4646
4647 static int patch_ca0132(struct hda_codec *codec)
4648 {
4649 struct ca0132_spec *spec;
4650 int err;
4651
4652 codec_dbg(codec, "patch_ca0132\n");
4653
4654 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
4655 if (!spec)
4656 return -ENOMEM;
4657 codec->spec = spec;
4658 spec->codec = codec;
4659
4660 spec->dsp_state = DSP_DOWNLOAD_INIT;
4661 spec->num_mixers = 1;
4662 spec->mixers[0] = ca0132_mixer;
4663
4664 spec->base_init_verbs = ca0132_base_init_verbs;
4665 spec->base_exit_verbs = ca0132_base_exit_verbs;
4666 spec->init_verbs[0] = ca0132_init_verbs0;
4667 spec->init_verbs[1] = ca0132_init_verbs1;
4668 spec->num_init_verbs = 2;
4669
4670 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
4671
4672 ca0132_init_chip(codec);
4673
4674 ca0132_config(codec);
4675
4676 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
4677 if (err < 0)
4678 return err;
4679
4680 codec->patch_ops = ca0132_patch_ops;
4681 codec->pcm_format_first = 1;
4682 codec->no_sticky_stream = 1;
4683
4684 return 0;
4685 }
4686
4687 /*
4688 * patch entries
4689 */
4690 static struct hda_codec_preset snd_hda_preset_ca0132[] = {
4691 { .id = 0x11020011, .name = "CA0132", .patch = patch_ca0132 },
4692 {} /* terminator */
4693 };
4694
4695 MODULE_ALIAS("snd-hda-codec-id:11020011");
4696
4697 MODULE_LICENSE("GPL");
4698 MODULE_DESCRIPTION("Creative Sound Core3D codec");
4699
4700 static struct hda_codec_driver ca0132_driver = {
4701 .preset = snd_hda_preset_ca0132,
4702 };
4703
4704 module_hda_codec_driver(ca0132_driver);
Linux with added FPC-III support