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qlcnic: Fix mailbox completion handling during spurious interrupt
[linux/fpc-iii.git] / sound / pci / hda / patch_hdmi.c
blob193426e223c93f9c7cd3e7d9db4069d3899610dc
1 /*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <sound/core.h>
37 #include <sound/jack.h>
38 #include <sound/asoundef.h>
39 #include <sound/tlv.h>
40 #include "hda_codec.h"
41 #include "hda_local.h"
42 #include "hda_jack.h"
43
44 static bool static_hdmi_pcm;
45 module_param(static_hdmi_pcm, bool, 0644);
46 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
47
48 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
49 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
50 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
51 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
52 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
53 || is_skylake(codec) || is_broxton(codec))
54
55 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
56 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
57 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
58
59 struct hdmi_spec_per_cvt {
60 hda_nid_t cvt_nid;
61 int assigned;
62 unsigned int channels_min;
63 unsigned int channels_max;
64 u32 rates;
65 u64 formats;
66 unsigned int maxbps;
67 };
68
69 /* max. connections to a widget */
70 #define HDA_MAX_CONNECTIONS 32
71
72 struct hdmi_spec_per_pin {
73 hda_nid_t pin_nid;
74 int num_mux_nids;
75 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
76 int mux_idx;
77 hda_nid_t cvt_nid;
78
79 struct hda_codec *codec;
80 struct hdmi_eld sink_eld;
81 struct mutex lock;
82 struct delayed_work work;
83 struct snd_kcontrol *eld_ctl;
84 int repoll_count;
85 bool setup; /* the stream has been set up by prepare callback */
86 int channels; /* current number of channels */
87 bool non_pcm;
88 bool chmap_set; /* channel-map override by ALSA API? */
89 unsigned char chmap[8]; /* ALSA API channel-map */
90 #ifdef CONFIG_PROC_FS
91 struct snd_info_entry *proc_entry;
92 #endif
93 };
94
95 struct cea_channel_speaker_allocation;
96
97 /* operations used by generic code that can be overridden by patches */
98 struct hdmi_ops {
99 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
100 unsigned char *buf, int *eld_size);
101
102 /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
103 int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
104 int asp_slot);
105 int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
106 int asp_slot, int channel);
107
108 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
109 int ca, int active_channels, int conn_type);
110
111 /* enable/disable HBR (HD passthrough) */
112 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
113
114 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
115 hda_nid_t pin_nid, u32 stream_tag, int format);
116
117 /* Helpers for producing the channel map TLVs. These can be overridden
118 * for devices that have non-standard mapping requirements. */
119 int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
120 int channels);
121 void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
122 unsigned int *chmap, int channels);
123
124 /* check that the user-given chmap is supported */
125 int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
126 };
127
128 struct hdmi_spec {
129 int num_cvts;
130 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
131 hda_nid_t cvt_nids[4]; /* only for haswell fix */
132
133 int num_pins;
134 struct snd_array pins; /* struct hdmi_spec_per_pin */
135 struct hda_pcm *pcm_rec[16];
136 unsigned int channels_max; /* max over all cvts */
137
138 struct hdmi_eld temp_eld;
139 struct hdmi_ops ops;
140
141 bool dyn_pin_out;
142
143 /*
144 * Non-generic VIA/NVIDIA specific
145 */
146 struct hda_multi_out multiout;
147 struct hda_pcm_stream pcm_playback;
148 };
149
150
151 struct hdmi_audio_infoframe {
152 u8 type; /* 0x84 */
153 u8 ver; /* 0x01 */
154 u8 len; /* 0x0a */
155
156 u8 checksum;
157
158 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
159 u8 SS01_SF24;
160 u8 CXT04;
161 u8 CA;
162 u8 LFEPBL01_LSV36_DM_INH7;
163 };
164
165 struct dp_audio_infoframe {
166 u8 type; /* 0x84 */
167 u8 len; /* 0x1b */
168 u8 ver; /* 0x11 << 2 */
169
170 u8 CC02_CT47; /* match with HDMI infoframe from this on */
171 u8 SS01_SF24;
172 u8 CXT04;
173 u8 CA;
174 u8 LFEPBL01_LSV36_DM_INH7;
175 };
176
177 union audio_infoframe {
178 struct hdmi_audio_infoframe hdmi;
179 struct dp_audio_infoframe dp;
180 u8 bytes[0];
181 };
182
183 /*
184 * CEA speaker placement:
185 *
186 * FLH FCH FRH
187 * FLW FL FLC FC FRC FR FRW
188 *
189 * LFE
190 * TC
191 *
192 * RL RLC RC RRC RR
193 *
194 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
195 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
196 */
197 enum cea_speaker_placement {
198 FL = (1 << 0), /* Front Left */
199 FC = (1 << 1), /* Front Center */
200 FR = (1 << 2), /* Front Right */
201 FLC = (1 << 3), /* Front Left Center */
202 FRC = (1 << 4), /* Front Right Center */
203 RL = (1 << 5), /* Rear Left */
204 RC = (1 << 6), /* Rear Center */
205 RR = (1 << 7), /* Rear Right */
206 RLC = (1 << 8), /* Rear Left Center */
207 RRC = (1 << 9), /* Rear Right Center */
208 LFE = (1 << 10), /* Low Frequency Effect */
209 FLW = (1 << 11), /* Front Left Wide */
210 FRW = (1 << 12), /* Front Right Wide */
211 FLH = (1 << 13), /* Front Left High */
212 FCH = (1 << 14), /* Front Center High */
213 FRH = (1 << 15), /* Front Right High */
214 TC = (1 << 16), /* Top Center */
215 };
216
217 /*
218 * ELD SA bits in the CEA Speaker Allocation data block
219 */
220 static int eld_speaker_allocation_bits[] = {
221 [0] = FL | FR,
222 [1] = LFE,
223 [2] = FC,
224 [3] = RL | RR,
225 [4] = RC,
226 [5] = FLC | FRC,
227 [6] = RLC | RRC,
228 /* the following are not defined in ELD yet */
229 [7] = FLW | FRW,
230 [8] = FLH | FRH,
231 [9] = TC,
232 [10] = FCH,
233 };
234
235 struct cea_channel_speaker_allocation {
236 int ca_index;
237 int speakers[8];
238
239 /* derived values, just for convenience */
240 int channels;
241 int spk_mask;
242 };
243
244 /*
245 * ALSA sequence is:
246 *
247 * surround40 surround41 surround50 surround51 surround71
248 * ch0 front left = = = =
249 * ch1 front right = = = =
250 * ch2 rear left = = = =
251 * ch3 rear right = = = =
252 * ch4 LFE center center center
253 * ch5 LFE LFE
254 * ch6 side left
255 * ch7 side right
256 *
257 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
258 */
259 static int hdmi_channel_mapping[0x32][8] = {
260 /* stereo */
261 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
262 /* 2.1 */
263 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
264 /* Dolby Surround */
265 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
266 /* surround40 */
267 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
268 /* 4ch */
269 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
270 /* surround41 */
271 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
272 /* surround50 */
273 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
274 /* surround51 */
275 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
276 /* 7.1 */
277 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
278 };
279
280 /*
281 * This is an ordered list!
282 *
283 * The preceding ones have better chances to be selected by
284 * hdmi_channel_allocation().
285 */
286 static struct cea_channel_speaker_allocation channel_allocations[] = {
287 /* channel: 7 6 5 4 3 2 1 0 */
288 { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
289 /* 2.1 */
290 { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
291 /* Dolby Surround */
292 { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
293 /* surround40 */
294 { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
295 /* surround41 */
296 { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
297 /* surround50 */
298 { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
299 /* surround51 */
300 { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
301 /* 6.1 */
302 { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
303 /* surround71 */
304 { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
305
306 { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
307 { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
308 { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
309 { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
310 { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
311 { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
312 { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
313 { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
314 { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
315 { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
316 { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
317 { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
318 { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
319 { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
320 { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
321 { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
322 { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
323 { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
324 { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
325 { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
326 { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
327 { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
328 { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
329 { .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
330 { .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
331 { .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
332 { .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
333 { .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
334 { .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
335 { .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
336 { .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
337 { .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
338 { .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
339 { .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
340 { .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
341 { .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
342 { .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
343 { .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
344 { .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
345 { .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
346 { .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
347 };
348
349
350 /*
351 * HDMI routines
352 */
353
354 #define get_pin(spec, idx) \
355 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
356 #define get_cvt(spec, idx) \
357 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
358 #define get_pcm_rec(spec, idx) ((spec)->pcm_rec[idx])
359
360 static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
361 {
362 struct hdmi_spec *spec = codec->spec;
363 int pin_idx;
364
365 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
366 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
367 return pin_idx;
368
369 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
370 return -EINVAL;
371 }
372
373 static int hinfo_to_pin_index(struct hda_codec *codec,
374 struct hda_pcm_stream *hinfo)
375 {
376 struct hdmi_spec *spec = codec->spec;
377 int pin_idx;
378
379 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
380 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
381 return pin_idx;
382
383 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
384 return -EINVAL;
385 }
386
387 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
388 {
389 struct hdmi_spec *spec = codec->spec;
390 int cvt_idx;
391
392 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
393 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
394 return cvt_idx;
395
396 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
397 return -EINVAL;
398 }
399
400 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
401 struct snd_ctl_elem_info *uinfo)
402 {
403 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
404 struct hdmi_spec *spec = codec->spec;
405 struct hdmi_spec_per_pin *per_pin;
406 struct hdmi_eld *eld;
407 int pin_idx;
408
409 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
410
411 pin_idx = kcontrol->private_value;
412 per_pin = get_pin(spec, pin_idx);
413 eld = &per_pin->sink_eld;
414
415 mutex_lock(&per_pin->lock);
416 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
417 mutex_unlock(&per_pin->lock);
418
419 return 0;
420 }
421
422 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
423 struct snd_ctl_elem_value *ucontrol)
424 {
425 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
426 struct hdmi_spec *spec = codec->spec;
427 struct hdmi_spec_per_pin *per_pin;
428 struct hdmi_eld *eld;
429 int pin_idx;
430
431 pin_idx = kcontrol->private_value;
432 per_pin = get_pin(spec, pin_idx);
433 eld = &per_pin->sink_eld;
434
435 mutex_lock(&per_pin->lock);
436 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
437 eld->eld_size > ELD_MAX_SIZE) {
438 mutex_unlock(&per_pin->lock);
439 snd_BUG();
440 return -EINVAL;
441 }
442
443 memset(ucontrol->value.bytes.data, 0,
444 ARRAY_SIZE(ucontrol->value.bytes.data));
445 if (eld->eld_valid)
446 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
447 eld->eld_size);
448 mutex_unlock(&per_pin->lock);
449
450 return 0;
451 }
452
453 static struct snd_kcontrol_new eld_bytes_ctl = {
454 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
455 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
456 .name = "ELD",
457 .info = hdmi_eld_ctl_info,
458 .get = hdmi_eld_ctl_get,
459 };
460
461 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
462 int device)
463 {
464 struct snd_kcontrol *kctl;
465 struct hdmi_spec *spec = codec->spec;
466 int err;
467
468 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
469 if (!kctl)
470 return -ENOMEM;
471 kctl->private_value = pin_idx;
472 kctl->id.device = device;
473
474 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
475 if (err < 0)
476 return err;
477
478 get_pin(spec, pin_idx)->eld_ctl = kctl;
479 return 0;
480 }
481
482 #ifdef BE_PARANOID
483 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
484 int *packet_index, int *byte_index)
485 {
486 int val;
487
488 val = snd_hda_codec_read(codec, pin_nid, 0,
489 AC_VERB_GET_HDMI_DIP_INDEX, 0);
490
491 *packet_index = val >> 5;
492 *byte_index = val & 0x1f;
493 }
494 #endif
495
496 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
497 int packet_index, int byte_index)
498 {
499 int val;
500
501 val = (packet_index << 5) | (byte_index & 0x1f);
502
503 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
504 }
505
506 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
507 unsigned char val)
508 {
509 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
510 }
511
512 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
513 {
514 struct hdmi_spec *spec = codec->spec;
515 int pin_out;
516
517 /* Unmute */
518 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
519 snd_hda_codec_write(codec, pin_nid, 0,
520 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
521
522 if (spec->dyn_pin_out)
523 /* Disable pin out until stream is active */
524 pin_out = 0;
525 else
526 /* Enable pin out: some machines with GM965 gets broken output
527 * when the pin is disabled or changed while using with HDMI
528 */
529 pin_out = PIN_OUT;
530
531 snd_hda_codec_write(codec, pin_nid, 0,
532 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
533 }
534
535 static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
536 {
537 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
538 AC_VERB_GET_CVT_CHAN_COUNT, 0);
539 }
540
541 static void hdmi_set_channel_count(struct hda_codec *codec,
542 hda_nid_t cvt_nid, int chs)
543 {
544 if (chs != hdmi_get_channel_count(codec, cvt_nid))
545 snd_hda_codec_write(codec, cvt_nid, 0,
546 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
547 }
548
549 /*
550 * ELD proc files
551 */
552
553 #ifdef CONFIG_PROC_FS
554 static void print_eld_info(struct snd_info_entry *entry,
555 struct snd_info_buffer *buffer)
556 {
557 struct hdmi_spec_per_pin *per_pin = entry->private_data;
558
559 mutex_lock(&per_pin->lock);
560 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
561 mutex_unlock(&per_pin->lock);
562 }
563
564 static void write_eld_info(struct snd_info_entry *entry,
565 struct snd_info_buffer *buffer)
566 {
567 struct hdmi_spec_per_pin *per_pin = entry->private_data;
568
569 mutex_lock(&per_pin->lock);
570 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
571 mutex_unlock(&per_pin->lock);
572 }
573
574 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
575 {
576 char name[32];
577 struct hda_codec *codec = per_pin->codec;
578 struct snd_info_entry *entry;
579 int err;
580
581 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
582 err = snd_card_proc_new(codec->card, name, &entry);
583 if (err < 0)
584 return err;
585
586 snd_info_set_text_ops(entry, per_pin, print_eld_info);
587 entry->c.text.write = write_eld_info;
588 entry->mode |= S_IWUSR;
589 per_pin->proc_entry = entry;
590
591 return 0;
592 }
593
594 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
595 {
596 if (!per_pin->codec->bus->shutdown && per_pin->proc_entry) {
597 snd_device_free(per_pin->codec->card, per_pin->proc_entry);
598 per_pin->proc_entry = NULL;
599 }
600 }
601 #else
602 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
603 int index)
604 {
605 return 0;
606 }
607 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
608 {
609 }
610 #endif
611
612 /*
613 * Channel mapping routines
614 */
615
616 /*
617 * Compute derived values in channel_allocations[].
618 */
619 static void init_channel_allocations(void)
620 {
621 int i, j;
622 struct cea_channel_speaker_allocation *p;
623
624 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
625 p = channel_allocations + i;
626 p->channels = 0;
627 p->spk_mask = 0;
628 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
629 if (p->speakers[j]) {
630 p->channels++;
631 p->spk_mask |= p->speakers[j];
632 }
633 }
634 }
635
636 static int get_channel_allocation_order(int ca)
637 {
638 int i;
639
640 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
641 if (channel_allocations[i].ca_index == ca)
642 break;
643 }
644 return i;
645 }
646
647 /*
648 * The transformation takes two steps:
649 *
650 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
651 * spk_mask => (channel_allocations[]) => ai->CA
652 *
653 * TODO: it could select the wrong CA from multiple candidates.
654 */
655 static int hdmi_channel_allocation(struct hda_codec *codec,
656 struct hdmi_eld *eld, int channels)
657 {
658 int i;
659 int ca = 0;
660 int spk_mask = 0;
661 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
662
663 /*
664 * CA defaults to 0 for basic stereo audio
665 */
666 if (channels <= 2)
667 return 0;
668
669 /*
670 * expand ELD's speaker allocation mask
671 *
672 * ELD tells the speaker mask in a compact(paired) form,
673 * expand ELD's notions to match the ones used by Audio InfoFrame.
674 */
675 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
676 if (eld->info.spk_alloc & (1 << i))
677 spk_mask |= eld_speaker_allocation_bits[i];
678 }
679
680 /* search for the first working match in the CA table */
681 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
682 if (channels == channel_allocations[i].channels &&
683 (spk_mask & channel_allocations[i].spk_mask) ==
684 channel_allocations[i].spk_mask) {
685 ca = channel_allocations[i].ca_index;
686 break;
687 }
688 }
689
690 if (!ca) {
691 /* if there was no match, select the regular ALSA channel
692 * allocation with the matching number of channels */
693 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
694 if (channels == channel_allocations[i].channels) {
695 ca = channel_allocations[i].ca_index;
696 break;
697 }
698 }
699 }
700
701 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
702 codec_dbg(codec, "HDMI: select CA 0x%x for %d-channel allocation: %s\n",
703 ca, channels, buf);
704
705 return ca;
706 }
707
708 static void hdmi_debug_channel_mapping(struct hda_codec *codec,
709 hda_nid_t pin_nid)
710 {
711 #ifdef CONFIG_SND_DEBUG_VERBOSE
712 struct hdmi_spec *spec = codec->spec;
713 int i;
714 int channel;
715
716 for (i = 0; i < 8; i++) {
717 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
718 codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n",
719 channel, i);
720 }
721 #endif
722 }
723
724 static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
725 hda_nid_t pin_nid,
726 bool non_pcm,
727 int ca)
728 {
729 struct hdmi_spec *spec = codec->spec;
730 struct cea_channel_speaker_allocation *ch_alloc;
731 int i;
732 int err;
733 int order;
734 int non_pcm_mapping[8];
735
736 order = get_channel_allocation_order(ca);
737 ch_alloc = &channel_allocations[order];
738
739 if (hdmi_channel_mapping[ca][1] == 0) {
740 int hdmi_slot = 0;
741 /* fill actual channel mappings in ALSA channel (i) order */
742 for (i = 0; i < ch_alloc->channels; i++) {
743 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
744 hdmi_slot++; /* skip zero slots */
745
746 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
747 }
748 /* fill the rest of the slots with ALSA channel 0xf */
749 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
750 if (!ch_alloc->speakers[7 - hdmi_slot])
751 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
752 }
753
754 if (non_pcm) {
755 for (i = 0; i < ch_alloc->channels; i++)
756 non_pcm_mapping[i] = (i << 4) | i;
757 for (; i < 8; i++)
758 non_pcm_mapping[i] = (0xf << 4) | i;
759 }
760
761 for (i = 0; i < 8; i++) {
762 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
763 int hdmi_slot = slotsetup & 0x0f;
764 int channel = (slotsetup & 0xf0) >> 4;
765 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
766 if (err) {
767 codec_dbg(codec, "HDMI: channel mapping failed\n");
768 break;
769 }
770 }
771 }
772
773 struct channel_map_table {
774 unsigned char map; /* ALSA API channel map position */
775 int spk_mask; /* speaker position bit mask */
776 };
777
778 static struct channel_map_table map_tables[] = {
779 { SNDRV_CHMAP_FL, FL },
780 { SNDRV_CHMAP_FR, FR },
781 { SNDRV_CHMAP_RL, RL },
782 { SNDRV_CHMAP_RR, RR },
783 { SNDRV_CHMAP_LFE, LFE },
784 { SNDRV_CHMAP_FC, FC },
785 { SNDRV_CHMAP_RLC, RLC },
786 { SNDRV_CHMAP_RRC, RRC },
787 { SNDRV_CHMAP_RC, RC },
788 { SNDRV_CHMAP_FLC, FLC },
789 { SNDRV_CHMAP_FRC, FRC },
790 { SNDRV_CHMAP_TFL, FLH },
791 { SNDRV_CHMAP_TFR, FRH },
792 { SNDRV_CHMAP_FLW, FLW },
793 { SNDRV_CHMAP_FRW, FRW },
794 { SNDRV_CHMAP_TC, TC },
795 { SNDRV_CHMAP_TFC, FCH },
796 {} /* terminator */
797 };
798
799 /* from ALSA API channel position to speaker bit mask */
800 static int to_spk_mask(unsigned char c)
801 {
802 struct channel_map_table *t = map_tables;
803 for (; t->map; t++) {
804 if (t->map == c)
805 return t->spk_mask;
806 }
807 return 0;
808 }
809
810 /* from ALSA API channel position to CEA slot */
811 static int to_cea_slot(int ordered_ca, unsigned char pos)
812 {
813 int mask = to_spk_mask(pos);
814 int i;
815
816 if (mask) {
817 for (i = 0; i < 8; i++) {
818 if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
819 return i;
820 }
821 }
822
823 return -1;
824 }
825
826 /* from speaker bit mask to ALSA API channel position */
827 static int spk_to_chmap(int spk)
828 {
829 struct channel_map_table *t = map_tables;
830 for (; t->map; t++) {
831 if (t->spk_mask == spk)
832 return t->map;
833 }
834 return 0;
835 }
836
837 /* from CEA slot to ALSA API channel position */
838 static int from_cea_slot(int ordered_ca, unsigned char slot)
839 {
840 int mask = channel_allocations[ordered_ca].speakers[7 - slot];
841
842 return spk_to_chmap(mask);
843 }
844
845 /* get the CA index corresponding to the given ALSA API channel map */
846 static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
847 {
848 int i, spks = 0, spk_mask = 0;
849
850 for (i = 0; i < chs; i++) {
851 int mask = to_spk_mask(map[i]);
852 if (mask) {
853 spk_mask |= mask;
854 spks++;
855 }
856 }
857
858 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
859 if ((chs == channel_allocations[i].channels ||
860 spks == channel_allocations[i].channels) &&
861 (spk_mask & channel_allocations[i].spk_mask) ==
862 channel_allocations[i].spk_mask)
863 return channel_allocations[i].ca_index;
864 }
865 return -1;
866 }
867
868 /* set up the channel slots for the given ALSA API channel map */
869 static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
870 hda_nid_t pin_nid,
871 int chs, unsigned char *map,
872 int ca)
873 {
874 struct hdmi_spec *spec = codec->spec;
875 int ordered_ca = get_channel_allocation_order(ca);
876 int alsa_pos, hdmi_slot;
877 int assignments[8] = {[0 ... 7] = 0xf};
878
879 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
880
881 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
882
883 if (hdmi_slot < 0)
884 continue; /* unassigned channel */
885
886 assignments[hdmi_slot] = alsa_pos;
887 }
888
889 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
890 int err;
891
892 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
893 assignments[hdmi_slot]);
894 if (err)
895 return -EINVAL;
896 }
897 return 0;
898 }
899
900 /* store ALSA API channel map from the current default map */
901 static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
902 {
903 int i;
904 int ordered_ca = get_channel_allocation_order(ca);
905 for (i = 0; i < 8; i++) {
906 if (i < channel_allocations[ordered_ca].channels)
907 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
908 else
909 map[i] = 0;
910 }
911 }
912
913 static void hdmi_setup_channel_mapping(struct hda_codec *codec,
914 hda_nid_t pin_nid, bool non_pcm, int ca,
915 int channels, unsigned char *map,
916 bool chmap_set)
917 {
918 if (!non_pcm && chmap_set) {
919 hdmi_manual_setup_channel_mapping(codec, pin_nid,
920 channels, map, ca);
921 } else {
922 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
923 hdmi_setup_fake_chmap(map, ca);
924 }
925
926 hdmi_debug_channel_mapping(codec, pin_nid);
927 }
928
929 static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
930 int asp_slot, int channel)
931 {
932 return snd_hda_codec_write(codec, pin_nid, 0,
933 AC_VERB_SET_HDMI_CHAN_SLOT,
934 (channel << 4) | asp_slot);
935 }
936
937 static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
938 int asp_slot)
939 {
940 return (snd_hda_codec_read(codec, pin_nid, 0,
941 AC_VERB_GET_HDMI_CHAN_SLOT,
942 asp_slot) & 0xf0) >> 4;
943 }
944
945 /*
946 * Audio InfoFrame routines
947 */
948
949 /*
950 * Enable Audio InfoFrame Transmission
951 */
952 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
953 hda_nid_t pin_nid)
954 {
955 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
956 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
957 AC_DIPXMIT_BEST);
958 }
959
960 /*
961 * Disable Audio InfoFrame Transmission
962 */
963 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
964 hda_nid_t pin_nid)
965 {
966 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
967 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
968 AC_DIPXMIT_DISABLE);
969 }
970
971 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
972 {
973 #ifdef CONFIG_SND_DEBUG_VERBOSE
974 int i;
975 int size;
976
977 size = snd_hdmi_get_eld_size(codec, pin_nid);
978 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
979
980 for (i = 0; i < 8; i++) {
981 size = snd_hda_codec_read(codec, pin_nid, 0,
982 AC_VERB_GET_HDMI_DIP_SIZE, i);
983 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
984 }
985 #endif
986 }
987
988 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
989 {
990 #ifdef BE_PARANOID
991 int i, j;
992 int size;
993 int pi, bi;
994 for (i = 0; i < 8; i++) {
995 size = snd_hda_codec_read(codec, pin_nid, 0,
996 AC_VERB_GET_HDMI_DIP_SIZE, i);
997 if (size == 0)
998 continue;
999
1000 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
1001 for (j = 1; j < 1000; j++) {
1002 hdmi_write_dip_byte(codec, pin_nid, 0x0);
1003 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
1004 if (pi != i)
1005 codec_dbg(codec, "dip index %d: %d != %d\n",
1006 bi, pi, i);
1007 if (bi == 0) /* byte index wrapped around */
1008 break;
1009 }
1010 codec_dbg(codec,
1011 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
1012 i, size, j);
1013 }
1014 #endif
1015 }
1016
1017 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
1018 {
1019 u8 *bytes = (u8 *)hdmi_ai;
1020 u8 sum = 0;
1021 int i;
1022
1023 hdmi_ai->checksum = 0;
1024
1025 for (i = 0; i < sizeof(*hdmi_ai); i++)
1026 sum += bytes[i];
1027
1028 hdmi_ai->checksum = -sum;
1029 }
1030
1031 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1032 hda_nid_t pin_nid,
1033 u8 *dip, int size)
1034 {
1035 int i;
1036
1037 hdmi_debug_dip_size(codec, pin_nid);
1038 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1039
1040 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1041 for (i = 0; i < size; i++)
1042 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
1043 }
1044
1045 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
1046 u8 *dip, int size)
1047 {
1048 u8 val;
1049 int i;
1050
1051 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1052 != AC_DIPXMIT_BEST)
1053 return false;
1054
1055 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1056 for (i = 0; i < size; i++) {
1057 val = snd_hda_codec_read(codec, pin_nid, 0,
1058 AC_VERB_GET_HDMI_DIP_DATA, 0);
1059 if (val != dip[i])
1060 return false;
1061 }
1062
1063 return true;
1064 }
1065
1066 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1067 hda_nid_t pin_nid,
1068 int ca, int active_channels,
1069 int conn_type)
1070 {
1071 union audio_infoframe ai;
1072
1073 memset(&ai, 0, sizeof(ai));
1074 if (conn_type == 0) { /* HDMI */
1075 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1076
1077 hdmi_ai->type = 0x84;
1078 hdmi_ai->ver = 0x01;
1079 hdmi_ai->len = 0x0a;
1080 hdmi_ai->CC02_CT47 = active_channels - 1;
1081 hdmi_ai->CA = ca;
1082 hdmi_checksum_audio_infoframe(hdmi_ai);
1083 } else if (conn_type == 1) { /* DisplayPort */
1084 struct dp_audio_infoframe *dp_ai = &ai.dp;
1085
1086 dp_ai->type = 0x84;
1087 dp_ai->len = 0x1b;
1088 dp_ai->ver = 0x11 << 2;
1089 dp_ai->CC02_CT47 = active_channels - 1;
1090 dp_ai->CA = ca;
1091 } else {
1092 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
1093 pin_nid);
1094 return;
1095 }
1096
1097 /*
1098 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1099 * sizeof(*dp_ai) to avoid partial match/update problems when
1100 * the user switches between HDMI/DP monitors.
1101 */
1102 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1103 sizeof(ai))) {
1104 codec_dbg(codec,
1105 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
1106 pin_nid,
1107 active_channels, ca);
1108 hdmi_stop_infoframe_trans(codec, pin_nid);
1109 hdmi_fill_audio_infoframe(codec, pin_nid,
1110 ai.bytes, sizeof(ai));
1111 hdmi_start_infoframe_trans(codec, pin_nid);
1112 }
1113 }
1114
1115 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1116 struct hdmi_spec_per_pin *per_pin,
1117 bool non_pcm)
1118 {
1119 struct hdmi_spec *spec = codec->spec;
1120 hda_nid_t pin_nid = per_pin->pin_nid;
1121 int channels = per_pin->channels;
1122 int active_channels;
1123 struct hdmi_eld *eld;
1124 int ca, ordered_ca;
1125
1126 if (!channels)
1127 return;
1128
1129 if (is_haswell_plus(codec))
1130 snd_hda_codec_write(codec, pin_nid, 0,
1131 AC_VERB_SET_AMP_GAIN_MUTE,
1132 AMP_OUT_UNMUTE);
1133
1134 eld = &per_pin->sink_eld;
1135
1136 if (!non_pcm && per_pin->chmap_set)
1137 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1138 else
1139 ca = hdmi_channel_allocation(codec, eld, channels);
1140 if (ca < 0)
1141 ca = 0;
1142
1143 ordered_ca = get_channel_allocation_order(ca);
1144 active_channels = channel_allocations[ordered_ca].channels;
1145
1146 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1147
1148 /*
1149 * always configure channel mapping, it may have been changed by the
1150 * user in the meantime
1151 */
1152 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1153 channels, per_pin->chmap,
1154 per_pin->chmap_set);
1155
1156 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1157 eld->info.conn_type);
1158
1159 per_pin->non_pcm = non_pcm;
1160 }
1161
1162 /*
1163 * Unsolicited events
1164 */
1165
1166 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
1167
1168 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
1169 {
1170 struct hdmi_spec *spec = codec->spec;
1171 int pin_idx = pin_nid_to_pin_index(codec, nid);
1172
1173 if (pin_idx < 0)
1174 return;
1175 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1176 snd_hda_jack_report_sync(codec);
1177 }
1178
1179 static void jack_callback(struct hda_codec *codec,
1180 struct hda_jack_callback *jack)
1181 {
1182 check_presence_and_report(codec, jack->nid);
1183 }
1184
1185 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1186 {
1187 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1188 struct hda_jack_tbl *jack;
1189 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
1190
1191 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1192 if (!jack)
1193 return;
1194 jack->jack_dirty = 1;
1195
1196 codec_dbg(codec,
1197 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
1198 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
1199 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
1200
1201 check_presence_and_report(codec, jack->nid);
1202 }
1203
1204 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1205 {
1206 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1207 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1208 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1209 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1210
1211 codec_info(codec,
1212 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
1213 codec->addr,
1214 tag,
1215 subtag,
1216 cp_state,
1217 cp_ready);
1218
1219 /* TODO */
1220 if (cp_state)
1221 ;
1222 if (cp_ready)
1223 ;
1224 }
1225
1226
1227 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1228 {
1229 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1230 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1231
1232 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
1233 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
1234 return;
1235 }
1236
1237 if (subtag == 0)
1238 hdmi_intrinsic_event(codec, res);
1239 else
1240 hdmi_non_intrinsic_event(codec, res);
1241 }
1242
1243 static void haswell_verify_D0(struct hda_codec *codec,
1244 hda_nid_t cvt_nid, hda_nid_t nid)
1245 {
1246 int pwr;
1247
1248 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1249 * thus pins could only choose converter 0 for use. Make sure the
1250 * converters are in correct power state */
1251 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
1252 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1253
1254 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
1255 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1256 AC_PWRST_D0);
1257 msleep(40);
1258 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1259 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1260 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1261 }
1262 }
1263
1264 /*
1265 * Callbacks
1266 */
1267
1268 /* HBR should be Non-PCM, 8 channels */
1269 #define is_hbr_format(format) \
1270 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1271
1272 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1273 bool hbr)
1274 {
1275 int pinctl, new_pinctl;
1276
1277 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1278 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1279 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1280
1281 if (pinctl < 0)
1282 return hbr ? -EINVAL : 0;
1283
1284 new_pinctl = pinctl & ~AC_PINCTL_EPT;
1285 if (hbr)
1286 new_pinctl |= AC_PINCTL_EPT_HBR;
1287 else
1288 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1289
1290 codec_dbg(codec,
1291 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
1292 pin_nid,
1293 pinctl == new_pinctl ? "" : "new-",
1294 new_pinctl);
1295
1296 if (pinctl != new_pinctl)
1297 snd_hda_codec_write(codec, pin_nid, 0,
1298 AC_VERB_SET_PIN_WIDGET_CONTROL,
1299 new_pinctl);
1300 } else if (hbr)
1301 return -EINVAL;
1302
1303 return 0;
1304 }
1305
1306 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1307 hda_nid_t pin_nid, u32 stream_tag, int format)
1308 {
1309 struct hdmi_spec *spec = codec->spec;
1310 int err;
1311
1312 if (is_haswell_plus(codec))
1313 haswell_verify_D0(codec, cvt_nid, pin_nid);
1314
1315 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1316
1317 if (err) {
1318 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
1319 return err;
1320 }
1321
1322 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
1323 return 0;
1324 }
1325
1326 static int hdmi_choose_cvt(struct hda_codec *codec,
1327 int pin_idx, int *cvt_id, int *mux_id)
1328 {
1329 struct hdmi_spec *spec = codec->spec;
1330 struct hdmi_spec_per_pin *per_pin;
1331 struct hdmi_spec_per_cvt *per_cvt = NULL;
1332 int cvt_idx, mux_idx = 0;
1333
1334 per_pin = get_pin(spec, pin_idx);
1335
1336 /* Dynamically assign converter to stream */
1337 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1338 per_cvt = get_cvt(spec, cvt_idx);
1339
1340 /* Must not already be assigned */
1341 if (per_cvt->assigned)
1342 continue;
1343 /* Must be in pin's mux's list of converters */
1344 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1345 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1346 break;
1347 /* Not in mux list */
1348 if (mux_idx == per_pin->num_mux_nids)
1349 continue;
1350 break;
1351 }
1352
1353 /* No free converters */
1354 if (cvt_idx == spec->num_cvts)
1355 return -ENODEV;
1356
1357 per_pin->mux_idx = mux_idx;
1358
1359 if (cvt_id)
1360 *cvt_id = cvt_idx;
1361 if (mux_id)
1362 *mux_id = mux_idx;
1363
1364 return 0;
1365 }
1366
1367 /* Assure the pin select the right convetor */
1368 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1369 struct hdmi_spec_per_pin *per_pin)
1370 {
1371 hda_nid_t pin_nid = per_pin->pin_nid;
1372 int mux_idx, curr;
1373
1374 mux_idx = per_pin->mux_idx;
1375 curr = snd_hda_codec_read(codec, pin_nid, 0,
1376 AC_VERB_GET_CONNECT_SEL, 0);
1377 if (curr != mux_idx)
1378 snd_hda_codec_write_cache(codec, pin_nid, 0,
1379 AC_VERB_SET_CONNECT_SEL,
1380 mux_idx);
1381 }
1382
1383 /* Intel HDMI workaround to fix audio routing issue:
1384 * For some Intel display codecs, pins share the same connection list.
1385 * So a conveter can be selected by multiple pins and playback on any of these
1386 * pins will generate sound on the external display, because audio flows from
1387 * the same converter to the display pipeline. Also muting one pin may make
1388 * other pins have no sound output.
1389 * So this function assures that an assigned converter for a pin is not selected
1390 * by any other pins.
1391 */
1392 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1393 hda_nid_t pin_nid, int mux_idx)
1394 {
1395 struct hdmi_spec *spec = codec->spec;
1396 hda_nid_t nid;
1397 int cvt_idx, curr;
1398 struct hdmi_spec_per_cvt *per_cvt;
1399
1400 /* configure all pins, including "no physical connection" ones */
1401 for_each_hda_codec_node(nid, codec) {
1402 unsigned int wid_caps = get_wcaps(codec, nid);
1403 unsigned int wid_type = get_wcaps_type(wid_caps);
1404
1405 if (wid_type != AC_WID_PIN)
1406 continue;
1407
1408 if (nid == pin_nid)
1409 continue;
1410
1411 curr = snd_hda_codec_read(codec, nid, 0,
1412 AC_VERB_GET_CONNECT_SEL, 0);
1413 if (curr != mux_idx)
1414 continue;
1415
1416 /* choose an unassigned converter. The conveters in the
1417 * connection list are in the same order as in the codec.
1418 */
1419 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1420 per_cvt = get_cvt(spec, cvt_idx);
1421 if (!per_cvt->assigned) {
1422 codec_dbg(codec,
1423 "choose cvt %d for pin nid %d\n",
1424 cvt_idx, nid);
1425 snd_hda_codec_write_cache(codec, nid, 0,
1426 AC_VERB_SET_CONNECT_SEL,
1427 cvt_idx);
1428 break;
1429 }
1430 }
1431 }
1432 }
1433
1434 /*
1435 * HDA PCM callbacks
1436 */
1437 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1438 struct hda_codec *codec,
1439 struct snd_pcm_substream *substream)
1440 {
1441 struct hdmi_spec *spec = codec->spec;
1442 struct snd_pcm_runtime *runtime = substream->runtime;
1443 int pin_idx, cvt_idx, mux_idx = 0;
1444 struct hdmi_spec_per_pin *per_pin;
1445 struct hdmi_eld *eld;
1446 struct hdmi_spec_per_cvt *per_cvt = NULL;
1447 int err;
1448
1449 /* Validate hinfo */
1450 pin_idx = hinfo_to_pin_index(codec, hinfo);
1451 if (snd_BUG_ON(pin_idx < 0))
1452 return -EINVAL;
1453 per_pin = get_pin(spec, pin_idx);
1454 eld = &per_pin->sink_eld;
1455
1456 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1457 if (err < 0)
1458 return err;
1459
1460 per_cvt = get_cvt(spec, cvt_idx);
1461 /* Claim converter */
1462 per_cvt->assigned = 1;
1463 per_pin->cvt_nid = per_cvt->cvt_nid;
1464 hinfo->nid = per_cvt->cvt_nid;
1465
1466 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1467 AC_VERB_SET_CONNECT_SEL,
1468 mux_idx);
1469
1470 /* configure unused pins to choose other converters */
1471 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
1472 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
1473
1474 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
1475
1476 /* Initially set the converter's capabilities */
1477 hinfo->channels_min = per_cvt->channels_min;
1478 hinfo->channels_max = per_cvt->channels_max;
1479 hinfo->rates = per_cvt->rates;
1480 hinfo->formats = per_cvt->formats;
1481 hinfo->maxbps = per_cvt->maxbps;
1482
1483 /* Restrict capabilities by ELD if this isn't disabled */
1484 if (!static_hdmi_pcm && eld->eld_valid) {
1485 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1486 if (hinfo->channels_min > hinfo->channels_max ||
1487 !hinfo->rates || !hinfo->formats) {
1488 per_cvt->assigned = 0;
1489 hinfo->nid = 0;
1490 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1491 return -ENODEV;
1492 }
1493 }
1494
1495 /* Store the updated parameters */
1496 runtime->hw.channels_min = hinfo->channels_min;
1497 runtime->hw.channels_max = hinfo->channels_max;
1498 runtime->hw.formats = hinfo->formats;
1499 runtime->hw.rates = hinfo->rates;
1500
1501 snd_pcm_hw_constraint_step(substream->runtime, 0,
1502 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1503 return 0;
1504 }
1505
1506 /*
1507 * HDA/HDMI auto parsing
1508 */
1509 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1510 {
1511 struct hdmi_spec *spec = codec->spec;
1512 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1513 hda_nid_t pin_nid = per_pin->pin_nid;
1514
1515 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1516 codec_warn(codec,
1517 "HDMI: pin %d wcaps %#x does not support connection list\n",
1518 pin_nid, get_wcaps(codec, pin_nid));
1519 return -EINVAL;
1520 }
1521
1522 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1523 per_pin->mux_nids,
1524 HDA_MAX_CONNECTIONS);
1525
1526 return 0;
1527 }
1528
1529 /* update per_pin ELD from the given new ELD;
1530 * setup info frame and notification accordingly
1531 */
1532 static void update_eld(struct hda_codec *codec,
1533 struct hdmi_spec_per_pin *per_pin,
1534 struct hdmi_eld *eld)
1535 {
1536 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1537 bool old_eld_valid = pin_eld->eld_valid;
1538 bool eld_changed;
1539
1540 if (eld->eld_valid)
1541 snd_hdmi_show_eld(codec, &eld->info);
1542
1543 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1544 if (eld->eld_valid && pin_eld->eld_valid)
1545 if (pin_eld->eld_size != eld->eld_size ||
1546 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1547 eld->eld_size) != 0)
1548 eld_changed = true;
1549
1550 pin_eld->monitor_present = eld->monitor_present;
1551 pin_eld->eld_valid = eld->eld_valid;
1552 pin_eld->eld_size = eld->eld_size;
1553 if (eld->eld_valid)
1554 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1555 pin_eld->info = eld->info;
1556
1557 /*
1558 * Re-setup pin and infoframe. This is needed e.g. when
1559 * - sink is first plugged-in
1560 * - transcoder can change during stream playback on Haswell
1561 * and this can make HW reset converter selection on a pin.
1562 */
1563 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1564 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1565 intel_verify_pin_cvt_connect(codec, per_pin);
1566 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
1567 per_pin->mux_idx);
1568 }
1569
1570 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1571 }
1572
1573 if (eld_changed)
1574 snd_ctl_notify(codec->card,
1575 SNDRV_CTL_EVENT_MASK_VALUE |
1576 SNDRV_CTL_EVENT_MASK_INFO,
1577 &per_pin->eld_ctl->id);
1578 }
1579
1580 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1581 {
1582 struct hda_jack_tbl *jack;
1583 struct hda_codec *codec = per_pin->codec;
1584 struct hdmi_spec *spec = codec->spec;
1585 struct hdmi_eld *eld = &spec->temp_eld;
1586 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1587 hda_nid_t pin_nid = per_pin->pin_nid;
1588 /*
1589 * Always execute a GetPinSense verb here, even when called from
1590 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1591 * response's PD bit is not the real PD value, but indicates that
1592 * the real PD value changed. An older version of the HD-audio
1593 * specification worked this way. Hence, we just ignore the data in
1594 * the unsolicited response to avoid custom WARs.
1595 */
1596 int present;
1597 bool ret;
1598
1599 snd_hda_power_up_pm(codec);
1600 present = snd_hda_pin_sense(codec, pin_nid);
1601
1602 mutex_lock(&per_pin->lock);
1603 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1604 eld->monitor_present = pin_eld->monitor_present;
1605
1606 if (pin_eld->monitor_present)
1607 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1608 else
1609 eld->eld_valid = false;
1610
1611 codec_dbg(codec,
1612 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1613 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
1614
1615 if (eld->eld_valid) {
1616 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1617 &eld->eld_size) < 0)
1618 eld->eld_valid = false;
1619 else {
1620 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1621 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1622 eld->eld_size) < 0)
1623 eld->eld_valid = false;
1624 }
1625 }
1626
1627 if (!eld->eld_valid && repoll)
1628 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1629 else
1630 update_eld(codec, per_pin, eld);
1631
1632 ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
1633
1634 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1635 if (jack)
1636 jack->block_report = !ret;
1637
1638 mutex_unlock(&per_pin->lock);
1639 snd_hda_power_down_pm(codec);
1640 return ret;
1641 }
1642
1643 static void hdmi_repoll_eld(struct work_struct *work)
1644 {
1645 struct hdmi_spec_per_pin *per_pin =
1646 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1647
1648 if (per_pin->repoll_count++ > 6)
1649 per_pin->repoll_count = 0;
1650
1651 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1652 snd_hda_jack_report_sync(per_pin->codec);
1653 }
1654
1655 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1656 hda_nid_t nid);
1657
1658 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1659 {
1660 struct hdmi_spec *spec = codec->spec;
1661 unsigned int caps, config;
1662 int pin_idx;
1663 struct hdmi_spec_per_pin *per_pin;
1664 int err;
1665
1666 caps = snd_hda_query_pin_caps(codec, pin_nid);
1667 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1668 return 0;
1669
1670 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1671 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1672 return 0;
1673
1674 if (is_haswell_plus(codec))
1675 intel_haswell_fixup_connect_list(codec, pin_nid);
1676
1677 pin_idx = spec->num_pins;
1678 per_pin = snd_array_new(&spec->pins);
1679 if (!per_pin)
1680 return -ENOMEM;
1681
1682 per_pin->pin_nid = pin_nid;
1683 per_pin->non_pcm = false;
1684
1685 err = hdmi_read_pin_conn(codec, pin_idx);
1686 if (err < 0)
1687 return err;
1688
1689 spec->num_pins++;
1690
1691 return 0;
1692 }
1693
1694 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1695 {
1696 struct hdmi_spec *spec = codec->spec;
1697 struct hdmi_spec_per_cvt *per_cvt;
1698 unsigned int chans;
1699 int err;
1700
1701 chans = get_wcaps(codec, cvt_nid);
1702 chans = get_wcaps_channels(chans);
1703
1704 per_cvt = snd_array_new(&spec->cvts);
1705 if (!per_cvt)
1706 return -ENOMEM;
1707
1708 per_cvt->cvt_nid = cvt_nid;
1709 per_cvt->channels_min = 2;
1710 if (chans <= 16) {
1711 per_cvt->channels_max = chans;
1712 if (chans > spec->channels_max)
1713 spec->channels_max = chans;
1714 }
1715
1716 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1717 &per_cvt->rates,
1718 &per_cvt->formats,
1719 &per_cvt->maxbps);
1720 if (err < 0)
1721 return err;
1722
1723 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1724 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1725 spec->num_cvts++;
1726
1727 return 0;
1728 }
1729
1730 static int hdmi_parse_codec(struct hda_codec *codec)
1731 {
1732 hda_nid_t nid;
1733 int i, nodes;
1734
1735 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1736 if (!nid || nodes < 0) {
1737 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1738 return -EINVAL;
1739 }
1740
1741 for (i = 0; i < nodes; i++, nid++) {
1742 unsigned int caps;
1743 unsigned int type;
1744
1745 caps = get_wcaps(codec, nid);
1746 type = get_wcaps_type(caps);
1747
1748 if (!(caps & AC_WCAP_DIGITAL))
1749 continue;
1750
1751 switch (type) {
1752 case AC_WID_AUD_OUT:
1753 hdmi_add_cvt(codec, nid);
1754 break;
1755 case AC_WID_PIN:
1756 hdmi_add_pin(codec, nid);
1757 break;
1758 }
1759 }
1760
1761 return 0;
1762 }
1763
1764 /*
1765 */
1766 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1767 {
1768 struct hda_spdif_out *spdif;
1769 bool non_pcm;
1770
1771 mutex_lock(&codec->spdif_mutex);
1772 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1773 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1774 mutex_unlock(&codec->spdif_mutex);
1775 return non_pcm;
1776 }
1777
1778
1779 /*
1780 * HDMI callbacks
1781 */
1782
1783 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1784 struct hda_codec *codec,
1785 unsigned int stream_tag,
1786 unsigned int format,
1787 struct snd_pcm_substream *substream)
1788 {
1789 hda_nid_t cvt_nid = hinfo->nid;
1790 struct hdmi_spec *spec = codec->spec;
1791 int pin_idx = hinfo_to_pin_index(codec, hinfo);
1792 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1793 hda_nid_t pin_nid = per_pin->pin_nid;
1794 bool non_pcm;
1795 int pinctl;
1796
1797 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1798 /* Verify pin:cvt selections to avoid silent audio after S3.
1799 * After S3, the audio driver restores pin:cvt selections
1800 * but this can happen before gfx is ready and such selection
1801 * is overlooked by HW. Thus multiple pins can share a same
1802 * default convertor and mute control will affect each other,
1803 * which can cause a resumed audio playback become silent
1804 * after S3.
1805 */
1806 intel_verify_pin_cvt_connect(codec, per_pin);
1807 intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
1808 }
1809
1810 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1811 mutex_lock(&per_pin->lock);
1812 per_pin->channels = substream->runtime->channels;
1813 per_pin->setup = true;
1814
1815 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1816 mutex_unlock(&per_pin->lock);
1817
1818 if (spec->dyn_pin_out) {
1819 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1820 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1821 snd_hda_codec_write(codec, pin_nid, 0,
1822 AC_VERB_SET_PIN_WIDGET_CONTROL,
1823 pinctl | PIN_OUT);
1824 }
1825
1826 return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
1827 }
1828
1829 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1830 struct hda_codec *codec,
1831 struct snd_pcm_substream *substream)
1832 {
1833 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1834 return 0;
1835 }
1836
1837 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1838 struct hda_codec *codec,
1839 struct snd_pcm_substream *substream)
1840 {
1841 struct hdmi_spec *spec = codec->spec;
1842 int cvt_idx, pin_idx;
1843 struct hdmi_spec_per_cvt *per_cvt;
1844 struct hdmi_spec_per_pin *per_pin;
1845 int pinctl;
1846
1847 if (hinfo->nid) {
1848 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1849 if (snd_BUG_ON(cvt_idx < 0))
1850 return -EINVAL;
1851 per_cvt = get_cvt(spec, cvt_idx);
1852
1853 snd_BUG_ON(!per_cvt->assigned);
1854 per_cvt->assigned = 0;
1855 hinfo->nid = 0;
1856
1857 pin_idx = hinfo_to_pin_index(codec, hinfo);
1858 if (snd_BUG_ON(pin_idx < 0))
1859 return -EINVAL;
1860 per_pin = get_pin(spec, pin_idx);
1861
1862 if (spec->dyn_pin_out) {
1863 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1864 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1865 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1866 AC_VERB_SET_PIN_WIDGET_CONTROL,
1867 pinctl & ~PIN_OUT);
1868 }
1869
1870 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1871
1872 mutex_lock(&per_pin->lock);
1873 per_pin->chmap_set = false;
1874 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1875
1876 per_pin->setup = false;
1877 per_pin->channels = 0;
1878 mutex_unlock(&per_pin->lock);
1879 }
1880
1881 return 0;
1882 }
1883
1884 static const struct hda_pcm_ops generic_ops = {
1885 .open = hdmi_pcm_open,
1886 .close = hdmi_pcm_close,
1887 .prepare = generic_hdmi_playback_pcm_prepare,
1888 .cleanup = generic_hdmi_playback_pcm_cleanup,
1889 };
1890
1891 /*
1892 * ALSA API channel-map control callbacks
1893 */
1894 static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1895 struct snd_ctl_elem_info *uinfo)
1896 {
1897 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1898 struct hda_codec *codec = info->private_data;
1899 struct hdmi_spec *spec = codec->spec;
1900 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1901 uinfo->count = spec->channels_max;
1902 uinfo->value.integer.min = 0;
1903 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1904 return 0;
1905 }
1906
1907 static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
1908 int channels)
1909 {
1910 /* If the speaker allocation matches the channel count, it is OK.*/
1911 if (cap->channels != channels)
1912 return -1;
1913
1914 /* all channels are remappable freely */
1915 return SNDRV_CTL_TLVT_CHMAP_VAR;
1916 }
1917
1918 static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
1919 unsigned int *chmap, int channels)
1920 {
1921 int count = 0;
1922 int c;
1923
1924 for (c = 7; c >= 0; c--) {
1925 int spk = cap->speakers[c];
1926 if (!spk)
1927 continue;
1928
1929 chmap[count++] = spk_to_chmap(spk);
1930 }
1931
1932 WARN_ON(count != channels);
1933 }
1934
1935 static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1936 unsigned int size, unsigned int __user *tlv)
1937 {
1938 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1939 struct hda_codec *codec = info->private_data;
1940 struct hdmi_spec *spec = codec->spec;
1941 unsigned int __user *dst;
1942 int chs, count = 0;
1943
1944 if (size < 8)
1945 return -ENOMEM;
1946 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1947 return -EFAULT;
1948 size -= 8;
1949 dst = tlv + 2;
1950 for (chs = 2; chs <= spec->channels_max; chs++) {
1951 int i;
1952 struct cea_channel_speaker_allocation *cap;
1953 cap = channel_allocations;
1954 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1955 int chs_bytes = chs * 4;
1956 int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
1957 unsigned int tlv_chmap[8];
1958
1959 if (type < 0)
1960 continue;
1961 if (size < 8)
1962 return -ENOMEM;
1963 if (put_user(type, dst) ||
1964 put_user(chs_bytes, dst + 1))
1965 return -EFAULT;
1966 dst += 2;
1967 size -= 8;
1968 count += 8;
1969 if (size < chs_bytes)
1970 return -ENOMEM;
1971 size -= chs_bytes;
1972 count += chs_bytes;
1973 spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
1974 if (copy_to_user(dst, tlv_chmap, chs_bytes))
1975 return -EFAULT;
1976 dst += chs;
1977 }
1978 }
1979 if (put_user(count, tlv + 1))
1980 return -EFAULT;
1981 return 0;
1982 }
1983
1984 static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1985 struct snd_ctl_elem_value *ucontrol)
1986 {
1987 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1988 struct hda_codec *codec = info->private_data;
1989 struct hdmi_spec *spec = codec->spec;
1990 int pin_idx = kcontrol->private_value;
1991 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1992 int i;
1993
1994 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1995 ucontrol->value.integer.value[i] = per_pin->chmap[i];
1996 return 0;
1997 }
1998
1999 static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
2000 struct snd_ctl_elem_value *ucontrol)
2001 {
2002 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2003 struct hda_codec *codec = info->private_data;
2004 struct hdmi_spec *spec = codec->spec;
2005 int pin_idx = kcontrol->private_value;
2006 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2007 unsigned int ctl_idx;
2008 struct snd_pcm_substream *substream;
2009 unsigned char chmap[8];
2010 int i, err, ca, prepared = 0;
2011
2012 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2013 substream = snd_pcm_chmap_substream(info, ctl_idx);
2014 if (!substream || !substream->runtime)
2015 return 0; /* just for avoiding error from alsactl restore */
2016 switch (substream->runtime->status->state) {
2017 case SNDRV_PCM_STATE_OPEN:
2018 case SNDRV_PCM_STATE_SETUP:
2019 break;
2020 case SNDRV_PCM_STATE_PREPARED:
2021 prepared = 1;
2022 break;
2023 default:
2024 return -EBUSY;
2025 }
2026 memset(chmap, 0, sizeof(chmap));
2027 for (i = 0; i < ARRAY_SIZE(chmap); i++)
2028 chmap[i] = ucontrol->value.integer.value[i];
2029 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
2030 return 0;
2031 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
2032 if (ca < 0)
2033 return -EINVAL;
2034 if (spec->ops.chmap_validate) {
2035 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
2036 if (err)
2037 return err;
2038 }
2039 mutex_lock(&per_pin->lock);
2040 per_pin->chmap_set = true;
2041 memcpy(per_pin->chmap, chmap, sizeof(chmap));
2042 if (prepared)
2043 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2044 mutex_unlock(&per_pin->lock);
2045
2046 return 0;
2047 }
2048
2049 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2050 {
2051 struct hdmi_spec *spec = codec->spec;
2052 int pin_idx;
2053
2054 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2055 struct hda_pcm *info;
2056 struct hda_pcm_stream *pstr;
2057 struct hdmi_spec_per_pin *per_pin;
2058
2059 per_pin = get_pin(spec, pin_idx);
2060 info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx);
2061 if (!info)
2062 return -ENOMEM;
2063 spec->pcm_rec[pin_idx] = info;
2064 info->pcm_type = HDA_PCM_TYPE_HDMI;
2065 info->own_chmap = true;
2066
2067 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2068 pstr->substreams = 1;
2069 pstr->ops = generic_ops;
2070 /* other pstr fields are set in open */
2071 }
2072
2073 return 0;
2074 }
2075
2076 static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
2077 {
2078 char hdmi_str[32] = "HDMI/DP";
2079 struct hdmi_spec *spec = codec->spec;
2080 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2081 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
2082
2083 if (pcmdev > 0)
2084 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2085 if (!is_jack_detectable(codec, per_pin->pin_nid))
2086 strncat(hdmi_str, " Phantom",
2087 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2088
2089 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
2090 }
2091
2092 static int generic_hdmi_build_controls(struct hda_codec *codec)
2093 {
2094 struct hdmi_spec *spec = codec->spec;
2095 int err;
2096 int pin_idx;
2097
2098 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2099 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2100
2101 err = generic_hdmi_build_jack(codec, pin_idx);
2102 if (err < 0)
2103 return err;
2104
2105 err = snd_hda_create_dig_out_ctls(codec,
2106 per_pin->pin_nid,
2107 per_pin->mux_nids[0],
2108 HDA_PCM_TYPE_HDMI);
2109 if (err < 0)
2110 return err;
2111 snd_hda_spdif_ctls_unassign(codec, pin_idx);
2112
2113 /* add control for ELD Bytes */
2114 err = hdmi_create_eld_ctl(codec, pin_idx,
2115 get_pcm_rec(spec, pin_idx)->device);
2116
2117 if (err < 0)
2118 return err;
2119
2120 hdmi_present_sense(per_pin, 0);
2121 }
2122
2123 /* add channel maps */
2124 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2125 struct hda_pcm *pcm;
2126 struct snd_pcm_chmap *chmap;
2127 struct snd_kcontrol *kctl;
2128 int i;
2129
2130 pcm = spec->pcm_rec[pin_idx];
2131 if (!pcm || !pcm->pcm)
2132 break;
2133 err = snd_pcm_add_chmap_ctls(pcm->pcm,
2134 SNDRV_PCM_STREAM_PLAYBACK,
2135 NULL, 0, pin_idx, &chmap);
2136 if (err < 0)
2137 return err;
2138 /* override handlers */
2139 chmap->private_data = codec;
2140 kctl = chmap->kctl;
2141 for (i = 0; i < kctl->count; i++)
2142 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2143 kctl->info = hdmi_chmap_ctl_info;
2144 kctl->get = hdmi_chmap_ctl_get;
2145 kctl->put = hdmi_chmap_ctl_put;
2146 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2147 }
2148
2149 return 0;
2150 }
2151
2152 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2153 {
2154 struct hdmi_spec *spec = codec->spec;
2155 int pin_idx;
2156
2157 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2158 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2159
2160 per_pin->codec = codec;
2161 mutex_init(&per_pin->lock);
2162 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2163 eld_proc_new(per_pin, pin_idx);
2164 }
2165 return 0;
2166 }
2167
2168 static int generic_hdmi_init(struct hda_codec *codec)
2169 {
2170 struct hdmi_spec *spec = codec->spec;
2171 int pin_idx;
2172
2173 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2174 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2175 hda_nid_t pin_nid = per_pin->pin_nid;
2176
2177 hdmi_init_pin(codec, pin_nid);
2178 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2179 codec->jackpoll_interval > 0 ? jack_callback : NULL);
2180 }
2181 return 0;
2182 }
2183
2184 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2185 {
2186 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2187 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2188 }
2189
2190 static void hdmi_array_free(struct hdmi_spec *spec)
2191 {
2192 snd_array_free(&spec->pins);
2193 snd_array_free(&spec->cvts);
2194 }
2195
2196 static void generic_hdmi_free(struct hda_codec *codec)
2197 {
2198 struct hdmi_spec *spec = codec->spec;
2199 int pin_idx;
2200
2201 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2202 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2203
2204 cancel_delayed_work_sync(&per_pin->work);
2205 eld_proc_free(per_pin);
2206 }
2207
2208 hdmi_array_free(spec);
2209 kfree(spec);
2210 }
2211
2212 #ifdef CONFIG_PM
2213 static int generic_hdmi_resume(struct hda_codec *codec)
2214 {
2215 struct hdmi_spec *spec = codec->spec;
2216 int pin_idx;
2217
2218 codec->patch_ops.init(codec);
2219 regcache_sync(codec->core.regmap);
2220
2221 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2222 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2223 hdmi_present_sense(per_pin, 1);
2224 }
2225 return 0;
2226 }
2227 #endif
2228
2229 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2230 .init = generic_hdmi_init,
2231 .free = generic_hdmi_free,
2232 .build_pcms = generic_hdmi_build_pcms,
2233 .build_controls = generic_hdmi_build_controls,
2234 .unsol_event = hdmi_unsol_event,
2235 #ifdef CONFIG_PM
2236 .resume = generic_hdmi_resume,
2237 #endif
2238 };
2239
2240 static const struct hdmi_ops generic_standard_hdmi_ops = {
2241 .pin_get_eld = snd_hdmi_get_eld,
2242 .pin_get_slot_channel = hdmi_pin_get_slot_channel,
2243 .pin_set_slot_channel = hdmi_pin_set_slot_channel,
2244 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2245 .pin_hbr_setup = hdmi_pin_hbr_setup,
2246 .setup_stream = hdmi_setup_stream,
2247 .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type,
2248 .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap,
2249 };
2250
2251
2252 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2253 hda_nid_t nid)
2254 {
2255 struct hdmi_spec *spec = codec->spec;
2256 hda_nid_t conns[4];
2257 int nconns;
2258
2259 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2260 if (nconns == spec->num_cvts &&
2261 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2262 return;
2263
2264 /* override pins connection list */
2265 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2266 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2267 }
2268
2269 #define INTEL_VENDOR_NID 0x08
2270 #define INTEL_GET_VENDOR_VERB 0xf81
2271 #define INTEL_SET_VENDOR_VERB 0x781
2272 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2273 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2274
2275 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2276 bool update_tree)
2277 {
2278 unsigned int vendor_param;
2279
2280 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2281 INTEL_GET_VENDOR_VERB, 0);
2282 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2283 return;
2284
2285 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2286 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2287 INTEL_SET_VENDOR_VERB, vendor_param);
2288 if (vendor_param == -1)
2289 return;
2290
2291 if (update_tree)
2292 snd_hda_codec_update_widgets(codec);
2293 }
2294
2295 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2296 {
2297 unsigned int vendor_param;
2298
2299 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2300 INTEL_GET_VENDOR_VERB, 0);
2301 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2302 return;
2303
2304 /* enable DP1.2 mode */
2305 vendor_param |= INTEL_EN_DP12;
2306 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2307 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2308 INTEL_SET_VENDOR_VERB, vendor_param);
2309 }
2310
2311 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2312 * Otherwise you may get severe h/w communication errors.
2313 */
2314 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2315 unsigned int power_state)
2316 {
2317 if (power_state == AC_PWRST_D0) {
2318 intel_haswell_enable_all_pins(codec, false);
2319 intel_haswell_fixup_enable_dp12(codec);
2320 }
2321
2322 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2323 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2324 }
2325
2326 static int patch_generic_hdmi(struct hda_codec *codec)
2327 {
2328 struct hdmi_spec *spec;
2329
2330 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2331 if (spec == NULL)
2332 return -ENOMEM;
2333
2334 spec->ops = generic_standard_hdmi_ops;
2335 codec->spec = spec;
2336 hdmi_array_init(spec, 4);
2337
2338 if (is_haswell_plus(codec)) {
2339 intel_haswell_enable_all_pins(codec, true);
2340 intel_haswell_fixup_enable_dp12(codec);
2341 }
2342
2343 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2344 codec->depop_delay = 0;
2345
2346 if (hdmi_parse_codec(codec) < 0) {
2347 codec->spec = NULL;
2348 kfree(spec);
2349 return -EINVAL;
2350 }
2351 codec->patch_ops = generic_hdmi_patch_ops;
2352 if (is_haswell_plus(codec)) {
2353 codec->patch_ops.set_power_state = haswell_set_power_state;
2354 codec->dp_mst = true;
2355 }
2356
2357 generic_hdmi_init_per_pins(codec);
2358
2359 init_channel_allocations();
2360
2361 return 0;
2362 }
2363
2364 /*
2365 * Shared non-generic implementations
2366 */
2367
2368 static int simple_playback_build_pcms(struct hda_codec *codec)
2369 {
2370 struct hdmi_spec *spec = codec->spec;
2371 struct hda_pcm *info;
2372 unsigned int chans;
2373 struct hda_pcm_stream *pstr;
2374 struct hdmi_spec_per_cvt *per_cvt;
2375
2376 per_cvt = get_cvt(spec, 0);
2377 chans = get_wcaps(codec, per_cvt->cvt_nid);
2378 chans = get_wcaps_channels(chans);
2379
2380 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2381 if (!info)
2382 return -ENOMEM;
2383 spec->pcm_rec[0] = info;
2384 info->pcm_type = HDA_PCM_TYPE_HDMI;
2385 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2386 *pstr = spec->pcm_playback;
2387 pstr->nid = per_cvt->cvt_nid;
2388 if (pstr->channels_max <= 2 && chans && chans <= 16)
2389 pstr->channels_max = chans;
2390
2391 return 0;
2392 }
2393
2394 /* unsolicited event for jack sensing */
2395 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2396 unsigned int res)
2397 {
2398 snd_hda_jack_set_dirty_all(codec);
2399 snd_hda_jack_report_sync(codec);
2400 }
2401
2402 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2403 * as long as spec->pins[] is set correctly
2404 */
2405 #define simple_hdmi_build_jack generic_hdmi_build_jack
2406
2407 static int simple_playback_build_controls(struct hda_codec *codec)
2408 {
2409 struct hdmi_spec *spec = codec->spec;
2410 struct hdmi_spec_per_cvt *per_cvt;
2411 int err;
2412
2413 per_cvt = get_cvt(spec, 0);
2414 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2415 per_cvt->cvt_nid,
2416 HDA_PCM_TYPE_HDMI);
2417 if (err < 0)
2418 return err;
2419 return simple_hdmi_build_jack(codec, 0);
2420 }
2421
2422 static int simple_playback_init(struct hda_codec *codec)
2423 {
2424 struct hdmi_spec *spec = codec->spec;
2425 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2426 hda_nid_t pin = per_pin->pin_nid;
2427
2428 snd_hda_codec_write(codec, pin, 0,
2429 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2430 /* some codecs require to unmute the pin */
2431 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2432 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2433 AMP_OUT_UNMUTE);
2434 snd_hda_jack_detect_enable(codec, pin);
2435 return 0;
2436 }
2437
2438 static void simple_playback_free(struct hda_codec *codec)
2439 {
2440 struct hdmi_spec *spec = codec->spec;
2441
2442 hdmi_array_free(spec);
2443 kfree(spec);
2444 }
2445
2446 /*
2447 * Nvidia specific implementations
2448 */
2449
2450 #define Nv_VERB_SET_Channel_Allocation 0xF79
2451 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2452 #define Nv_VERB_SET_Audio_Protection_On 0xF98
2453 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
2454
2455 #define nvhdmi_master_con_nid_7x 0x04
2456 #define nvhdmi_master_pin_nid_7x 0x05
2457
2458 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2459 /*front, rear, clfe, rear_surr */
2460 0x6, 0x8, 0xa, 0xc,
2461 };
2462
2463 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2464 /* set audio protect on */
2465 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2466 /* enable digital output on pin widget */
2467 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2468 {} /* terminator */
2469 };
2470
2471 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2472 /* set audio protect on */
2473 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2474 /* enable digital output on pin widget */
2475 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2476 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2477 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2478 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2479 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2480 {} /* terminator */
2481 };
2482
2483 #ifdef LIMITED_RATE_FMT_SUPPORT
2484 /* support only the safe format and rate */
2485 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2486 #define SUPPORTED_MAXBPS 16
2487 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2488 #else
2489 /* support all rates and formats */
2490 #define SUPPORTED_RATES \
2491 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2492 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2493 SNDRV_PCM_RATE_192000)
2494 #define SUPPORTED_MAXBPS 24
2495 #define SUPPORTED_FORMATS \
2496 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2497 #endif
2498
2499 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2500 {
2501 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2502 return 0;
2503 }
2504
2505 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2506 {
2507 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2508 return 0;
2509 }
2510
2511 static unsigned int channels_2_6_8[] = {
2512 2, 6, 8
2513 };
2514
2515 static unsigned int channels_2_8[] = {
2516 2, 8
2517 };
2518
2519 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2520 .count = ARRAY_SIZE(channels_2_6_8),
2521 .list = channels_2_6_8,
2522 .mask = 0,
2523 };
2524
2525 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2526 .count = ARRAY_SIZE(channels_2_8),
2527 .list = channels_2_8,
2528 .mask = 0,
2529 };
2530
2531 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2532 struct hda_codec *codec,
2533 struct snd_pcm_substream *substream)
2534 {
2535 struct hdmi_spec *spec = codec->spec;
2536 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2537
2538 switch (codec->preset->id) {
2539 case 0x10de0002:
2540 case 0x10de0003:
2541 case 0x10de0005:
2542 case 0x10de0006:
2543 hw_constraints_channels = &hw_constraints_2_8_channels;
2544 break;
2545 case 0x10de0007:
2546 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2547 break;
2548 default:
2549 break;
2550 }
2551
2552 if (hw_constraints_channels != NULL) {
2553 snd_pcm_hw_constraint_list(substream->runtime, 0,
2554 SNDRV_PCM_HW_PARAM_CHANNELS,
2555 hw_constraints_channels);
2556 } else {
2557 snd_pcm_hw_constraint_step(substream->runtime, 0,
2558 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2559 }
2560
2561 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2562 }
2563
2564 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2565 struct hda_codec *codec,
2566 struct snd_pcm_substream *substream)
2567 {
2568 struct hdmi_spec *spec = codec->spec;
2569 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2570 }
2571
2572 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2573 struct hda_codec *codec,
2574 unsigned int stream_tag,
2575 unsigned int format,
2576 struct snd_pcm_substream *substream)
2577 {
2578 struct hdmi_spec *spec = codec->spec;
2579 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2580 stream_tag, format, substream);
2581 }
2582
2583 static const struct hda_pcm_stream simple_pcm_playback = {
2584 .substreams = 1,
2585 .channels_min = 2,
2586 .channels_max = 2,
2587 .ops = {
2588 .open = simple_playback_pcm_open,
2589 .close = simple_playback_pcm_close,
2590 .prepare = simple_playback_pcm_prepare
2591 },
2592 };
2593
2594 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2595 .build_controls = simple_playback_build_controls,
2596 .build_pcms = simple_playback_build_pcms,
2597 .init = simple_playback_init,
2598 .free = simple_playback_free,
2599 .unsol_event = simple_hdmi_unsol_event,
2600 };
2601
2602 static int patch_simple_hdmi(struct hda_codec *codec,
2603 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2604 {
2605 struct hdmi_spec *spec;
2606 struct hdmi_spec_per_cvt *per_cvt;
2607 struct hdmi_spec_per_pin *per_pin;
2608
2609 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2610 if (!spec)
2611 return -ENOMEM;
2612
2613 codec->spec = spec;
2614 hdmi_array_init(spec, 1);
2615
2616 spec->multiout.num_dacs = 0; /* no analog */
2617 spec->multiout.max_channels = 2;
2618 spec->multiout.dig_out_nid = cvt_nid;
2619 spec->num_cvts = 1;
2620 spec->num_pins = 1;
2621 per_pin = snd_array_new(&spec->pins);
2622 per_cvt = snd_array_new(&spec->cvts);
2623 if (!per_pin || !per_cvt) {
2624 simple_playback_free(codec);
2625 return -ENOMEM;
2626 }
2627 per_cvt->cvt_nid = cvt_nid;
2628 per_pin->pin_nid = pin_nid;
2629 spec->pcm_playback = simple_pcm_playback;
2630
2631 codec->patch_ops = simple_hdmi_patch_ops;
2632
2633 return 0;
2634 }
2635
2636 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2637 int channels)
2638 {
2639 unsigned int chanmask;
2640 int chan = channels ? (channels - 1) : 1;
2641
2642 switch (channels) {
2643 default:
2644 case 0:
2645 case 2:
2646 chanmask = 0x00;
2647 break;
2648 case 4:
2649 chanmask = 0x08;
2650 break;
2651 case 6:
2652 chanmask = 0x0b;
2653 break;
2654 case 8:
2655 chanmask = 0x13;
2656 break;
2657 }
2658
2659 /* Set the audio infoframe channel allocation and checksum fields. The
2660 * channel count is computed implicitly by the hardware. */
2661 snd_hda_codec_write(codec, 0x1, 0,
2662 Nv_VERB_SET_Channel_Allocation, chanmask);
2663
2664 snd_hda_codec_write(codec, 0x1, 0,
2665 Nv_VERB_SET_Info_Frame_Checksum,
2666 (0x71 - chan - chanmask));
2667 }
2668
2669 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2670 struct hda_codec *codec,
2671 struct snd_pcm_substream *substream)
2672 {
2673 struct hdmi_spec *spec = codec->spec;
2674 int i;
2675
2676 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2677 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2678 for (i = 0; i < 4; i++) {
2679 /* set the stream id */
2680 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2681 AC_VERB_SET_CHANNEL_STREAMID, 0);
2682 /* set the stream format */
2683 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2684 AC_VERB_SET_STREAM_FORMAT, 0);
2685 }
2686
2687 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2688 * streams are disabled. */
2689 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2690
2691 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2692 }
2693
2694 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2695 struct hda_codec *codec,
2696 unsigned int stream_tag,
2697 unsigned int format,
2698 struct snd_pcm_substream *substream)
2699 {
2700 int chs;
2701 unsigned int dataDCC2, channel_id;
2702 int i;
2703 struct hdmi_spec *spec = codec->spec;
2704 struct hda_spdif_out *spdif;
2705 struct hdmi_spec_per_cvt *per_cvt;
2706
2707 mutex_lock(&codec->spdif_mutex);
2708 per_cvt = get_cvt(spec, 0);
2709 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2710
2711 chs = substream->runtime->channels;
2712
2713 dataDCC2 = 0x2;
2714
2715 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2716 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2717 snd_hda_codec_write(codec,
2718 nvhdmi_master_con_nid_7x,
2719 0,
2720 AC_VERB_SET_DIGI_CONVERT_1,
2721 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2722
2723 /* set the stream id */
2724 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2725 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2726
2727 /* set the stream format */
2728 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2729 AC_VERB_SET_STREAM_FORMAT, format);
2730
2731 /* turn on again (if needed) */
2732 /* enable and set the channel status audio/data flag */
2733 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
2734 snd_hda_codec_write(codec,
2735 nvhdmi_master_con_nid_7x,
2736 0,
2737 AC_VERB_SET_DIGI_CONVERT_1,
2738 spdif->ctls & 0xff);
2739 snd_hda_codec_write(codec,
2740 nvhdmi_master_con_nid_7x,
2741 0,
2742 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2743 }
2744
2745 for (i = 0; i < 4; i++) {
2746 if (chs == 2)
2747 channel_id = 0;
2748 else
2749 channel_id = i * 2;
2750
2751 /* turn off SPDIF once;
2752 *otherwise the IEC958 bits won't be updated
2753 */
2754 if (codec->spdif_status_reset &&
2755 (spdif->ctls & AC_DIG1_ENABLE))
2756 snd_hda_codec_write(codec,
2757 nvhdmi_con_nids_7x[i],
2758 0,
2759 AC_VERB_SET_DIGI_CONVERT_1,
2760 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2761 /* set the stream id */
2762 snd_hda_codec_write(codec,
2763 nvhdmi_con_nids_7x[i],
2764 0,
2765 AC_VERB_SET_CHANNEL_STREAMID,
2766 (stream_tag << 4) | channel_id);
2767 /* set the stream format */
2768 snd_hda_codec_write(codec,
2769 nvhdmi_con_nids_7x[i],
2770 0,
2771 AC_VERB_SET_STREAM_FORMAT,
2772 format);
2773 /* turn on again (if needed) */
2774 /* enable and set the channel status audio/data flag */
2775 if (codec->spdif_status_reset &&
2776 (spdif->ctls & AC_DIG1_ENABLE)) {
2777 snd_hda_codec_write(codec,
2778 nvhdmi_con_nids_7x[i],
2779 0,
2780 AC_VERB_SET_DIGI_CONVERT_1,
2781 spdif->ctls & 0xff);
2782 snd_hda_codec_write(codec,
2783 nvhdmi_con_nids_7x[i],
2784 0,
2785 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2786 }
2787 }
2788
2789 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
2790
2791 mutex_unlock(&codec->spdif_mutex);
2792 return 0;
2793 }
2794
2795 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
2796 .substreams = 1,
2797 .channels_min = 2,
2798 .channels_max = 8,
2799 .nid = nvhdmi_master_con_nid_7x,
2800 .rates = SUPPORTED_RATES,
2801 .maxbps = SUPPORTED_MAXBPS,
2802 .formats = SUPPORTED_FORMATS,
2803 .ops = {
2804 .open = simple_playback_pcm_open,
2805 .close = nvhdmi_8ch_7x_pcm_close,
2806 .prepare = nvhdmi_8ch_7x_pcm_prepare
2807 },
2808 };
2809
2810 static int patch_nvhdmi_2ch(struct hda_codec *codec)
2811 {
2812 struct hdmi_spec *spec;
2813 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2814 nvhdmi_master_pin_nid_7x);
2815 if (err < 0)
2816 return err;
2817
2818 codec->patch_ops.init = nvhdmi_7x_init_2ch;
2819 /* override the PCM rates, etc, as the codec doesn't give full list */
2820 spec = codec->spec;
2821 spec->pcm_playback.rates = SUPPORTED_RATES;
2822 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2823 spec->pcm_playback.formats = SUPPORTED_FORMATS;
2824 return 0;
2825 }
2826
2827 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2828 {
2829 struct hdmi_spec *spec = codec->spec;
2830 int err = simple_playback_build_pcms(codec);
2831 if (!err) {
2832 struct hda_pcm *info = get_pcm_rec(spec, 0);
2833 info->own_chmap = true;
2834 }
2835 return err;
2836 }
2837
2838 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2839 {
2840 struct hdmi_spec *spec = codec->spec;
2841 struct hda_pcm *info;
2842 struct snd_pcm_chmap *chmap;
2843 int err;
2844
2845 err = simple_playback_build_controls(codec);
2846 if (err < 0)
2847 return err;
2848
2849 /* add channel maps */
2850 info = get_pcm_rec(spec, 0);
2851 err = snd_pcm_add_chmap_ctls(info->pcm,
2852 SNDRV_PCM_STREAM_PLAYBACK,
2853 snd_pcm_alt_chmaps, 8, 0, &chmap);
2854 if (err < 0)
2855 return err;
2856 switch (codec->preset->id) {
2857 case 0x10de0002:
2858 case 0x10de0003:
2859 case 0x10de0005:
2860 case 0x10de0006:
2861 chmap->channel_mask = (1U << 2) | (1U << 8);
2862 break;
2863 case 0x10de0007:
2864 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2865 }
2866 return 0;
2867 }
2868
2869 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2870 {
2871 struct hdmi_spec *spec;
2872 int err = patch_nvhdmi_2ch(codec);
2873 if (err < 0)
2874 return err;
2875 spec = codec->spec;
2876 spec->multiout.max_channels = 8;
2877 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
2878 codec->patch_ops.init = nvhdmi_7x_init_8ch;
2879 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2880 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
2881
2882 /* Initialize the audio infoframe channel mask and checksum to something
2883 * valid */
2884 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2885
2886 return 0;
2887 }
2888
2889 /*
2890 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
2891 * - 0x10de0015
2892 * - 0x10de0040
2893 */
2894 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
2895 int channels)
2896 {
2897 if (cap->ca_index == 0x00 && channels == 2)
2898 return SNDRV_CTL_TLVT_CHMAP_FIXED;
2899
2900 return hdmi_chmap_cea_alloc_validate_get_type(cap, channels);
2901 }
2902
2903 static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
2904 {
2905 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
2906 return -EINVAL;
2907
2908 return 0;
2909 }
2910
2911 static int patch_nvhdmi(struct hda_codec *codec)
2912 {
2913 struct hdmi_spec *spec;
2914 int err;
2915
2916 err = patch_generic_hdmi(codec);
2917 if (err)
2918 return err;
2919
2920 spec = codec->spec;
2921 spec->dyn_pin_out = true;
2922
2923 spec->ops.chmap_cea_alloc_validate_get_type =
2924 nvhdmi_chmap_cea_alloc_validate_get_type;
2925 spec->ops.chmap_validate = nvhdmi_chmap_validate;
2926
2927 return 0;
2928 }
2929
2930 /*
2931 * ATI/AMD-specific implementations
2932 */
2933
2934 #define is_amdhdmi_rev3_or_later(codec) \
2935 ((codec)->core.vendor_id == 0x1002aa01 && \
2936 ((codec)->core.revision_id & 0xff00) >= 0x0300)
2937 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
2938
2939 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
2940 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
2941 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
2942 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
2943 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
2944 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
2945 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
2946 #define ATI_VERB_SET_HBR_CONTROL 0x77c
2947 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
2948 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
2949 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
2950 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
2951 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
2952 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
2953 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
2954 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
2955 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
2956 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
2957 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
2958 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
2959 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
2960 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
2961 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
2962 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
2963 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
2964
2965 /* AMD specific HDA cvt verbs */
2966 #define ATI_VERB_SET_RAMP_RATE 0x770
2967 #define ATI_VERB_GET_RAMP_RATE 0xf70
2968
2969 #define ATI_OUT_ENABLE 0x1
2970
2971 #define ATI_MULTICHANNEL_MODE_PAIRED 0
2972 #define ATI_MULTICHANNEL_MODE_SINGLE 1
2973
2974 #define ATI_HBR_CAPABLE 0x01
2975 #define ATI_HBR_ENABLE 0x10
2976
2977 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
2978 unsigned char *buf, int *eld_size)
2979 {
2980 /* call hda_eld.c ATI/AMD-specific function */
2981 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
2982 is_amdhdmi_rev3_or_later(codec));
2983 }
2984
2985 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
2986 int active_channels, int conn_type)
2987 {
2988 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
2989 }
2990
2991 static int atihdmi_paired_swap_fc_lfe(int pos)
2992 {
2993 /*
2994 * ATI/AMD have automatic FC/LFE swap built-in
2995 * when in pairwise mapping mode.
2996 */
2997
2998 switch (pos) {
2999 /* see channel_allocations[].speakers[] */
3000 case 2: return 3;
3001 case 3: return 2;
3002 default: break;
3003 }
3004
3005 return pos;
3006 }
3007
3008 static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
3009 {
3010 struct cea_channel_speaker_allocation *cap;
3011 int i, j;
3012
3013 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3014
3015 cap = &channel_allocations[get_channel_allocation_order(ca)];
3016 for (i = 0; i < chs; ++i) {
3017 int mask = to_spk_mask(map[i]);
3018 bool ok = false;
3019 bool companion_ok = false;
3020
3021 if (!mask)
3022 continue;
3023
3024 for (j = 0 + i % 2; j < 8; j += 2) {
3025 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3026 if (cap->speakers[chan_idx] == mask) {
3027 /* channel is in a supported position */
3028 ok = true;
3029
3030 if (i % 2 == 0 && i + 1 < chs) {
3031 /* even channel, check the odd companion */
3032 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3033 int comp_mask_req = to_spk_mask(map[i+1]);
3034 int comp_mask_act = cap->speakers[comp_chan_idx];
3035
3036 if (comp_mask_req == comp_mask_act)
3037 companion_ok = true;
3038 else
3039 return -EINVAL;
3040 }
3041 break;
3042 }
3043 }
3044
3045 if (!ok)
3046 return -EINVAL;
3047
3048 if (companion_ok)
3049 i++; /* companion channel already checked */
3050 }
3051
3052 return 0;
3053 }
3054
3055 static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3056 int hdmi_slot, int stream_channel)
3057 {
3058 int verb;
3059 int ati_channel_setup = 0;
3060
3061 if (hdmi_slot > 7)
3062 return -EINVAL;
3063
3064 if (!has_amd_full_remap_support(codec)) {
3065 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3066
3067 /* In case this is an odd slot but without stream channel, do not
3068 * disable the slot since the corresponding even slot could have a
3069 * channel. In case neither have a channel, the slot pair will be
3070 * disabled when this function is called for the even slot. */
3071 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3072 return 0;
3073
3074 hdmi_slot -= hdmi_slot % 2;
3075
3076 if (stream_channel != 0xf)
3077 stream_channel -= stream_channel % 2;
3078 }
3079
3080 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3081
3082 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3083
3084 if (stream_channel != 0xf)
3085 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3086
3087 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3088 }
3089
3090 static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3091 int asp_slot)
3092 {
3093 bool was_odd = false;
3094 int ati_asp_slot = asp_slot;
3095 int verb;
3096 int ati_channel_setup;
3097
3098 if (asp_slot > 7)
3099 return -EINVAL;
3100
3101 if (!has_amd_full_remap_support(codec)) {
3102 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3103 if (ati_asp_slot % 2 != 0) {
3104 ati_asp_slot -= 1;
3105 was_odd = true;
3106 }
3107 }
3108
3109 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3110
3111 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3112
3113 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3114 return 0xf;
3115
3116 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3117 }
3118
3119 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3120 int channels)
3121 {
3122 int c;
3123
3124 /*
3125 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3126 * we need to take that into account (a single channel may take 2
3127 * channel slots if we need to carry a silent channel next to it).
3128 * On Rev3+ AMD codecs this function is not used.
3129 */
3130 int chanpairs = 0;
3131
3132 /* We only produce even-numbered channel count TLVs */
3133 if ((channels % 2) != 0)
3134 return -1;
3135
3136 for (c = 0; c < 7; c += 2) {
3137 if (cap->speakers[c] || cap->speakers[c+1])
3138 chanpairs++;
3139 }
3140
3141 if (chanpairs * 2 != channels)
3142 return -1;
3143
3144 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3145 }
3146
3147 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3148 unsigned int *chmap, int channels)
3149 {
3150 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3151 int count = 0;
3152 int c;
3153
3154 for (c = 7; c >= 0; c--) {
3155 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3156 int spk = cap->speakers[chan];
3157 if (!spk) {
3158 /* add N/A channel if the companion channel is occupied */
3159 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3160 chmap[count++] = SNDRV_CHMAP_NA;
3161
3162 continue;
3163 }
3164
3165 chmap[count++] = spk_to_chmap(spk);
3166 }
3167
3168 WARN_ON(count != channels);
3169 }
3170
3171 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3172 bool hbr)
3173 {
3174 int hbr_ctl, hbr_ctl_new;
3175
3176 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3177 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3178 if (hbr)
3179 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3180 else
3181 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3182
3183 codec_dbg(codec,
3184 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3185 pin_nid,
3186 hbr_ctl == hbr_ctl_new ? "" : "new-",
3187 hbr_ctl_new);
3188
3189 if (hbr_ctl != hbr_ctl_new)
3190 snd_hda_codec_write(codec, pin_nid, 0,
3191 ATI_VERB_SET_HBR_CONTROL,
3192 hbr_ctl_new);
3193
3194 } else if (hbr)
3195 return -EINVAL;
3196
3197 return 0;
3198 }
3199
3200 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3201 hda_nid_t pin_nid, u32 stream_tag, int format)
3202 {
3203
3204 if (is_amdhdmi_rev3_or_later(codec)) {
3205 int ramp_rate = 180; /* default as per AMD spec */
3206 /* disable ramp-up/down for non-pcm as per AMD spec */
3207 if (format & AC_FMT_TYPE_NON_PCM)
3208 ramp_rate = 0;
3209
3210 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3211 }
3212
3213 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3214 }
3215
3216
3217 static int atihdmi_init(struct hda_codec *codec)
3218 {
3219 struct hdmi_spec *spec = codec->spec;
3220 int pin_idx, err;
3221
3222 err = generic_hdmi_init(codec);
3223
3224 if (err)
3225 return err;
3226
3227 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3228 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3229
3230 /* make sure downmix information in infoframe is zero */
3231 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3232
3233 /* enable channel-wise remap mode if supported */
3234 if (has_amd_full_remap_support(codec))
3235 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3236 ATI_VERB_SET_MULTICHANNEL_MODE,
3237 ATI_MULTICHANNEL_MODE_SINGLE);
3238 }
3239
3240 return 0;
3241 }
3242
3243 static int patch_atihdmi(struct hda_codec *codec)
3244 {
3245 struct hdmi_spec *spec;
3246 struct hdmi_spec_per_cvt *per_cvt;
3247 int err, cvt_idx;
3248
3249 err = patch_generic_hdmi(codec);
3250
3251 if (err)
3252 return err;
3253
3254 codec->patch_ops.init = atihdmi_init;
3255
3256 spec = codec->spec;
3257
3258 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3259 spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3260 spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3261 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3262 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3263 spec->ops.setup_stream = atihdmi_setup_stream;
3264
3265 if (!has_amd_full_remap_support(codec)) {
3266 /* override to ATI/AMD-specific versions with pairwise mapping */
3267 spec->ops.chmap_cea_alloc_validate_get_type =
3268 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3269 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
3270 spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
3271 }
3272
3273 /* ATI/AMD converters do not advertise all of their capabilities */
3274 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3275 per_cvt = get_cvt(spec, cvt_idx);
3276 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3277 per_cvt->rates |= SUPPORTED_RATES;
3278 per_cvt->formats |= SUPPORTED_FORMATS;
3279 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3280 }
3281
3282 spec->channels_max = max(spec->channels_max, 8u);
3283
3284 return 0;
3285 }
3286
3287 /* VIA HDMI Implementation */
3288 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3289 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3290
3291 static int patch_via_hdmi(struct hda_codec *codec)
3292 {
3293 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3294 }
3295
3296 /*
3297 * patch entries
3298 */
3299 static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
3300 { .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
3301 { .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
3302 { .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
3303 { .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_atihdmi },
3304 { .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
3305 { .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
3306 { .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
3307 { .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3308 { .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3309 { .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3310 { .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3311 { .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
3312 { .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_nvhdmi },
3313 { .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_nvhdmi },
3314 { .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_nvhdmi },
3315 { .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_nvhdmi },
3316 { .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_nvhdmi },
3317 { .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_nvhdmi },
3318 { .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_nvhdmi },
3319 { .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_nvhdmi },
3320 { .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_nvhdmi },
3321 { .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_nvhdmi },
3322 { .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_nvhdmi },
3323 /* 17 is known to be absent */
3324 { .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_nvhdmi },
3325 { .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_nvhdmi },
3326 { .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_nvhdmi },
3327 { .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_nvhdmi },
3328 { .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_nvhdmi },
3329 { .id = 0x10de0028, .name = "Tegra12x HDMI", .patch = patch_nvhdmi },
3330 { .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_nvhdmi },
3331 { .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_nvhdmi },
3332 { .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_nvhdmi },
3333 { .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_nvhdmi },
3334 { .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_nvhdmi },
3335 { .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_nvhdmi },
3336 { .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_nvhdmi },
3337 { .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
3338 { .id = 0x10de0070, .name = "GPU 70 HDMI/DP", .patch = patch_nvhdmi },
3339 { .id = 0x10de0071, .name = "GPU 71 HDMI/DP", .patch = patch_nvhdmi },
3340 { .id = 0x10de0072, .name = "GPU 72 HDMI/DP", .patch = patch_nvhdmi },
3341 { .id = 0x10de007d, .name = "GPU 7d HDMI/DP", .patch = patch_nvhdmi },
3342 { .id = 0x10de0082, .name = "GPU 82 HDMI/DP", .patch = patch_nvhdmi },
3343 { .id = 0x10de0083, .name = "GPU 83 HDMI/DP", .patch = patch_nvhdmi },
3344 { .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
3345 { .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3346 { .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3347 { .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
3348 { .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
3349 { .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3350 { .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
3351 { .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
3352 { .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
3353 { .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3354 { .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
3355 { .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
3356 { .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
3357 { .id = 0x80862808, .name = "Broadwell HDMI", .patch = patch_generic_hdmi },
3358 { .id = 0x80862809, .name = "Skylake HDMI", .patch = patch_generic_hdmi },
3359 { .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
3360 { .id = 0x80862882, .name = "Valleyview2 HDMI", .patch = patch_generic_hdmi },
3361 { .id = 0x80862883, .name = "Braswell HDMI", .patch = patch_generic_hdmi },
3362 { .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
3363 /* special ID for generic HDMI */
3364 { .id = HDA_CODEC_ID_GENERIC_HDMI, .patch = patch_generic_hdmi },
3365 {} /* terminator */
3366 };
3367
3368 MODULE_ALIAS("snd-hda-codec-id:1002793c");
3369 MODULE_ALIAS("snd-hda-codec-id:10027919");
3370 MODULE_ALIAS("snd-hda-codec-id:1002791a");
3371 MODULE_ALIAS("snd-hda-codec-id:1002aa01");
3372 MODULE_ALIAS("snd-hda-codec-id:10951390");
3373 MODULE_ALIAS("snd-hda-codec-id:10951392");
3374 MODULE_ALIAS("snd-hda-codec-id:10de0002");
3375 MODULE_ALIAS("snd-hda-codec-id:10de0003");
3376 MODULE_ALIAS("snd-hda-codec-id:10de0005");
3377 MODULE_ALIAS("snd-hda-codec-id:10de0006");
3378 MODULE_ALIAS("snd-hda-codec-id:10de0007");
3379 MODULE_ALIAS("snd-hda-codec-id:10de000a");
3380 MODULE_ALIAS("snd-hda-codec-id:10de000b");
3381 MODULE_ALIAS("snd-hda-codec-id:10de000c");
3382 MODULE_ALIAS("snd-hda-codec-id:10de000d");
3383 MODULE_ALIAS("snd-hda-codec-id:10de0010");
3384 MODULE_ALIAS("snd-hda-codec-id:10de0011");
3385 MODULE_ALIAS("snd-hda-codec-id:10de0012");
3386 MODULE_ALIAS("snd-hda-codec-id:10de0013");
3387 MODULE_ALIAS("snd-hda-codec-id:10de0014");
3388 MODULE_ALIAS("snd-hda-codec-id:10de0015");
3389 MODULE_ALIAS("snd-hda-codec-id:10de0016");
3390 MODULE_ALIAS("snd-hda-codec-id:10de0018");
3391 MODULE_ALIAS("snd-hda-codec-id:10de0019");
3392 MODULE_ALIAS("snd-hda-codec-id:10de001a");
3393 MODULE_ALIAS("snd-hda-codec-id:10de001b");
3394 MODULE_ALIAS("snd-hda-codec-id:10de001c");
3395 MODULE_ALIAS("snd-hda-codec-id:10de0028");
3396 MODULE_ALIAS("snd-hda-codec-id:10de0040");
3397 MODULE_ALIAS("snd-hda-codec-id:10de0041");
3398 MODULE_ALIAS("snd-hda-codec-id:10de0042");
3399 MODULE_ALIAS("snd-hda-codec-id:10de0043");
3400 MODULE_ALIAS("snd-hda-codec-id:10de0044");
3401 MODULE_ALIAS("snd-hda-codec-id:10de0051");
3402 MODULE_ALIAS("snd-hda-codec-id:10de0060");
3403 MODULE_ALIAS("snd-hda-codec-id:10de0067");
3404 MODULE_ALIAS("snd-hda-codec-id:10de0070");
3405 MODULE_ALIAS("snd-hda-codec-id:10de0071");
3406 MODULE_ALIAS("snd-hda-codec-id:10de0072");
3407 MODULE_ALIAS("snd-hda-codec-id:10de007d");
3408 MODULE_ALIAS("snd-hda-codec-id:10de8001");
3409 MODULE_ALIAS("snd-hda-codec-id:11069f80");
3410 MODULE_ALIAS("snd-hda-codec-id:11069f81");
3411 MODULE_ALIAS("snd-hda-codec-id:11069f84");
3412 MODULE_ALIAS("snd-hda-codec-id:11069f85");
3413 MODULE_ALIAS("snd-hda-codec-id:17e80047");
3414 MODULE_ALIAS("snd-hda-codec-id:80860054");
3415 MODULE_ALIAS("snd-hda-codec-id:80862801");
3416 MODULE_ALIAS("snd-hda-codec-id:80862802");
3417 MODULE_ALIAS("snd-hda-codec-id:80862803");
3418 MODULE_ALIAS("snd-hda-codec-id:80862804");
3419 MODULE_ALIAS("snd-hda-codec-id:80862805");
3420 MODULE_ALIAS("snd-hda-codec-id:80862806");
3421 MODULE_ALIAS("snd-hda-codec-id:80862807");
3422 MODULE_ALIAS("snd-hda-codec-id:80862808");
3423 MODULE_ALIAS("snd-hda-codec-id:80862809");
3424 MODULE_ALIAS("snd-hda-codec-id:80862880");
3425 MODULE_ALIAS("snd-hda-codec-id:80862882");
3426 MODULE_ALIAS("snd-hda-codec-id:80862883");
3427 MODULE_ALIAS("snd-hda-codec-id:808629fb");
3428
3429 MODULE_LICENSE("GPL");
3430 MODULE_DESCRIPTION("HDMI HD-audio codec");
3431 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3432 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3433 MODULE_ALIAS("snd-hda-codec-atihdmi");
3434
3435 static struct hda_codec_driver hdmi_driver = {
3436 .preset = snd_hda_preset_hdmi,
3437 };
3438
3439 module_hda_codec_driver(hdmi_driver);
Linux with added FPC-III support