8 select MULTI_IRQ_HANDLER
16 select MULTI_IRQ_HANDLER
21 select GENERIC_IRQ_CHIP
26 select MULTI_IRQ_HANDLER
30 default 4 if ARCH_S5PV210
34 The maximum number of VICs available in the system, for
39 select GENERIC_IRQ_CHIP
41 select MULTI_IRQ_HANDLER
46 select GENERIC_IRQ_CHIP
48 select MULTI_IRQ_HANDLER
54 select GENERIC_IRQ_CHIP
63 select GENERIC_IRQ_CHIP
66 config CLPS711X_IRQCHIP
68 depends on ARCH_CLPS711X
70 select MULTI_IRQ_HANDLER
80 select GENERIC_IRQ_CHIP
86 select MULTI_IRQ_HANDLER
88 config RENESAS_INTC_IRQPIN
99 select GENERIC_IRQ_CHIP
101 config VERSATILE_FPGA_IRQ
105 config VERSATILE_FPGA_IRQ_NR
108 depends on VERSATILE_FPGA_IRQ
117 Support for a CROSSBAR ip that precedes the main interrupt controller.
118 The primary irqchip invokes the crossbar's callback which inturn allocates
119 a free irq and configures the IP. Thus the peripheral interrupts are
120 routed to one of the free irqchip interrupt lines.
123 tristate "Keystone 2 IRQ controller IP"
124 depends on ARCH_KEYSTONE
126 Support for Texas Instruments Keystone 2 IRQ controller IP which
127 is part of the Keystone 2 IPC mechanism