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ARM: perf: use pr_* instead of printk
[linux/fpc-iii.git] / drivers / irqchip / irq-renesas-intc-irqpin.c
blob542e850f4946808ebc19cbf80f71b7e2b9b7b4d8
1 /*
2 * Renesas INTC External IRQ Pin Driver
3 *
4 * Copyright (C) 2013 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/clk.h>
21 #include <linux/init.h>
22 #include <linux/of.h>
23 #include <linux/platform_device.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/ioport.h>
27 #include <linux/io.h>
28 #include <linux/irq.h>
29 #include <linux/irqdomain.h>
30 #include <linux/err.h>
31 #include <linux/slab.h>
32 #include <linux/module.h>
33 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
34 #include <linux/pm_runtime.h>
35
36 #define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
37
38 #define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
39 #define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
40 #define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
41 #define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
42 #define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
43 #define INTC_IRQPIN_REG_NR 5
44
45 /* INTC external IRQ PIN hardware register access:
46 *
47 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
48 * PRIO is read-write 32-bit with 4-bits per IRQ (**)
49 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
50 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
51 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
52 *
53 * (*) May be accessed by more than one driver instance - lock needed
54 * (**) Read-modify-write access by one driver instance - lock needed
55 * (***) Accessed by one driver instance only - no locking needed
56 */
57
58 struct intc_irqpin_iomem {
59 void __iomem *iomem;
60 unsigned long (*read)(void __iomem *iomem);
61 void (*write)(void __iomem *iomem, unsigned long data);
62 int width;
63 };
64
65 struct intc_irqpin_irq {
66 int hw_irq;
67 int requested_irq;
68 int domain_irq;
69 struct intc_irqpin_priv *p;
70 };
71
72 struct intc_irqpin_priv {
73 struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
74 struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
75 struct renesas_intc_irqpin_config config;
76 unsigned int number_of_irqs;
77 struct platform_device *pdev;
78 struct irq_chip irq_chip;
79 struct irq_domain *irq_domain;
80 struct clk *clk;
81 bool shared_irqs;
82 u8 shared_irq_mask;
83 };
84
85 static unsigned long intc_irqpin_read32(void __iomem *iomem)
86 {
87 return ioread32(iomem);
88 }
89
90 static unsigned long intc_irqpin_read8(void __iomem *iomem)
91 {
92 return ioread8(iomem);
93 }
94
95 static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
96 {
97 iowrite32(data, iomem);
98 }
99
100 static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
101 {
102 iowrite8(data, iomem);
103 }
104
105 static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
106 int reg)
107 {
108 struct intc_irqpin_iomem *i = &p->iomem[reg];
109
110 return i->read(i->iomem);
111 }
112
113 static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
114 int reg, unsigned long data)
115 {
116 struct intc_irqpin_iomem *i = &p->iomem[reg];
117
118 i->write(i->iomem, data);
119 }
120
121 static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
122 int reg, int hw_irq)
123 {
124 return BIT((p->iomem[reg].width - 1) - hw_irq);
125 }
126
127 static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
128 int reg, int hw_irq)
129 {
130 intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
131 }
132
133 static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
134
135 static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
136 int reg, int shift,
137 int width, int value)
138 {
139 unsigned long flags;
140 unsigned long tmp;
141
142 raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
143
144 tmp = intc_irqpin_read(p, reg);
145 tmp &= ~(((1 << width) - 1) << shift);
146 tmp |= value << shift;
147 intc_irqpin_write(p, reg, tmp);
148
149 raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
150 }
151
152 static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
153 int irq, int do_mask)
154 {
155 /* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */
156 int bitfield_width = 4;
157 int shift = 32 - (irq + 1) * bitfield_width;
158
159 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
160 shift, bitfield_width,
161 do_mask ? 0 : (1 << bitfield_width) - 1);
162 }
163
164 static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
165 {
166 /* The SENSE register is assumed to be 32-bit. */
167 int bitfield_width = p->config.sense_bitfield_width;
168 int shift = 32 - (irq + 1) * bitfield_width;
169
170 dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
171
172 if (value >= (1 << bitfield_width))
173 return -EINVAL;
174
175 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
176 bitfield_width, value);
177 return 0;
178 }
179
180 static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str)
181 {
182 dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
183 str, i->requested_irq, i->hw_irq, i->domain_irq);
184 }
185
186 static void intc_irqpin_irq_enable(struct irq_data *d)
187 {
188 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
189 int hw_irq = irqd_to_hwirq(d);
190
191 intc_irqpin_dbg(&p->irq[hw_irq], "enable");
192 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
193 }
194
195 static void intc_irqpin_irq_disable(struct irq_data *d)
196 {
197 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
198 int hw_irq = irqd_to_hwirq(d);
199
200 intc_irqpin_dbg(&p->irq[hw_irq], "disable");
201 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
202 }
203
204 static void intc_irqpin_shared_irq_enable(struct irq_data *d)
205 {
206 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
207 int hw_irq = irqd_to_hwirq(d);
208
209 intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");
210 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
211
212 p->shared_irq_mask &= ~BIT(hw_irq);
213 }
214
215 static void intc_irqpin_shared_irq_disable(struct irq_data *d)
216 {
217 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
218 int hw_irq = irqd_to_hwirq(d);
219
220 intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");
221 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
222
223 p->shared_irq_mask |= BIT(hw_irq);
224 }
225
226 static void intc_irqpin_irq_enable_force(struct irq_data *d)
227 {
228 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
229 int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
230
231 intc_irqpin_irq_enable(d);
232
233 /* enable interrupt through parent interrupt controller,
234 * assumes non-shared interrupt with 1:1 mapping
235 * needed for busted IRQs on some SoCs like sh73a0
236 */
237 irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
238 }
239
240 static void intc_irqpin_irq_disable_force(struct irq_data *d)
241 {
242 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
243 int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
244
245 /* disable interrupt through parent interrupt controller,
246 * assumes non-shared interrupt with 1:1 mapping
247 * needed for busted IRQs on some SoCs like sh73a0
248 */
249 irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
250 intc_irqpin_irq_disable(d);
251 }
252
253 #define INTC_IRQ_SENSE_VALID 0x10
254 #define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
255
256 static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
257 [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
258 [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
259 [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
260 [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
261 [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
262 };
263
264 static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
265 {
266 unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
267 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
268
269 if (!(value & INTC_IRQ_SENSE_VALID))
270 return -EINVAL;
271
272 return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
273 value ^ INTC_IRQ_SENSE_VALID);
274 }
275
276 static int intc_irqpin_irq_set_wake(struct irq_data *d, unsigned int on)
277 {
278 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
279
280 if (!p->clk)
281 return 0;
282
283 if (on)
284 clk_enable(p->clk);
285 else
286 clk_disable(p->clk);
287
288 return 0;
289 }
290
291 static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
292 {
293 struct intc_irqpin_irq *i = dev_id;
294 struct intc_irqpin_priv *p = i->p;
295 unsigned long bit;
296
297 intc_irqpin_dbg(i, "demux1");
298 bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
299
300 if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
301 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
302 intc_irqpin_dbg(i, "demux2");
303 generic_handle_irq(i->domain_irq);
304 return IRQ_HANDLED;
305 }
306 return IRQ_NONE;
307 }
308
309 static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id)
310 {
311 struct intc_irqpin_priv *p = dev_id;
312 unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE);
313 irqreturn_t status = IRQ_NONE;
314 int k;
315
316 for (k = 0; k < 8; k++) {
317 if (reg_source & BIT(7 - k)) {
318 if (BIT(k) & p->shared_irq_mask)
319 continue;
320
321 status |= intc_irqpin_irq_handler(irq, &p->irq[k]);
322 }
323 }
324
325 return status;
326 }
327
328 static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
329 irq_hw_number_t hw)
330 {
331 struct intc_irqpin_priv *p = h->host_data;
332
333 p->irq[hw].domain_irq = virq;
334 p->irq[hw].hw_irq = hw;
335
336 intc_irqpin_dbg(&p->irq[hw], "map");
337 irq_set_chip_data(virq, h->host_data);
338 irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
339 set_irq_flags(virq, IRQF_VALID); /* kill me now */
340 return 0;
341 }
342
343 static struct irq_domain_ops intc_irqpin_irq_domain_ops = {
344 .map = intc_irqpin_irq_domain_map,
345 .xlate = irq_domain_xlate_twocell,
346 };
347
348 static int intc_irqpin_probe(struct platform_device *pdev)
349 {
350 struct device *dev = &pdev->dev;
351 struct renesas_intc_irqpin_config *pdata = dev->platform_data;
352 struct intc_irqpin_priv *p;
353 struct intc_irqpin_iomem *i;
354 struct resource *io[INTC_IRQPIN_REG_NR];
355 struct resource *irq;
356 struct irq_chip *irq_chip;
357 void (*enable_fn)(struct irq_data *d);
358 void (*disable_fn)(struct irq_data *d);
359 const char *name = dev_name(dev);
360 int ref_irq;
361 int ret;
362 int k;
363
364 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
365 if (!p) {
366 dev_err(dev, "failed to allocate driver data\n");
367 return -ENOMEM;
368 }
369
370 /* deal with driver instance configuration */
371 if (pdata) {
372 memcpy(&p->config, pdata, sizeof(*pdata));
373 } else {
374 of_property_read_u32(dev->of_node, "sense-bitfield-width",
375 &p->config.sense_bitfield_width);
376 p->config.control_parent = of_property_read_bool(dev->of_node,
377 "control-parent");
378 }
379 if (!p->config.sense_bitfield_width)
380 p->config.sense_bitfield_width = 4; /* default to 4 bits */
381
382 p->pdev = pdev;
383 platform_set_drvdata(pdev, p);
384
385 p->clk = devm_clk_get(dev, NULL);
386 if (IS_ERR(p->clk)) {
387 dev_warn(dev, "unable to get clock\n");
388 p->clk = NULL;
389 }
390
391 pm_runtime_enable(dev);
392 pm_runtime_get_sync(dev);
393
394 /* get hold of manadatory IOMEM */
395 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
396 io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
397 if (!io[k]) {
398 dev_err(dev, "not enough IOMEM resources\n");
399 ret = -EINVAL;
400 goto err0;
401 }
402 }
403
404 /* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
405 for (k = 0; k < INTC_IRQPIN_MAX; k++) {
406 irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
407 if (!irq)
408 break;
409
410 p->irq[k].p = p;
411 p->irq[k].requested_irq = irq->start;
412 }
413
414 p->number_of_irqs = k;
415 if (p->number_of_irqs < 1) {
416 dev_err(dev, "not enough IRQ resources\n");
417 ret = -EINVAL;
418 goto err0;
419 }
420
421 /* ioremap IOMEM and setup read/write callbacks */
422 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
423 i = &p->iomem[k];
424
425 switch (resource_size(io[k])) {
426 case 1:
427 i->width = 8;
428 i->read = intc_irqpin_read8;
429 i->write = intc_irqpin_write8;
430 break;
431 case 4:
432 i->width = 32;
433 i->read = intc_irqpin_read32;
434 i->write = intc_irqpin_write32;
435 break;
436 default:
437 dev_err(dev, "IOMEM size mismatch\n");
438 ret = -EINVAL;
439 goto err0;
440 }
441
442 i->iomem = devm_ioremap_nocache(dev, io[k]->start,
443 resource_size(io[k]));
444 if (!i->iomem) {
445 dev_err(dev, "failed to remap IOMEM\n");
446 ret = -ENXIO;
447 goto err0;
448 }
449 }
450
451 /* mask all interrupts using priority */
452 for (k = 0; k < p->number_of_irqs; k++)
453 intc_irqpin_mask_unmask_prio(p, k, 1);
454
455 /* clear all pending interrupts */
456 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0);
457
458 /* scan for shared interrupt lines */
459 ref_irq = p->irq[0].requested_irq;
460 p->shared_irqs = true;
461 for (k = 1; k < p->number_of_irqs; k++) {
462 if (ref_irq != p->irq[k].requested_irq) {
463 p->shared_irqs = false;
464 break;
465 }
466 }
467
468 /* use more severe masking method if requested */
469 if (p->config.control_parent) {
470 enable_fn = intc_irqpin_irq_enable_force;
471 disable_fn = intc_irqpin_irq_disable_force;
472 } else if (!p->shared_irqs) {
473 enable_fn = intc_irqpin_irq_enable;
474 disable_fn = intc_irqpin_irq_disable;
475 } else {
476 enable_fn = intc_irqpin_shared_irq_enable;
477 disable_fn = intc_irqpin_shared_irq_disable;
478 }
479
480 irq_chip = &p->irq_chip;
481 irq_chip->name = name;
482 irq_chip->irq_mask = disable_fn;
483 irq_chip->irq_unmask = enable_fn;
484 irq_chip->irq_set_type = intc_irqpin_irq_set_type;
485 irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;
486 irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
487
488 p->irq_domain = irq_domain_add_simple(dev->of_node,
489 p->number_of_irqs,
490 p->config.irq_base,
491 &intc_irqpin_irq_domain_ops, p);
492 if (!p->irq_domain) {
493 ret = -ENXIO;
494 dev_err(dev, "cannot initialize irq domain\n");
495 goto err0;
496 }
497
498 if (p->shared_irqs) {
499 /* request one shared interrupt */
500 if (devm_request_irq(dev, p->irq[0].requested_irq,
501 intc_irqpin_shared_irq_handler,
502 IRQF_SHARED, name, p)) {
503 dev_err(dev, "failed to request low IRQ\n");
504 ret = -ENOENT;
505 goto err1;
506 }
507 } else {
508 /* request interrupts one by one */
509 for (k = 0; k < p->number_of_irqs; k++) {
510 if (devm_request_irq(dev, p->irq[k].requested_irq,
511 intc_irqpin_irq_handler, 0, name,
512 &p->irq[k])) {
513 dev_err(dev, "failed to request low IRQ\n");
514 ret = -ENOENT;
515 goto err1;
516 }
517 }
518 }
519
520 /* unmask all interrupts on prio level */
521 for (k = 0; k < p->number_of_irqs; k++)
522 intc_irqpin_mask_unmask_prio(p, k, 0);
523
524 dev_info(dev, "driving %d irqs\n", p->number_of_irqs);
525
526 /* warn in case of mismatch if irq base is specified */
527 if (p->config.irq_base) {
528 if (p->config.irq_base != p->irq[0].domain_irq)
529 dev_warn(dev, "irq base mismatch (%d/%d)\n",
530 p->config.irq_base, p->irq[0].domain_irq);
531 }
532
533 return 0;
534
535 err1:
536 irq_domain_remove(p->irq_domain);
537 err0:
538 pm_runtime_put(dev);
539 pm_runtime_disable(dev);
540 return ret;
541 }
542
543 static int intc_irqpin_remove(struct platform_device *pdev)
544 {
545 struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
546
547 irq_domain_remove(p->irq_domain);
548 pm_runtime_put(&pdev->dev);
549 pm_runtime_disable(&pdev->dev);
550 return 0;
551 }
552
553 static const struct of_device_id intc_irqpin_dt_ids[] = {
554 { .compatible = "renesas,intc-irqpin", },
555 {},
556 };
557 MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
558
559 static struct platform_driver intc_irqpin_device_driver = {
560 .probe = intc_irqpin_probe,
561 .remove = intc_irqpin_remove,
562 .driver = {
563 .name = "renesas_intc_irqpin",
564 .of_match_table = intc_irqpin_dt_ids,
565 .owner = THIS_MODULE,
566 }
567 };
568
569 static int __init intc_irqpin_init(void)
570 {
571 return platform_driver_register(&intc_irqpin_device_driver);
572 }
573 postcore_initcall(intc_irqpin_init);
574
575 static void __exit intc_irqpin_exit(void)
576 {
577 platform_driver_unregister(&intc_irqpin_device_driver);
578 }
579 module_exit(intc_irqpin_exit);
580
581 MODULE_AUTHOR("Magnus Damm");
582 MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
583 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support