?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 2.6.17.3
[linux/fpc-iii.git] / drivers / net / smc91x.h
blobe1be1af51201b67b7f72c6693ce824ca8162027d
1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org>
32 .
33 ---------------------------------------------------------------------------*/
34 #ifndef _SMC91X_H_
35 #define _SMC91X_H_
36
37
38 /*
39 * Define your architecture specific bus configuration parameters here.
40 */
41
42 #if defined(CONFIG_ARCH_LUBBOCK)
43
44 /* We can only do 16-bit reads and writes in the static memory space. */
45 #define SMC_CAN_USE_8BIT 0
46 #define SMC_CAN_USE_16BIT 1
47 #define SMC_CAN_USE_32BIT 0
48 #define SMC_NOWAIT 1
49
50 /* The first two address lines aren't connected... */
51 #define SMC_IO_SHIFT 2
52
53 #define SMC_inw(a, r) readw((a) + (r))
54 #define SMC_outw(v, a, r) writew(v, (a) + (r))
55 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
56 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
57
58 #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
59
60 /* We can only do 16-bit reads and writes in the static memory space. */
61 #define SMC_CAN_USE_8BIT 0
62 #define SMC_CAN_USE_16BIT 1
63 #define SMC_CAN_USE_32BIT 0
64 #define SMC_NOWAIT 1
65
66 #define SMC_IO_SHIFT 0
67
68 #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
69 #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
70 #define SMC_insw(a, r, p, l) \
71 do { \
72 unsigned long __port = (a) + (r); \
73 u16 *__p = (u16 *)(p); \
74 int __l = (l); \
75 insw(__port, __p, __l); \
76 while (__l > 0) { \
77 *__p = swab16(*__p); \
78 __p++; \
79 __l--; \
80 } \
81 } while (0)
82 #define SMC_outsw(a, r, p, l) \
83 do { \
84 unsigned long __port = (a) + (r); \
85 u16 *__p = (u16 *)(p); \
86 int __l = (l); \
87 while (__l > 0) { \
88 /* Believe it or not, the swab isn't needed. */ \
89 outw( /* swab16 */ (*__p++), __port); \
90 __l--; \
91 } \
92 } while (0)
93 #define SMC_IRQ_FLAGS (0)
94
95 #elif defined(CONFIG_SA1100_PLEB)
96 /* We can only do 16-bit reads and writes in the static memory space. */
97 #define SMC_CAN_USE_8BIT 1
98 #define SMC_CAN_USE_16BIT 1
99 #define SMC_CAN_USE_32BIT 0
100 #define SMC_IO_SHIFT 0
101 #define SMC_NOWAIT 1
102
103 #define SMC_inb(a, r) readb((a) + (r))
104 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
105 #define SMC_inw(a, r) readw((a) + (r))
106 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
107 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
108 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
109 #define SMC_outw(v, a, r) writew(v, (a) + (r))
110 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
111
112 #define SMC_IRQ_FLAGS (0)
113
114 #elif defined(CONFIG_SA1100_ASSABET)
115
116 #include <asm/arch/neponset.h>
117
118 /* We can only do 8-bit reads and writes in the static memory space. */
119 #define SMC_CAN_USE_8BIT 1
120 #define SMC_CAN_USE_16BIT 0
121 #define SMC_CAN_USE_32BIT 0
122 #define SMC_NOWAIT 1
123
124 /* The first two address lines aren't connected... */
125 #define SMC_IO_SHIFT 2
126
127 #define SMC_inb(a, r) readb((a) + (r))
128 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
129 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
130 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
131
132 #elif defined(CONFIG_ARCH_INNOKOM) || \
133 defined(CONFIG_MACH_MAINSTONE) || \
134 defined(CONFIG_ARCH_PXA_IDP) || \
135 defined(CONFIG_ARCH_RAMSES)
136
137 #define SMC_CAN_USE_8BIT 1
138 #define SMC_CAN_USE_16BIT 1
139 #define SMC_CAN_USE_32BIT 1
140 #define SMC_IO_SHIFT 0
141 #define SMC_NOWAIT 1
142 #define SMC_USE_PXA_DMA 1
143
144 #define SMC_inb(a, r) readb((a) + (r))
145 #define SMC_inw(a, r) readw((a) + (r))
146 #define SMC_inl(a, r) readl((a) + (r))
147 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
148 #define SMC_outl(v, a, r) writel(v, (a) + (r))
149 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
150 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
151
152 /* We actually can't write halfwords properly if not word aligned */
153 static inline void
154 SMC_outw(u16 val, void __iomem *ioaddr, int reg)
155 {
156 if (reg & 2) {
157 unsigned int v = val << 16;
158 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
159 writel(v, ioaddr + (reg & ~2));
160 } else {
161 writew(val, ioaddr + reg);
162 }
163 }
164
165 #elif defined(CONFIG_ARCH_OMAP)
166
167 /* We can only do 16-bit reads and writes in the static memory space. */
168 #define SMC_CAN_USE_8BIT 0
169 #define SMC_CAN_USE_16BIT 1
170 #define SMC_CAN_USE_32BIT 0
171 #define SMC_IO_SHIFT 0
172 #define SMC_NOWAIT 1
173
174 #define SMC_inb(a, r) readb((a) + (r))
175 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
176 #define SMC_inw(a, r) readw((a) + (r))
177 #define SMC_outw(v, a, r) writew(v, (a) + (r))
178 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
179 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
180 #define SMC_inl(a, r) readl((a) + (r))
181 #define SMC_outl(v, a, r) writel(v, (a) + (r))
182 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
183 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
184
185 #include <asm/mach-types.h>
186 #include <asm/arch/cpu.h>
187
188 #define SMC_IRQ_FLAGS (( \
189 machine_is_omap_h2() \
190 || machine_is_omap_h3() \
191 || (machine_is_omap_innovator() && !cpu_is_omap1510()) \
192 ) ? SA_TRIGGER_FALLING : SA_TRIGGER_RISING)
193
194
195 #elif defined(CONFIG_SH_SH4202_MICRODEV)
196
197 #define SMC_CAN_USE_8BIT 0
198 #define SMC_CAN_USE_16BIT 1
199 #define SMC_CAN_USE_32BIT 0
200
201 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
202 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
203 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
204 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
205 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
206 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
207 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
208 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
209 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
210 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
211
212 #define SMC_IRQ_FLAGS (0)
213
214 #elif defined(CONFIG_ISA)
215
216 #define SMC_CAN_USE_8BIT 1
217 #define SMC_CAN_USE_16BIT 1
218 #define SMC_CAN_USE_32BIT 0
219
220 #define SMC_inb(a, r) inb((a) + (r))
221 #define SMC_inw(a, r) inw((a) + (r))
222 #define SMC_outb(v, a, r) outb(v, (a) + (r))
223 #define SMC_outw(v, a, r) outw(v, (a) + (r))
224 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
225 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
226
227 #elif defined(CONFIG_M32R)
228
229 #define SMC_CAN_USE_8BIT 0
230 #define SMC_CAN_USE_16BIT 1
231 #define SMC_CAN_USE_32BIT 0
232
233 #define SMC_inb(a, r) inb((u32)a) + (r))
234 #define SMC_inw(a, r) inw(((u32)a) + (r))
235 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
236 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
237 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
238 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
239
240 #define SMC_IRQ_FLAGS (0)
241
242 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
243 #define RPC_LSB_DEFAULT RPC_LED_100_10
244
245 #elif defined(CONFIG_MACH_LPD7A400) || defined(CONFIG_MACH_LPD7A404)
246
247 /* The LPD7A40X_IOBARRIER is necessary to overcome a mismatch between
248 * the way that the CPU handles chip selects and the way that the SMC
249 * chip expects the chip select to operate. Refer to
250 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
251 * IOBARRIER is a byte as a least-common denominator of possible
252 * regions to use as the barrier. It would be wasteful to read 32
253 * bits from a byte oriented region.
254 *
255 * There is no explicit protection against interrupts intervening
256 * between the writew and the IOBARRIER. In SMC ISR there is a
257 * preamble that performs an IOBARRIER in the extremely unlikely event
258 * that the driver interrupts itself between a writew to the chip an
259 * the IOBARRIER that follows *and* the cache is large enough that the
260 * first off-chip access while handing the interrupt is to the SMC
261 * chip. Other devices in the same address space as the SMC chip must
262 * be aware of the potential for trouble and perform a similar
263 * IOBARRIER on entry to their ISR.
264 */
265
266 #include <asm/arch/constants.h> /* IOBARRIER_VIRT */
267
268 #define SMC_CAN_USE_8BIT 0
269 #define SMC_CAN_USE_16BIT 1
270 #define SMC_CAN_USE_32BIT 0
271 #define SMC_NOWAIT 0
272 #define LPD7A40X_IOBARRIER readb (IOBARRIER_VIRT)
273
274 #define SMC_inw(a,r) readw ((void*) ((a) + (r)))
275 #define SMC_insw(a,r,p,l) readsw ((void*) ((a) + (r)), p, l)
276 #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7A40X_IOBARRIER; })
277
278 #define SMC_outsw LPD7A40X_SMC_outsw
279
280 static inline void LPD7A40X_SMC_outsw(unsigned long a, int r,
281 unsigned char* p, int l)
282 {
283 unsigned short* ps = (unsigned short*) p;
284 while (l-- > 0) {
285 writew (*ps++, a + r);
286 LPD7A40X_IOBARRIER;
287 }
288 }
289
290 #define SMC_INTERRUPT_PREAMBLE LPD7A40X_IOBARRIER
291
292 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
293 #define RPC_LSB_DEFAULT RPC_LED_100_10
294
295 #elif defined(CONFIG_SOC_AU1X00)
296
297 #include <au1xxx.h>
298
299 /* We can only do 16-bit reads and writes in the static memory space. */
300 #define SMC_CAN_USE_8BIT 0
301 #define SMC_CAN_USE_16BIT 1
302 #define SMC_CAN_USE_32BIT 0
303 #define SMC_IO_SHIFT 0
304 #define SMC_NOWAIT 1
305
306 #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
307 #define SMC_insw(a, r, p, l) \
308 do { \
309 unsigned long _a = (unsigned long)((a) + (r)); \
310 int _l = (l); \
311 u16 *_p = (u16 *)(p); \
312 while (_l-- > 0) \
313 *_p++ = au_readw(_a); \
314 } while(0)
315 #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
316 #define SMC_outsw(a, r, p, l) \
317 do { \
318 unsigned long _a = (unsigned long)((a) + (r)); \
319 int _l = (l); \
320 const u16 *_p = (const u16 *)(p); \
321 while (_l-- > 0) \
322 au_writew(*_p++ , _a); \
323 } while(0)
324
325 #define SMC_IRQ_FLAGS (0)
326
327 #else
328
329 #define SMC_CAN_USE_8BIT 1
330 #define SMC_CAN_USE_16BIT 1
331 #define SMC_CAN_USE_32BIT 1
332 #define SMC_NOWAIT 1
333
334 #define SMC_inb(a, r) readb((a) + (r))
335 #define SMC_inw(a, r) readw((a) + (r))
336 #define SMC_inl(a, r) readl((a) + (r))
337 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
338 #define SMC_outw(v, a, r) writew(v, (a) + (r))
339 #define SMC_outl(v, a, r) writel(v, (a) + (r))
340 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
341 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
342
343 #define RPC_LSA_DEFAULT RPC_LED_100_10
344 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
345
346 #endif
347
348 #ifdef SMC_USE_PXA_DMA
349 /*
350 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
351 * always happening in irq context so no need to worry about races. TX is
352 * different and probably not worth it for that reason, and not as critical
353 * as RX which can overrun memory and lose packets.
354 */
355 #include <linux/dma-mapping.h>
356 #include <asm/dma.h>
357 #include <asm/arch/pxa-regs.h>
358
359 #ifdef SMC_insl
360 #undef SMC_insl
361 #define SMC_insl(a, r, p, l) \
362 smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l)
363 static inline void
364 smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
365 u_char *buf, int len)
366 {
367 dma_addr_t dmabuf;
368
369 /* fallback if no DMA available */
370 if (dma == (unsigned char)-1) {
371 readsl(ioaddr + reg, buf, len);
372 return;
373 }
374
375 /* 64 bit alignment is required for memory to memory DMA */
376 if ((long)buf & 4) {
377 *((u32 *)buf) = SMC_inl(ioaddr, reg);
378 buf += 4;
379 len--;
380 }
381
382 len *= 4;
383 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
384 DCSR(dma) = DCSR_NODESC;
385 DTADR(dma) = dmabuf;
386 DSADR(dma) = physaddr + reg;
387 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
388 DCMD_WIDTH4 | (DCMD_LENGTH & len));
389 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
390 while (!(DCSR(dma) & DCSR_STOPSTATE))
391 cpu_relax();
392 DCSR(dma) = 0;
393 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
394 }
395 #endif
396
397 #ifdef SMC_insw
398 #undef SMC_insw
399 #define SMC_insw(a, r, p, l) \
400 smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l)
401 static inline void
402 smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
403 u_char *buf, int len)
404 {
405 dma_addr_t dmabuf;
406
407 /* fallback if no DMA available */
408 if (dma == (unsigned char)-1) {
409 readsw(ioaddr + reg, buf, len);
410 return;
411 }
412
413 /* 64 bit alignment is required for memory to memory DMA */
414 while ((long)buf & 6) {
415 *((u16 *)buf) = SMC_inw(ioaddr, reg);
416 buf += 2;
417 len--;
418 }
419
420 len *= 2;
421 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
422 DCSR(dma) = DCSR_NODESC;
423 DTADR(dma) = dmabuf;
424 DSADR(dma) = physaddr + reg;
425 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
426 DCMD_WIDTH2 | (DCMD_LENGTH & len));
427 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
428 while (!(DCSR(dma) & DCSR_STOPSTATE))
429 cpu_relax();
430 DCSR(dma) = 0;
431 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
432 }
433 #endif
434
435 static void
436 smc_pxa_dma_irq(int dma, void *dummy, struct pt_regs *regs)
437 {
438 DCSR(dma) = 0;
439 }
440 #endif /* SMC_USE_PXA_DMA */
441
442
443 /*
444 * Everything a particular hardware setup needs should have been defined
445 * at this point. Add stubs for the undefined cases, mainly to avoid
446 * compilation warnings since they'll be optimized away, or to prevent buggy
447 * use of them.
448 */
449
450 #if ! SMC_CAN_USE_32BIT
451 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
452 #define SMC_outl(x, ioaddr, reg) BUG()
453 #define SMC_insl(a, r, p, l) BUG()
454 #define SMC_outsl(a, r, p, l) BUG()
455 #endif
456
457 #if !defined(SMC_insl) || !defined(SMC_outsl)
458 #define SMC_insl(a, r, p, l) BUG()
459 #define SMC_outsl(a, r, p, l) BUG()
460 #endif
461
462 #if ! SMC_CAN_USE_16BIT
463
464 /*
465 * Any 16-bit access is performed with two 8-bit accesses if the hardware
466 * can't do it directly. Most registers are 16-bit so those are mandatory.
467 */
468 #define SMC_outw(x, ioaddr, reg) \
469 do { \
470 unsigned int __val16 = (x); \
471 SMC_outb( __val16, ioaddr, reg ); \
472 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
473 } while (0)
474 #define SMC_inw(ioaddr, reg) \
475 ({ \
476 unsigned int __val16; \
477 __val16 = SMC_inb( ioaddr, reg ); \
478 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
479 __val16; \
480 })
481
482 #define SMC_insw(a, r, p, l) BUG()
483 #define SMC_outsw(a, r, p, l) BUG()
484
485 #endif
486
487 #if !defined(SMC_insw) || !defined(SMC_outsw)
488 #define SMC_insw(a, r, p, l) BUG()
489 #define SMC_outsw(a, r, p, l) BUG()
490 #endif
491
492 #if ! SMC_CAN_USE_8BIT
493 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
494 #define SMC_outb(x, ioaddr, reg) BUG()
495 #define SMC_insb(a, r, p, l) BUG()
496 #define SMC_outsb(a, r, p, l) BUG()
497 #endif
498
499 #if !defined(SMC_insb) || !defined(SMC_outsb)
500 #define SMC_insb(a, r, p, l) BUG()
501 #define SMC_outsb(a, r, p, l) BUG()
502 #endif
503
504 #ifndef SMC_CAN_USE_DATACS
505 #define SMC_CAN_USE_DATACS 0
506 #endif
507
508 #ifndef SMC_IO_SHIFT
509 #define SMC_IO_SHIFT 0
510 #endif
511
512 #ifndef SMC_IRQ_FLAGS
513 #define SMC_IRQ_FLAGS SA_TRIGGER_RISING
514 #endif
515
516 #ifndef SMC_INTERRUPT_PREAMBLE
517 #define SMC_INTERRUPT_PREAMBLE
518 #endif
519
520
521 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
522 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
523 #define SMC_DATA_EXTENT (4)
524
525 /*
526 . Bank Select Register:
527 .
528 . yyyy yyyy 0000 00xx
529 . xx = bank number
530 . yyyy yyyy = 0x33, for identification purposes.
531 */
532 #define BANK_SELECT (14 << SMC_IO_SHIFT)
533
534
535 // Transmit Control Register
536 /* BANK 0 */
537 #define TCR_REG SMC_REG(0x0000, 0)
538 #define TCR_ENABLE 0x0001 // When 1 we can transmit
539 #define TCR_LOOP 0x0002 // Controls output pin LBK
540 #define TCR_FORCOL 0x0004 // When 1 will force a collision
541 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
542 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
543 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
544 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
545 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
546 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
547 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
548
549 #define TCR_CLEAR 0 /* do NOTHING */
550 /* the default settings for the TCR register : */
551 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
552
553
554 // EPH Status Register
555 /* BANK 0 */
556 #define EPH_STATUS_REG SMC_REG(0x0002, 0)
557 #define ES_TX_SUC 0x0001 // Last TX was successful
558 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
559 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
560 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
561 #define ES_16COL 0x0010 // 16 Collisions Reached
562 #define ES_SQET 0x0020 // Signal Quality Error Test
563 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
564 #define ES_TXDEFR 0x0080 // Transmit Deferred
565 #define ES_LATCOL 0x0200 // Late collision detected on last tx
566 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
567 #define ES_EXC_DEF 0x0800 // Excessive Deferral
568 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
569 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
570 #define ES_TXUNRN 0x8000 // Tx Underrun
571
572
573 // Receive Control Register
574 /* BANK 0 */
575 #define RCR_REG SMC_REG(0x0004, 0)
576 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
577 #define RCR_PRMS 0x0002 // Enable promiscuous mode
578 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
579 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
580 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
581 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
582 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
583 #define RCR_SOFTRST 0x8000 // resets the chip
584
585 /* the normal settings for the RCR register : */
586 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
587 #define RCR_CLEAR 0x0 // set it to a base state
588
589
590 // Counter Register
591 /* BANK 0 */
592 #define COUNTER_REG SMC_REG(0x0006, 0)
593
594
595 // Memory Information Register
596 /* BANK 0 */
597 #define MIR_REG SMC_REG(0x0008, 0)
598
599
600 // Receive/Phy Control Register
601 /* BANK 0 */
602 #define RPC_REG SMC_REG(0x000A, 0)
603 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
604 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
605 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
606 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
607 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
608 #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
609 #define RPC_LED_RES (0x01) // LED = Reserved
610 #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
611 #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
612 #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
613 #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
614 #define RPC_LED_TX (0x06) // LED = TX packet occurred
615 #define RPC_LED_RX (0x07) // LED = RX packet occurred
616
617 #ifndef RPC_LSA_DEFAULT
618 #define RPC_LSA_DEFAULT RPC_LED_100
619 #endif
620 #ifndef RPC_LSB_DEFAULT
621 #define RPC_LSB_DEFAULT RPC_LED_FD
622 #endif
623
624 #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
625
626
627 /* Bank 0 0x0C is reserved */
628
629 // Bank Select Register
630 /* All Banks */
631 #define BSR_REG 0x000E
632
633
634 // Configuration Reg
635 /* BANK 1 */
636 #define CONFIG_REG SMC_REG(0x0000, 1)
637 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
638 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
639 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
640 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
641
642 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
643 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
644
645
646 // Base Address Register
647 /* BANK 1 */
648 #define BASE_REG SMC_REG(0x0002, 1)
649
650
651 // Individual Address Registers
652 /* BANK 1 */
653 #define ADDR0_REG SMC_REG(0x0004, 1)
654 #define ADDR1_REG SMC_REG(0x0006, 1)
655 #define ADDR2_REG SMC_REG(0x0008, 1)
656
657
658 // General Purpose Register
659 /* BANK 1 */
660 #define GP_REG SMC_REG(0x000A, 1)
661
662
663 // Control Register
664 /* BANK 1 */
665 #define CTL_REG SMC_REG(0x000C, 1)
666 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
667 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
668 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
669 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
670 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
671 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
672 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
673 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
674
675
676 // MMU Command Register
677 /* BANK 2 */
678 #define MMU_CMD_REG SMC_REG(0x0000, 2)
679 #define MC_BUSY 1 // When 1 the last release has not completed
680 #define MC_NOP (0<<5) // No Op
681 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
682 #define MC_RESET (2<<5) // Reset MMU to initial state
683 #define MC_REMOVE (3<<5) // Remove the current rx packet
684 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
685 #define MC_FREEPKT (5<<5) // Release packet in PNR register
686 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
687 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
688
689
690 // Packet Number Register
691 /* BANK 2 */
692 #define PN_REG SMC_REG(0x0002, 2)
693
694
695 // Allocation Result Register
696 /* BANK 2 */
697 #define AR_REG SMC_REG(0x0003, 2)
698 #define AR_FAILED 0x80 // Alocation Failed
699
700
701 // TX FIFO Ports Register
702 /* BANK 2 */
703 #define TXFIFO_REG SMC_REG(0x0004, 2)
704 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
705
706 // RX FIFO Ports Register
707 /* BANK 2 */
708 #define RXFIFO_REG SMC_REG(0x0005, 2)
709 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
710
711 #define FIFO_REG SMC_REG(0x0004, 2)
712
713 // Pointer Register
714 /* BANK 2 */
715 #define PTR_REG SMC_REG(0x0006, 2)
716 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
717 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
718 #define PTR_READ 0x2000 // When 1 the operation is a read
719
720
721 // Data Register
722 /* BANK 2 */
723 #define DATA_REG SMC_REG(0x0008, 2)
724
725
726 // Interrupt Status/Acknowledge Register
727 /* BANK 2 */
728 #define INT_REG SMC_REG(0x000C, 2)
729
730
731 // Interrupt Mask Register
732 /* BANK 2 */
733 #define IM_REG SMC_REG(0x000D, 2)
734 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
735 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
736 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
737 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
738 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
739 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
740 #define IM_TX_INT 0x02 // Transmit Interrupt
741 #define IM_RCV_INT 0x01 // Receive Interrupt
742
743
744 // Multicast Table Registers
745 /* BANK 3 */
746 #define MCAST_REG1 SMC_REG(0x0000, 3)
747 #define MCAST_REG2 SMC_REG(0x0002, 3)
748 #define MCAST_REG3 SMC_REG(0x0004, 3)
749 #define MCAST_REG4 SMC_REG(0x0006, 3)
750
751
752 // Management Interface Register (MII)
753 /* BANK 3 */
754 #define MII_REG SMC_REG(0x0008, 3)
755 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
756 #define MII_MDOE 0x0008 // MII Output Enable
757 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
758 #define MII_MDI 0x0002 // MII Input, pin MDI
759 #define MII_MDO 0x0001 // MII Output, pin MDO
760
761
762 // Revision Register
763 /* BANK 3 */
764 /* ( hi: chip id low: rev # ) */
765 #define REV_REG SMC_REG(0x000A, 3)
766
767
768 // Early RCV Register
769 /* BANK 3 */
770 /* this is NOT on SMC9192 */
771 #define ERCV_REG SMC_REG(0x000C, 3)
772 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
773 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
774
775
776 // External Register
777 /* BANK 7 */
778 #define EXT_REG SMC_REG(0x0000, 7)
779
780
781 #define CHIP_9192 3
782 #define CHIP_9194 4
783 #define CHIP_9195 5
784 #define CHIP_9196 6
785 #define CHIP_91100 7
786 #define CHIP_91100FD 8
787 #define CHIP_91111FD 9
788
789 static const char * chip_ids[ 16 ] = {
790 NULL, NULL, NULL,
791 /* 3 */ "SMC91C90/91C92",
792 /* 4 */ "SMC91C94",
793 /* 5 */ "SMC91C95",
794 /* 6 */ "SMC91C96",
795 /* 7 */ "SMC91C100",
796 /* 8 */ "SMC91C100FD",
797 /* 9 */ "SMC91C11xFD",
798 NULL, NULL, NULL,
799 NULL, NULL, NULL};
800
801
802 /*
803 . Receive status bits
804 */
805 #define RS_ALGNERR 0x8000
806 #define RS_BRODCAST 0x4000
807 #define RS_BADCRC 0x2000
808 #define RS_ODDFRAME 0x1000
809 #define RS_TOOLONG 0x0800
810 #define RS_TOOSHORT 0x0400
811 #define RS_MULTICAST 0x0001
812 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
813
814
815 /*
816 * PHY IDs
817 * LAN83C183 == LAN91C111 Internal PHY
818 */
819 #define PHY_LAN83C183 0x0016f840
820 #define PHY_LAN83C180 0x02821c50
821
822 /*
823 * PHY Register Addresses (LAN91C111 Internal PHY)
824 *
825 * Generic PHY registers can be found in <linux/mii.h>
826 *
827 * These phy registers are specific to our on-board phy.
828 */
829
830 // PHY Configuration Register 1
831 #define PHY_CFG1_REG 0x10
832 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
833 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
834 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
835 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
836 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
837 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
838 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
839 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
840 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
841 #define PHY_CFG1_TLVL_MASK 0x003C
842 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
843
844
845 // PHY Configuration Register 2
846 #define PHY_CFG2_REG 0x11
847 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
848 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
849 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
850 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
851
852 // PHY Status Output (and Interrupt status) Register
853 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
854 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
855 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
856 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
857 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
858 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
859 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
860 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
861 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
862 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
863 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
864
865 // PHY Interrupt/Status Mask Register
866 #define PHY_MASK_REG 0x13 // Interrupt Mask
867 // Uses the same bit definitions as PHY_INT_REG
868
869
870 /*
871 * SMC91C96 ethernet config and status registers.
872 * These are in the "attribute" space.
873 */
874 #define ECOR 0x8000
875 #define ECOR_RESET 0x80
876 #define ECOR_LEVEL_IRQ 0x40
877 #define ECOR_WR_ATTRIB 0x04
878 #define ECOR_ENABLE 0x01
879
880 #define ECSR 0x8002
881 #define ECSR_IOIS8 0x20
882 #define ECSR_PWRDWN 0x04
883 #define ECSR_INT 0x02
884
885 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
886
887
888 /*
889 * Macros to abstract register access according to the data bus
890 * capabilities. Please use those and not the in/out primitives.
891 * Note: the following macros do *not* select the bank -- this must
892 * be done separately as needed in the main code. The SMC_REG() macro
893 * only uses the bank argument for debugging purposes (when enabled).
894 *
895 * Note: despite inline functions being safer, everything leading to this
896 * should preferably be macros to let BUG() display the line number in
897 * the core source code since we're interested in the top call site
898 * not in any inline function location.
899 */
900
901 #if SMC_DEBUG > 0
902 #define SMC_REG(reg, bank) \
903 ({ \
904 int __b = SMC_CURRENT_BANK(); \
905 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
906 printk( "%s: bank reg screwed (0x%04x)\n", \
907 CARDNAME, __b ); \
908 BUG(); \
909 } \
910 reg<<SMC_IO_SHIFT; \
911 })
912 #else
913 #define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT)
914 #endif
915
916 /*
917 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
918 * aligned to a 32 bit boundary. I tell you that does exist!
919 * Fortunately the affected register accesses can be easily worked around
920 * since we can write zeroes to the preceeding 16 bits without adverse
921 * effects and use a 32-bit access.
922 *
923 * Enforce it on any 32-bit capable setup for now.
924 */
925 #define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT
926
927 #define SMC_GET_PN() \
928 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG)) \
929 : (SMC_inw(ioaddr, PN_REG) & 0xFF) )
930
931 #define SMC_SET_PN(x) \
932 do { \
933 if (SMC_MUST_ALIGN_WRITE) \
934 SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2)); \
935 else if (SMC_CAN_USE_8BIT) \
936 SMC_outb(x, ioaddr, PN_REG); \
937 else \
938 SMC_outw(x, ioaddr, PN_REG); \
939 } while (0)
940
941 #define SMC_GET_AR() \
942 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG)) \
943 : (SMC_inw(ioaddr, PN_REG) >> 8) )
944
945 #define SMC_GET_TXFIFO() \
946 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG)) \
947 : (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) )
948
949 #define SMC_GET_RXFIFO() \
950 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG)) \
951 : (SMC_inw(ioaddr, TXFIFO_REG) >> 8) )
952
953 #define SMC_GET_INT() \
954 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG)) \
955 : (SMC_inw(ioaddr, INT_REG) & 0xFF) )
956
957 #define SMC_ACK_INT(x) \
958 do { \
959 if (SMC_CAN_USE_8BIT) \
960 SMC_outb(x, ioaddr, INT_REG); \
961 else { \
962 unsigned long __flags; \
963 int __mask; \
964 local_irq_save(__flags); \
965 __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \
966 SMC_outw( __mask | (x), ioaddr, INT_REG ); \
967 local_irq_restore(__flags); \
968 } \
969 } while (0)
970
971 #define SMC_GET_INT_MASK() \
972 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \
973 : (SMC_inw( ioaddr, INT_REG ) >> 8) )
974
975 #define SMC_SET_INT_MASK(x) \
976 do { \
977 if (SMC_CAN_USE_8BIT) \
978 SMC_outb(x, ioaddr, IM_REG); \
979 else \
980 SMC_outw((x) << 8, ioaddr, INT_REG); \
981 } while (0)
982
983 #define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT)
984
985 #define SMC_SELECT_BANK(x) \
986 do { \
987 if (SMC_MUST_ALIGN_WRITE) \
988 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
989 else \
990 SMC_outw(x, ioaddr, BANK_SELECT); \
991 } while (0)
992
993 #define SMC_GET_BASE() SMC_inw(ioaddr, BASE_REG)
994
995 #define SMC_SET_BASE(x) SMC_outw(x, ioaddr, BASE_REG)
996
997 #define SMC_GET_CONFIG() SMC_inw(ioaddr, CONFIG_REG)
998
999 #define SMC_SET_CONFIG(x) SMC_outw(x, ioaddr, CONFIG_REG)
1000
1001 #define SMC_GET_COUNTER() SMC_inw(ioaddr, COUNTER_REG)
1002
1003 #define SMC_GET_CTL() SMC_inw(ioaddr, CTL_REG)
1004
1005 #define SMC_SET_CTL(x) SMC_outw(x, ioaddr, CTL_REG)
1006
1007 #define SMC_GET_MII() SMC_inw(ioaddr, MII_REG)
1008
1009 #define SMC_SET_MII(x) SMC_outw(x, ioaddr, MII_REG)
1010
1011 #define SMC_GET_MIR() SMC_inw(ioaddr, MIR_REG)
1012
1013 #define SMC_SET_MIR(x) SMC_outw(x, ioaddr, MIR_REG)
1014
1015 #define SMC_GET_MMU_CMD() SMC_inw(ioaddr, MMU_CMD_REG)
1016
1017 #define SMC_SET_MMU_CMD(x) SMC_outw(x, ioaddr, MMU_CMD_REG)
1018
1019 #define SMC_GET_FIFO() SMC_inw(ioaddr, FIFO_REG)
1020
1021 #define SMC_GET_PTR() SMC_inw(ioaddr, PTR_REG)
1022
1023 #define SMC_SET_PTR(x) \
1024 do { \
1025 if (SMC_MUST_ALIGN_WRITE) \
1026 SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2)); \
1027 else \
1028 SMC_outw(x, ioaddr, PTR_REG); \
1029 } while (0)
1030
1031 #define SMC_GET_EPH_STATUS() SMC_inw(ioaddr, EPH_STATUS_REG)
1032
1033 #define SMC_GET_RCR() SMC_inw(ioaddr, RCR_REG)
1034
1035 #define SMC_SET_RCR(x) SMC_outw(x, ioaddr, RCR_REG)
1036
1037 #define SMC_GET_REV() SMC_inw(ioaddr, REV_REG)
1038
1039 #define SMC_GET_RPC() SMC_inw(ioaddr, RPC_REG)
1040
1041 #define SMC_SET_RPC(x) \
1042 do { \
1043 if (SMC_MUST_ALIGN_WRITE) \
1044 SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0)); \
1045 else \
1046 SMC_outw(x, ioaddr, RPC_REG); \
1047 } while (0)
1048
1049 #define SMC_GET_TCR() SMC_inw(ioaddr, TCR_REG)
1050
1051 #define SMC_SET_TCR(x) SMC_outw(x, ioaddr, TCR_REG)
1052
1053 #ifndef SMC_GET_MAC_ADDR
1054 #define SMC_GET_MAC_ADDR(addr) \
1055 do { \
1056 unsigned int __v; \
1057 __v = SMC_inw( ioaddr, ADDR0_REG ); \
1058 addr[0] = __v; addr[1] = __v >> 8; \
1059 __v = SMC_inw( ioaddr, ADDR1_REG ); \
1060 addr[2] = __v; addr[3] = __v >> 8; \
1061 __v = SMC_inw( ioaddr, ADDR2_REG ); \
1062 addr[4] = __v; addr[5] = __v >> 8; \
1063 } while (0)
1064 #endif
1065
1066 #define SMC_SET_MAC_ADDR(addr) \
1067 do { \
1068 SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \
1069 SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \
1070 SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \
1071 } while (0)
1072
1073 #define SMC_SET_MCAST(x) \
1074 do { \
1075 const unsigned char *mt = (x); \
1076 SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \
1077 SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \
1078 SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \
1079 SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \
1080 } while (0)
1081
1082 #define SMC_PUT_PKT_HDR(status, length) \
1083 do { \
1084 if (SMC_CAN_USE_32BIT) \
1085 SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \
1086 else { \
1087 SMC_outw(status, ioaddr, DATA_REG); \
1088 SMC_outw(length, ioaddr, DATA_REG); \
1089 } \
1090 } while (0)
1091
1092 #define SMC_GET_PKT_HDR(status, length) \
1093 do { \
1094 if (SMC_CAN_USE_32BIT) { \
1095 unsigned int __val = SMC_inl(ioaddr, DATA_REG); \
1096 (status) = __val & 0xffff; \
1097 (length) = __val >> 16; \
1098 } else { \
1099 (status) = SMC_inw(ioaddr, DATA_REG); \
1100 (length) = SMC_inw(ioaddr, DATA_REG); \
1101 } \
1102 } while (0)
1103
1104 #define SMC_PUSH_DATA(p, l) \
1105 do { \
1106 if (SMC_CAN_USE_32BIT) { \
1107 void *__ptr = (p); \
1108 int __len = (l); \
1109 void *__ioaddr = ioaddr; \
1110 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1111 __len -= 2; \
1112 SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \
1113 __ptr += 2; \
1114 } \
1115 if (SMC_CAN_USE_DATACS && lp->datacs) \
1116 __ioaddr = lp->datacs; \
1117 SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1118 if (__len & 2) { \
1119 __ptr += (__len & ~3); \
1120 SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \
1121 } \
1122 } else if (SMC_CAN_USE_16BIT) \
1123 SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1); \
1124 else if (SMC_CAN_USE_8BIT) \
1125 SMC_outsb(ioaddr, DATA_REG, p, l); \
1126 } while (0)
1127
1128 #define SMC_PULL_DATA(p, l) \
1129 do { \
1130 if (SMC_CAN_USE_32BIT) { \
1131 void *__ptr = (p); \
1132 int __len = (l); \
1133 void *__ioaddr = ioaddr; \
1134 if ((unsigned long)__ptr & 2) { \
1135 /* \
1136 * We want 32bit alignment here. \
1137 * Since some buses perform a full \
1138 * 32bit fetch even for 16bit data \
1139 * we can't use SMC_inw() here. \
1140 * Back both source (on-chip) and \
1141 * destination pointers of 2 bytes. \
1142 * This is possible since the call to \
1143 * SMC_GET_PKT_HDR() already advanced \
1144 * the source pointer of 4 bytes, and \
1145 * the skb_reserve(skb, 2) advanced \
1146 * the destination pointer of 2 bytes. \
1147 */ \
1148 __ptr -= 2; \
1149 __len += 2; \
1150 SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1151 } \
1152 if (SMC_CAN_USE_DATACS && lp->datacs) \
1153 __ioaddr = lp->datacs; \
1154 __len += 2; \
1155 SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1156 } else if (SMC_CAN_USE_16BIT) \
1157 SMC_insw(ioaddr, DATA_REG, p, (l) >> 1); \
1158 else if (SMC_CAN_USE_8BIT) \
1159 SMC_insb(ioaddr, DATA_REG, p, l); \
1160 } while (0)
1161
1162 #endif /* _SMC91X_H_ */
Linux with added FPC-III support