5 "EventName": "L1D_RO_EXCL_WRITES",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 "PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line"
12 "EventName": "DTLB2_WRITES",
13 "BriefDescription": "DTLB2 Writes",
14 "PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache"
19 "EventName": "DTLB2_MISSES",
20 "BriefDescription": "DTLB2 Misses",
21 "PublicDescription": "A TLB2 miss is in progress for a request made by the data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle"
26 "EventName": "DTLB2_HPAGE_WRITES",
27 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
28 "PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page or a Last Host Translation was done"
33 "EventName": "DTLB2_GPAGE_WRITES",
34 "BriefDescription": "DTLB2 Two-Gigabyte Page Writes",
35 "PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB"
40 "EventName": "L1D_L2D_SOURCED_WRITES",
41 "BriefDescription": "L1D L2D Sourced Writes",
42 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache"
47 "EventName": "ITLB2_WRITES",
48 "BriefDescription": "ITLB2 Writes",
49 "PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache"
54 "EventName": "ITLB2_MISSES",
55 "BriefDescription": "ITLB2 Misses",
56 "PublicDescription": "A TLB2 miss is in progress for a request made by the instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle"
61 "EventName": "L1I_L2I_SOURCED_WRITES",
62 "BriefDescription": "L1I L2I Sourced Writes",
63 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
68 "EventName": "TLB2_PTE_WRITES",
69 "BriefDescription": "TLB2 PTE Writes",
70 "PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB"
75 "EventName": "TLB2_CRSTE_WRITES",
76 "BriefDescription": "TLB2 CRSTE Writes",
77 "PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB"
82 "EventName": "TLB2_ENGINES_BUSY",
83 "BriefDescription": "TLB2 Engines Busy",
84 "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle"
89 "EventName": "TX_C_TEND",
90 "BriefDescription": "Completed TEND instructions in constrained TX mode",
91 "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode"
96 "EventName": "TX_NC_TEND",
97 "BriefDescription": "Completed TEND instructions in non-constrained TX mode",
98 "PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode"
103 "EventName": "L1C_TLB2_MISSES",
104 "BriefDescription": "L1C TLB2 Misses",
105 "PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is in progress"
110 "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
111 "BriefDescription": "L1D On-Chip L3 Sourced Writes",
112 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention"
117 "EventName": "L1D_ONCHIP_MEMORY_SOURCED_WRITES",
118 "BriefDescription": "L1D On-Chip Memory Sourced Writes",
119 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory"
124 "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
125 "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
126 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention"
131 "EventName": "L1D_ONCLUSTER_L3_SOURCED_WRITES",
132 "BriefDescription": "L1D On-Cluster L3 Sourced Writes",
133 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Cluster Level-3 cache withountervention"
138 "EventName": "L1D_ONCLUSTER_MEMORY_SOURCED_WRITES",
139 "BriefDescription": "L1D On-Cluster Memory Sourced Writes",
140 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster memory"
145 "EventName": "L1D_ONCLUSTER_L3_SOURCED_WRITES_IV",
146 "BriefDescription": "L1D On-Cluster L3 Sourced Writes with Intervention",
147 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache with intervention"
152 "EventName": "L1D_OFFCLUSTER_L3_SOURCED_WRITES",
153 "BriefDescription": "L1D Off-Cluster L3 Sourced Writes",
154 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention"
159 "EventName": "L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES",
160 "BriefDescription": "L1D Off-Cluster Memory Sourced Writes",
161 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Cluster memory"
166 "EventName": "L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV",
167 "BriefDescription": "L1D Off-Cluster L3 Sourced Writes with Intervention",
168 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention"
173 "EventName": "L1D_OFFDRAWER_L3_SOURCED_WRITES",
174 "BriefDescription": "L1D Off-Drawer L3 Sourced Writes",
175 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention"
180 "EventName": "L1D_OFFDRAWER_MEMORY_SOURCED_WRITES",
181 "BriefDescription": "L1D Off-Drawer Memory Sourced Writes",
182 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory"
187 "EventName": "L1D_OFFDRAWER_L3_SOURCED_WRITES_IV",
188 "BriefDescription": "L1D Off-Drawer L3 Sourced Writes with Intervention",
189 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention"
194 "EventName": "L1D_ONDRAWER_L4_SOURCED_WRITES",
195 "BriefDescription": "L1D On-Drawer L4 Sourced Writes",
196 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer Level-4 cache"
201 "EventName": "L1D_OFFDRAWER_L4_SOURCED_WRITES",
202 "BriefDescription": "L1D Off-Drawer L4 Sourced Writes",
203 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache"
208 "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_RO",
209 "BriefDescription": "L1D On-Chip L3 Sourced Writes read-only",
210 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip L3 but a read-only invalidate was done to remove other copies of the cache line"
215 "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
216 "BriefDescription": "L1I On-Chip L3 Sourced Writes",
217 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache without intervention"
222 "EventName": "L1I_ONCHIP_MEMORY_SOURCED_WRITES",
223 "BriefDescription": "L1I On-Chip Memory Sourced Writes",
224 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from On-Chip memory"
229 "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
230 "BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention",
231 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache with intervention"
236 "EventName": "L1I_ONCLUSTER_L3_SOURCED_WRITES",
237 "BriefDescription": "L1I On-Cluster L3 Sourced Writes",
238 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache without intervention"
243 "EventName": "L1I_ONCLUSTER_MEMORY_SOURCED_WRITES",
244 "BriefDescription": "L1I On-Cluster Memory Sourced Writes",
245 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster memory"
250 "EventName": "L1I_ONCLUSTER_L3_SOURCED_WRITES_IV",
251 "BriefDescription": "L1I On-Cluster L3 Sourced Writes with Intervention",
252 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Cluster Level-3 cache with intervention"
257 "EventName": "L1I_OFFCLUSTER_L3_SOURCED_WRITES",
258 "BriefDescription": "L1I Off-Cluster L3 Sourced Writes",
259 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention"
264 "EventName": "L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES",
265 "BriefDescription": "L1I Off-Cluster Memory Sourced Writes",
266 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Cluster memory"
271 "EventName": "L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV",
272 "BriefDescription": "L1I Off-Cluster L3 Sourced Writes with Intervention",
273 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention"
278 "EventName": "L1I_OFFDRAWER_L3_SOURCED_WRITES",
279 "BriefDescription": "L1I Off-Drawer L3 Sourced Writes",
280 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention"
285 "EventName": "L1I_OFFDRAWER_MEMORY_SOURCED_WRITES",
286 "BriefDescription": "L1I Off-Drawer Memory Sourced Writes",
287 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory"
292 "EventName": "L1I_OFFDRAWER_L3_SOURCED_WRITES_IV",
293 "BriefDescription": "L1I Off-Drawer L3 Sourced Writes with Intervention",
294 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention"
299 "EventName": "L1I_ONDRAWER_L4_SOURCED_WRITES",
300 "BriefDescription": "L1I On-Drawer L4 Sourced Writes",
301 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer Level-4 cache"
306 "EventName": "L1I_OFFDRAWER_L4_SOURCED_WRITES",
307 "BriefDescription": "L1I Off-Drawer L4 Sourced Writes",
308 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache"
313 "EventName": "BCD_DFP_EXECUTION_SLOTS",
314 "BriefDescription": "BCD DFP Execution Slots",
315 "PublicDescription": "Count of floating point execution slots used for finished Binary Coded Decimal to Decimal Floating Point conversions. Instructions: CDZT, CXZT, CZDT, CZXT"
320 "EventName": "VX_BCD_EXECUTION_SLOTS",
321 "BriefDescription": "VX BCD Execution Slots",
322 "PublicDescription": "Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMPVMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVDVCVDG"
327 "EventName": "DECIMAL_INSTRUCTIONS",
328 "BriefDescription": "Decimal Instructions",
329 "PublicDescription": "Decimal instructions dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP"
334 "EventName": "LAST_HOST_TRANSLATIONS",
335 "BriefDescription": "Last host translation done",
336 "PublicDescription": "Last Host Translation done"
341 "EventName": "TX_NC_TABORT",
342 "BriefDescription": "Aborted transactions in non-constrained TX mode",
343 "PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode"
348 "EventName": "TX_C_TABORT_NO_SPECIAL",
349 "BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic",
350 "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete"
355 "EventName": "TX_C_TABORT_SPECIAL",
356 "BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
357 "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete"
362 "EventName": "MT_DIAG_CYCLES_ONE_THR_ACTIVE",
363 "BriefDescription": "Cycle count with one thread active",
364 "PublicDescription": "Cycle count with one thread active"
369 "EventName": "MT_DIAG_CYCLES_TWO_THR_ACTIVE",
370 "BriefDescription": "Cycle count with two threads active",
371 "PublicDescription": "Cycle count with two threads active"