3 "EventName": "ls_bad_status2.stli_other",
5 "BriefDescription": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. Store To Load Interlock (STLI) are loads that were unable to complete because of a possible match with an older store, and the older store could not do STLF for some reason.",
6 "PublicDescription" : "Store-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older store. Most commonly, a load's address range partially but not completely overlaps with an uncompleted older store. Software can avoid this problem by using same-size and same-alignment loads and stores when accessing the same data. Vector/SIMD code is particularly susceptible to this problem; software should construct wide vector stores by manipulating vector elements in registers using shuffle/blend/swap instructions prior to storing to memory, instead of using narrow element-by-element stores.",
10 "EventName": "ls_locks.spec_lock_hi_spec",
12 "BriefDescription": "Retired lock instructions. High speculative cacheable lock speculation succeeded.",
16 "EventName": "ls_locks.spec_lock_lo_spec",
18 "BriefDescription": "Retired lock instructions. Low speculative cacheable lock speculation succeeded.",
22 "EventName": "ls_locks.non_spec_lock",
24 "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.",
28 "EventName": "ls_locks.bus_lock",
30 "BriefDescription": "Retired lock instructions. Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type. Comparable to legacy bus lock.",
34 "EventName": "ls_ret_cl_flush",
36 "BriefDescription": "Number of retired CLFLUSH instructions."
39 "EventName": "ls_ret_cpuid",
41 "BriefDescription": "Number of retired CPUID instructions."
44 "EventName": "ls_dispatch.ld_st_dispatch",
46 "BriefDescription": "Dispatch of a single op that performs a load from and store to the same memory address. Number of single ops that do load/store to an address.",
50 "EventName": "ls_dispatch.store_dispatch",
52 "BriefDescription": "Number of stores dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
56 "EventName": "ls_dispatch.ld_dispatch",
58 "BriefDescription": "Number of loads dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
62 "EventName": "ls_smi_rx",
64 "BriefDescription": "Number of SMIs received."
67 "EventName": "ls_int_taken",
69 "BriefDescription": "Number of interrupts taken."
72 "EventName": "ls_rdtsc",
74 "BriefDescription": "Number of reads of the TSC (RDTSC instructions). The count is speculative."
77 "EventName": "ls_stlf",
79 "BriefDescription": "Number of STLF hits."
82 "EventName": "ls_st_commit_cancel2.st_commit_cancel_wcb_full",
84 "BriefDescription": "A non-cacheable store and the non-cacheable commit buffer is full."
87 "EventName": "ls_dc_accesses",
89 "BriefDescription": "Number of accesses to the dcache for load/store references.",
90 "PublicDescription": "The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event."
93 "EventName": "ls_mab_alloc.dc_prefetcher",
95 "BriefDescription": "LS MAB Allocates by Type. DC prefetcher.",
99 "EventName": "ls_mab_alloc.stores",
101 "BriefDescription": "LS MAB Allocates by Type. Stores.",
105 "EventName": "ls_mab_alloc.loads",
107 "BriefDescription": "LS MAB Allocates by Type. Loads.",
111 "EventName": "ls_refills_from_sys.ls_mabresp_rmt_dram",
113 "BriefDescription": "Demand Data Cache Fills by Data Source. DRAM or IO from different die.",
117 "EventName": "ls_refills_from_sys.ls_mabresp_rmt_cache",
119 "BriefDescription": "Demand Data Cache Fills by Data Source. Hit in cache; Remote CCX and the address's Home Node is on a different die.",
123 "EventName": "ls_refills_from_sys.ls_mabresp_lcl_dram",
125 "BriefDescription": "Demand Data Cache Fills by Data Source. DRAM or IO from this thread's die.",
129 "EventName": "ls_refills_from_sys.ls_mabresp_lcl_cache",
131 "BriefDescription": "Demand Data Cache Fills by Data Source. Hit in cache; local CCX (not Local L2), or Remote CCX and the address's Home Node is on this thread's die.",
135 "EventName": "ls_refills_from_sys.ls_mabresp_lcl_l2",
137 "BriefDescription": "Demand Data Cache Fills by Data Source. Local L2 hit.",
141 "EventName": "ls_l1_d_tlb_miss.all",
143 "BriefDescription": "All L1 DTLB Misses or Reloads.",
147 "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss",
149 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 1G page that miss in the L2 TLB.",
153 "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss",
155 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 2M page that miss in the L2 TLB.",
159 "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss",
161 "BriefDescription": "L1 DTLB Miss. DTLB reload coalesced page miss.",
165 "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss",
167 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 4K page that miss the L2 TLB.",
171 "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit",
173 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 1G page that hit in the L2 TLB.",
177 "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit",
179 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 2M page that hit in the L2 TLB.",
183 "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit",
185 "BriefDescription": "L1 DTLB Miss. DTLB reload hit a coalesced page.",
189 "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit",
191 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 4K page that hit in the L2 TLB.",
195 "EventName": "ls_tablewalker.iside",
197 "BriefDescription": "Total Page Table Walks on I-side.",
201 "EventName": "ls_tablewalker.ic_type1",
203 "BriefDescription": "Total Page Table Walks IC Type 1.",
207 "EventName": "ls_tablewalker.ic_type0",
209 "BriefDescription": "Total Page Table Walks IC Type 0.",
213 "EventName": "ls_tablewalker.dside",
215 "BriefDescription": "Total Page Table Walks on D-side.",
219 "EventName": "ls_tablewalker.dc_type1",
221 "BriefDescription": "Total Page Table Walks DC Type 1.",
225 "EventName": "ls_tablewalker.dc_type0",
227 "BriefDescription": "Total Page Table Walks DC Type 0.",
231 "EventName": "ls_misal_accesses",
233 "BriefDescription": "Misaligned loads."
236 "EventName": "ls_pref_instr_disp",
238 "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative).",
242 "EventName": "ls_pref_instr_disp.prefetch_nta",
244 "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). PrefetchNTA instruction. See docAPM3 PREFETCHlevel.",
248 "EventName": "ls_pref_instr_disp.prefetch_w",
250 "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). See docAPM3 PREFETCHW.",
254 "EventName": "ls_pref_instr_disp.prefetch",
256 "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). Prefetch_T0_T1_T2. PrefetchT0, T1 and T2 instructions. See docAPM3 PREFETCHlevel.",
260 "EventName": "ls_inef_sw_pref.mab_mch_cnt",
262 "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a match on an already-allocated miss request buffer.",
266 "EventName": "ls_inef_sw_pref.data_pipe_sw_pf_dc_hit",
268 "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a DC hit.",
272 "EventName": "ls_sw_pf_dc_fill.ls_mabresp_rmt_dram",
274 "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From DRAM (home node remote).",
278 "EventName": "ls_sw_pf_dc_fill.ls_mabresp_rmt_cache",
280 "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From another cache (home node remote).",
284 "EventName": "ls_sw_pf_dc_fill.ls_mabresp_lcl_dram",
286 "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. DRAM or IO from this thread's die. From DRAM (home node local).",
290 "EventName": "ls_sw_pf_dc_fill.ls_mabresp_lcl_cache",
292 "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From another cache (home node local).",
296 "EventName": "ls_sw_pf_dc_fill.ls_mabresp_lcl_l2",
298 "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. Local L2 hit.",
302 "EventName": "ls_hw_pf_dc_fill.ls_mabresp_rmt_dram",
304 "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node remote).",
308 "EventName": "ls_hw_pf_dc_fill.ls_mabresp_rmt_cache",
310 "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node remote).",
314 "EventName": "ls_hw_pf_dc_fill.ls_mabresp_lcl_dram",
316 "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node local).",
320 "EventName": "ls_hw_pf_dc_fill.ls_mabresp_lcl_cache",
322 "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node local).",
326 "EventName": "ls_hw_pf_dc_fill.ls_mabresp_lcl_l2",
328 "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. Local L2 hit.",
332 "EventName": "ls_not_halted_cyc",
334 "BriefDescription": "Cycles not in Halt."
337 "EventName": "ls_tlb_flush",
339 "BriefDescription": "All TLB Flushes"