| blob | 777b500a5c9f3ef2cf3a37da339edfc94d2e294c |
1 [
2 {
3 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
4 "EventCode": "0x08",
5 "Counter": "0,1,2,3",
6 "UMask": "0x1",
7 "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
8 "SampleAfterValue": "100003",
9 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
10 "CounterHTOff": "0,1,2,3,4,5,6,7"
11 },
12 {
13 "PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.",
14 "EventCode": "0x08",
15 "Counter": "0,1,2,3",
16 "UMask": "0x2",
17 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
18 "SampleAfterValue": "2000003",
19 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
20 "CounterHTOff": "0,1,2,3,4,5,6,7"
21 },
22 {
23 "PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.",
24 "EventCode": "0x08",
25 "Counter": "0,1,2,3",
26 "UMask": "0x4",
27 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
28 "SampleAfterValue": "2000003",
29 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
30 "CounterHTOff": "0,1,2,3,4,5,6,7"
31 },
32 {
33 "EventCode": "0x08",
34 "Counter": "0,1,2,3",
35 "UMask": "0x8",
36 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
37 "SampleAfterValue": "2000003",
38 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
39 "CounterHTOff": "0,1,2,3,4,5,6,7"
40 },
41 {
42 "PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.",
43 "EventCode": "0x08",
44 "Counter": "0,1,2,3",
45 "UMask": "0xe",
46 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
47 "SampleAfterValue": "100003",
48 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
49 "CounterHTOff": "0,1,2,3,4,5,6,7"
50 },
51 {
52 "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
53 "EventCode": "0x08",
54 "Counter": "0,1,2,3",
55 "UMask": "0x10",
56 "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
57 "SampleAfterValue": "2000003",
58 "BriefDescription": "Cycles when PMH is busy with page walks",
59 "CounterHTOff": "0,1,2,3,4,5,6,7"
60 },
61 {
62 "PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
63 "EventCode": "0x08",
64 "Counter": "0,1,2,3",
65 "UMask": "0x20",
66 "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
67 "SampleAfterValue": "2000003",
68 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)",
69 "CounterHTOff": "0,1,2,3,4,5,6,7"
70 },
71 {
72 "PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
73 "EventCode": "0x08",
74 "Counter": "0,1,2,3",
75 "UMask": "0x40",
76 "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
77 "SampleAfterValue": "2000003",
78 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)",
79 "CounterHTOff": "0,1,2,3,4,5,6,7"
80 },
81 {
82 "PublicDescription": "Number of cache load STLB hits. No page walk.",
83 "EventCode": "0x08",
84 "Counter": "0,1,2,3",
85 "UMask": "0x60",
86 "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
87 "SampleAfterValue": "2000003",
88 "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
89 "CounterHTOff": "0,1,2,3,4,5,6,7"
90 },
91 {
92 "PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.",
93 "EventCode": "0x08",
94 "Counter": "0,1,2,3",
95 "UMask": "0x80",
96 "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS",
97 "SampleAfterValue": "100003",
98 "BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed",
99 "CounterHTOff": "0,1,2,3,4,5,6,7"
100 },
101 {
102 "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
103 "EventCode": "0x49",
104 "Counter": "0,1,2,3",
105 "UMask": "0x1",
106 "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
107 "SampleAfterValue": "100003",
108 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
109 "CounterHTOff": "0,1,2,3,4,5,6,7"
110 },
111 {
112 "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.",
113 "EventCode": "0x49",
114 "Counter": "0,1,2,3",
115 "UMask": "0x2",
116 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
117 "SampleAfterValue": "100003",
118 "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
119 "CounterHTOff": "0,1,2,3,4,5,6,7"
120 },
121 {
122 "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.",
123 "EventCode": "0x49",
124 "Counter": "0,1,2,3",
125 "UMask": "0x4",
126 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
127 "SampleAfterValue": "100003",
128 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
129 "CounterHTOff": "0,1,2,3,4,5,6,7"
130 },
131 {
132 "EventCode": "0x49",
133 "Counter": "0,1,2,3",
134 "UMask": "0x8",
135 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
136 "SampleAfterValue": "100003",
137 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks. (1G)",
138 "CounterHTOff": "0,1,2,3,4,5,6,7"
139 },
140 {
141 "PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).",
142 "EventCode": "0x49",
143 "Counter": "0,1,2,3",
144 "UMask": "0xe",
145 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
146 "SampleAfterValue": "100003",
147 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
148 "CounterHTOff": "0,1,2,3,4,5,6,7"
149 },
150 {
151 "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses.",
152 "EventCode": "0x49",
153 "Counter": "0,1,2,3",
154 "UMask": "0x10",
155 "EventName": "DTLB_STORE_MISSES.WALK_DURATION",
156 "SampleAfterValue": "100003",
157 "BriefDescription": "Cycles when PMH is busy with page walks",
158 "CounterHTOff": "0,1,2,3,4,5,6,7"
159 },
160 {
161 "PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
162 "EventCode": "0x49",
163 "Counter": "0,1,2,3",
164 "UMask": "0x20",
165 "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
166 "SampleAfterValue": "100003",
167 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)",
168 "CounterHTOff": "0,1,2,3,4,5,6,7"
169 },
170 {
171 "PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
172 "EventCode": "0x49",
173 "Counter": "0,1,2,3",
174 "UMask": "0x40",
175 "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
176 "SampleAfterValue": "100003",
177 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)",
178 "CounterHTOff": "0,1,2,3,4,5,6,7"
179 },
180 {
181 "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
182 "EventCode": "0x49",
183 "Counter": "0,1,2,3",
184 "UMask": "0x60",
185 "EventName": "DTLB_STORE_MISSES.STLB_HIT",
186 "SampleAfterValue": "100003",
187 "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
188 "CounterHTOff": "0,1,2,3,4,5,6,7"
189 },
190 {
191 "PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed.",
192 "EventCode": "0x49",
193 "Counter": "0,1,2,3",
194 "UMask": "0x80",
195 "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS",
196 "SampleAfterValue": "100003",
197 "BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed",
198 "CounterHTOff": "0,1,2,3,4,5,6,7"
199 },
200 {
201 "EventCode": "0x4f",
202 "Counter": "0,1,2,3",
203 "UMask": "0x10",
204 "EventName": "EPT.WALK_CYCLES",
205 "SampleAfterValue": "2000003",
206 "BriefDescription": "Cycle count for an Extended Page table walk.",
207 "CounterHTOff": "0,1,2,3,4,5,6,7"
208 },
209 {
210 "PublicDescription": "Misses in ITLB that causes a page walk of any page size.",
211 "EventCode": "0x85",
212 "Counter": "0,1,2,3",
213 "UMask": "0x1",
214 "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
215 "SampleAfterValue": "100003",
216 "BriefDescription": "Misses at all ITLB levels that cause page walks",
217 "CounterHTOff": "0,1,2,3,4,5,6,7"
218 },
219 {
220 "PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.",
221 "EventCode": "0x85",
222 "Counter": "0,1,2,3",
223 "UMask": "0x2",
224 "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
225 "SampleAfterValue": "100003",
226 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
227 "CounterHTOff": "0,1,2,3,4,5,6,7"
228 },
229 {
230 "PublicDescription": "Completed page walks due to misses in ITLB 2M/4M page entries.",
231 "EventCode": "0x85",
232 "Counter": "0,1,2,3",
233 "UMask": "0x4",
234 "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
235 "SampleAfterValue": "100003",
236 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
237 "CounterHTOff": "0,1,2,3,4,5,6,7"
238 },
239 {
240 "EventCode": "0x85",
241 "Counter": "0,1,2,3",
242 "UMask": "0x8",
243 "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
244 "SampleAfterValue": "100003",
245 "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
246 "CounterHTOff": "0,1,2,3,4,5,6,7"
247 },
248 {
249 "PublicDescription": "Completed page walks in ITLB of any page size.",
250 "EventCode": "0x85",
251 "Counter": "0,1,2,3",
252 "UMask": "0xe",
253 "EventName": "ITLB_MISSES.WALK_COMPLETED",
254 "SampleAfterValue": "100003",
255 "BriefDescription": "Misses in all ITLB levels that cause completed page walks",
256 "CounterHTOff": "0,1,2,3,4,5,6,7"
257 },
258 {
259 "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses.",
260 "EventCode": "0x85",
261 "Counter": "0,1,2,3",
262 "UMask": "0x10",
263 "EventName": "ITLB_MISSES.WALK_DURATION",
264 "SampleAfterValue": "100003",
265 "BriefDescription": "Cycles when PMH is busy with page walks",
266 "CounterHTOff": "0,1,2,3,4,5,6,7"
267 },
268 {
269 "PublicDescription": "ITLB misses that hit STLB (4K).",
270 "EventCode": "0x85",
271 "Counter": "0,1,2,3",
272 "UMask": "0x20",
273 "EventName": "ITLB_MISSES.STLB_HIT_4K",
274 "SampleAfterValue": "100003",
275 "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K)",
276 "CounterHTOff": "0,1,2,3,4,5,6,7"
277 },
278 {
279 "PublicDescription": "ITLB misses that hit STLB (2M).",
280 "EventCode": "0x85",
281 "Counter": "0,1,2,3",
282 "UMask": "0x40",
283 "EventName": "ITLB_MISSES.STLB_HIT_2M",
284 "SampleAfterValue": "100003",
285 "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M)",
286 "CounterHTOff": "0,1,2,3,4,5,6,7"
287 },
288 {
289 "PublicDescription": "ITLB misses that hit STLB. No page walk.",
290 "EventCode": "0x85",
291 "Counter": "0,1,2,3",
292 "UMask": "0x60",
293 "EventName": "ITLB_MISSES.STLB_HIT",
294 "SampleAfterValue": "100003",
295 "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",
296 "CounterHTOff": "0,1,2,3,4,5,6,7"
297 },
298 {
299 "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.",
300 "EventCode": "0xae",
301 "Counter": "0,1,2,3",
302 "UMask": "0x1",
303 "EventName": "ITLB.ITLB_FLUSH",
304 "SampleAfterValue": "100003",
305 "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
306 "CounterHTOff": "0,1,2,3,4,5,6,7"
307 },
308 {
309 "PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.",
310 "EventCode": "0xBC",
311 "Counter": "0,1,2,3",
312 "UMask": "0x11",
313 "EventName": "PAGE_WALKER_LOADS.DTLB_L1",
314 "SampleAfterValue": "2000003",
315 "BriefDescription": "Number of DTLB page walker hits in the L1+FB",
316 "CounterHTOff": "0,1,2,3"
317 },
318 {
319 "PublicDescription": "Number of DTLB page walker loads that hit in the L2.",
320 "EventCode": "0xBC",
321 "Counter": "0,1,2,3",
322 "UMask": "0x12",
323 "EventName": "PAGE_WALKER_LOADS.DTLB_L2",
324 "SampleAfterValue": "2000003",
325 "BriefDescription": "Number of DTLB page walker hits in the L2",
326 "CounterHTOff": "0,1,2,3"
327 },
328 {
329 "PublicDescription": "Number of DTLB page walker loads that hit in the L3.",
330 "EventCode": "0xBC",
331 "Counter": "0,1,2,3",
332 "UMask": "0x14",
333 "Errata": "HSD25",
334 "EventName": "PAGE_WALKER_LOADS.DTLB_L3",
335 "SampleAfterValue": "2000003",
336 "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP",
337 "CounterHTOff": "0,1,2,3"
338 },
339 {
340 "PublicDescription": "Number of DTLB page walker loads from memory.",
341 "EventCode": "0xBC",
342 "Counter": "0,1,2,3",
343 "UMask": "0x18",
344 "Errata": "HSD25",
345 "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
346 "SampleAfterValue": "2000003",
347 "BriefDescription": "Number of DTLB page walker hits in Memory",
348 "CounterHTOff": "0,1,2,3"
349 },
350 {
351 "PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.",
352 "EventCode": "0xBC",
353 "Counter": "0,1,2,3",
354 "UMask": "0x21",
355 "EventName": "PAGE_WALKER_LOADS.ITLB_L1",
356 "SampleAfterValue": "2000003",
357 "BriefDescription": "Number of ITLB page walker hits in the L1+FB",
358 "CounterHTOff": "0,1,2,3"
359 },
360 {
361 "PublicDescription": "Number of ITLB page walker loads that hit in the L2.",
362 "EventCode": "0xBC",
363 "Counter": "0,1,2,3",
364 "UMask": "0x22",
365 "EventName": "PAGE_WALKER_LOADS.ITLB_L2",
366 "SampleAfterValue": "2000003",
367 "BriefDescription": "Number of ITLB page walker hits in the L2",
368 "CounterHTOff": "0,1,2,3"
369 },
370 {
371 "PublicDescription": "Number of ITLB page walker loads that hit in the L3.",
372 "EventCode": "0xBC",
373 "Counter": "0,1,2,3",
374 "UMask": "0x24",
375 "Errata": "HSD25",
376 "EventName": "PAGE_WALKER_LOADS.ITLB_L3",
377 "SampleAfterValue": "2000003",
378 "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP",
379 "CounterHTOff": "0,1,2,3"
380 },
381 {
382 "PublicDescription": "Number of ITLB page walker loads from memory.",
383 "EventCode": "0xBC",
384 "Counter": "0,1,2,3",
385 "UMask": "0x28",
386 "Errata": "HSD25",
387 "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY",
388 "SampleAfterValue": "2000003",
389 "BriefDescription": "Number of ITLB page walker hits in Memory",
390 "CounterHTOff": "0,1,2,3"
391 },
392 {
393 "EventCode": "0xBC",
394 "Counter": "0,1,2,3",
395 "UMask": "0x41",
396 "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1",
397 "SampleAfterValue": "2000003",
398 "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.",
399 "CounterHTOff": "0,1,2,3"
400 },
401 {
402 "EventCode": "0xBC",
403 "Counter": "0,1,2,3",
404 "UMask": "0x42",
405 "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2",
406 "SampleAfterValue": "2000003",
407 "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.",
408 "CounterHTOff": "0,1,2,3"
409 },
410 {
411 "EventCode": "0xBC",
412 "Counter": "0,1,2,3",
413 "UMask": "0x44",
414 "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3",
415 "SampleAfterValue": "2000003",
416 "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.",
417 "CounterHTOff": "0,1,2,3"
418 },
419 {
420 "EventCode": "0xBC",
421 "Counter": "0,1,2,3",
422 "UMask": "0x48",
423 "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY",
424 "SampleAfterValue": "2000003",
425 "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.",
426 "CounterHTOff": "0,1,2,3"
427 },
428 {
429 "EventCode": "0xBC",
430 "Counter": "0,1,2,3",
431 "UMask": "0x81",
432 "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1",
433 "SampleAfterValue": "2000003",
434 "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.",
435 "CounterHTOff": "0,1,2,3"
436 },
437 {
438 "EventCode": "0xBC",
439 "Counter": "0,1,2,3",
440 "UMask": "0x82",
441 "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2",
442 "SampleAfterValue": "2000003",
443 "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
444 "CounterHTOff": "0,1,2,3"
445 },
446 {
447 "EventCode": "0xBC",
448 "Counter": "0,1,2,3",
449 "UMask": "0x84",
450 "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3",
451 "SampleAfterValue": "2000003",
452 "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
453 "CounterHTOff": "0,1,2,3"
454 },
455 {
456 "EventCode": "0xBC",
457 "Counter": "0,1,2,3",
458 "UMask": "0x88",
459 "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY",
460 "SampleAfterValue": "2000003",
461 "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.",
462 "CounterHTOff": "0,1,2,3"
463 },
464 {
465 "PublicDescription": "DTLB flush attempts of the thread-specific entries.",
466 "EventCode": "0xBD",
467 "Counter": "0,1,2,3",
468 "UMask": "0x1",
469 "EventName": "TLB_FLUSH.DTLB_THREAD",
470 "SampleAfterValue": "100003",
471 "BriefDescription": "DTLB flush attempts of the thread-specific entries",
472 "CounterHTOff": "0,1,2,3,4,5,6,7"
473 },
474 {
475 "PublicDescription": "Count number of STLB flush attempts.",
476 "EventCode": "0xBD",
477 "Counter": "0,1,2,3",
478 "UMask": "0x20",
479 "EventName": "TLB_FLUSH.STLB_ANY",
480 "SampleAfterValue": "100003",
481 "BriefDescription": "STLB flush attempts",
482 "CounterHTOff": "0,1,2,3,4,5,6,7"
483 }
484 ]