| blob | a9e62d4357af06352bff37bebf6460a8cfb8c2e3 |
1 [
2 {
3 "EventCode": "0x24",
4 "UMask": "0x21",
5 "BriefDescription": "Demand Data Read miss L2, no rejects",
6 "Counter": "0,1,2,3",
7 "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
8 "Errata": "HSD78",
9 "PublicDescription": "Demand data read requests that missed L2, no rejects.",
10 "SampleAfterValue": "200003",
11 "CounterHTOff": "0,1,2,3,4,5,6,7"
12 },
13 {
14 "EventCode": "0x24",
15 "UMask": "0x22",
16 "BriefDescription": "RFO requests that miss L2 cache",
17 "Counter": "0,1,2,3",
18 "EventName": "L2_RQSTS.RFO_MISS",
19 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
20 "SampleAfterValue": "200003",
21 "CounterHTOff": "0,1,2,3,4,5,6,7"
22 },
23 {
24 "EventCode": "0x24",
25 "UMask": "0x24",
26 "BriefDescription": "L2 cache misses when fetching instructions",
27 "Counter": "0,1,2,3",
28 "EventName": "L2_RQSTS.CODE_RD_MISS",
29 "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
30 "SampleAfterValue": "200003",
31 "CounterHTOff": "0,1,2,3,4,5,6,7"
32 },
33 {
34 "EventCode": "0x24",
35 "UMask": "0x27",
36 "BriefDescription": "Demand requests that miss L2 cache",
37 "Counter": "0,1,2,3",
38 "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
39 "Errata": "HSD78",
40 "PublicDescription": "Demand requests that miss L2 cache.",
41 "SampleAfterValue": "200003",
42 "CounterHTOff": "0,1,2,3,4,5,6,7"
43 },
44 {
45 "EventCode": "0x24",
46 "UMask": "0x30",
47 "BriefDescription": "L2 prefetch requests that miss L2 cache",
48 "Counter": "0,1,2,3",
49 "EventName": "L2_RQSTS.L2_PF_MISS",
50 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
51 "SampleAfterValue": "200003",
52 "CounterHTOff": "0,1,2,3,4,5,6,7"
53 },
54 {
55 "EventCode": "0x24",
56 "UMask": "0x3f",
57 "BriefDescription": "All requests that miss L2 cache",
58 "Counter": "0,1,2,3",
59 "EventName": "L2_RQSTS.MISS",
60 "Errata": "HSD78",
61 "PublicDescription": "All requests that missed L2.",
62 "SampleAfterValue": "200003",
63 "CounterHTOff": "0,1,2,3,4,5,6,7"
64 },
65 {
66 "EventCode": "0x24",
67 "UMask": "0xc1",
68 "BriefDescription": "Demand Data Read requests that hit L2 cache",
69 "Counter": "0,1,2,3",
70 "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
71 "Errata": "HSD78",
72 "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache",
73 "SampleAfterValue": "200003",
74 "CounterHTOff": "0,1,2,3,4,5,6,7"
75 },
76 {
77 "EventCode": "0x24",
78 "UMask": "0xc2",
79 "BriefDescription": "RFO requests that hit L2 cache",
80 "Counter": "0,1,2,3",
81 "EventName": "L2_RQSTS.RFO_HIT",
82 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.",
83 "SampleAfterValue": "200003",
84 "CounterHTOff": "0,1,2,3,4,5,6,7"
85 },
86 {
87 "EventCode": "0x24",
88 "UMask": "0xc4",
89 "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
90 "Counter": "0,1,2,3",
91 "EventName": "L2_RQSTS.CODE_RD_HIT",
92 "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
93 "SampleAfterValue": "200003",
94 "CounterHTOff": "0,1,2,3,4,5,6,7"
95 },
96 {
97 "EventCode": "0x24",
98 "UMask": "0xd0",
99 "BriefDescription": "L2 prefetch requests that hit L2 cache",
100 "Counter": "0,1,2,3",
101 "EventName": "L2_RQSTS.L2_PF_HIT",
102 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
103 "SampleAfterValue": "200003",
104 "CounterHTOff": "0,1,2,3,4,5,6,7"
105 },
106 {
107 "EventCode": "0x24",
108 "UMask": "0xe1",
109 "BriefDescription": "Demand Data Read requests",
110 "Counter": "0,1,2,3",
111 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
112 "Errata": "HSD78",
113 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
114 "SampleAfterValue": "200003",
115 "CounterHTOff": "0,1,2,3,4,5,6,7"
116 },
117 {
118 "EventCode": "0x24",
119 "UMask": "0xe2",
120 "BriefDescription": "RFO requests to L2 cache",
121 "Counter": "0,1,2,3",
122 "EventName": "L2_RQSTS.ALL_RFO",
123 "PublicDescription": "Counts all L2 store RFO requests.",
124 "SampleAfterValue": "200003",
125 "CounterHTOff": "0,1,2,3,4,5,6,7"
126 },
127 {
128 "EventCode": "0x24",
129 "UMask": "0xe4",
130 "BriefDescription": "L2 code requests",
131 "Counter": "0,1,2,3",
132 "EventName": "L2_RQSTS.ALL_CODE_RD",
133 "PublicDescription": "Counts all L2 code requests.",
134 "SampleAfterValue": "200003",
135 "CounterHTOff": "0,1,2,3,4,5,6,7"
136 },
137 {
138 "EventCode": "0x24",
139 "UMask": "0xe7",
140 "BriefDescription": "Demand requests to L2 cache",
141 "Counter": "0,1,2,3",
142 "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
143 "Errata": "HSD78",
144 "PublicDescription": "Demand requests to L2 cache.",
145 "SampleAfterValue": "200003",
146 "CounterHTOff": "0,1,2,3,4,5,6,7"
147 },
148 {
149 "EventCode": "0x24",
150 "UMask": "0xf8",
151 "BriefDescription": "Requests from L2 hardware prefetchers",
152 "Counter": "0,1,2,3",
153 "EventName": "L2_RQSTS.ALL_PF",
154 "PublicDescription": "Counts all L2 HW prefetcher requests.",
155 "SampleAfterValue": "200003",
156 "CounterHTOff": "0,1,2,3,4,5,6,7"
157 },
158 {
159 "EventCode": "0x24",
160 "UMask": "0xff",
161 "BriefDescription": "All L2 requests",
162 "Counter": "0,1,2,3",
163 "EventName": "L2_RQSTS.REFERENCES",
164 "Errata": "HSD78",
165 "PublicDescription": "All requests to L2 cache.",
166 "SampleAfterValue": "200003",
167 "CounterHTOff": "0,1,2,3,4,5,6,7"
168 },
169 {
170 "EventCode": "0x27",
171 "UMask": "0x50",
172 "BriefDescription": "Not rejected writebacks that hit L2 cache",
173 "Counter": "0,1,2,3",
174 "EventName": "L2_DEMAND_RQSTS.WB_HIT",
175 "PublicDescription": "Not rejected writebacks that hit L2 cache.",
176 "SampleAfterValue": "200003",
177 "CounterHTOff": "0,1,2,3,4,5,6,7"
178 },
179 {
180 "EventCode": "0x2E",
181 "UMask": "0x41",
182 "BriefDescription": "Core-originated cacheable demand requests missed L3",
183 "Counter": "0,1,2,3",
184 "EventName": "LONGEST_LAT_CACHE.MISS",
185 "PublicDescription": "This event counts each cache miss condition for references to the last level cache.",
186 "SampleAfterValue": "100003",
187 "CounterHTOff": "0,1,2,3,4,5,6,7"
188 },
189 {
190 "EventCode": "0x2E",
191 "UMask": "0x4f",
192 "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
193 "Counter": "0,1,2,3",
194 "EventName": "LONGEST_LAT_CACHE.REFERENCE",
195 "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",
196 "SampleAfterValue": "100003",
197 "CounterHTOff": "0,1,2,3,4,5,6,7"
198 },
199 {
200 "EventCode": "0x48",
201 "UMask": "0x1",
202 "BriefDescription": "L1D miss oustandings duration in cycles",
203 "Counter": "2",
204 "EventName": "L1D_PEND_MISS.PENDING",
205 "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
206 "SampleAfterValue": "2000003",
207 "CounterHTOff": "2"
208 },
209 {
210 "EventCode": "0x48",
211 "UMask": "0x1",
212 "BriefDescription": "Cycles with L1D load Misses outstanding.",
213 "Counter": "2",
214 "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
215 "CounterMask": "1",
216 "SampleAfterValue": "2000003",
217 "CounterHTOff": "2"
218 },
219 {
220 "EventCode": "0x48",
221 "UMask": "0x1",
222 "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
223 "Counter": "2",
224 "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
225 "AnyThread": "1",
226 "CounterMask": "1",
227 "SampleAfterValue": "2000003",
228 "CounterHTOff": "2"
229 },
230 {
231 "EventCode": "0x48",
232 "UMask": "0x2",
233 "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.",
234 "Counter": "0,1,2,3",
235 "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL",
236 "SampleAfterValue": "2000003",
237 "CounterHTOff": "0,1,2,3,4,5,6,7"
238 },
239 {
240 "EventCode": "0x48",
241 "UMask": "0x2",
242 "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
243 "Counter": "0,1,2,3",
244 "EventName": "L1D_PEND_MISS.FB_FULL",
245 "CounterMask": "1",
246 "SampleAfterValue": "2000003",
247 "CounterHTOff": "0,1,2,3,4,5,6,7"
248 },
249 {
250 "EventCode": "0x51",
251 "UMask": "0x1",
252 "BriefDescription": "L1D data line replacements",
253 "Counter": "0,1,2,3",
254 "EventName": "L1D.REPLACEMENT",
255 "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.",
256 "SampleAfterValue": "2000003",
257 "CounterHTOff": "0,1,2,3,4,5,6,7"
258 },
259 {
260 "EventCode": "0x60",
261 "UMask": "0x1",
262 "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
263 "Counter": "0,1,2,3",
264 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
265 "Errata": "HSD78, HSD62, HSD61",
266 "PublicDescription": "Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
267 "SampleAfterValue": "2000003",
268 "CounterHTOff": "0,1,2,3,4,5,6,7"
269 },
270 {
271 "EventCode": "0x60",
272 "UMask": "0x1",
273 "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
274 "Counter": "0,1,2,3",
275 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
276 "CounterMask": "1",
277 "Errata": "HSD78, HSD62, HSD61",
278 "SampleAfterValue": "2000003",
279 "CounterHTOff": "0,1,2,3,4,5,6,7"
280 },
281 {
282 "EventCode": "0x60",
283 "UMask": "0x1",
284 "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
285 "Counter": "0,1,2,3",
286 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
287 "CounterMask": "6",
288 "Errata": "HSD78, HSD62, HSD61",
289 "SampleAfterValue": "2000003",
290 "CounterHTOff": "0,1,2,3,4,5,6,7"
291 },
292 {
293 "EventCode": "0x60",
294 "UMask": "0x2",
295 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
296 "Counter": "0,1,2,3",
297 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
298 "Errata": "HSD62, HSD61",
299 "PublicDescription": "Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
300 "SampleAfterValue": "2000003",
301 "CounterHTOff": "0,1,2,3,4,5,6,7"
302 },
303 {
304 "EventCode": "0x60",
305 "UMask": "0x4",
306 "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
307 "Counter": "0,1,2,3",
308 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
309 "Errata": "HSD62, HSD61",
310 "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.",
311 "SampleAfterValue": "2000003",
312 "CounterHTOff": "0,1,2,3,4,5,6,7"
313 },
314 {
315 "EventCode": "0x60",
316 "UMask": "0x4",
317 "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
318 "Counter": "0,1,2,3",
319 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
320 "CounterMask": "1",
321 "Errata": "HSD62, HSD61",
322 "SampleAfterValue": "2000003",
323 "CounterHTOff": "0,1,2,3,4,5,6,7"
324 },
325 {
326 "EventCode": "0x60",
327 "UMask": "0x8",
328 "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
329 "Counter": "0,1,2,3",
330 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
331 "Errata": "HSD62, HSD61",
332 "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
333 "SampleAfterValue": "2000003",
334 "CounterHTOff": "0,1,2,3,4,5,6,7"
335 },
336 {
337 "EventCode": "0x60",
338 "UMask": "0x8",
339 "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
340 "Counter": "0,1,2,3",
341 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
342 "CounterMask": "1",
343 "Errata": "HSD62, HSD61",
344 "SampleAfterValue": "2000003",
345 "CounterHTOff": "0,1,2,3,4,5,6,7"
346 },
347 {
348 "EventCode": "0x63",
349 "UMask": "0x2",
350 "BriefDescription": "Cycles when L1D is locked",
351 "Counter": "0,1,2,3",
352 "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
353 "PublicDescription": "Cycles in which the L1D is locked.",
354 "SampleAfterValue": "2000003",
355 "CounterHTOff": "0,1,2,3,4,5,6,7"
356 },
357 {
358 "EventCode": "0xB0",
359 "UMask": "0x1",
360 "BriefDescription": "Demand Data Read requests sent to uncore",
361 "Counter": "0,1,2,3",
362 "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
363 "Errata": "HSD78",
364 "PublicDescription": "Demand data read requests sent to uncore.",
365 "SampleAfterValue": "100003",
366 "CounterHTOff": "0,1,2,3,4,5,6,7"
367 },
368 {
369 "EventCode": "0xB0",
370 "UMask": "0x2",
371 "BriefDescription": "Cacheable and noncachaeble code read requests",
372 "Counter": "0,1,2,3",
373 "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
374 "PublicDescription": "Demand code read requests sent to uncore.",
375 "SampleAfterValue": "100003",
376 "CounterHTOff": "0,1,2,3,4,5,6,7"
377 },
378 {
379 "EventCode": "0xB0",
380 "UMask": "0x4",
381 "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
382 "Counter": "0,1,2,3",
383 "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
384 "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",
385 "SampleAfterValue": "100003",
386 "CounterHTOff": "0,1,2,3,4,5,6,7"
387 },
388 {
389 "EventCode": "0xB0",
390 "UMask": "0x8",
391 "BriefDescription": "Demand and prefetch data reads",
392 "Counter": "0,1,2,3",
393 "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
394 "PublicDescription": "Data read requests sent to uncore (demand and prefetch).",
395 "SampleAfterValue": "100003",
396 "CounterHTOff": "0,1,2,3,4,5,6,7"
397 },
398 {
399 "EventCode": "0xb2",
400 "UMask": "0x1",
401 "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
402 "Counter": "0,1,2,3",
403 "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
404 "SampleAfterValue": "2000003",
405 "CounterHTOff": "0,1,2,3,4,5,6,7"
406 },
407 {
408 "EventCode": "0xB7, 0xBB",
409 "UMask": "0x1",
410 "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
411 "Counter": "0,1,2,3",
412 "EventName": "OFFCORE_RESPONSE",
413 "SampleAfterValue": "100003",
414 "CounterHTOff": "0,1,2,3"
415 },
416 {
417 "EventCode": "0xD0",
418 "UMask": "0x11",
419 "BriefDescription": "Retired load uops that miss the STLB.",
420 "Data_LA": "1",
421 "PEBS": "1",
422 "Counter": "0,1,2,3",
423 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
424 "Errata": "HSD29, HSM30",
425 "SampleAfterValue": "100003",
426 "CounterHTOff": "0,1,2,3"
427 },
428 {
429 "EventCode": "0xD0",
430 "UMask": "0x12",
431 "BriefDescription": "Retired store uops that miss the STLB.",
432 "Data_LA": "1",
433 "PEBS": "1",
434 "Counter": "0,1,2,3",
435 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
436 "Errata": "HSD29, HSM30",
437 "L1_Hit_Indication": "1",
438 "SampleAfterValue": "100003",
439 "CounterHTOff": "0,1,2,3"
440 },
441 {
442 "EventCode": "0xD0",
443 "UMask": "0x21",
444 "BriefDescription": "Retired load uops with locked access.",
445 "Data_LA": "1",
446 "PEBS": "1",
447 "Counter": "0,1,2,3",
448 "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
449 "Errata": "HSD76, HSD29, HSM30",
450 "SampleAfterValue": "100003",
451 "CounterHTOff": "0,1,2,3"
452 },
453 {
454 "EventCode": "0xD0",
455 "UMask": "0x41",
456 "BriefDescription": "Retired load uops that split across a cacheline boundary.",
457 "Data_LA": "1",
458 "PEBS": "1",
459 "Counter": "0,1,2,3",
460 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
461 "Errata": "HSD29, HSM30",
462 "SampleAfterValue": "100003",
463 "CounterHTOff": "0,1,2,3"
464 },
465 {
466 "EventCode": "0xD0",
467 "UMask": "0x42",
468 "BriefDescription": "Retired store uops that split across a cacheline boundary.",
469 "Data_LA": "1",
470 "PEBS": "1",
471 "Counter": "0,1,2,3",
472 "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
473 "Errata": "HSD29, HSM30",
474 "L1_Hit_Indication": "1",
475 "SampleAfterValue": "100003",
476 "CounterHTOff": "0,1,2,3"
477 },
478 {
479 "EventCode": "0xD0",
480 "UMask": "0x81",
481 "BriefDescription": "All retired load uops.",
482 "Data_LA": "1",
483 "PEBS": "1",
484 "Counter": "0,1,2,3",
485 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
486 "Errata": "HSD29, HSM30",
487 "SampleAfterValue": "2000003",
488 "CounterHTOff": "0,1,2,3"
489 },
490 {
491 "EventCode": "0xD0",
492 "UMask": "0x82",
493 "BriefDescription": "All retired store uops.",
494 "Data_LA": "1",
495 "PEBS": "1",
496 "Counter": "0,1,2,3",
497 "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
498 "Errata": "HSD29, HSM30",
499 "L1_Hit_Indication": "1",
500 "SampleAfterValue": "2000003",
501 "CounterHTOff": "0,1,2,3"
502 },
503 {
504 "EventCode": "0xD1",
505 "UMask": "0x1",
506 "BriefDescription": "Retired load uops with L1 cache hits as data sources.",
507 "Data_LA": "1",
508 "PEBS": "1",
509 "Counter": "0,1,2,3",
510 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
511 "Errata": "HSD29, HSM30",
512 "SampleAfterValue": "2000003",
513 "CounterHTOff": "0,1,2,3"
514 },
515 {
516 "EventCode": "0xD1",
517 "UMask": "0x2",
518 "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
519 "Data_LA": "1",
520 "PEBS": "1",
521 "Counter": "0,1,2,3",
522 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
523 "Errata": "HSD76, HSD29, HSM30",
524 "SampleAfterValue": "100003",
525 "CounterHTOff": "0,1,2,3"
526 },
527 {
528 "EventCode": "0xD1",
529 "UMask": "0x4",
530 "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.",
531 "Data_LA": "1",
532 "PEBS": "1",
533 "Counter": "0,1,2,3",
534 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
535 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
536 "PublicDescription": "Retired load uops with L3 cache hits as data sources.",
537 "SampleAfterValue": "50021",
538 "CounterHTOff": "0,1,2,3"
539 },
540 {
541 "EventCode": "0xD1",
542 "UMask": "0x8",
543 "BriefDescription": "Retired load uops misses in L1 cache as data sources.",
544 "Data_LA": "1",
545 "PEBS": "1",
546 "Counter": "0,1,2,3",
547 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
548 "Errata": "HSM30",
549 "PublicDescription": "Retired load uops missed L1 cache as data sources.",
550 "SampleAfterValue": "100003",
551 "CounterHTOff": "0,1,2,3"
552 },
553 {
554 "EventCode": "0xD1",
555 "UMask": "0x10",
556 "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
557 "Data_LA": "1",
558 "PEBS": "1",
559 "Counter": "0,1,2,3",
560 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
561 "Errata": "HSD29, HSM30",
562 "PublicDescription": "Retired load uops missed L2. Unknown data source excluded.",
563 "SampleAfterValue": "50021",
564 "CounterHTOff": "0,1,2,3"
565 },
566 {
567 "EventCode": "0xD1",
568 "UMask": "0x20",
569 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
570 "Data_LA": "1",
571 "PEBS": "1",
572 "Counter": "0,1,2,3",
573 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS",
574 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
575 "PublicDescription": "Retired load uops missed L3. Excludes unknown data source .",
576 "SampleAfterValue": "100003",
577 "CounterHTOff": "0,1,2,3"
578 },
579 {
580 "EventCode": "0xD1",
581 "UMask": "0x40",
582 "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
583 "Data_LA": "1",
584 "PEBS": "1",
585 "Counter": "0,1,2,3",
586 "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
587 "Errata": "HSM30",
588 "SampleAfterValue": "100003",
589 "CounterHTOff": "0,1,2,3"
590 },
591 {
592 "EventCode": "0xD2",
593 "UMask": "0x1",
594 "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
595 "Data_LA": "1",
596 "PEBS": "1",
597 "Counter": "0,1,2,3",
598 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS",
599 "Errata": "HSD29, HSD25, HSM26, HSM30",
600 "SampleAfterValue": "20011",
601 "CounterHTOff": "0,1,2,3"
602 },
603 {
604 "EventCode": "0xD2",
605 "UMask": "0x2",
606 "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",
607 "Data_LA": "1",
608 "PEBS": "1",
609 "Counter": "0,1,2,3",
610 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT",
611 "Errata": "HSD29, HSD25, HSM26, HSM30",
612 "SampleAfterValue": "20011",
613 "CounterHTOff": "0,1,2,3"
614 },
615 {
616 "EventCode": "0xD2",
617 "UMask": "0x4",
618 "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",
619 "Data_LA": "1",
620 "PEBS": "1",
621 "Counter": "0,1,2,3",
622 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM",
623 "Errata": "HSD29, HSD25, HSM26, HSM30",
624 "SampleAfterValue": "20011",
625 "CounterHTOff": "0,1,2,3"
626 },
627 {
628 "EventCode": "0xD2",
629 "UMask": "0x8",
630 "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.",
631 "Data_LA": "1",
632 "PEBS": "1",
633 "Counter": "0,1,2,3",
634 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE",
635 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
636 "SampleAfterValue": "100003",
637 "CounterHTOff": "0,1,2,3"
638 },
639 {
640 "EventCode": "0xD3",
641 "UMask": "0x1",
642 "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",
643 "Data_LA": "1",
644 "PEBS": "1",
645 "Counter": "0,1,2,3",
646 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM",
647 "Errata": "HSD74, HSD29, HSD25, HSM30",
648 "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches.",
649 "SampleAfterValue": "100003",
650 "CounterHTOff": "0,1,2,3"
651 },
652 {
653 "EventCode": "0xD3",
654 "UMask": "0x4",
655 "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)",
656 "Data_LA": "1",
657 "PEBS": "1",
658 "Counter": "0,1,2,3",
659 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM",
660 "Errata": "HSD29, HSM30",
661 "SampleAfterValue": "100003",
662 "CounterHTOff": "0,1,2,3"
663 },
664 {
665 "EventCode": "0xD3",
666 "UMask": "0x10",
667 "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM",
668 "Data_LA": "1",
669 "PEBS": "1",
670 "Counter": "0,1,2,3",
671 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM",
672 "Errata": "HSM30",
673 "SampleAfterValue": "100003",
674 "CounterHTOff": "0,1,2,3"
675 },
676 {
677 "EventCode": "0xD3",
678 "UMask": "0x20",
679 "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache",
680 "Data_LA": "1",
681 "PEBS": "1",
682 "Counter": "0,1,2,3",
683 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD",
684 "Errata": "HSM30",
685 "SampleAfterValue": "100003",
686 "CounterHTOff": "0,1,2,3"
687 },
688 {
689 "EventCode": "0xf0",
690 "UMask": "0x1",
691 "BriefDescription": "Demand Data Read requests that access L2 cache",
692 "Counter": "0,1,2,3",
693 "EventName": "L2_TRANS.DEMAND_DATA_RD",
694 "PublicDescription": "Demand data read requests that access L2 cache.",
695 "SampleAfterValue": "200003",
696 "CounterHTOff": "0,1,2,3,4,5,6,7"
697 },
698 {
699 "EventCode": "0xf0",
700 "UMask": "0x2",
701 "BriefDescription": "RFO requests that access L2 cache",
702 "Counter": "0,1,2,3",
703 "EventName": "L2_TRANS.RFO",
704 "PublicDescription": "RFO requests that access L2 cache.",
705 "SampleAfterValue": "200003",
706 "CounterHTOff": "0,1,2,3,4,5,6,7"
707 },
708 {
709 "EventCode": "0xf0",
710 "UMask": "0x4",
711 "BriefDescription": "L2 cache accesses when fetching instructions",
712 "Counter": "0,1,2,3",
713 "EventName": "L2_TRANS.CODE_RD",
714 "PublicDescription": "L2 cache accesses when fetching instructions.",
715 "SampleAfterValue": "200003",
716 "CounterHTOff": "0,1,2,3,4,5,6,7"
717 },
718 {
719 "EventCode": "0xf0",
720 "UMask": "0x8",
721 "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
722 "Counter": "0,1,2,3",
723 "EventName": "L2_TRANS.ALL_PF",
724 "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.",
725 "SampleAfterValue": "200003",
726 "CounterHTOff": "0,1,2,3,4,5,6,7"
727 },
728 {
729 "EventCode": "0xf0",
730 "UMask": "0x10",
731 "BriefDescription": "L1D writebacks that access L2 cache",
732 "Counter": "0,1,2,3",
733 "EventName": "L2_TRANS.L1D_WB",
734 "PublicDescription": "L1D writebacks that access L2 cache.",
735 "SampleAfterValue": "200003",
736 "CounterHTOff": "0,1,2,3,4,5,6,7"
737 },
738 {
739 "EventCode": "0xf0",
740 "UMask": "0x20",
741 "BriefDescription": "L2 fill requests that access L2 cache",
742 "Counter": "0,1,2,3",
743 "EventName": "L2_TRANS.L2_FILL",
744 "PublicDescription": "L2 fill requests that access L2 cache.",
745 "SampleAfterValue": "200003",
746 "CounterHTOff": "0,1,2,3,4,5,6,7"
747 },
748 {
749 "EventCode": "0xf0",
750 "UMask": "0x40",
751 "BriefDescription": "L2 writebacks that access L2 cache",
752 "Counter": "0,1,2,3",
753 "EventName": "L2_TRANS.L2_WB",
754 "PublicDescription": "L2 writebacks that access L2 cache.",
755 "SampleAfterValue": "200003",
756 "CounterHTOff": "0,1,2,3,4,5,6,7"
757 },
758 {
759 "EventCode": "0xf0",
760 "UMask": "0x80",
761 "BriefDescription": "Transactions accessing L2 pipe",
762 "Counter": "0,1,2,3",
763 "EventName": "L2_TRANS.ALL_REQUESTS",
764 "PublicDescription": "Transactions accessing L2 pipe.",
765 "SampleAfterValue": "200003",
766 "CounterHTOff": "0,1,2,3,4,5,6,7"
767 },
768 {
769 "EventCode": "0xF1",
770 "UMask": "0x1",
771 "BriefDescription": "L2 cache lines in I state filling L2",
772 "Counter": "0,1,2,3",
773 "EventName": "L2_LINES_IN.I",
774 "PublicDescription": "L2 cache lines in I state filling L2.",
775 "SampleAfterValue": "100003",
776 "CounterHTOff": "0,1,2,3,4,5,6,7"
777 },
778 {
779 "EventCode": "0xF1",
780 "UMask": "0x2",
781 "BriefDescription": "L2 cache lines in S state filling L2",
782 "Counter": "0,1,2,3",
783 "EventName": "L2_LINES_IN.S",
784 "PublicDescription": "L2 cache lines in S state filling L2.",
785 "SampleAfterValue": "100003",
786 "CounterHTOff": "0,1,2,3,4,5,6,7"
787 },
788 {
789 "EventCode": "0xF1",
790 "UMask": "0x4",
791 "BriefDescription": "L2 cache lines in E state filling L2",
792 "Counter": "0,1,2,3",
793 "EventName": "L2_LINES_IN.E",
794 "PublicDescription": "L2 cache lines in E state filling L2.",
795 "SampleAfterValue": "100003",
796 "CounterHTOff": "0,1,2,3,4,5,6,7"
797 },
798 {
799 "EventCode": "0xF1",
800 "UMask": "0x7",
801 "BriefDescription": "L2 cache lines filling L2",
802 "Counter": "0,1,2,3",
803 "EventName": "L2_LINES_IN.ALL",
804 "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.",
805 "SampleAfterValue": "100003",
806 "CounterHTOff": "0,1,2,3,4,5,6,7"
807 },
808 {
809 "EventCode": "0xF2",
810 "UMask": "0x5",
811 "BriefDescription": "Clean L2 cache lines evicted by demand",
812 "Counter": "0,1,2,3",
813 "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
814 "PublicDescription": "Clean L2 cache lines evicted by demand.",
815 "SampleAfterValue": "100003",
816 "CounterHTOff": "0,1,2,3,4,5,6,7"
817 },
818 {
819 "EventCode": "0xF2",
820 "UMask": "0x6",
821 "BriefDescription": "Dirty L2 cache lines evicted by demand",
822 "Counter": "0,1,2,3",
823 "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
824 "PublicDescription": "Dirty L2 cache lines evicted by demand.",
825 "SampleAfterValue": "100003",
826 "CounterHTOff": "0,1,2,3,4,5,6,7"
827 },
828 {
829 "EventCode": "0xf4",
830 "UMask": "0x10",
831 "BriefDescription": "Split locks in SQ",
832 "Counter": "0,1,2,3",
833 "EventName": "SQ_MISC.SPLIT_LOCK",
834 "SampleAfterValue": "100003",
835 "CounterHTOff": "0,1,2,3,4,5,6,7"
836 },
837 {
838 "Offcore": "1",
839 "EventCode": "0xB7, 0xBB",
840 "UMask": "0x1",
841 "BriefDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
842 "MSRValue": "0x04003C0001",
843 "Counter": "0,1,2,3",
844 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
845 "MSRIndex": "0x1a6,0x1a7",
846 "PublicDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
847 "SampleAfterValue": "100003",
848 "CounterHTOff": "0,1,2,3"
849 },
850 {
851 "Offcore": "1",
852 "EventCode": "0xB7, 0xBB",
853 "UMask": "0x1",
854 "BriefDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
855 "MSRValue": "0x10003C0001",
856 "Counter": "0,1,2,3",
857 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
858 "MSRIndex": "0x1a6,0x1a7",
859 "PublicDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
860 "SampleAfterValue": "100003",
861 "CounterHTOff": "0,1,2,3"
862 },
863 {
864 "Offcore": "1",
865 "EventCode": "0xB7, 0xBB",
866 "UMask": "0x1",
867 "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
868 "MSRValue": "0x04003C0002",
869 "Counter": "0,1,2,3",
870 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
871 "MSRIndex": "0x1a6,0x1a7",
872 "PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
873 "SampleAfterValue": "100003",
874 "CounterHTOff": "0,1,2,3"
875 },
876 {
877 "Offcore": "1",
878 "EventCode": "0xB7, 0xBB",
879 "UMask": "0x1",
880 "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
881 "MSRValue": "0x10003C0002",
882 "Counter": "0,1,2,3",
883 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
884 "MSRIndex": "0x1a6,0x1a7",
885 "PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
886 "SampleAfterValue": "100003",
887 "CounterHTOff": "0,1,2,3"
888 },
889 {
890 "Offcore": "1",
891 "EventCode": "0xB7, 0xBB",
892 "UMask": "0x1",
893 "BriefDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
894 "MSRValue": "0x04003C0004",
895 "Counter": "0,1,2,3",
896 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
897 "MSRIndex": "0x1a6,0x1a7",
898 "PublicDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
899 "SampleAfterValue": "100003",
900 "CounterHTOff": "0,1,2,3"
901 },
902 {
903 "Offcore": "1",
904 "EventCode": "0xB7, 0xBB",
905 "UMask": "0x1",
906 "BriefDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
907 "MSRValue": "0x10003C0004",
908 "Counter": "0,1,2,3",
909 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE",
910 "MSRIndex": "0x1a6,0x1a7",
911 "PublicDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
912 "SampleAfterValue": "100003",
913 "CounterHTOff": "0,1,2,3"
914 },
915 {
916 "Offcore": "1",
917 "EventCode": "0xB7, 0xBB",
918 "UMask": "0x1",
919 "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3",
920 "MSRValue": "0x3F803C0010",
921 "Counter": "0,1,2,3",
922 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",
923 "MSRIndex": "0x1a6,0x1a7",
924 "PublicDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3",
925 "SampleAfterValue": "100003",
926 "CounterHTOff": "0,1,2,3"
927 },
928 {
929 "Offcore": "1",
930 "EventCode": "0xB7, 0xBB",
931 "UMask": "0x1",
932 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3",
933 "MSRValue": "0x3F803C0020",
934 "Counter": "0,1,2,3",
935 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE",
936 "MSRIndex": "0x1a6,0x1a7",
937 "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3",
938 "SampleAfterValue": "100003",
939 "CounterHTOff": "0,1,2,3"
940 },
941 {
942 "Offcore": "1",
943 "EventCode": "0xB7, 0xBB",
944 "UMask": "0x1",
945 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3",
946 "MSRValue": "0x3F803C0040",
947 "Counter": "0,1,2,3",
948 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",
949 "MSRIndex": "0x1a6,0x1a7",
950 "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3",
951 "SampleAfterValue": "100003",
952 "CounterHTOff": "0,1,2,3"
953 },
954 {
955 "Offcore": "1",
956 "EventCode": "0xB7, 0xBB",
957 "UMask": "0x1",
958 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3",
959 "MSRValue": "0x3F803C0080",
960 "Counter": "0,1,2,3",
961 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",
962 "MSRIndex": "0x1a6,0x1a7",
963 "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3",
964 "SampleAfterValue": "100003",
965 "CounterHTOff": "0,1,2,3"
966 },
967 {
968 "Offcore": "1",
969 "EventCode": "0xB7, 0xBB",
970 "UMask": "0x1",
971 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3",
972 "MSRValue": "0x3F803C0100",
973 "Counter": "0,1,2,3",
974 "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE",
975 "MSRIndex": "0x1a6,0x1a7",
976 "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3",
977 "SampleAfterValue": "100003",
978 "CounterHTOff": "0,1,2,3"
979 },
980 {
981 "Offcore": "1",
982 "EventCode": "0xB7, 0xBB",
983 "UMask": "0x1",
984 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3",
985 "MSRValue": "0x3F803C0200",
986 "Counter": "0,1,2,3",
987 "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
988 "MSRIndex": "0x1a6,0x1a7",
989 "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3",
990 "SampleAfterValue": "100003",
991 "CounterHTOff": "0,1,2,3"
992 },
993 {
994 "Offcore": "1",
995 "EventCode": "0xB7, 0xBB",
996 "UMask": "0x1",
997 "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
998 "MSRValue": "0x04003C0091",
999 "Counter": "0,1,2,3",
1000 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1001 "MSRIndex": "0x1a6,0x1a7",
1002 "PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1003 "SampleAfterValue": "100003",
1004 "CounterHTOff": "0,1,2,3"
1005 },
1006 {
1007 "Offcore": "1",
1008 "EventCode": "0xB7, 0xBB",
1009 "UMask": "0x1",
1010 "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1011 "MSRValue": "0x10003C0091",
1012 "Counter": "0,1,2,3",
1013 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
1014 "MSRIndex": "0x1a6,0x1a7",
1015 "PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1016 "SampleAfterValue": "100003",
1017 "CounterHTOff": "0,1,2,3"
1018 },
1019 {
1020 "Offcore": "1",
1021 "EventCode": "0xB7, 0xBB",
1022 "UMask": "0x1",
1023 "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1024 "MSRValue": "0x04003C0122",
1025 "Counter": "0,1,2,3",
1026 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1027 "MSRIndex": "0x1a6,0x1a7",
1028 "PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1029 "SampleAfterValue": "100003",
1030 "CounterHTOff": "0,1,2,3"
1031 },
1032 {
1033 "Offcore": "1",
1034 "EventCode": "0xB7, 0xBB",
1035 "UMask": "0x1",
1036 "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1037 "MSRValue": "0x10003C0122",
1038 "Counter": "0,1,2,3",
1039 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE",
1040 "MSRIndex": "0x1a6,0x1a7",
1041 "PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1042 "SampleAfterValue": "100003",
1043 "CounterHTOff": "0,1,2,3"
1044 },
1045 {
1046 "Offcore": "1",
1047 "EventCode": "0xB7, 0xBB",
1048 "UMask": "0x1",
1049 "BriefDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1050 "MSRValue": "0x04003C0244",
1051 "Counter": "0,1,2,3",
1052 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1053 "MSRIndex": "0x1a6,0x1a7",
1054 "PublicDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1055 "SampleAfterValue": "100003",
1056 "CounterHTOff": "0,1,2,3"
1057 },
1058 {
1059 "Offcore": "1",
1060 "EventCode": "0xB7, 0xBB",
1061 "UMask": "0x1",
1062 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1063 "MSRValue": "0x04003C07F7",
1064 "Counter": "0,1,2,3",
1065 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1066 "MSRIndex": "0x1a6,0x1a7",
1067 "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1068 "SampleAfterValue": "100003",
1069 "CounterHTOff": "0,1,2,3"
1070 },
1071 {
1072 "Offcore": "1",
1073 "EventCode": "0xB7, 0xBB",
1074 "UMask": "0x1",
1075 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1076 "MSRValue": "0x10003C07F7",
1077 "Counter": "0,1,2,3",
1078 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
1079 "MSRIndex": "0x1a6,0x1a7",
1080 "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1081 "SampleAfterValue": "100003",
1082 "CounterHTOff": "0,1,2,3"
1083 },
1084 {
1085 "Offcore": "1",
1086 "EventCode": "0xB7, 0xBB",
1087 "UMask": "0x1",
1088 "BriefDescription": "Counts all requests hit in the L3",
1089 "MSRValue": "0x3F803C8FFF",
1090 "Counter": "0,1,2,3",
1091 "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE",
1092 "MSRIndex": "0x1a6,0x1a7",
1093 "PublicDescription": "Counts all requests hit in the L3",
1094 "SampleAfterValue": "100003",
1095 "CounterHTOff": "0,1,2,3"
1096 }
1097 ]