4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_BUILTIN_BSWAP
10 select ARCH_USE_CMPXCHG_LOCKREF
11 select ARCH_WANT_IPC_PARSE_VERSION
12 select BUILDTIME_EXTABLE_SORT if MMU
13 select CLONE_BACKWARDS
14 select CPU_PM if (SUSPEND || CPU_IDLE)
15 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
16 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
17 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_IRQ_PROBE
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_SCHED_CLOCK
23 select GENERIC_SMP_IDLE_THREAD
24 select GENERIC_STRNCPY_FROM_USER
25 select GENERIC_STRNLEN_USER
26 select HARDIRQS_SW_RESEND
27 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
28 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
30 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
31 select HAVE_ARCH_TRACEHOOK
33 select HAVE_CC_STACKPROTECTOR
34 select HAVE_CONTEXT_TRACKING
35 select HAVE_C_RECORDMCOUNT
36 select HAVE_DEBUG_KMEMLEAK
37 select HAVE_DMA_API_DEBUG
39 select HAVE_DMA_CONTIGUOUS if MMU
40 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
41 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
42 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
43 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
44 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
45 select HAVE_GENERIC_DMA_COHERENT
46 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
47 select HAVE_IDE if PCI || ISA || PCMCIA
48 select HAVE_IRQ_TIME_ACCOUNTING
49 select HAVE_KERNEL_GZIP
50 select HAVE_KERNEL_LZ4
51 select HAVE_KERNEL_LZMA
52 select HAVE_KERNEL_LZO
54 select HAVE_KPROBES if !XIP_KERNEL
55 select HAVE_KRETPROBES if (HAVE_KPROBES)
57 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
59 select HAVE_PERF_EVENTS
61 select HAVE_PERF_USER_STACK_DUMP
62 select HAVE_REGS_AND_STACK_ACCESS_API
63 select HAVE_SYSCALL_TRACEPOINTS
65 select HAVE_VIRT_CPU_ACCOUNTING_GEN
66 select IRQ_FORCED_THREADING
68 select MODULES_USE_ELF_REL
71 select OLD_SIGSUSPEND3
72 select PERF_USE_VMALLOC
74 select SYS_SUPPORTS_APM_EMULATION
75 # Above selects are sorted alphabetically; please add new ones
76 # according to that. Thanks.
78 The ARM series is a line of low-power-consumption RISC chip designs
79 licensed by ARM Ltd and targeted at embedded applications and
80 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
81 manufactured, but legacy ARM-based PC hardware remains popular in
82 Europe. There is an ARM Linux project with a web page at
83 <http://www.arm.linux.org.uk/>.
85 config ARM_HAS_SG_CHAIN
88 config NEED_SG_DMA_LENGTH
91 config ARM_DMA_USE_IOMMU
93 select ARM_HAS_SG_CHAIN
94 select NEED_SG_DMA_LENGTH
98 config ARM_DMA_IOMMU_ALIGNMENT
99 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
103 DMA mapping framework by default aligns all buffers to the smallest
104 PAGE_SIZE order which is greater than or equal to the requested buffer
105 size. This works well for buffers up to a few hundreds kilobytes, but
106 for larger buffers it just a waste of address space. Drivers which has
107 relatively small addressing window (like 64Mib) might run out of
108 virtual space with just a few allocations.
110 With this parameter you can specify the maximum PAGE_SIZE order for
111 DMA IOMMU buffers. Larger buffers will be aligned only to this
112 specified order. The order is expressed as a power of two multiplied
117 config MIGHT_HAVE_PCI
120 config SYS_SUPPORTS_APM_EMULATION
125 select GENERIC_ALLOCATOR
136 The Extended Industry Standard Architecture (EISA) bus was
137 developed as an open alternative to the IBM MicroChannel bus.
139 The EISA bus provided some of the features of the IBM MicroChannel
140 bus while maintaining backward compatibility with cards made for
141 the older ISA bus. The EISA bus saw limited use between 1988 and
142 1995 when it was made obsolete by the PCI bus.
144 Say Y here if you are building a kernel for an EISA-based machine.
151 config STACKTRACE_SUPPORT
155 config HAVE_LATENCYTOP_SUPPORT
160 config LOCKDEP_SUPPORT
164 config TRACE_IRQFLAGS_SUPPORT
168 config RWSEM_XCHGADD_ALGORITHM
172 config ARCH_HAS_ILOG2_U32
175 config ARCH_HAS_ILOG2_U64
178 config ARCH_HAS_CPUFREQ
181 Internal node to signify that the ARCH has CPUFREQ support
182 and that the relevant menu configurations are displayed for
185 config ARCH_HAS_BANDGAP
188 config GENERIC_HWEIGHT
192 config GENERIC_CALIBRATE_DELAY
196 config ARCH_MAY_HAVE_PC_FDC
202 config NEED_DMA_MAP_STATE
205 config ARCH_SUPPORTS_UPROBES
208 config ARCH_HAS_DMA_SET_COHERENT_MASK
211 config GENERIC_ISA_DMA
217 config NEED_RET_TO_USER
225 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
226 default DRAM_BASE if REMAP_VECTORS_TO_RAM
229 The base address of exception vectors. This must be two pages
232 config ARM_PATCH_PHYS_VIRT
233 bool "Patch physical to virtual translations at runtime" if EMBEDDED
235 depends on !XIP_KERNEL && MMU
236 depends on !ARCH_REALVIEW || !SPARSEMEM
238 Patch phys-to-virt and virt-to-phys translation functions at
239 boot and module load time according to the position of the
240 kernel in system memory.
242 This can only be used with non-XIP MMU kernels where the base
243 of physical memory is at a 16MB boundary.
245 Only disable this option if you know that you do not require
246 this feature (eg, building a kernel for a single machine) and
247 you need to shrink the kernel to the minimal size.
249 config NEED_MACH_GPIO_H
252 Select this when mach/gpio.h is required to provide special
253 definitions for this platform. The need for mach/gpio.h should
254 be avoided when possible.
256 config NEED_MACH_IO_H
259 Select this when mach/io.h is required to provide special
260 definitions for this platform. The need for mach/io.h should
261 be avoided when possible.
263 config NEED_MACH_MEMORY_H
266 Select this when mach/memory.h is required to provide special
267 definitions for this platform. The need for mach/memory.h should
268 be avoided when possible.
271 hex "Physical address of main memory" if MMU
272 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
273 default DRAM_BASE if !MMU
275 Please provide the physical address corresponding to the
276 location of main memory in your system.
282 source "init/Kconfig"
284 source "kernel/Kconfig.freezer"
289 bool "MMU-based Paged Memory Management Support"
292 Select if you want MMU-based virtualised addressing space
293 support by paged memory management. If unsure, say 'Y'.
296 # The "ARM system type" choice list is ordered alphabetically by option
297 # text. Please add new entries in the option alphabetic order.
300 prompt "ARM system type"
301 default ARCH_VERSATILE if !MMU
302 default ARCH_MULTIPLATFORM if MMU
304 config ARCH_MULTIPLATFORM
305 bool "Allow multiple platforms to be selected"
307 select ARCH_WANT_OPTIONAL_GPIOLIB
308 select ARM_HAS_SG_CHAIN
309 select ARM_PATCH_PHYS_VIRT
313 select GENERIC_CLOCKEVENTS
314 select MIGHT_HAVE_PCI
315 select MULTI_IRQ_HANDLER
319 config ARCH_INTEGRATOR
320 bool "ARM Ltd. Integrator family"
321 select ARCH_HAS_CPUFREQ
323 select ARM_PATCH_PHYS_VIRT
326 select COMMON_CLK_VERSATILE
327 select GENERIC_CLOCKEVENTS
330 select MULTI_IRQ_HANDLER
331 select NEED_MACH_MEMORY_H
332 select PLAT_VERSATILE
335 select VERSATILE_FPGA_IRQ
337 Support for ARM's Integrator platform.
340 bool "ARM Ltd. RealView family"
341 select ARCH_WANT_OPTIONAL_GPIOLIB
343 select ARM_TIMER_SP804
345 select COMMON_CLK_VERSATILE
346 select GENERIC_CLOCKEVENTS
347 select GPIO_PL061 if GPIOLIB
349 select NEED_MACH_MEMORY_H
350 select PLAT_VERSATILE
351 select PLAT_VERSATILE_CLCD
353 This enables support for ARM Ltd RealView boards.
355 config ARCH_VERSATILE
356 bool "ARM Ltd. Versatile family"
357 select ARCH_WANT_OPTIONAL_GPIOLIB
359 select ARM_TIMER_SP804
362 select GENERIC_CLOCKEVENTS
363 select HAVE_MACH_CLKDEV
365 select PLAT_VERSATILE
366 select PLAT_VERSATILE_CLCD
367 select PLAT_VERSATILE_CLOCK
368 select VERSATILE_FPGA_IRQ
370 This enables support for ARM Ltd Versatile board.
374 select ARCH_REQUIRE_GPIOLIB
377 select NEED_MACH_IO_H if PCCARD
379 select PINCTRL_AT91 if USE_OF
381 This enables support for systems based on Atmel
382 AT91RM9200 and AT91SAM9* processors.
385 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
386 select ARCH_REQUIRE_GPIOLIB
391 select GENERIC_CLOCKEVENTS
394 Support for Cirrus Logic 711x/721x/731x based boards.
397 bool "Cortina Systems Gemini"
398 select ARCH_REQUIRE_GPIOLIB
401 select GENERIC_CLOCKEVENTS
403 Support for the Cortina Systems Gemini family SoCs
407 select ARCH_USES_GETTIMEOFFSET
410 select NEED_MACH_IO_H
411 select NEED_MACH_MEMORY_H
414 This is an evaluation board for the StrongARM processor available
415 from Digital. It has limited hardware on-board, including an
416 Ethernet interface, two PCMCIA sockets, two serial ports and a
420 bool "Energy Micro efm32"
422 select ARCH_REQUIRE_GPIOLIB
428 select GENERIC_CLOCKEVENTS
434 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
439 select ARCH_HAS_HOLES_MEMORYMODEL
440 select ARCH_REQUIRE_GPIOLIB
441 select ARCH_USES_GETTIMEOFFSET
446 select NEED_MACH_MEMORY_H
448 This enables support for the Cirrus EP93xx series of CPUs.
450 config ARCH_FOOTBRIDGE
454 select GENERIC_CLOCKEVENTS
456 select NEED_MACH_IO_H if !MMU
457 select NEED_MACH_MEMORY_H
459 Support for systems based on the DC21285 companion chip
460 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
463 bool "Hilscher NetX based"
467 select GENERIC_CLOCKEVENTS
469 This enables support for systems based on the Hilscher NetX Soc
475 select NEED_MACH_MEMORY_H
476 select NEED_RET_TO_USER
482 Support for Intel's IOP13XX (XScale) family of processors.
487 select ARCH_REQUIRE_GPIOLIB
490 select NEED_RET_TO_USER
494 Support for Intel's 80219 and IOP32X (XScale) family of
500 select ARCH_REQUIRE_GPIOLIB
503 select NEED_RET_TO_USER
507 Support for Intel's IOP33X (XScale) family of processors.
512 select ARCH_HAS_DMA_SET_COHERENT_MASK
513 select ARCH_REQUIRE_GPIOLIB
514 select ARCH_SUPPORTS_BIG_ENDIAN
517 select DMABOUNCE if PCI
518 select GENERIC_CLOCKEVENTS
519 select MIGHT_HAVE_PCI
520 select NEED_MACH_IO_H
521 select USB_EHCI_BIG_ENDIAN_DESC
522 select USB_EHCI_BIG_ENDIAN_MMIO
524 Support for Intel's IXP4XX (XScale) family of processors.
528 select ARCH_REQUIRE_GPIOLIB
530 select GENERIC_CLOCKEVENTS
531 select MIGHT_HAVE_PCI
535 select PLAT_ORION_LEGACY
537 Support for the Marvell Dove SoC 88AP510
540 bool "Marvell Kirkwood"
541 select ARCH_HAS_CPUFREQ
542 select ARCH_REQUIRE_GPIOLIB
544 select GENERIC_CLOCKEVENTS
549 select PINCTRL_KIRKWOOD
550 select PLAT_ORION_LEGACY
552 Support for the following Marvell Kirkwood series SoCs:
553 88F6180, 88F6192 and 88F6281.
556 bool "Marvell MV78xx0"
557 select ARCH_REQUIRE_GPIOLIB
559 select GENERIC_CLOCKEVENTS
562 select PLAT_ORION_LEGACY
564 Support for the following Marvell MV78xx0 series SoCs:
570 select ARCH_REQUIRE_GPIOLIB
572 select GENERIC_CLOCKEVENTS
575 select PLAT_ORION_LEGACY
577 Support for the following Marvell Orion 5x series SoCs:
578 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
579 Orion-2 (5281), Orion-1-90 (6183).
582 bool "Marvell PXA168/910/MMP2"
584 select ARCH_REQUIRE_GPIOLIB
586 select GENERIC_ALLOCATOR
587 select GENERIC_CLOCKEVENTS
590 select MULTI_IRQ_HANDLER
595 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
598 bool "Micrel/Kendin KS8695"
599 select ARCH_REQUIRE_GPIOLIB
602 select GENERIC_CLOCKEVENTS
603 select NEED_MACH_MEMORY_H
605 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
606 System-on-Chip devices.
609 bool "Nuvoton W90X900 CPU"
610 select ARCH_REQUIRE_GPIOLIB
614 select GENERIC_CLOCKEVENTS
616 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
617 At present, the w90x900 has been renamed nuc900, regarding
618 the ARM series product line, you can login the following
619 link address to know more.
621 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
622 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
626 select ARCH_REQUIRE_GPIOLIB
631 select GENERIC_CLOCKEVENTS
635 Support for the NXP LPC32XX family of processors
638 bool "PXA2xx/PXA3xx-based"
640 select ARCH_HAS_CPUFREQ
642 select ARCH_REQUIRE_GPIOLIB
643 select ARM_CPU_SUSPEND if PM
647 select GENERIC_CLOCKEVENTS
650 select MULTI_IRQ_HANDLER
654 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
657 bool "Qualcomm MSM (non-multiplatform)"
658 select ARCH_REQUIRE_GPIOLIB
660 select GENERIC_CLOCKEVENTS
662 Support for Qualcomm MSM/QSD based systems. This runs on the
663 apps processor of the MSM/QSD and depends on a shared memory
664 interface to the modem processor which runs the baseband
665 stack and controls some vital subsystems
666 (clock and power control, etc).
668 config ARCH_SHMOBILE_LEGACY
669 bool "Renesas ARM SoCs (non-multiplatform)"
671 select ARM_PATCH_PHYS_VIRT
673 select GENERIC_CLOCKEVENTS
674 select HAVE_ARM_SCU if SMP
675 select HAVE_ARM_TWD if SMP
676 select HAVE_MACH_CLKDEV
678 select MIGHT_HAVE_CACHE_L2X0
679 select MULTI_IRQ_HANDLER
682 select PM_GENERIC_DOMAINS if PM
685 Support for Renesas ARM SoC platforms using a non-multiplatform
686 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
692 select ARCH_MAY_HAVE_PC_FDC
693 select ARCH_SPARSEMEM_ENABLE
694 select ARCH_USES_GETTIMEOFFSET
698 select HAVE_PATA_PLATFORM
700 select NEED_MACH_IO_H
701 select NEED_MACH_MEMORY_H
705 On the Acorn Risc-PC, Linux can support the internal IDE disk and
706 CD-ROM interface, serial and parallel port, and the floppy drive.
710 select ARCH_HAS_CPUFREQ
712 select ARCH_REQUIRE_GPIOLIB
713 select ARCH_SPARSEMEM_ENABLE
718 select GENERIC_CLOCKEVENTS
721 select NEED_MACH_MEMORY_H
724 Support for StrongARM 11x0 based boards.
727 bool "Samsung S3C24XX SoCs"
728 select ARCH_HAS_CPUFREQ
729 select ARCH_REQUIRE_GPIOLIB
732 select CLKSRC_SAMSUNG_PWM
733 select GENERIC_CLOCKEVENTS
735 select HAVE_S3C2410_I2C if I2C
736 select HAVE_S3C2410_WATCHDOG if WATCHDOG
737 select HAVE_S3C_RTC if RTC_CLASS
738 select MULTI_IRQ_HANDLER
739 select NEED_MACH_IO_H
742 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
743 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
744 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
745 Samsung SMDK2410 development board (and derivatives).
748 bool "Samsung S3C64XX"
749 select ARCH_HAS_CPUFREQ
750 select ARCH_REQUIRE_GPIOLIB
755 select CLKSRC_SAMSUNG_PWM
756 select COMMON_CLK_SAMSUNG
758 select GENERIC_CLOCKEVENTS
760 select HAVE_S3C2410_I2C if I2C
761 select HAVE_S3C2410_WATCHDOG if WATCHDOG
765 select PM_GENERIC_DOMAINS if PM
767 select S3C_GPIO_TRACK
769 select SAMSUNG_WAKEMASK
770 select SAMSUNG_WDT_RESET
772 Samsung S3C64XX series based systems
775 bool "Samsung S5P6440 S5P6450"
778 select CLKSRC_SAMSUNG_PWM
780 select GENERIC_CLOCKEVENTS
782 select HAVE_S3C2410_I2C if I2C
783 select HAVE_S3C2410_WATCHDOG if WATCHDOG
784 select HAVE_S3C_RTC if RTC_CLASS
785 select NEED_MACH_GPIO_H
787 select SAMSUNG_WDT_RESET
789 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
793 bool "Samsung S5PC100"
794 select ARCH_REQUIRE_GPIOLIB
797 select CLKSRC_SAMSUNG_PWM
799 select GENERIC_CLOCKEVENTS
801 select HAVE_S3C2410_I2C if I2C
802 select HAVE_S3C2410_WATCHDOG if WATCHDOG
803 select HAVE_S3C_RTC if RTC_CLASS
804 select NEED_MACH_GPIO_H
806 select SAMSUNG_WDT_RESET
808 Samsung S5PC100 series based systems
811 bool "Samsung S5PV210/S5PC110"
812 select ARCH_HAS_CPUFREQ
813 select ARCH_HAS_HOLES_MEMORYMODEL
814 select ARCH_SPARSEMEM_ENABLE
817 select CLKSRC_SAMSUNG_PWM
819 select GENERIC_CLOCKEVENTS
821 select HAVE_S3C2410_I2C if I2C
822 select HAVE_S3C2410_WATCHDOG if WATCHDOG
823 select HAVE_S3C_RTC if RTC_CLASS
824 select NEED_MACH_GPIO_H
825 select NEED_MACH_MEMORY_H
828 Samsung S5PV210/S5PC110 series based systems
832 select ARCH_HAS_HOLES_MEMORYMODEL
833 select ARCH_REQUIRE_GPIOLIB
835 select GENERIC_ALLOCATOR
836 select GENERIC_CLOCKEVENTS
837 select GENERIC_IRQ_CHIP
843 Support for TI's DaVinci platform.
848 select ARCH_HAS_CPUFREQ
849 select ARCH_HAS_HOLES_MEMORYMODEL
851 select ARCH_REQUIRE_GPIOLIB
854 select GENERIC_CLOCKEVENTS
855 select GENERIC_IRQ_CHIP
858 select NEED_MACH_IO_H if PCCARD
859 select NEED_MACH_MEMORY_H
861 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
865 menu "Multiple platform selection"
866 depends on ARCH_MULTIPLATFORM
868 comment "CPU Core family selection"
871 bool "ARMv4 based platforms (FA526)"
872 depends on !ARCH_MULTI_V6_V7
873 select ARCH_MULTI_V4_V5
876 config ARCH_MULTI_V4T
877 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
878 depends on !ARCH_MULTI_V6_V7
879 select ARCH_MULTI_V4_V5
880 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
881 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
882 CPU_ARM925T || CPU_ARM940T)
885 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
886 depends on !ARCH_MULTI_V6_V7
887 select ARCH_MULTI_V4_V5
888 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
889 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
890 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
892 config ARCH_MULTI_V4_V5
896 bool "ARMv6 based platforms (ARM11)"
897 select ARCH_MULTI_V6_V7
901 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
903 select ARCH_MULTI_V6_V7
907 config ARCH_MULTI_V6_V7
909 select MIGHT_HAVE_CACHE_L2X0
911 config ARCH_MULTI_CPU_AUTO
912 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
918 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
922 select HAVE_ARM_ARCH_TIMER
925 # This is sorted alphabetically by mach-* pathname. However, plat-*
926 # Kconfigs may be included either alphabetically (according to the
927 # plat- suffix) or along side the corresponding mach-* source.
929 source "arch/arm/mach-mvebu/Kconfig"
931 source "arch/arm/mach-at91/Kconfig"
933 source "arch/arm/mach-axxia/Kconfig"
935 source "arch/arm/mach-bcm/Kconfig"
937 source "arch/arm/mach-berlin/Kconfig"
939 source "arch/arm/mach-clps711x/Kconfig"
941 source "arch/arm/mach-cns3xxx/Kconfig"
943 source "arch/arm/mach-davinci/Kconfig"
945 source "arch/arm/mach-dove/Kconfig"
947 source "arch/arm/mach-ep93xx/Kconfig"
949 source "arch/arm/mach-footbridge/Kconfig"
951 source "arch/arm/mach-gemini/Kconfig"
953 source "arch/arm/mach-highbank/Kconfig"
955 source "arch/arm/mach-hisi/Kconfig"
957 source "arch/arm/mach-integrator/Kconfig"
959 source "arch/arm/mach-iop32x/Kconfig"
961 source "arch/arm/mach-iop33x/Kconfig"
963 source "arch/arm/mach-iop13xx/Kconfig"
965 source "arch/arm/mach-ixp4xx/Kconfig"
967 source "arch/arm/mach-keystone/Kconfig"
969 source "arch/arm/mach-kirkwood/Kconfig"
971 source "arch/arm/mach-ks8695/Kconfig"
973 source "arch/arm/mach-msm/Kconfig"
975 source "arch/arm/mach-moxart/Kconfig"
977 source "arch/arm/mach-mv78xx0/Kconfig"
979 source "arch/arm/mach-imx/Kconfig"
981 source "arch/arm/mach-mxs/Kconfig"
983 source "arch/arm/mach-netx/Kconfig"
985 source "arch/arm/mach-nomadik/Kconfig"
987 source "arch/arm/mach-nspire/Kconfig"
989 source "arch/arm/plat-omap/Kconfig"
991 source "arch/arm/mach-omap1/Kconfig"
993 source "arch/arm/mach-omap2/Kconfig"
995 source "arch/arm/mach-orion5x/Kconfig"
997 source "arch/arm/mach-picoxcell/Kconfig"
999 source "arch/arm/mach-pxa/Kconfig"
1000 source "arch/arm/plat-pxa/Kconfig"
1002 source "arch/arm/mach-mmp/Kconfig"
1004 source "arch/arm/mach-qcom/Kconfig"
1006 source "arch/arm/mach-realview/Kconfig"
1008 source "arch/arm/mach-rockchip/Kconfig"
1010 source "arch/arm/mach-sa1100/Kconfig"
1012 source "arch/arm/plat-samsung/Kconfig"
1014 source "arch/arm/mach-socfpga/Kconfig"
1016 source "arch/arm/mach-spear/Kconfig"
1018 source "arch/arm/mach-sti/Kconfig"
1020 source "arch/arm/mach-s3c24xx/Kconfig"
1022 source "arch/arm/mach-s3c64xx/Kconfig"
1024 source "arch/arm/mach-s5p64x0/Kconfig"
1026 source "arch/arm/mach-s5pc100/Kconfig"
1028 source "arch/arm/mach-s5pv210/Kconfig"
1030 source "arch/arm/mach-exynos/Kconfig"
1032 source "arch/arm/mach-shmobile/Kconfig"
1034 source "arch/arm/mach-sunxi/Kconfig"
1036 source "arch/arm/mach-prima2/Kconfig"
1038 source "arch/arm/mach-tegra/Kconfig"
1040 source "arch/arm/mach-u300/Kconfig"
1042 source "arch/arm/mach-ux500/Kconfig"
1044 source "arch/arm/mach-versatile/Kconfig"
1046 source "arch/arm/mach-vexpress/Kconfig"
1047 source "arch/arm/plat-versatile/Kconfig"
1049 source "arch/arm/mach-vt8500/Kconfig"
1051 source "arch/arm/mach-w90x900/Kconfig"
1053 source "arch/arm/mach-zynq/Kconfig"
1055 # Definitions to make life easier
1061 select GENERIC_CLOCKEVENTS
1067 select GENERIC_IRQ_CHIP
1070 config PLAT_ORION_LEGACY
1077 config PLAT_VERSATILE
1080 config ARM_TIMER_SP804
1083 select CLKSRC_OF if OF
1085 source "arch/arm/firmware/Kconfig"
1087 source arch/arm/mm/Kconfig
1090 bool "Enable iWMMXt support"
1091 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1092 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1094 Enable support for iWMMXt context switching at run time if
1095 running on a CPU that supports it.
1097 config MULTI_IRQ_HANDLER
1100 Allow each machine to specify it's own IRQ handler at run time.
1103 source "arch/arm/Kconfig-nommu"
1106 config PJ4B_ERRATA_4742
1107 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1108 depends on CPU_PJ4B && MACH_ARMADA_370
1111 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1112 Event (WFE) IDLE states, a specific timing sensitivity exists between
1113 the retiring WFI/WFE instructions and the newly issued subsequent
1114 instructions. This sensitivity can result in a CPU hang scenario.
1116 The software must insert either a Data Synchronization Barrier (DSB)
1117 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1120 config ARM_ERRATA_326103
1121 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1124 Executing a SWP instruction to read-only memory does not set bit 11
1125 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1126 treat the access as a read, preventing a COW from occurring and
1127 causing the faulting task to livelock.
1129 config ARM_ERRATA_411920
1130 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1131 depends on CPU_V6 || CPU_V6K
1133 Invalidation of the Instruction Cache operation can
1134 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1135 It does not affect the MPCore. This option enables the ARM Ltd.
1136 recommended workaround.
1138 config ARM_ERRATA_430973
1139 bool "ARM errata: Stale prediction on replaced interworking branch"
1142 This option enables the workaround for the 430973 Cortex-A8
1143 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1144 interworking branch is replaced with another code sequence at the
1145 same virtual address, whether due to self-modifying code or virtual
1146 to physical address re-mapping, Cortex-A8 does not recover from the
1147 stale interworking branch prediction. This results in Cortex-A8
1148 executing the new code sequence in the incorrect ARM or Thumb state.
1149 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1150 and also flushes the branch target cache at every context switch.
1151 Note that setting specific bits in the ACTLR register may not be
1152 available in non-secure mode.
1154 config ARM_ERRATA_458693
1155 bool "ARM errata: Processor deadlock when a false hazard is created"
1157 depends on !ARCH_MULTIPLATFORM
1159 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1160 erratum. For very specific sequences of memory operations, it is
1161 possible for a hazard condition intended for a cache line to instead
1162 be incorrectly associated with a different cache line. This false
1163 hazard might then cause a processor deadlock. The workaround enables
1164 the L1 caching of the NEON accesses and disables the PLD instruction
1165 in the ACTLR register. Note that setting specific bits in the ACTLR
1166 register may not be available in non-secure mode.
1168 config ARM_ERRATA_460075
1169 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1171 depends on !ARCH_MULTIPLATFORM
1173 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1174 erratum. Any asynchronous access to the L2 cache may encounter a
1175 situation in which recent store transactions to the L2 cache are lost
1176 and overwritten with stale memory contents from external memory. The
1177 workaround disables the write-allocate mode for the L2 cache via the
1178 ACTLR register. Note that setting specific bits in the ACTLR register
1179 may not be available in non-secure mode.
1181 config ARM_ERRATA_742230
1182 bool "ARM errata: DMB operation may be faulty"
1183 depends on CPU_V7 && SMP
1184 depends on !ARCH_MULTIPLATFORM
1186 This option enables the workaround for the 742230 Cortex-A9
1187 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1188 between two write operations may not ensure the correct visibility
1189 ordering of the two writes. This workaround sets a specific bit in
1190 the diagnostic register of the Cortex-A9 which causes the DMB
1191 instruction to behave as a DSB, ensuring the correct behaviour of
1194 config ARM_ERRATA_742231
1195 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1196 depends on CPU_V7 && SMP
1197 depends on !ARCH_MULTIPLATFORM
1199 This option enables the workaround for the 742231 Cortex-A9
1200 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1201 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1202 accessing some data located in the same cache line, may get corrupted
1203 data due to bad handling of the address hazard when the line gets
1204 replaced from one of the CPUs at the same time as another CPU is
1205 accessing it. This workaround sets specific bits in the diagnostic
1206 register of the Cortex-A9 which reduces the linefill issuing
1207 capabilities of the processor.
1209 config ARM_ERRATA_643719
1210 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1211 depends on CPU_V7 && SMP
1213 This option enables the workaround for the 643719 Cortex-A9 (prior to
1214 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1215 register returns zero when it should return one. The workaround
1216 corrects this value, ensuring cache maintenance operations which use
1217 it behave as intended and avoiding data corruption.
1219 config ARM_ERRATA_720789
1220 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1223 This option enables the workaround for the 720789 Cortex-A9 (prior to
1224 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1225 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1226 As a consequence of this erratum, some TLB entries which should be
1227 invalidated are not, resulting in an incoherency in the system page
1228 tables. The workaround changes the TLB flushing routines to invalidate
1229 entries regardless of the ASID.
1231 config ARM_ERRATA_743622
1232 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1234 depends on !ARCH_MULTIPLATFORM
1236 This option enables the workaround for the 743622 Cortex-A9
1237 (r2p*) erratum. Under very rare conditions, a faulty
1238 optimisation in the Cortex-A9 Store Buffer may lead to data
1239 corruption. This workaround sets a specific bit in the diagnostic
1240 register of the Cortex-A9 which disables the Store Buffer
1241 optimisation, preventing the defect from occurring. This has no
1242 visible impact on the overall performance or power consumption of the
1245 config ARM_ERRATA_751472
1246 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1248 depends on !ARCH_MULTIPLATFORM
1250 This option enables the workaround for the 751472 Cortex-A9 (prior
1251 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1252 completion of a following broadcasted operation if the second
1253 operation is received by a CPU before the ICIALLUIS has completed,
1254 potentially leading to corrupted entries in the cache or TLB.
1256 config ARM_ERRATA_754322
1257 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1260 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1261 r3p*) erratum. A speculative memory access may cause a page table walk
1262 which starts prior to an ASID switch but completes afterwards. This
1263 can populate the micro-TLB with a stale entry which may be hit with
1264 the new ASID. This workaround places two dsb instructions in the mm
1265 switching code so that no page table walks can cross the ASID switch.
1267 config ARM_ERRATA_754327
1268 bool "ARM errata: no automatic Store Buffer drain"
1269 depends on CPU_V7 && SMP
1271 This option enables the workaround for the 754327 Cortex-A9 (prior to
1272 r2p0) erratum. The Store Buffer does not have any automatic draining
1273 mechanism and therefore a livelock may occur if an external agent
1274 continuously polls a memory location waiting to observe an update.
1275 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1276 written polling loops from denying visibility of updates to memory.
1278 config ARM_ERRATA_364296
1279 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1282 This options enables the workaround for the 364296 ARM1136
1283 r0p2 erratum (possible cache data corruption with
1284 hit-under-miss enabled). It sets the undocumented bit 31 in
1285 the auxiliary control register and the FI bit in the control
1286 register, thus disabling hit-under-miss without putting the
1287 processor into full low interrupt latency mode. ARM11MPCore
1290 config ARM_ERRATA_764369
1291 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1292 depends on CPU_V7 && SMP
1294 This option enables the workaround for erratum 764369
1295 affecting Cortex-A9 MPCore with two or more processors (all
1296 current revisions). Under certain timing circumstances, a data
1297 cache line maintenance operation by MVA targeting an Inner
1298 Shareable memory region may fail to proceed up to either the
1299 Point of Coherency or to the Point of Unification of the
1300 system. This workaround adds a DSB instruction before the
1301 relevant cache maintenance functions and sets a specific bit
1302 in the diagnostic control register of the SCU.
1304 config ARM_ERRATA_775420
1305 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1308 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1309 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1310 operation aborts with MMU exception, it might cause the processor
1311 to deadlock. This workaround puts DSB before executing ISB if
1312 an abort may occur on cache maintenance.
1314 config ARM_ERRATA_798181
1315 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1316 depends on CPU_V7 && SMP
1318 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1319 adequately shooting down all use of the old entries. This
1320 option enables the Linux kernel workaround for this erratum
1321 which sends an IPI to the CPUs that are running the same ASID
1322 as the one being invalidated.
1324 config ARM_ERRATA_773022
1325 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1328 This option enables the workaround for the 773022 Cortex-A15
1329 (up to r0p4) erratum. In certain rare sequences of code, the
1330 loop buffer may deliver incorrect instructions. This
1331 workaround disables the loop buffer to avoid the erratum.
1335 source "arch/arm/common/Kconfig"
1345 Find out whether you have ISA slots on your motherboard. ISA is the
1346 name of a bus system, i.e. the way the CPU talks to the other stuff
1347 inside your box. Other bus systems are PCI, EISA, MicroChannel
1348 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1349 newer boards don't support it. If you have ISA, say Y, otherwise N.
1351 # Select ISA DMA controller support
1356 # Select ISA DMA interface
1361 bool "PCI support" if MIGHT_HAVE_PCI
1363 Find out whether you have a PCI motherboard. PCI is the name of a
1364 bus system, i.e. the way the CPU talks to the other stuff inside
1365 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1366 VESA. If you have PCI, say Y, otherwise N.
1372 config PCI_NANOENGINE
1373 bool "BSE nanoEngine PCI support"
1374 depends on SA1100_NANOENGINE
1376 Enable PCI on the BSE nanoEngine board.
1381 config PCI_HOST_ITE8152
1383 depends on PCI && MACH_ARMCORE
1387 source "drivers/pci/Kconfig"
1388 source "drivers/pci/pcie/Kconfig"
1390 source "drivers/pcmcia/Kconfig"
1394 menu "Kernel Features"
1399 This option should be selected by machines which have an SMP-
1402 The only effect of this option is to make the SMP-related
1403 options available to the user for configuration.
1406 bool "Symmetric Multi-Processing"
1407 depends on CPU_V6K || CPU_V7
1408 depends on GENERIC_CLOCKEVENTS
1410 depends on MMU || ARM_MPU
1412 This enables support for systems with more than one CPU. If you have
1413 a system with only one CPU, say N. If you have a system with more
1414 than one CPU, say Y.
1416 If you say N here, the kernel will run on uni- and multiprocessor
1417 machines, but will use only one CPU of a multiprocessor machine. If
1418 you say Y here, the kernel will run on many, but not all,
1419 uniprocessor machines. On a uniprocessor machine, the kernel
1420 will run faster if you say N here.
1422 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1423 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1424 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1426 If you don't know what to do here, say N.
1429 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1430 depends on SMP && !XIP_KERNEL && MMU
1433 SMP kernels contain instructions which fail on non-SMP processors.
1434 Enabling this option allows the kernel to modify itself to make
1435 these instructions safe. Disabling it allows about 1K of space
1438 If you don't know what to do here, say Y.
1440 config ARM_CPU_TOPOLOGY
1441 bool "Support cpu topology definition"
1442 depends on SMP && CPU_V7
1445 Support ARM cpu topology definition. The MPIDR register defines
1446 affinity between processors which is then used to describe the cpu
1447 topology of an ARM System.
1450 bool "Multi-core scheduler support"
1451 depends on ARM_CPU_TOPOLOGY
1453 Multi-core scheduler support improves the CPU scheduler's decision
1454 making when dealing with multi-core CPU chips at a cost of slightly
1455 increased overhead in some places. If unsure say N here.
1458 bool "SMT scheduler support"
1459 depends on ARM_CPU_TOPOLOGY
1461 Improves the CPU scheduler's decision making when dealing with
1462 MultiThreading at a cost of slightly increased overhead in some
1463 places. If unsure say N here.
1468 This option enables support for the ARM system coherency unit
1470 config HAVE_ARM_ARCH_TIMER
1471 bool "Architected timer support"
1473 select ARM_ARCH_TIMER
1474 select GENERIC_CLOCKEVENTS
1476 This option enables support for the ARM architected timer
1481 select CLKSRC_OF if OF
1483 This options enables support for the ARM timer and watchdog unit
1486 bool "Multi-Cluster Power Management"
1487 depends on CPU_V7 && SMP
1489 This option provides the common power management infrastructure
1490 for (multi-)cluster based systems, such as big.LITTLE based
1494 bool "big.LITTLE support (Experimental)"
1495 depends on CPU_V7 && SMP
1498 This option enables support selections for the big.LITTLE
1499 system architecture.
1502 bool "big.LITTLE switcher support"
1503 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1504 select ARM_CPU_SUSPEND
1507 The big.LITTLE "switcher" provides the core functionality to
1508 transparently handle transition between a cluster of A15's
1509 and a cluster of A7's in a big.LITTLE system.
1511 config BL_SWITCHER_DUMMY_IF
1512 tristate "Simple big.LITTLE switcher user interface"
1513 depends on BL_SWITCHER && DEBUG_KERNEL
1515 This is a simple and dummy char dev interface to control
1516 the big.LITTLE switcher core code. It is meant for
1517 debugging purposes only.
1520 prompt "Memory split"
1524 Select the desired split between kernel and user memory.
1526 If you are not absolutely sure what you are doing, leave this
1530 bool "3G/1G user/kernel split"
1532 bool "2G/2G user/kernel split"
1534 bool "1G/3G user/kernel split"
1539 default PHYS_OFFSET if !MMU
1540 default 0x40000000 if VMSPLIT_1G
1541 default 0x80000000 if VMSPLIT_2G
1545 int "Maximum number of CPUs (2-32)"
1551 bool "Support for hot-pluggable CPUs"
1554 Say Y here to experiment with turning CPUs off and on. CPUs
1555 can be controlled through /sys/devices/system/cpu.
1558 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1561 Say Y here if you want Linux to communicate with system firmware
1562 implementing the PSCI specification for CPU-centric power
1563 management operations described in ARM document number ARM DEN
1564 0022A ("Power State Coordination Interface System Software on
1567 # The GPIO number here must be sorted by descending number. In case of
1568 # a multiplatform kernel, we just want the highest value required by the
1569 # selected platforms.
1572 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1573 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1574 default 416 if ARCH_SUNXI
1575 default 392 if ARCH_U8500
1576 default 352 if ARCH_VT8500
1577 default 264 if MACH_H4700
1580 Maximum number of GPIOs in the system.
1582 If unsure, leave the default value.
1584 source kernel/Kconfig.preempt
1588 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1589 ARCH_S5PV210 || ARCH_EXYNOS4
1590 default AT91_TIMER_HZ if ARCH_AT91
1591 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1595 depends on HZ_FIXED = 0
1596 prompt "Timer frequency"
1620 default HZ_FIXED if HZ_FIXED != 0
1621 default 100 if HZ_100
1622 default 200 if HZ_200
1623 default 250 if HZ_250
1624 default 300 if HZ_300
1625 default 500 if HZ_500
1629 def_bool HIGH_RES_TIMERS
1631 config THUMB2_KERNEL
1632 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1633 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1634 default y if CPU_THUMBONLY
1636 select ARM_ASM_UNIFIED
1639 By enabling this option, the kernel will be compiled in
1640 Thumb-2 mode. A compiler/assembler that understand the unified
1641 ARM-Thumb syntax is needed.
1645 config THUMB2_AVOID_R_ARM_THM_JUMP11
1646 bool "Work around buggy Thumb-2 short branch relocations in gas"
1647 depends on THUMB2_KERNEL && MODULES
1650 Various binutils versions can resolve Thumb-2 branches to
1651 locally-defined, preemptible global symbols as short-range "b.n"
1652 branch instructions.
1654 This is a problem, because there's no guarantee the final
1655 destination of the symbol, or any candidate locations for a
1656 trampoline, are within range of the branch. For this reason, the
1657 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1658 relocation in modules at all, and it makes little sense to add
1661 The symptom is that the kernel fails with an "unsupported
1662 relocation" error when loading some modules.
1664 Until fixed tools are available, passing
1665 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1666 code which hits this problem, at the cost of a bit of extra runtime
1667 stack usage in some cases.
1669 The problem is described in more detail at:
1670 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1672 Only Thumb-2 kernels are affected.
1674 Unless you are sure your tools don't have this problem, say Y.
1676 config ARM_ASM_UNIFIED
1680 bool "Use the ARM EABI to compile the kernel"
1682 This option allows for the kernel to be compiled using the latest
1683 ARM ABI (aka EABI). This is only useful if you are using a user
1684 space environment that is also compiled with EABI.
1686 Since there are major incompatibilities between the legacy ABI and
1687 EABI, especially with regard to structure member alignment, this
1688 option also changes the kernel syscall calling convention to
1689 disambiguate both ABIs and allow for backward compatibility support
1690 (selected with CONFIG_OABI_COMPAT).
1692 To use this you need GCC version 4.0.0 or later.
1695 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1696 depends on AEABI && !THUMB2_KERNEL
1698 This option preserves the old syscall interface along with the
1699 new (ARM EABI) one. It also provides a compatibility layer to
1700 intercept syscalls that have structure arguments which layout
1701 in memory differs between the legacy ABI and the new ARM EABI
1702 (only for non "thumb" binaries). This option adds a tiny
1703 overhead to all syscalls and produces a slightly larger kernel.
1705 The seccomp filter system will not be available when this is
1706 selected, since there is no way yet to sensibly distinguish
1707 between calling conventions during filtering.
1709 If you know you'll be using only pure EABI user space then you
1710 can say N here. If this option is not selected and you attempt
1711 to execute a legacy ABI binary then the result will be
1712 UNPREDICTABLE (in fact it can be predicted that it won't work
1713 at all). If in doubt say N.
1715 config ARCH_HAS_HOLES_MEMORYMODEL
1718 config ARCH_SPARSEMEM_ENABLE
1721 config ARCH_SPARSEMEM_DEFAULT
1722 def_bool ARCH_SPARSEMEM_ENABLE
1724 config ARCH_SELECT_MEMORY_MODEL
1725 def_bool ARCH_SPARSEMEM_ENABLE
1727 config HAVE_ARCH_PFN_VALID
1728 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1731 bool "High Memory Support"
1734 The address space of ARM processors is only 4 Gigabytes large
1735 and it has to accommodate user address space, kernel address
1736 space as well as some memory mapped IO. That means that, if you
1737 have a large amount of physical memory and/or IO, not all of the
1738 memory can be "permanently mapped" by the kernel. The physical
1739 memory that is not permanently mapped is called "high memory".
1741 Depending on the selected kernel/user memory split, minimum
1742 vmalloc space and actual amount of RAM, you may not need this
1743 option which should result in a slightly faster kernel.
1748 bool "Allocate 2nd-level pagetables from highmem"
1751 config HW_PERF_EVENTS
1752 bool "Enable hardware performance counter support for perf events"
1753 depends on PERF_EVENTS
1756 Enable hardware performance counter support for perf events. If
1757 disabled, perf events will use software events only.
1759 config SYS_SUPPORTS_HUGETLBFS
1763 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1767 config ARCH_WANT_GENERAL_HUGETLB
1772 config FORCE_MAX_ZONEORDER
1773 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1774 range 11 64 if ARCH_SHMOBILE_LEGACY
1775 default "12" if SOC_AM33XX
1776 default "9" if SA1111 || ARCH_EFM32
1779 The kernel memory allocator divides physically contiguous memory
1780 blocks into "zones", where each zone is a power of two number of
1781 pages. This option selects the largest power of two that the kernel
1782 keeps in the memory allocator. If you need to allocate very large
1783 blocks of physically contiguous memory, then you may need to
1784 increase this value.
1786 This config option is actually maximum order plus one. For example,
1787 a value of 11 means that the largest free memory block is 2^10 pages.
1789 config ALIGNMENT_TRAP
1791 depends on CPU_CP15_MMU
1792 default y if !ARCH_EBSA110
1793 select HAVE_PROC_CPU if PROC_FS
1795 ARM processors cannot fetch/store information which is not
1796 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1797 address divisible by 4. On 32-bit ARM processors, these non-aligned
1798 fetch/store instructions will be emulated in software if you say
1799 here, which has a severe performance impact. This is necessary for
1800 correct operation of some network protocols. With an IP-only
1801 configuration it is safe to say N, otherwise say Y.
1803 config UACCESS_WITH_MEMCPY
1804 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1806 default y if CPU_FEROCEON
1808 Implement faster copy_to_user and clear_user methods for CPU
1809 cores where a 8-word STM instruction give significantly higher
1810 memory write throughput than a sequence of individual 32bit stores.
1812 A possible side effect is a slight increase in scheduling latency
1813 between threads sharing the same address space if they invoke
1814 such copy operations with large buffers.
1816 However, if the CPU data cache is using a write-allocate mode,
1817 this option is unlikely to provide any performance gain.
1821 prompt "Enable seccomp to safely compute untrusted bytecode"
1823 This kernel feature is useful for number crunching applications
1824 that may need to compute untrusted bytecode during their
1825 execution. By using pipes or other transports made available to
1826 the process as file descriptors supporting the read/write
1827 syscalls, it's possible to isolate those applications in
1828 their own address space using seccomp. Once seccomp is
1829 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1830 and the task is only allowed to execute a few safe syscalls
1831 defined by each seccomp mode.
1844 bool "Xen guest support on ARM (EXPERIMENTAL)"
1845 depends on ARM && AEABI && OF
1846 depends on CPU_V7 && !CPU_V6
1847 depends on !GENERIC_ATOMIC64
1849 select ARCH_DMA_ADDR_T_64BIT
1853 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1860 bool "Flattened Device Tree support"
1863 select OF_EARLY_FLATTREE
1864 select OF_RESERVED_MEM
1866 Include support for flattened device tree machine descriptions.
1869 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1872 This is the traditional way of passing data to the kernel at boot
1873 time. If you are solely relying on the flattened device tree (or
1874 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1875 to remove ATAGS support from your kernel binary. If unsure,
1878 config DEPRECATED_PARAM_STRUCT
1879 bool "Provide old way to pass kernel parameters"
1882 This was deprecated in 2001 and announced to live on for 5 years.
1883 Some old boot loaders still use this way.
1885 # Compressed boot loader in ROM. Yes, we really want to ask about
1886 # TEXT and BSS so we preserve their values in the config files.
1887 config ZBOOT_ROM_TEXT
1888 hex "Compressed ROM boot loader base address"
1891 The physical address at which the ROM-able zImage is to be
1892 placed in the target. Platforms which normally make use of
1893 ROM-able zImage formats normally set this to a suitable
1894 value in their defconfig file.
1896 If ZBOOT_ROM is not enabled, this has no effect.
1898 config ZBOOT_ROM_BSS
1899 hex "Compressed ROM boot loader BSS address"
1902 The base address of an area of read/write memory in the target
1903 for the ROM-able zImage which must be available while the
1904 decompressor is running. It must be large enough to hold the
1905 entire decompressed kernel plus an additional 128 KiB.
1906 Platforms which normally make use of ROM-able zImage formats
1907 normally set this to a suitable value in their defconfig file.
1909 If ZBOOT_ROM is not enabled, this has no effect.
1912 bool "Compressed boot loader in ROM/flash"
1913 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1914 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1916 Say Y here if you intend to execute your compressed kernel image
1917 (zImage) directly from ROM or flash. If unsure, say N.
1920 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1921 depends on ZBOOT_ROM && ARCH_SH7372
1922 default ZBOOT_ROM_NONE
1924 Include experimental SD/MMC loading code in the ROM-able zImage.
1925 With this enabled it is possible to write the ROM-able zImage
1926 kernel image to an MMC or SD card and boot the kernel straight
1927 from the reset vector. At reset the processor Mask ROM will load
1928 the first part of the ROM-able zImage which in turn loads the
1929 rest the kernel image to RAM.
1931 config ZBOOT_ROM_NONE
1932 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1934 Do not load image from SD or MMC
1936 config ZBOOT_ROM_MMCIF
1937 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1939 Load image from MMCIF hardware block.
1941 config ZBOOT_ROM_SH_MOBILE_SDHI
1942 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1944 Load image from SDHI hardware block
1948 config ARM_APPENDED_DTB
1949 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1952 With this option, the boot code will look for a device tree binary
1953 (DTB) appended to zImage
1954 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1956 This is meant as a backward compatibility convenience for those
1957 systems with a bootloader that can't be upgraded to accommodate
1958 the documented boot protocol using a device tree.
1960 Beware that there is very little in terms of protection against
1961 this option being confused by leftover garbage in memory that might
1962 look like a DTB header after a reboot if no actual DTB is appended
1963 to zImage. Do not leave this option active in a production kernel
1964 if you don't intend to always append a DTB. Proper passing of the
1965 location into r2 of a bootloader provided DTB is always preferable
1968 config ARM_ATAG_DTB_COMPAT
1969 bool "Supplement the appended DTB with traditional ATAG information"
1970 depends on ARM_APPENDED_DTB
1972 Some old bootloaders can't be updated to a DTB capable one, yet
1973 they provide ATAGs with memory configuration, the ramdisk address,
1974 the kernel cmdline string, etc. Such information is dynamically
1975 provided by the bootloader and can't always be stored in a static
1976 DTB. To allow a device tree enabled kernel to be used with such
1977 bootloaders, this option allows zImage to extract the information
1978 from the ATAG list and store it at run time into the appended DTB.
1981 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1982 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1984 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1985 bool "Use bootloader kernel arguments if available"
1987 Uses the command-line options passed by the boot loader instead of
1988 the device tree bootargs property. If the boot loader doesn't provide
1989 any, the device tree bootargs property will be used.
1991 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1992 bool "Extend with bootloader kernel arguments"
1994 The command-line arguments provided by the boot loader will be
1995 appended to the the device tree bootargs property.
2000 string "Default kernel command string"
2003 On some architectures (EBSA110 and CATS), there is currently no way
2004 for the boot loader to pass arguments to the kernel. For these
2005 architectures, you should supply some command-line options at build
2006 time by entering them here. As a minimum, you should specify the
2007 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2010 prompt "Kernel command line type" if CMDLINE != ""
2011 default CMDLINE_FROM_BOOTLOADER
2014 config CMDLINE_FROM_BOOTLOADER
2015 bool "Use bootloader kernel arguments if available"
2017 Uses the command-line options passed by the boot loader. If
2018 the boot loader doesn't provide any, the default kernel command
2019 string provided in CMDLINE will be used.
2021 config CMDLINE_EXTEND
2022 bool "Extend bootloader kernel arguments"
2024 The command-line arguments provided by the boot loader will be
2025 appended to the default kernel command string.
2027 config CMDLINE_FORCE
2028 bool "Always use the default kernel command string"
2030 Always use the default kernel command string, even if the boot
2031 loader passes other arguments to the kernel.
2032 This is useful if you cannot or don't want to change the
2033 command-line options your boot loader passes to the kernel.
2037 bool "Kernel Execute-In-Place from ROM"
2038 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2040 Execute-In-Place allows the kernel to run from non-volatile storage
2041 directly addressable by the CPU, such as NOR flash. This saves RAM
2042 space since the text section of the kernel is not loaded from flash
2043 to RAM. Read-write sections, such as the data section and stack,
2044 are still copied to RAM. The XIP kernel is not compressed since
2045 it has to run directly from flash, so it will take more space to
2046 store it. The flash address used to link the kernel object files,
2047 and for storing it, is configuration dependent. Therefore, if you
2048 say Y here, you must know the proper physical address where to
2049 store the kernel image depending on your own flash memory usage.
2051 Also note that the make target becomes "make xipImage" rather than
2052 "make zImage" or "make Image". The final kernel binary to put in
2053 ROM memory will be arch/arm/boot/xipImage.
2057 config XIP_PHYS_ADDR
2058 hex "XIP Kernel Physical Location"
2059 depends on XIP_KERNEL
2060 default "0x00080000"
2062 This is the physical address in your flash memory the kernel will
2063 be linked for and stored to. This address is dependent on your
2067 bool "Kexec system call (EXPERIMENTAL)"
2068 depends on (!SMP || PM_SLEEP_SMP)
2070 kexec is a system call that implements the ability to shutdown your
2071 current kernel, and to start another kernel. It is like a reboot
2072 but it is independent of the system firmware. And like a reboot
2073 you can start any kernel with it, not just Linux.
2075 It is an ongoing process to be certain the hardware in a machine
2076 is properly shutdown, so do not be surprised if this code does not
2077 initially work for you.
2080 bool "Export atags in procfs"
2081 depends on ATAGS && KEXEC
2084 Should the atags used to boot the kernel be exported in an "atags"
2085 file in procfs. Useful with kexec.
2088 bool "Build kdump crash kernel (EXPERIMENTAL)"
2090 Generate crash dump after being started by kexec. This should
2091 be normally only set in special crash dump kernels which are
2092 loaded in the main kernel with kexec-tools into a specially
2093 reserved region and then later executed after a crash by
2094 kdump/kexec. The crash dump kernel must be compiled to a
2095 memory address not used by the main kernel
2097 For more details see Documentation/kdump/kdump.txt
2099 config AUTO_ZRELADDR
2100 bool "Auto calculation of the decompressed kernel image address"
2102 ZRELADDR is the physical address where the decompressed kernel
2103 image will be placed. If AUTO_ZRELADDR is selected, the address
2104 will be determined at run-time by masking the current IP with
2105 0xf8000000. This assumes the zImage being placed in the first 128MB
2106 from start of memory.
2110 menu "CPU Power Management"
2113 source "drivers/cpufreq/Kconfig"
2116 source "drivers/cpuidle/Kconfig"
2120 menu "Floating point emulation"
2122 comment "At least one emulation must be selected"
2125 bool "NWFPE math emulation"
2126 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2128 Say Y to include the NWFPE floating point emulator in the kernel.
2129 This is necessary to run most binaries. Linux does not currently
2130 support floating point hardware so you need to say Y here even if
2131 your machine has an FPA or floating point co-processor podule.
2133 You may say N here if you are going to load the Acorn FPEmulator
2134 early in the bootup.
2137 bool "Support extended precision"
2138 depends on FPE_NWFPE
2140 Say Y to include 80-bit support in the kernel floating-point
2141 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2142 Note that gcc does not generate 80-bit operations by default,
2143 so in most cases this option only enlarges the size of the
2144 floating point emulator without any good reason.
2146 You almost surely want to say N here.
2149 bool "FastFPE math emulation (EXPERIMENTAL)"
2150 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2152 Say Y here to include the FAST floating point emulator in the kernel.
2153 This is an experimental much faster emulator which now also has full
2154 precision for the mantissa. It does not support any exceptions.
2155 It is very simple, and approximately 3-6 times faster than NWFPE.
2157 It should be sufficient for most programs. It may be not suitable
2158 for scientific calculations, but you have to check this for yourself.
2159 If you do not feel you need a faster FP emulation you should better
2163 bool "VFP-format floating point maths"
2164 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2166 Say Y to include VFP support code in the kernel. This is needed
2167 if your hardware includes a VFP unit.
2169 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2170 release notes and additional status information.
2172 Say N if your target does not have VFP hardware.
2180 bool "Advanced SIMD (NEON) Extension support"
2181 depends on VFPv3 && CPU_V7
2183 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2186 config KERNEL_MODE_NEON
2187 bool "Support for NEON in kernel mode"
2188 depends on NEON && AEABI
2190 Say Y to include support for NEON in kernel mode.
2194 menu "Userspace binary formats"
2196 source "fs/Kconfig.binfmt"
2199 tristate "RISC OS personality"
2202 Say Y here to include the kernel code necessary if you want to run
2203 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2204 experimental; if this sounds frightening, say N and sleep in peace.
2205 You can also say M here to compile this support as a module (which
2206 will be called arthur).
2210 menu "Power management options"
2212 source "kernel/power/Kconfig"
2214 config ARCH_SUSPEND_POSSIBLE
2215 depends on !ARCH_S5PC100
2216 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2217 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2220 config ARM_CPU_SUSPEND
2223 config ARCH_HIBERNATION_POSSIBLE
2226 default y if ARCH_SUSPEND_POSSIBLE
2230 source "net/Kconfig"
2232 source "drivers/Kconfig"
2236 source "arch/arm/Kconfig.debug"
2238 source "security/Kconfig"
2240 source "crypto/Kconfig"
2242 source "lib/Kconfig"
2244 source "arch/arm/kvm/Kconfig"