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KVM: nVMX: Fix returned value of MSR_IA32_VMX_VMCS_ENUM
[linux/fpc-iii.git] / arch / x86 / kvm / x86.c
blob451d6acea808edbb1b67a872b55c1aea14938a04
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
34 #include <linux/fs.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <trace/events/kvm.h>
52
53 #define CREATE_TRACE_POINTS
54 #include "trace.h"
55
56 #include <asm/debugreg.h>
57 #include <asm/msr.h>
58 #include <asm/desc.h>
59 #include <asm/mtrr.h>
60 #include <asm/mce.h>
61 #include <asm/i387.h>
62 #include <asm/fpu-internal.h> /* Ugh! */
63 #include <asm/xcr.h>
64 #include <asm/pvclock.h>
65 #include <asm/div64.h>
66
67 #define MAX_IO_MSRS 256
68 #define KVM_MAX_MCE_BANKS 32
69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
70
71 #define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
74 /* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78 #ifdef CONFIG_X86_64
79 static
80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
81 #else
82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
83 #endif
84
85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
87
88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
89 static void process_nmi(struct kvm_vcpu *vcpu);
90
91 struct kvm_x86_ops *kvm_x86_ops;
92 EXPORT_SYMBOL_GPL(kvm_x86_ops);
93
94 static bool ignore_msrs = 0;
95 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
96
97 unsigned int min_timer_period_us = 500;
98 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
99
100 bool kvm_has_tsc_control;
101 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102 u32 kvm_max_guest_tsc_khz;
103 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104
105 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106 static u32 tsc_tolerance_ppm = 250;
107 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108
109 static bool backwards_tsc_observed = false;
110
111 #define KVM_NR_SHARED_MSRS 16
112
113 struct kvm_shared_msrs_global {
114 int nr;
115 u32 msrs[KVM_NR_SHARED_MSRS];
116 };
117
118 struct kvm_shared_msrs {
119 struct user_return_notifier urn;
120 bool registered;
121 struct kvm_shared_msr_values {
122 u64 host;
123 u64 curr;
124 } values[KVM_NR_SHARED_MSRS];
125 };
126
127 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
128 static struct kvm_shared_msrs __percpu *shared_msrs;
129
130 struct kvm_stats_debugfs_item debugfs_entries[] = {
131 { "pf_fixed", VCPU_STAT(pf_fixed) },
132 { "pf_guest", VCPU_STAT(pf_guest) },
133 { "tlb_flush", VCPU_STAT(tlb_flush) },
134 { "invlpg", VCPU_STAT(invlpg) },
135 { "exits", VCPU_STAT(exits) },
136 { "io_exits", VCPU_STAT(io_exits) },
137 { "mmio_exits", VCPU_STAT(mmio_exits) },
138 { "signal_exits", VCPU_STAT(signal_exits) },
139 { "irq_window", VCPU_STAT(irq_window_exits) },
140 { "nmi_window", VCPU_STAT(nmi_window_exits) },
141 { "halt_exits", VCPU_STAT(halt_exits) },
142 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
143 { "hypercalls", VCPU_STAT(hypercalls) },
144 { "request_irq", VCPU_STAT(request_irq_exits) },
145 { "irq_exits", VCPU_STAT(irq_exits) },
146 { "host_state_reload", VCPU_STAT(host_state_reload) },
147 { "efer_reload", VCPU_STAT(efer_reload) },
148 { "fpu_reload", VCPU_STAT(fpu_reload) },
149 { "insn_emulation", VCPU_STAT(insn_emulation) },
150 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
151 { "irq_injections", VCPU_STAT(irq_injections) },
152 { "nmi_injections", VCPU_STAT(nmi_injections) },
153 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
154 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
155 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
156 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
157 { "mmu_flooded", VM_STAT(mmu_flooded) },
158 { "mmu_recycled", VM_STAT(mmu_recycled) },
159 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
160 { "mmu_unsync", VM_STAT(mmu_unsync) },
161 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
162 { "largepages", VM_STAT(lpages) },
163 { NULL }
164 };
165
166 u64 __read_mostly host_xcr0;
167
168 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
169
170 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
171 {
172 int i;
173 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
174 vcpu->arch.apf.gfns[i] = ~0;
175 }
176
177 static void kvm_on_user_return(struct user_return_notifier *urn)
178 {
179 unsigned slot;
180 struct kvm_shared_msrs *locals
181 = container_of(urn, struct kvm_shared_msrs, urn);
182 struct kvm_shared_msr_values *values;
183
184 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
185 values = &locals->values[slot];
186 if (values->host != values->curr) {
187 wrmsrl(shared_msrs_global.msrs[slot], values->host);
188 values->curr = values->host;
189 }
190 }
191 locals->registered = false;
192 user_return_notifier_unregister(urn);
193 }
194
195 static void shared_msr_update(unsigned slot, u32 msr)
196 {
197 u64 value;
198 unsigned int cpu = smp_processor_id();
199 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
200
201 /* only read, and nobody should modify it at this time,
202 * so don't need lock */
203 if (slot >= shared_msrs_global.nr) {
204 printk(KERN_ERR "kvm: invalid MSR slot!");
205 return;
206 }
207 rdmsrl_safe(msr, &value);
208 smsr->values[slot].host = value;
209 smsr->values[slot].curr = value;
210 }
211
212 void kvm_define_shared_msr(unsigned slot, u32 msr)
213 {
214 if (slot >= shared_msrs_global.nr)
215 shared_msrs_global.nr = slot + 1;
216 shared_msrs_global.msrs[slot] = msr;
217 /* we need ensured the shared_msr_global have been updated */
218 smp_wmb();
219 }
220 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
221
222 static void kvm_shared_msr_cpu_online(void)
223 {
224 unsigned i;
225
226 for (i = 0; i < shared_msrs_global.nr; ++i)
227 shared_msr_update(i, shared_msrs_global.msrs[i]);
228 }
229
230 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
231 {
232 unsigned int cpu = smp_processor_id();
233 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
234
235 if (((value ^ smsr->values[slot].curr) & mask) == 0)
236 return;
237 smsr->values[slot].curr = value;
238 wrmsrl(shared_msrs_global.msrs[slot], value);
239 if (!smsr->registered) {
240 smsr->urn.on_user_return = kvm_on_user_return;
241 user_return_notifier_register(&smsr->urn);
242 smsr->registered = true;
243 }
244 }
245 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
246
247 static void drop_user_return_notifiers(void *ignore)
248 {
249 unsigned int cpu = smp_processor_id();
250 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
251
252 if (smsr->registered)
253 kvm_on_user_return(&smsr->urn);
254 }
255
256 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
257 {
258 return vcpu->arch.apic_base;
259 }
260 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
261
262 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
263 {
264 u64 old_state = vcpu->arch.apic_base &
265 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
266 u64 new_state = msr_info->data &
267 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
268 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
269 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
270
271 if (!msr_info->host_initiated &&
272 ((msr_info->data & reserved_bits) != 0 ||
273 new_state == X2APIC_ENABLE ||
274 (new_state == MSR_IA32_APICBASE_ENABLE &&
275 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
276 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
277 old_state == 0)))
278 return 1;
279
280 kvm_lapic_set_base(vcpu, msr_info->data);
281 return 0;
282 }
283 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
284
285 asmlinkage __visible void kvm_spurious_fault(void)
286 {
287 /* Fault while not rebooting. We want the trace. */
288 BUG();
289 }
290 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
291
292 #define EXCPT_BENIGN 0
293 #define EXCPT_CONTRIBUTORY 1
294 #define EXCPT_PF 2
295
296 static int exception_class(int vector)
297 {
298 switch (vector) {
299 case PF_VECTOR:
300 return EXCPT_PF;
301 case DE_VECTOR:
302 case TS_VECTOR:
303 case NP_VECTOR:
304 case SS_VECTOR:
305 case GP_VECTOR:
306 return EXCPT_CONTRIBUTORY;
307 default:
308 break;
309 }
310 return EXCPT_BENIGN;
311 }
312
313 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
314 unsigned nr, bool has_error, u32 error_code,
315 bool reinject)
316 {
317 u32 prev_nr;
318 int class1, class2;
319
320 kvm_make_request(KVM_REQ_EVENT, vcpu);
321
322 if (!vcpu->arch.exception.pending) {
323 queue:
324 vcpu->arch.exception.pending = true;
325 vcpu->arch.exception.has_error_code = has_error;
326 vcpu->arch.exception.nr = nr;
327 vcpu->arch.exception.error_code = error_code;
328 vcpu->arch.exception.reinject = reinject;
329 return;
330 }
331
332 /* to check exception */
333 prev_nr = vcpu->arch.exception.nr;
334 if (prev_nr == DF_VECTOR) {
335 /* triple fault -> shutdown */
336 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
337 return;
338 }
339 class1 = exception_class(prev_nr);
340 class2 = exception_class(nr);
341 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
342 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
343 /* generate double fault per SDM Table 5-5 */
344 vcpu->arch.exception.pending = true;
345 vcpu->arch.exception.has_error_code = true;
346 vcpu->arch.exception.nr = DF_VECTOR;
347 vcpu->arch.exception.error_code = 0;
348 } else
349 /* replace previous exception with a new one in a hope
350 that instruction re-execution will regenerate lost
351 exception */
352 goto queue;
353 }
354
355 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
356 {
357 kvm_multiple_exception(vcpu, nr, false, 0, false);
358 }
359 EXPORT_SYMBOL_GPL(kvm_queue_exception);
360
361 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
362 {
363 kvm_multiple_exception(vcpu, nr, false, 0, true);
364 }
365 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
366
367 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
368 {
369 if (err)
370 kvm_inject_gp(vcpu, 0);
371 else
372 kvm_x86_ops->skip_emulated_instruction(vcpu);
373 }
374 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
375
376 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
377 {
378 ++vcpu->stat.pf_guest;
379 vcpu->arch.cr2 = fault->address;
380 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
381 }
382 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
383
384 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
385 {
386 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
387 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
388 else
389 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
390 }
391
392 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
393 {
394 atomic_inc(&vcpu->arch.nmi_queued);
395 kvm_make_request(KVM_REQ_NMI, vcpu);
396 }
397 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
398
399 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
400 {
401 kvm_multiple_exception(vcpu, nr, true, error_code, false);
402 }
403 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
404
405 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
406 {
407 kvm_multiple_exception(vcpu, nr, true, error_code, true);
408 }
409 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
410
411 /*
412 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
413 * a #GP and return false.
414 */
415 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
416 {
417 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
418 return true;
419 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
420 return false;
421 }
422 EXPORT_SYMBOL_GPL(kvm_require_cpl);
423
424 /*
425 * This function will be used to read from the physical memory of the currently
426 * running guest. The difference to kvm_read_guest_page is that this function
427 * can read from guest physical or from the guest's guest physical memory.
428 */
429 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
430 gfn_t ngfn, void *data, int offset, int len,
431 u32 access)
432 {
433 gfn_t real_gfn;
434 gpa_t ngpa;
435
436 ngpa = gfn_to_gpa(ngfn);
437 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
438 if (real_gfn == UNMAPPED_GVA)
439 return -EFAULT;
440
441 real_gfn = gpa_to_gfn(real_gfn);
442
443 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
444 }
445 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
446
447 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
448 void *data, int offset, int len, u32 access)
449 {
450 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
451 data, offset, len, access);
452 }
453
454 /*
455 * Load the pae pdptrs. Return true is they are all valid.
456 */
457 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
458 {
459 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
460 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
461 int i;
462 int ret;
463 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
464
465 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
466 offset * sizeof(u64), sizeof(pdpte),
467 PFERR_USER_MASK|PFERR_WRITE_MASK);
468 if (ret < 0) {
469 ret = 0;
470 goto out;
471 }
472 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
473 if (is_present_gpte(pdpte[i]) &&
474 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
475 ret = 0;
476 goto out;
477 }
478 }
479 ret = 1;
480
481 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
482 __set_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_avail);
484 __set_bit(VCPU_EXREG_PDPTR,
485 (unsigned long *)&vcpu->arch.regs_dirty);
486 out:
487
488 return ret;
489 }
490 EXPORT_SYMBOL_GPL(load_pdptrs);
491
492 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
493 {
494 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
495 bool changed = true;
496 int offset;
497 gfn_t gfn;
498 int r;
499
500 if (is_long_mode(vcpu) || !is_pae(vcpu))
501 return false;
502
503 if (!test_bit(VCPU_EXREG_PDPTR,
504 (unsigned long *)&vcpu->arch.regs_avail))
505 return true;
506
507 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
508 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
509 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
510 PFERR_USER_MASK | PFERR_WRITE_MASK);
511 if (r < 0)
512 goto out;
513 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
514 out:
515
516 return changed;
517 }
518
519 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
520 {
521 unsigned long old_cr0 = kvm_read_cr0(vcpu);
522 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
523 X86_CR0_CD | X86_CR0_NW;
524
525 cr0 |= X86_CR0_ET;
526
527 #ifdef CONFIG_X86_64
528 if (cr0 & 0xffffffff00000000UL)
529 return 1;
530 #endif
531
532 cr0 &= ~CR0_RESERVED_BITS;
533
534 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
535 return 1;
536
537 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
538 return 1;
539
540 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
541 #ifdef CONFIG_X86_64
542 if ((vcpu->arch.efer & EFER_LME)) {
543 int cs_db, cs_l;
544
545 if (!is_pae(vcpu))
546 return 1;
547 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
548 if (cs_l)
549 return 1;
550 } else
551 #endif
552 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
553 kvm_read_cr3(vcpu)))
554 return 1;
555 }
556
557 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
558 return 1;
559
560 kvm_x86_ops->set_cr0(vcpu, cr0);
561
562 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
563 kvm_clear_async_pf_completion_queue(vcpu);
564 kvm_async_pf_hash_reset(vcpu);
565 }
566
567 if ((cr0 ^ old_cr0) & update_bits)
568 kvm_mmu_reset_context(vcpu);
569 return 0;
570 }
571 EXPORT_SYMBOL_GPL(kvm_set_cr0);
572
573 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
574 {
575 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
576 }
577 EXPORT_SYMBOL_GPL(kvm_lmsw);
578
579 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
580 {
581 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
582 !vcpu->guest_xcr0_loaded) {
583 /* kvm_set_xcr() also depends on this */
584 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
585 vcpu->guest_xcr0_loaded = 1;
586 }
587 }
588
589 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
590 {
591 if (vcpu->guest_xcr0_loaded) {
592 if (vcpu->arch.xcr0 != host_xcr0)
593 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
594 vcpu->guest_xcr0_loaded = 0;
595 }
596 }
597
598 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
599 {
600 u64 xcr0 = xcr;
601 u64 old_xcr0 = vcpu->arch.xcr0;
602 u64 valid_bits;
603
604 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
605 if (index != XCR_XFEATURE_ENABLED_MASK)
606 return 1;
607 if (!(xcr0 & XSTATE_FP))
608 return 1;
609 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
610 return 1;
611
612 /*
613 * Do not allow the guest to set bits that we do not support
614 * saving. However, xcr0 bit 0 is always set, even if the
615 * emulated CPU does not support XSAVE (see fx_init).
616 */
617 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
618 if (xcr0 & ~valid_bits)
619 return 1;
620
621 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
622 return 1;
623
624 kvm_put_guest_xcr0(vcpu);
625 vcpu->arch.xcr0 = xcr0;
626
627 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
628 kvm_update_cpuid(vcpu);
629 return 0;
630 }
631
632 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
633 {
634 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
635 __kvm_set_xcr(vcpu, index, xcr)) {
636 kvm_inject_gp(vcpu, 0);
637 return 1;
638 }
639 return 0;
640 }
641 EXPORT_SYMBOL_GPL(kvm_set_xcr);
642
643 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
644 {
645 unsigned long old_cr4 = kvm_read_cr4(vcpu);
646 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
647 X86_CR4_PAE | X86_CR4_SMEP;
648 if (cr4 & CR4_RESERVED_BITS)
649 return 1;
650
651 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
652 return 1;
653
654 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
655 return 1;
656
657 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
658 return 1;
659
660 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
661 return 1;
662
663 if (is_long_mode(vcpu)) {
664 if (!(cr4 & X86_CR4_PAE))
665 return 1;
666 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
667 && ((cr4 ^ old_cr4) & pdptr_bits)
668 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
669 kvm_read_cr3(vcpu)))
670 return 1;
671
672 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
673 if (!guest_cpuid_has_pcid(vcpu))
674 return 1;
675
676 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
677 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
678 return 1;
679 }
680
681 if (kvm_x86_ops->set_cr4(vcpu, cr4))
682 return 1;
683
684 if (((cr4 ^ old_cr4) & pdptr_bits) ||
685 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
686 kvm_mmu_reset_context(vcpu);
687
688 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
689 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
690
691 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
692 kvm_update_cpuid(vcpu);
693
694 return 0;
695 }
696 EXPORT_SYMBOL_GPL(kvm_set_cr4);
697
698 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
699 {
700 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
701 kvm_mmu_sync_roots(vcpu);
702 kvm_mmu_flush_tlb(vcpu);
703 return 0;
704 }
705
706 if (is_long_mode(vcpu)) {
707 if (cr3 & CR3_L_MODE_RESERVED_BITS)
708 return 1;
709 } else if (is_pae(vcpu) && is_paging(vcpu) &&
710 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
711 return 1;
712
713 vcpu->arch.cr3 = cr3;
714 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
715 kvm_mmu_new_cr3(vcpu);
716 return 0;
717 }
718 EXPORT_SYMBOL_GPL(kvm_set_cr3);
719
720 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
721 {
722 if (cr8 & CR8_RESERVED_BITS)
723 return 1;
724 if (irqchip_in_kernel(vcpu->kvm))
725 kvm_lapic_set_tpr(vcpu, cr8);
726 else
727 vcpu->arch.cr8 = cr8;
728 return 0;
729 }
730 EXPORT_SYMBOL_GPL(kvm_set_cr8);
731
732 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
733 {
734 if (irqchip_in_kernel(vcpu->kvm))
735 return kvm_lapic_get_cr8(vcpu);
736 else
737 return vcpu->arch.cr8;
738 }
739 EXPORT_SYMBOL_GPL(kvm_get_cr8);
740
741 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
742 {
743 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
744 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
745 }
746
747 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
748 {
749 unsigned long dr7;
750
751 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
752 dr7 = vcpu->arch.guest_debug_dr7;
753 else
754 dr7 = vcpu->arch.dr7;
755 kvm_x86_ops->set_dr7(vcpu, dr7);
756 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
757 if (dr7 & DR7_BP_EN_MASK)
758 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
759 }
760
761 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
762 {
763 switch (dr) {
764 case 0 ... 3:
765 vcpu->arch.db[dr] = val;
766 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
767 vcpu->arch.eff_db[dr] = val;
768 break;
769 case 4:
770 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
771 return 1; /* #UD */
772 /* fall through */
773 case 6:
774 if (val & 0xffffffff00000000ULL)
775 return -1; /* #GP */
776 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
777 kvm_update_dr6(vcpu);
778 break;
779 case 5:
780 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
781 return 1; /* #UD */
782 /* fall through */
783 default: /* 7 */
784 if (val & 0xffffffff00000000ULL)
785 return -1; /* #GP */
786 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
787 kvm_update_dr7(vcpu);
788 break;
789 }
790
791 return 0;
792 }
793
794 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
795 {
796 int res;
797
798 res = __kvm_set_dr(vcpu, dr, val);
799 if (res > 0)
800 kvm_queue_exception(vcpu, UD_VECTOR);
801 else if (res < 0)
802 kvm_inject_gp(vcpu, 0);
803
804 return res;
805 }
806 EXPORT_SYMBOL_GPL(kvm_set_dr);
807
808 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
809 {
810 switch (dr) {
811 case 0 ... 3:
812 *val = vcpu->arch.db[dr];
813 break;
814 case 4:
815 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
816 return 1;
817 /* fall through */
818 case 6:
819 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
820 *val = vcpu->arch.dr6;
821 else
822 *val = kvm_x86_ops->get_dr6(vcpu);
823 break;
824 case 5:
825 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
826 return 1;
827 /* fall through */
828 default: /* 7 */
829 *val = vcpu->arch.dr7;
830 break;
831 }
832
833 return 0;
834 }
835
836 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
837 {
838 if (_kvm_get_dr(vcpu, dr, val)) {
839 kvm_queue_exception(vcpu, UD_VECTOR);
840 return 1;
841 }
842 return 0;
843 }
844 EXPORT_SYMBOL_GPL(kvm_get_dr);
845
846 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
847 {
848 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
849 u64 data;
850 int err;
851
852 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
853 if (err)
854 return err;
855 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
856 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
857 return err;
858 }
859 EXPORT_SYMBOL_GPL(kvm_rdpmc);
860
861 /*
862 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
863 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
864 *
865 * This list is modified at module load time to reflect the
866 * capabilities of the host cpu. This capabilities test skips MSRs that are
867 * kvm-specific. Those are put in the beginning of the list.
868 */
869
870 #define KVM_SAVE_MSRS_BEGIN 12
871 static u32 msrs_to_save[] = {
872 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
873 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
874 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
875 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
876 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
877 MSR_KVM_PV_EOI_EN,
878 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
879 MSR_STAR,
880 #ifdef CONFIG_X86_64
881 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
882 #endif
883 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
884 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
885 };
886
887 static unsigned num_msrs_to_save;
888
889 static const u32 emulated_msrs[] = {
890 MSR_IA32_TSC_ADJUST,
891 MSR_IA32_TSCDEADLINE,
892 MSR_IA32_MISC_ENABLE,
893 MSR_IA32_MCG_STATUS,
894 MSR_IA32_MCG_CTL,
895 };
896
897 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
898 {
899 if (efer & efer_reserved_bits)
900 return false;
901
902 if (efer & EFER_FFXSR) {
903 struct kvm_cpuid_entry2 *feat;
904
905 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
906 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
907 return false;
908 }
909
910 if (efer & EFER_SVME) {
911 struct kvm_cpuid_entry2 *feat;
912
913 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
914 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
915 return false;
916 }
917
918 return true;
919 }
920 EXPORT_SYMBOL_GPL(kvm_valid_efer);
921
922 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
923 {
924 u64 old_efer = vcpu->arch.efer;
925
926 if (!kvm_valid_efer(vcpu, efer))
927 return 1;
928
929 if (is_paging(vcpu)
930 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
931 return 1;
932
933 efer &= ~EFER_LMA;
934 efer |= vcpu->arch.efer & EFER_LMA;
935
936 kvm_x86_ops->set_efer(vcpu, efer);
937
938 /* Update reserved bits */
939 if ((efer ^ old_efer) & EFER_NX)
940 kvm_mmu_reset_context(vcpu);
941
942 return 0;
943 }
944
945 void kvm_enable_efer_bits(u64 mask)
946 {
947 efer_reserved_bits &= ~mask;
948 }
949 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
950
951
952 /*
953 * Writes msr value into into the appropriate "register".
954 * Returns 0 on success, non-0 otherwise.
955 * Assumes vcpu_load() was already called.
956 */
957 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
958 {
959 return kvm_x86_ops->set_msr(vcpu, msr);
960 }
961
962 /*
963 * Adapt set_msr() to msr_io()'s calling convention
964 */
965 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
966 {
967 struct msr_data msr;
968
969 msr.data = *data;
970 msr.index = index;
971 msr.host_initiated = true;
972 return kvm_set_msr(vcpu, &msr);
973 }
974
975 #ifdef CONFIG_X86_64
976 struct pvclock_gtod_data {
977 seqcount_t seq;
978
979 struct { /* extract of a clocksource struct */
980 int vclock_mode;
981 cycle_t cycle_last;
982 cycle_t mask;
983 u32 mult;
984 u32 shift;
985 } clock;
986
987 /* open coded 'struct timespec' */
988 u64 monotonic_time_snsec;
989 time_t monotonic_time_sec;
990 };
991
992 static struct pvclock_gtod_data pvclock_gtod_data;
993
994 static void update_pvclock_gtod(struct timekeeper *tk)
995 {
996 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
997
998 write_seqcount_begin(&vdata->seq);
999
1000 /* copy pvclock gtod data */
1001 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
1002 vdata->clock.cycle_last = tk->clock->cycle_last;
1003 vdata->clock.mask = tk->clock->mask;
1004 vdata->clock.mult = tk->mult;
1005 vdata->clock.shift = tk->shift;
1006
1007 vdata->monotonic_time_sec = tk->xtime_sec
1008 + tk->wall_to_monotonic.tv_sec;
1009 vdata->monotonic_time_snsec = tk->xtime_nsec
1010 + (tk->wall_to_monotonic.tv_nsec
1011 << tk->shift);
1012 while (vdata->monotonic_time_snsec >=
1013 (((u64)NSEC_PER_SEC) << tk->shift)) {
1014 vdata->monotonic_time_snsec -=
1015 ((u64)NSEC_PER_SEC) << tk->shift;
1016 vdata->monotonic_time_sec++;
1017 }
1018
1019 write_seqcount_end(&vdata->seq);
1020 }
1021 #endif
1022
1023
1024 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1025 {
1026 int version;
1027 int r;
1028 struct pvclock_wall_clock wc;
1029 struct timespec boot;
1030
1031 if (!wall_clock)
1032 return;
1033
1034 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1035 if (r)
1036 return;
1037
1038 if (version & 1)
1039 ++version; /* first time write, random junk */
1040
1041 ++version;
1042
1043 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1044
1045 /*
1046 * The guest calculates current wall clock time by adding
1047 * system time (updated by kvm_guest_time_update below) to the
1048 * wall clock specified here. guest system time equals host
1049 * system time for us, thus we must fill in host boot time here.
1050 */
1051 getboottime(&boot);
1052
1053 if (kvm->arch.kvmclock_offset) {
1054 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1055 boot = timespec_sub(boot, ts);
1056 }
1057 wc.sec = boot.tv_sec;
1058 wc.nsec = boot.tv_nsec;
1059 wc.version = version;
1060
1061 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1062
1063 version++;
1064 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1065 }
1066
1067 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1068 {
1069 uint32_t quotient, remainder;
1070
1071 /* Don't try to replace with do_div(), this one calculates
1072 * "(dividend << 32) / divisor" */
1073 __asm__ ( "divl %4"
1074 : "=a" (quotient), "=d" (remainder)
1075 : "0" (0), "1" (dividend), "r" (divisor) );
1076 return quotient;
1077 }
1078
1079 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1080 s8 *pshift, u32 *pmultiplier)
1081 {
1082 uint64_t scaled64;
1083 int32_t shift = 0;
1084 uint64_t tps64;
1085 uint32_t tps32;
1086
1087 tps64 = base_khz * 1000LL;
1088 scaled64 = scaled_khz * 1000LL;
1089 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1090 tps64 >>= 1;
1091 shift--;
1092 }
1093
1094 tps32 = (uint32_t)tps64;
1095 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1096 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1097 scaled64 >>= 1;
1098 else
1099 tps32 <<= 1;
1100 shift++;
1101 }
1102
1103 *pshift = shift;
1104 *pmultiplier = div_frac(scaled64, tps32);
1105
1106 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1107 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1108 }
1109
1110 static inline u64 get_kernel_ns(void)
1111 {
1112 struct timespec ts;
1113
1114 ktime_get_ts(&ts);
1115 monotonic_to_bootbased(&ts);
1116 return timespec_to_ns(&ts);
1117 }
1118
1119 #ifdef CONFIG_X86_64
1120 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1121 #endif
1122
1123 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1124 unsigned long max_tsc_khz;
1125
1126 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1127 {
1128 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1129 vcpu->arch.virtual_tsc_shift);
1130 }
1131
1132 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1133 {
1134 u64 v = (u64)khz * (1000000 + ppm);
1135 do_div(v, 1000000);
1136 return v;
1137 }
1138
1139 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1140 {
1141 u32 thresh_lo, thresh_hi;
1142 int use_scaling = 0;
1143
1144 /* tsc_khz can be zero if TSC calibration fails */
1145 if (this_tsc_khz == 0)
1146 return;
1147
1148 /* Compute a scale to convert nanoseconds in TSC cycles */
1149 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1150 &vcpu->arch.virtual_tsc_shift,
1151 &vcpu->arch.virtual_tsc_mult);
1152 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1153
1154 /*
1155 * Compute the variation in TSC rate which is acceptable
1156 * within the range of tolerance and decide if the
1157 * rate being applied is within that bounds of the hardware
1158 * rate. If so, no scaling or compensation need be done.
1159 */
1160 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1161 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1162 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1163 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1164 use_scaling = 1;
1165 }
1166 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1167 }
1168
1169 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1170 {
1171 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1172 vcpu->arch.virtual_tsc_mult,
1173 vcpu->arch.virtual_tsc_shift);
1174 tsc += vcpu->arch.this_tsc_write;
1175 return tsc;
1176 }
1177
1178 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1179 {
1180 #ifdef CONFIG_X86_64
1181 bool vcpus_matched;
1182 bool do_request = false;
1183 struct kvm_arch *ka = &vcpu->kvm->arch;
1184 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1185
1186 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1187 atomic_read(&vcpu->kvm->online_vcpus));
1188
1189 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1190 if (!ka->use_master_clock)
1191 do_request = 1;
1192
1193 if (!vcpus_matched && ka->use_master_clock)
1194 do_request = 1;
1195
1196 if (do_request)
1197 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1198
1199 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1200 atomic_read(&vcpu->kvm->online_vcpus),
1201 ka->use_master_clock, gtod->clock.vclock_mode);
1202 #endif
1203 }
1204
1205 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1206 {
1207 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1208 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1209 }
1210
1211 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1212 {
1213 struct kvm *kvm = vcpu->kvm;
1214 u64 offset, ns, elapsed;
1215 unsigned long flags;
1216 s64 usdiff;
1217 bool matched;
1218 u64 data = msr->data;
1219
1220 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1221 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1222 ns = get_kernel_ns();
1223 elapsed = ns - kvm->arch.last_tsc_nsec;
1224
1225 if (vcpu->arch.virtual_tsc_khz) {
1226 int faulted = 0;
1227
1228 /* n.b - signed multiplication and division required */
1229 usdiff = data - kvm->arch.last_tsc_write;
1230 #ifdef CONFIG_X86_64
1231 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1232 #else
1233 /* do_div() only does unsigned */
1234 asm("1: idivl %[divisor]\n"
1235 "2: xor %%edx, %%edx\n"
1236 " movl $0, %[faulted]\n"
1237 "3:\n"
1238 ".section .fixup,\"ax\"\n"
1239 "4: movl $1, %[faulted]\n"
1240 " jmp 3b\n"
1241 ".previous\n"
1242
1243 _ASM_EXTABLE(1b, 4b)
1244
1245 : "=A"(usdiff), [faulted] "=r" (faulted)
1246 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1247
1248 #endif
1249 do_div(elapsed, 1000);
1250 usdiff -= elapsed;
1251 if (usdiff < 0)
1252 usdiff = -usdiff;
1253
1254 /* idivl overflow => difference is larger than USEC_PER_SEC */
1255 if (faulted)
1256 usdiff = USEC_PER_SEC;
1257 } else
1258 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1259
1260 /*
1261 * Special case: TSC write with a small delta (1 second) of virtual
1262 * cycle time against real time is interpreted as an attempt to
1263 * synchronize the CPU.
1264 *
1265 * For a reliable TSC, we can match TSC offsets, and for an unstable
1266 * TSC, we add elapsed time in this computation. We could let the
1267 * compensation code attempt to catch up if we fall behind, but
1268 * it's better to try to match offsets from the beginning.
1269 */
1270 if (usdiff < USEC_PER_SEC &&
1271 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1272 if (!check_tsc_unstable()) {
1273 offset = kvm->arch.cur_tsc_offset;
1274 pr_debug("kvm: matched tsc offset for %llu\n", data);
1275 } else {
1276 u64 delta = nsec_to_cycles(vcpu, elapsed);
1277 data += delta;
1278 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1279 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1280 }
1281 matched = true;
1282 } else {
1283 /*
1284 * We split periods of matched TSC writes into generations.
1285 * For each generation, we track the original measured
1286 * nanosecond time, offset, and write, so if TSCs are in
1287 * sync, we can match exact offset, and if not, we can match
1288 * exact software computation in compute_guest_tsc()
1289 *
1290 * These values are tracked in kvm->arch.cur_xxx variables.
1291 */
1292 kvm->arch.cur_tsc_generation++;
1293 kvm->arch.cur_tsc_nsec = ns;
1294 kvm->arch.cur_tsc_write = data;
1295 kvm->arch.cur_tsc_offset = offset;
1296 matched = false;
1297 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1298 kvm->arch.cur_tsc_generation, data);
1299 }
1300
1301 /*
1302 * We also track th most recent recorded KHZ, write and time to
1303 * allow the matching interval to be extended at each write.
1304 */
1305 kvm->arch.last_tsc_nsec = ns;
1306 kvm->arch.last_tsc_write = data;
1307 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1308
1309 vcpu->arch.last_guest_tsc = data;
1310
1311 /* Keep track of which generation this VCPU has synchronized to */
1312 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1313 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1314 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1315
1316 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1317 update_ia32_tsc_adjust_msr(vcpu, offset);
1318 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1319 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1320
1321 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1322 if (matched)
1323 kvm->arch.nr_vcpus_matched_tsc++;
1324 else
1325 kvm->arch.nr_vcpus_matched_tsc = 0;
1326
1327 kvm_track_tsc_matching(vcpu);
1328 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1329 }
1330
1331 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1332
1333 #ifdef CONFIG_X86_64
1334
1335 static cycle_t read_tsc(void)
1336 {
1337 cycle_t ret;
1338 u64 last;
1339
1340 /*
1341 * Empirically, a fence (of type that depends on the CPU)
1342 * before rdtsc is enough to ensure that rdtsc is ordered
1343 * with respect to loads. The various CPU manuals are unclear
1344 * as to whether rdtsc can be reordered with later loads,
1345 * but no one has ever seen it happen.
1346 */
1347 rdtsc_barrier();
1348 ret = (cycle_t)vget_cycles();
1349
1350 last = pvclock_gtod_data.clock.cycle_last;
1351
1352 if (likely(ret >= last))
1353 return ret;
1354
1355 /*
1356 * GCC likes to generate cmov here, but this branch is extremely
1357 * predictable (it's just a funciton of time and the likely is
1358 * very likely) and there's a data dependence, so force GCC
1359 * to generate a branch instead. I don't barrier() because
1360 * we don't actually need a barrier, and if this function
1361 * ever gets inlined it will generate worse code.
1362 */
1363 asm volatile ("");
1364 return last;
1365 }
1366
1367 static inline u64 vgettsc(cycle_t *cycle_now)
1368 {
1369 long v;
1370 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1371
1372 *cycle_now = read_tsc();
1373
1374 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1375 return v * gtod->clock.mult;
1376 }
1377
1378 static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1379 {
1380 unsigned long seq;
1381 u64 ns;
1382 int mode;
1383 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1384
1385 ts->tv_nsec = 0;
1386 do {
1387 seq = read_seqcount_begin(&gtod->seq);
1388 mode = gtod->clock.vclock_mode;
1389 ts->tv_sec = gtod->monotonic_time_sec;
1390 ns = gtod->monotonic_time_snsec;
1391 ns += vgettsc(cycle_now);
1392 ns >>= gtod->clock.shift;
1393 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1394 timespec_add_ns(ts, ns);
1395
1396 return mode;
1397 }
1398
1399 /* returns true if host is using tsc clocksource */
1400 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1401 {
1402 struct timespec ts;
1403
1404 /* checked again under seqlock below */
1405 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1406 return false;
1407
1408 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1409 return false;
1410
1411 monotonic_to_bootbased(&ts);
1412 *kernel_ns = timespec_to_ns(&ts);
1413
1414 return true;
1415 }
1416 #endif
1417
1418 /*
1419 *
1420 * Assuming a stable TSC across physical CPUS, and a stable TSC
1421 * across virtual CPUs, the following condition is possible.
1422 * Each numbered line represents an event visible to both
1423 * CPUs at the next numbered event.
1424 *
1425 * "timespecX" represents host monotonic time. "tscX" represents
1426 * RDTSC value.
1427 *
1428 * VCPU0 on CPU0 | VCPU1 on CPU1
1429 *
1430 * 1. read timespec0,tsc0
1431 * 2. | timespec1 = timespec0 + N
1432 * | tsc1 = tsc0 + M
1433 * 3. transition to guest | transition to guest
1434 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1435 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1436 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1437 *
1438 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1439 *
1440 * - ret0 < ret1
1441 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1442 * ...
1443 * - 0 < N - M => M < N
1444 *
1445 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1446 * always the case (the difference between two distinct xtime instances
1447 * might be smaller then the difference between corresponding TSC reads,
1448 * when updating guest vcpus pvclock areas).
1449 *
1450 * To avoid that problem, do not allow visibility of distinct
1451 * system_timestamp/tsc_timestamp values simultaneously: use a master
1452 * copy of host monotonic time values. Update that master copy
1453 * in lockstep.
1454 *
1455 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1456 *
1457 */
1458
1459 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1460 {
1461 #ifdef CONFIG_X86_64
1462 struct kvm_arch *ka = &kvm->arch;
1463 int vclock_mode;
1464 bool host_tsc_clocksource, vcpus_matched;
1465
1466 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1467 atomic_read(&kvm->online_vcpus));
1468
1469 /*
1470 * If the host uses TSC clock, then passthrough TSC as stable
1471 * to the guest.
1472 */
1473 host_tsc_clocksource = kvm_get_time_and_clockread(
1474 &ka->master_kernel_ns,
1475 &ka->master_cycle_now);
1476
1477 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1478 && !backwards_tsc_observed;
1479
1480 if (ka->use_master_clock)
1481 atomic_set(&kvm_guest_has_master_clock, 1);
1482
1483 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1484 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1485 vcpus_matched);
1486 #endif
1487 }
1488
1489 static void kvm_gen_update_masterclock(struct kvm *kvm)
1490 {
1491 #ifdef CONFIG_X86_64
1492 int i;
1493 struct kvm_vcpu *vcpu;
1494 struct kvm_arch *ka = &kvm->arch;
1495
1496 spin_lock(&ka->pvclock_gtod_sync_lock);
1497 kvm_make_mclock_inprogress_request(kvm);
1498 /* no guest entries from this point */
1499 pvclock_update_vm_gtod_copy(kvm);
1500
1501 kvm_for_each_vcpu(i, vcpu, kvm)
1502 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1503
1504 /* guest entries allowed */
1505 kvm_for_each_vcpu(i, vcpu, kvm)
1506 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1507
1508 spin_unlock(&ka->pvclock_gtod_sync_lock);
1509 #endif
1510 }
1511
1512 static int kvm_guest_time_update(struct kvm_vcpu *v)
1513 {
1514 unsigned long flags, this_tsc_khz;
1515 struct kvm_vcpu_arch *vcpu = &v->arch;
1516 struct kvm_arch *ka = &v->kvm->arch;
1517 s64 kernel_ns;
1518 u64 tsc_timestamp, host_tsc;
1519 struct pvclock_vcpu_time_info guest_hv_clock;
1520 u8 pvclock_flags;
1521 bool use_master_clock;
1522
1523 kernel_ns = 0;
1524 host_tsc = 0;
1525
1526 /*
1527 * If the host uses TSC clock, then passthrough TSC as stable
1528 * to the guest.
1529 */
1530 spin_lock(&ka->pvclock_gtod_sync_lock);
1531 use_master_clock = ka->use_master_clock;
1532 if (use_master_clock) {
1533 host_tsc = ka->master_cycle_now;
1534 kernel_ns = ka->master_kernel_ns;
1535 }
1536 spin_unlock(&ka->pvclock_gtod_sync_lock);
1537
1538 /* Keep irq disabled to prevent changes to the clock */
1539 local_irq_save(flags);
1540 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1541 if (unlikely(this_tsc_khz == 0)) {
1542 local_irq_restore(flags);
1543 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1544 return 1;
1545 }
1546 if (!use_master_clock) {
1547 host_tsc = native_read_tsc();
1548 kernel_ns = get_kernel_ns();
1549 }
1550
1551 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1552
1553 /*
1554 * We may have to catch up the TSC to match elapsed wall clock
1555 * time for two reasons, even if kvmclock is used.
1556 * 1) CPU could have been running below the maximum TSC rate
1557 * 2) Broken TSC compensation resets the base at each VCPU
1558 * entry to avoid unknown leaps of TSC even when running
1559 * again on the same CPU. This may cause apparent elapsed
1560 * time to disappear, and the guest to stand still or run
1561 * very slowly.
1562 */
1563 if (vcpu->tsc_catchup) {
1564 u64 tsc = compute_guest_tsc(v, kernel_ns);
1565 if (tsc > tsc_timestamp) {
1566 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1567 tsc_timestamp = tsc;
1568 }
1569 }
1570
1571 local_irq_restore(flags);
1572
1573 if (!vcpu->pv_time_enabled)
1574 return 0;
1575
1576 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1577 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1578 &vcpu->hv_clock.tsc_shift,
1579 &vcpu->hv_clock.tsc_to_system_mul);
1580 vcpu->hw_tsc_khz = this_tsc_khz;
1581 }
1582
1583 /* With all the info we got, fill in the values */
1584 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1585 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1586 vcpu->last_guest_tsc = tsc_timestamp;
1587
1588 /*
1589 * The interface expects us to write an even number signaling that the
1590 * update is finished. Since the guest won't see the intermediate
1591 * state, we just increase by 2 at the end.
1592 */
1593 vcpu->hv_clock.version += 2;
1594
1595 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1596 &guest_hv_clock, sizeof(guest_hv_clock))))
1597 return 0;
1598
1599 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1600 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1601
1602 if (vcpu->pvclock_set_guest_stopped_request) {
1603 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1604 vcpu->pvclock_set_guest_stopped_request = false;
1605 }
1606
1607 /* If the host uses TSC clocksource, then it is stable */
1608 if (use_master_clock)
1609 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1610
1611 vcpu->hv_clock.flags = pvclock_flags;
1612
1613 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1614 &vcpu->hv_clock,
1615 sizeof(vcpu->hv_clock));
1616 return 0;
1617 }
1618
1619 /*
1620 * kvmclock updates which are isolated to a given vcpu, such as
1621 * vcpu->cpu migration, should not allow system_timestamp from
1622 * the rest of the vcpus to remain static. Otherwise ntp frequency
1623 * correction applies to one vcpu's system_timestamp but not
1624 * the others.
1625 *
1626 * So in those cases, request a kvmclock update for all vcpus.
1627 * We need to rate-limit these requests though, as they can
1628 * considerably slow guests that have a large number of vcpus.
1629 * The time for a remote vcpu to update its kvmclock is bound
1630 * by the delay we use to rate-limit the updates.
1631 */
1632
1633 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1634
1635 static void kvmclock_update_fn(struct work_struct *work)
1636 {
1637 int i;
1638 struct delayed_work *dwork = to_delayed_work(work);
1639 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1640 kvmclock_update_work);
1641 struct kvm *kvm = container_of(ka, struct kvm, arch);
1642 struct kvm_vcpu *vcpu;
1643
1644 kvm_for_each_vcpu(i, vcpu, kvm) {
1645 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1646 kvm_vcpu_kick(vcpu);
1647 }
1648 }
1649
1650 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1651 {
1652 struct kvm *kvm = v->kvm;
1653
1654 set_bit(KVM_REQ_CLOCK_UPDATE, &v->requests);
1655 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1656 KVMCLOCK_UPDATE_DELAY);
1657 }
1658
1659 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1660
1661 static void kvmclock_sync_fn(struct work_struct *work)
1662 {
1663 struct delayed_work *dwork = to_delayed_work(work);
1664 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1665 kvmclock_sync_work);
1666 struct kvm *kvm = container_of(ka, struct kvm, arch);
1667
1668 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1669 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1670 KVMCLOCK_SYNC_PERIOD);
1671 }
1672
1673 static bool msr_mtrr_valid(unsigned msr)
1674 {
1675 switch (msr) {
1676 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1677 case MSR_MTRRfix64K_00000:
1678 case MSR_MTRRfix16K_80000:
1679 case MSR_MTRRfix16K_A0000:
1680 case MSR_MTRRfix4K_C0000:
1681 case MSR_MTRRfix4K_C8000:
1682 case MSR_MTRRfix4K_D0000:
1683 case MSR_MTRRfix4K_D8000:
1684 case MSR_MTRRfix4K_E0000:
1685 case MSR_MTRRfix4K_E8000:
1686 case MSR_MTRRfix4K_F0000:
1687 case MSR_MTRRfix4K_F8000:
1688 case MSR_MTRRdefType:
1689 case MSR_IA32_CR_PAT:
1690 return true;
1691 case 0x2f8:
1692 return true;
1693 }
1694 return false;
1695 }
1696
1697 static bool valid_pat_type(unsigned t)
1698 {
1699 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1700 }
1701
1702 static bool valid_mtrr_type(unsigned t)
1703 {
1704 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1705 }
1706
1707 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1708 {
1709 int i;
1710
1711 if (!msr_mtrr_valid(msr))
1712 return false;
1713
1714 if (msr == MSR_IA32_CR_PAT) {
1715 for (i = 0; i < 8; i++)
1716 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1717 return false;
1718 return true;
1719 } else if (msr == MSR_MTRRdefType) {
1720 if (data & ~0xcff)
1721 return false;
1722 return valid_mtrr_type(data & 0xff);
1723 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1724 for (i = 0; i < 8 ; i++)
1725 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1726 return false;
1727 return true;
1728 }
1729
1730 /* variable MTRRs */
1731 return valid_mtrr_type(data & 0xff);
1732 }
1733
1734 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1735 {
1736 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1737
1738 if (!mtrr_valid(vcpu, msr, data))
1739 return 1;
1740
1741 if (msr == MSR_MTRRdefType) {
1742 vcpu->arch.mtrr_state.def_type = data;
1743 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1744 } else if (msr == MSR_MTRRfix64K_00000)
1745 p[0] = data;
1746 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1747 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1748 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1749 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1750 else if (msr == MSR_IA32_CR_PAT)
1751 vcpu->arch.pat = data;
1752 else { /* Variable MTRRs */
1753 int idx, is_mtrr_mask;
1754 u64 *pt;
1755
1756 idx = (msr - 0x200) / 2;
1757 is_mtrr_mask = msr - 0x200 - 2 * idx;
1758 if (!is_mtrr_mask)
1759 pt =
1760 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1761 else
1762 pt =
1763 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1764 *pt = data;
1765 }
1766
1767 kvm_mmu_reset_context(vcpu);
1768 return 0;
1769 }
1770
1771 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1772 {
1773 u64 mcg_cap = vcpu->arch.mcg_cap;
1774 unsigned bank_num = mcg_cap & 0xff;
1775
1776 switch (msr) {
1777 case MSR_IA32_MCG_STATUS:
1778 vcpu->arch.mcg_status = data;
1779 break;
1780 case MSR_IA32_MCG_CTL:
1781 if (!(mcg_cap & MCG_CTL_P))
1782 return 1;
1783 if (data != 0 && data != ~(u64)0)
1784 return -1;
1785 vcpu->arch.mcg_ctl = data;
1786 break;
1787 default:
1788 if (msr >= MSR_IA32_MC0_CTL &&
1789 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1790 u32 offset = msr - MSR_IA32_MC0_CTL;
1791 /* only 0 or all 1s can be written to IA32_MCi_CTL
1792 * some Linux kernels though clear bit 10 in bank 4 to
1793 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1794 * this to avoid an uncatched #GP in the guest
1795 */
1796 if ((offset & 0x3) == 0 &&
1797 data != 0 && (data | (1 << 10)) != ~(u64)0)
1798 return -1;
1799 vcpu->arch.mce_banks[offset] = data;
1800 break;
1801 }
1802 return 1;
1803 }
1804 return 0;
1805 }
1806
1807 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1808 {
1809 struct kvm *kvm = vcpu->kvm;
1810 int lm = is_long_mode(vcpu);
1811 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1812 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1813 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1814 : kvm->arch.xen_hvm_config.blob_size_32;
1815 u32 page_num = data & ~PAGE_MASK;
1816 u64 page_addr = data & PAGE_MASK;
1817 u8 *page;
1818 int r;
1819
1820 r = -E2BIG;
1821 if (page_num >= blob_size)
1822 goto out;
1823 r = -ENOMEM;
1824 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1825 if (IS_ERR(page)) {
1826 r = PTR_ERR(page);
1827 goto out;
1828 }
1829 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1830 goto out_free;
1831 r = 0;
1832 out_free:
1833 kfree(page);
1834 out:
1835 return r;
1836 }
1837
1838 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1839 {
1840 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1841 }
1842
1843 static bool kvm_hv_msr_partition_wide(u32 msr)
1844 {
1845 bool r = false;
1846 switch (msr) {
1847 case HV_X64_MSR_GUEST_OS_ID:
1848 case HV_X64_MSR_HYPERCALL:
1849 case HV_X64_MSR_REFERENCE_TSC:
1850 case HV_X64_MSR_TIME_REF_COUNT:
1851 r = true;
1852 break;
1853 }
1854
1855 return r;
1856 }
1857
1858 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1859 {
1860 struct kvm *kvm = vcpu->kvm;
1861
1862 switch (msr) {
1863 case HV_X64_MSR_GUEST_OS_ID:
1864 kvm->arch.hv_guest_os_id = data;
1865 /* setting guest os id to zero disables hypercall page */
1866 if (!kvm->arch.hv_guest_os_id)
1867 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1868 break;
1869 case HV_X64_MSR_HYPERCALL: {
1870 u64 gfn;
1871 unsigned long addr;
1872 u8 instructions[4];
1873
1874 /* if guest os id is not set hypercall should remain disabled */
1875 if (!kvm->arch.hv_guest_os_id)
1876 break;
1877 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1878 kvm->arch.hv_hypercall = data;
1879 break;
1880 }
1881 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1882 addr = gfn_to_hva(kvm, gfn);
1883 if (kvm_is_error_hva(addr))
1884 return 1;
1885 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1886 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1887 if (__copy_to_user((void __user *)addr, instructions, 4))
1888 return 1;
1889 kvm->arch.hv_hypercall = data;
1890 mark_page_dirty(kvm, gfn);
1891 break;
1892 }
1893 case HV_X64_MSR_REFERENCE_TSC: {
1894 u64 gfn;
1895 HV_REFERENCE_TSC_PAGE tsc_ref;
1896 memset(&tsc_ref, 0, sizeof(tsc_ref));
1897 kvm->arch.hv_tsc_page = data;
1898 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1899 break;
1900 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1901 if (kvm_write_guest(kvm, data,
1902 &tsc_ref, sizeof(tsc_ref)))
1903 return 1;
1904 mark_page_dirty(kvm, gfn);
1905 break;
1906 }
1907 default:
1908 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1909 "data 0x%llx\n", msr, data);
1910 return 1;
1911 }
1912 return 0;
1913 }
1914
1915 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1916 {
1917 switch (msr) {
1918 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1919 u64 gfn;
1920 unsigned long addr;
1921
1922 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1923 vcpu->arch.hv_vapic = data;
1924 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
1925 return 1;
1926 break;
1927 }
1928 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1929 addr = gfn_to_hva(vcpu->kvm, gfn);
1930 if (kvm_is_error_hva(addr))
1931 return 1;
1932 if (__clear_user((void __user *)addr, PAGE_SIZE))
1933 return 1;
1934 vcpu->arch.hv_vapic = data;
1935 mark_page_dirty(vcpu->kvm, gfn);
1936 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
1937 return 1;
1938 break;
1939 }
1940 case HV_X64_MSR_EOI:
1941 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1942 case HV_X64_MSR_ICR:
1943 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1944 case HV_X64_MSR_TPR:
1945 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1946 default:
1947 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1948 "data 0x%llx\n", msr, data);
1949 return 1;
1950 }
1951
1952 return 0;
1953 }
1954
1955 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1956 {
1957 gpa_t gpa = data & ~0x3f;
1958
1959 /* Bits 2:5 are reserved, Should be zero */
1960 if (data & 0x3c)
1961 return 1;
1962
1963 vcpu->arch.apf.msr_val = data;
1964
1965 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1966 kvm_clear_async_pf_completion_queue(vcpu);
1967 kvm_async_pf_hash_reset(vcpu);
1968 return 0;
1969 }
1970
1971 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1972 sizeof(u32)))
1973 return 1;
1974
1975 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1976 kvm_async_pf_wakeup_all(vcpu);
1977 return 0;
1978 }
1979
1980 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1981 {
1982 vcpu->arch.pv_time_enabled = false;
1983 }
1984
1985 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1986 {
1987 u64 delta;
1988
1989 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1990 return;
1991
1992 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1993 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1994 vcpu->arch.st.accum_steal = delta;
1995 }
1996
1997 static void record_steal_time(struct kvm_vcpu *vcpu)
1998 {
1999 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2000 return;
2001
2002 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2003 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2004 return;
2005
2006 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2007 vcpu->arch.st.steal.version += 2;
2008 vcpu->arch.st.accum_steal = 0;
2009
2010 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2011 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2012 }
2013
2014 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2015 {
2016 bool pr = false;
2017 u32 msr = msr_info->index;
2018 u64 data = msr_info->data;
2019
2020 switch (msr) {
2021 case MSR_AMD64_NB_CFG:
2022 case MSR_IA32_UCODE_REV:
2023 case MSR_IA32_UCODE_WRITE:
2024 case MSR_VM_HSAVE_PA:
2025 case MSR_AMD64_PATCH_LOADER:
2026 case MSR_AMD64_BU_CFG2:
2027 break;
2028
2029 case MSR_EFER:
2030 return set_efer(vcpu, data);
2031 case MSR_K7_HWCR:
2032 data &= ~(u64)0x40; /* ignore flush filter disable */
2033 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2034 data &= ~(u64)0x8; /* ignore TLB cache disable */
2035 if (data != 0) {
2036 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2037 data);
2038 return 1;
2039 }
2040 break;
2041 case MSR_FAM10H_MMIO_CONF_BASE:
2042 if (data != 0) {
2043 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2044 "0x%llx\n", data);
2045 return 1;
2046 }
2047 break;
2048 case MSR_IA32_DEBUGCTLMSR:
2049 if (!data) {
2050 /* We support the non-activated case already */
2051 break;
2052 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2053 /* Values other than LBR and BTF are vendor-specific,
2054 thus reserved and should throw a #GP */
2055 return 1;
2056 }
2057 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2058 __func__, data);
2059 break;
2060 case 0x200 ... 0x2ff:
2061 return set_msr_mtrr(vcpu, msr, data);
2062 case MSR_IA32_APICBASE:
2063 return kvm_set_apic_base(vcpu, msr_info);
2064 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2065 return kvm_x2apic_msr_write(vcpu, msr, data);
2066 case MSR_IA32_TSCDEADLINE:
2067 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2068 break;
2069 case MSR_IA32_TSC_ADJUST:
2070 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2071 if (!msr_info->host_initiated) {
2072 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2073 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2074 }
2075 vcpu->arch.ia32_tsc_adjust_msr = data;
2076 }
2077 break;
2078 case MSR_IA32_MISC_ENABLE:
2079 vcpu->arch.ia32_misc_enable_msr = data;
2080 break;
2081 case MSR_KVM_WALL_CLOCK_NEW:
2082 case MSR_KVM_WALL_CLOCK:
2083 vcpu->kvm->arch.wall_clock = data;
2084 kvm_write_wall_clock(vcpu->kvm, data);
2085 break;
2086 case MSR_KVM_SYSTEM_TIME_NEW:
2087 case MSR_KVM_SYSTEM_TIME: {
2088 u64 gpa_offset;
2089 kvmclock_reset(vcpu);
2090
2091 vcpu->arch.time = data;
2092 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2093
2094 /* we verify if the enable bit is set... */
2095 if (!(data & 1))
2096 break;
2097
2098 gpa_offset = data & ~(PAGE_MASK | 1);
2099
2100 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2101 &vcpu->arch.pv_time, data & ~1ULL,
2102 sizeof(struct pvclock_vcpu_time_info)))
2103 vcpu->arch.pv_time_enabled = false;
2104 else
2105 vcpu->arch.pv_time_enabled = true;
2106
2107 break;
2108 }
2109 case MSR_KVM_ASYNC_PF_EN:
2110 if (kvm_pv_enable_async_pf(vcpu, data))
2111 return 1;
2112 break;
2113 case MSR_KVM_STEAL_TIME:
2114
2115 if (unlikely(!sched_info_on()))
2116 return 1;
2117
2118 if (data & KVM_STEAL_RESERVED_MASK)
2119 return 1;
2120
2121 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2122 data & KVM_STEAL_VALID_BITS,
2123 sizeof(struct kvm_steal_time)))
2124 return 1;
2125
2126 vcpu->arch.st.msr_val = data;
2127
2128 if (!(data & KVM_MSR_ENABLED))
2129 break;
2130
2131 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2132
2133 preempt_disable();
2134 accumulate_steal_time(vcpu);
2135 preempt_enable();
2136
2137 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2138
2139 break;
2140 case MSR_KVM_PV_EOI_EN:
2141 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2142 return 1;
2143 break;
2144
2145 case MSR_IA32_MCG_CTL:
2146 case MSR_IA32_MCG_STATUS:
2147 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2148 return set_msr_mce(vcpu, msr, data);
2149
2150 /* Performance counters are not protected by a CPUID bit,
2151 * so we should check all of them in the generic path for the sake of
2152 * cross vendor migration.
2153 * Writing a zero into the event select MSRs disables them,
2154 * which we perfectly emulate ;-). Any other value should be at least
2155 * reported, some guests depend on them.
2156 */
2157 case MSR_K7_EVNTSEL0:
2158 case MSR_K7_EVNTSEL1:
2159 case MSR_K7_EVNTSEL2:
2160 case MSR_K7_EVNTSEL3:
2161 if (data != 0)
2162 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2163 "0x%x data 0x%llx\n", msr, data);
2164 break;
2165 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2166 * so we ignore writes to make it happy.
2167 */
2168 case MSR_K7_PERFCTR0:
2169 case MSR_K7_PERFCTR1:
2170 case MSR_K7_PERFCTR2:
2171 case MSR_K7_PERFCTR3:
2172 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2173 "0x%x data 0x%llx\n", msr, data);
2174 break;
2175 case MSR_P6_PERFCTR0:
2176 case MSR_P6_PERFCTR1:
2177 pr = true;
2178 case MSR_P6_EVNTSEL0:
2179 case MSR_P6_EVNTSEL1:
2180 if (kvm_pmu_msr(vcpu, msr))
2181 return kvm_pmu_set_msr(vcpu, msr_info);
2182
2183 if (pr || data != 0)
2184 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2185 "0x%x data 0x%llx\n", msr, data);
2186 break;
2187 case MSR_K7_CLK_CTL:
2188 /*
2189 * Ignore all writes to this no longer documented MSR.
2190 * Writes are only relevant for old K7 processors,
2191 * all pre-dating SVM, but a recommended workaround from
2192 * AMD for these chips. It is possible to specify the
2193 * affected processor models on the command line, hence
2194 * the need to ignore the workaround.
2195 */
2196 break;
2197 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2198 if (kvm_hv_msr_partition_wide(msr)) {
2199 int r;
2200 mutex_lock(&vcpu->kvm->lock);
2201 r = set_msr_hyperv_pw(vcpu, msr, data);
2202 mutex_unlock(&vcpu->kvm->lock);
2203 return r;
2204 } else
2205 return set_msr_hyperv(vcpu, msr, data);
2206 break;
2207 case MSR_IA32_BBL_CR_CTL3:
2208 /* Drop writes to this legacy MSR -- see rdmsr
2209 * counterpart for further detail.
2210 */
2211 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2212 break;
2213 case MSR_AMD64_OSVW_ID_LENGTH:
2214 if (!guest_cpuid_has_osvw(vcpu))
2215 return 1;
2216 vcpu->arch.osvw.length = data;
2217 break;
2218 case MSR_AMD64_OSVW_STATUS:
2219 if (!guest_cpuid_has_osvw(vcpu))
2220 return 1;
2221 vcpu->arch.osvw.status = data;
2222 break;
2223 default:
2224 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2225 return xen_hvm_config(vcpu, data);
2226 if (kvm_pmu_msr(vcpu, msr))
2227 return kvm_pmu_set_msr(vcpu, msr_info);
2228 if (!ignore_msrs) {
2229 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2230 msr, data);
2231 return 1;
2232 } else {
2233 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2234 msr, data);
2235 break;
2236 }
2237 }
2238 return 0;
2239 }
2240 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2241
2242
2243 /*
2244 * Reads an msr value (of 'msr_index') into 'pdata'.
2245 * Returns 0 on success, non-0 otherwise.
2246 * Assumes vcpu_load() was already called.
2247 */
2248 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2249 {
2250 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2251 }
2252
2253 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2254 {
2255 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2256
2257 if (!msr_mtrr_valid(msr))
2258 return 1;
2259
2260 if (msr == MSR_MTRRdefType)
2261 *pdata = vcpu->arch.mtrr_state.def_type +
2262 (vcpu->arch.mtrr_state.enabled << 10);
2263 else if (msr == MSR_MTRRfix64K_00000)
2264 *pdata = p[0];
2265 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2266 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2267 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2268 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2269 else if (msr == MSR_IA32_CR_PAT)
2270 *pdata = vcpu->arch.pat;
2271 else { /* Variable MTRRs */
2272 int idx, is_mtrr_mask;
2273 u64 *pt;
2274
2275 idx = (msr - 0x200) / 2;
2276 is_mtrr_mask = msr - 0x200 - 2 * idx;
2277 if (!is_mtrr_mask)
2278 pt =
2279 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2280 else
2281 pt =
2282 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2283 *pdata = *pt;
2284 }
2285
2286 return 0;
2287 }
2288
2289 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2290 {
2291 u64 data;
2292 u64 mcg_cap = vcpu->arch.mcg_cap;
2293 unsigned bank_num = mcg_cap & 0xff;
2294
2295 switch (msr) {
2296 case MSR_IA32_P5_MC_ADDR:
2297 case MSR_IA32_P5_MC_TYPE:
2298 data = 0;
2299 break;
2300 case MSR_IA32_MCG_CAP:
2301 data = vcpu->arch.mcg_cap;
2302 break;
2303 case MSR_IA32_MCG_CTL:
2304 if (!(mcg_cap & MCG_CTL_P))
2305 return 1;
2306 data = vcpu->arch.mcg_ctl;
2307 break;
2308 case MSR_IA32_MCG_STATUS:
2309 data = vcpu->arch.mcg_status;
2310 break;
2311 default:
2312 if (msr >= MSR_IA32_MC0_CTL &&
2313 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2314 u32 offset = msr - MSR_IA32_MC0_CTL;
2315 data = vcpu->arch.mce_banks[offset];
2316 break;
2317 }
2318 return 1;
2319 }
2320 *pdata = data;
2321 return 0;
2322 }
2323
2324 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2325 {
2326 u64 data = 0;
2327 struct kvm *kvm = vcpu->kvm;
2328
2329 switch (msr) {
2330 case HV_X64_MSR_GUEST_OS_ID:
2331 data = kvm->arch.hv_guest_os_id;
2332 break;
2333 case HV_X64_MSR_HYPERCALL:
2334 data = kvm->arch.hv_hypercall;
2335 break;
2336 case HV_X64_MSR_TIME_REF_COUNT: {
2337 data =
2338 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2339 break;
2340 }
2341 case HV_X64_MSR_REFERENCE_TSC:
2342 data = kvm->arch.hv_tsc_page;
2343 break;
2344 default:
2345 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2346 return 1;
2347 }
2348
2349 *pdata = data;
2350 return 0;
2351 }
2352
2353 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2354 {
2355 u64 data = 0;
2356
2357 switch (msr) {
2358 case HV_X64_MSR_VP_INDEX: {
2359 int r;
2360 struct kvm_vcpu *v;
2361 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2362 if (v == vcpu) {
2363 data = r;
2364 break;
2365 }
2366 }
2367 break;
2368 }
2369 case HV_X64_MSR_EOI:
2370 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2371 case HV_X64_MSR_ICR:
2372 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2373 case HV_X64_MSR_TPR:
2374 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2375 case HV_X64_MSR_APIC_ASSIST_PAGE:
2376 data = vcpu->arch.hv_vapic;
2377 break;
2378 default:
2379 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2380 return 1;
2381 }
2382 *pdata = data;
2383 return 0;
2384 }
2385
2386 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2387 {
2388 u64 data;
2389
2390 switch (msr) {
2391 case MSR_IA32_PLATFORM_ID:
2392 case MSR_IA32_EBL_CR_POWERON:
2393 case MSR_IA32_DEBUGCTLMSR:
2394 case MSR_IA32_LASTBRANCHFROMIP:
2395 case MSR_IA32_LASTBRANCHTOIP:
2396 case MSR_IA32_LASTINTFROMIP:
2397 case MSR_IA32_LASTINTTOIP:
2398 case MSR_K8_SYSCFG:
2399 case MSR_K7_HWCR:
2400 case MSR_VM_HSAVE_PA:
2401 case MSR_K7_EVNTSEL0:
2402 case MSR_K7_PERFCTR0:
2403 case MSR_K8_INT_PENDING_MSG:
2404 case MSR_AMD64_NB_CFG:
2405 case MSR_FAM10H_MMIO_CONF_BASE:
2406 case MSR_AMD64_BU_CFG2:
2407 data = 0;
2408 break;
2409 case MSR_P6_PERFCTR0:
2410 case MSR_P6_PERFCTR1:
2411 case MSR_P6_EVNTSEL0:
2412 case MSR_P6_EVNTSEL1:
2413 if (kvm_pmu_msr(vcpu, msr))
2414 return kvm_pmu_get_msr(vcpu, msr, pdata);
2415 data = 0;
2416 break;
2417 case MSR_IA32_UCODE_REV:
2418 data = 0x100000000ULL;
2419 break;
2420 case MSR_MTRRcap:
2421 data = 0x500 | KVM_NR_VAR_MTRR;
2422 break;
2423 case 0x200 ... 0x2ff:
2424 return get_msr_mtrr(vcpu, msr, pdata);
2425 case 0xcd: /* fsb frequency */
2426 data = 3;
2427 break;
2428 /*
2429 * MSR_EBC_FREQUENCY_ID
2430 * Conservative value valid for even the basic CPU models.
2431 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2432 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2433 * and 266MHz for model 3, or 4. Set Core Clock
2434 * Frequency to System Bus Frequency Ratio to 1 (bits
2435 * 31:24) even though these are only valid for CPU
2436 * models > 2, however guests may end up dividing or
2437 * multiplying by zero otherwise.
2438 */
2439 case MSR_EBC_FREQUENCY_ID:
2440 data = 1 << 24;
2441 break;
2442 case MSR_IA32_APICBASE:
2443 data = kvm_get_apic_base(vcpu);
2444 break;
2445 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2446 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2447 break;
2448 case MSR_IA32_TSCDEADLINE:
2449 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2450 break;
2451 case MSR_IA32_TSC_ADJUST:
2452 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2453 break;
2454 case MSR_IA32_MISC_ENABLE:
2455 data = vcpu->arch.ia32_misc_enable_msr;
2456 break;
2457 case MSR_IA32_PERF_STATUS:
2458 /* TSC increment by tick */
2459 data = 1000ULL;
2460 /* CPU multiplier */
2461 data |= (((uint64_t)4ULL) << 40);
2462 break;
2463 case MSR_EFER:
2464 data = vcpu->arch.efer;
2465 break;
2466 case MSR_KVM_WALL_CLOCK:
2467 case MSR_KVM_WALL_CLOCK_NEW:
2468 data = vcpu->kvm->arch.wall_clock;
2469 break;
2470 case MSR_KVM_SYSTEM_TIME:
2471 case MSR_KVM_SYSTEM_TIME_NEW:
2472 data = vcpu->arch.time;
2473 break;
2474 case MSR_KVM_ASYNC_PF_EN:
2475 data = vcpu->arch.apf.msr_val;
2476 break;
2477 case MSR_KVM_STEAL_TIME:
2478 data = vcpu->arch.st.msr_val;
2479 break;
2480 case MSR_KVM_PV_EOI_EN:
2481 data = vcpu->arch.pv_eoi.msr_val;
2482 break;
2483 case MSR_IA32_P5_MC_ADDR:
2484 case MSR_IA32_P5_MC_TYPE:
2485 case MSR_IA32_MCG_CAP:
2486 case MSR_IA32_MCG_CTL:
2487 case MSR_IA32_MCG_STATUS:
2488 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2489 return get_msr_mce(vcpu, msr, pdata);
2490 case MSR_K7_CLK_CTL:
2491 /*
2492 * Provide expected ramp-up count for K7. All other
2493 * are set to zero, indicating minimum divisors for
2494 * every field.
2495 *
2496 * This prevents guest kernels on AMD host with CPU
2497 * type 6, model 8 and higher from exploding due to
2498 * the rdmsr failing.
2499 */
2500 data = 0x20000000;
2501 break;
2502 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2503 if (kvm_hv_msr_partition_wide(msr)) {
2504 int r;
2505 mutex_lock(&vcpu->kvm->lock);
2506 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2507 mutex_unlock(&vcpu->kvm->lock);
2508 return r;
2509 } else
2510 return get_msr_hyperv(vcpu, msr, pdata);
2511 break;
2512 case MSR_IA32_BBL_CR_CTL3:
2513 /* This legacy MSR exists but isn't fully documented in current
2514 * silicon. It is however accessed by winxp in very narrow
2515 * scenarios where it sets bit #19, itself documented as
2516 * a "reserved" bit. Best effort attempt to source coherent
2517 * read data here should the balance of the register be
2518 * interpreted by the guest:
2519 *
2520 * L2 cache control register 3: 64GB range, 256KB size,
2521 * enabled, latency 0x1, configured
2522 */
2523 data = 0xbe702111;
2524 break;
2525 case MSR_AMD64_OSVW_ID_LENGTH:
2526 if (!guest_cpuid_has_osvw(vcpu))
2527 return 1;
2528 data = vcpu->arch.osvw.length;
2529 break;
2530 case MSR_AMD64_OSVW_STATUS:
2531 if (!guest_cpuid_has_osvw(vcpu))
2532 return 1;
2533 data = vcpu->arch.osvw.status;
2534 break;
2535 default:
2536 if (kvm_pmu_msr(vcpu, msr))
2537 return kvm_pmu_get_msr(vcpu, msr, pdata);
2538 if (!ignore_msrs) {
2539 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2540 return 1;
2541 } else {
2542 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2543 data = 0;
2544 }
2545 break;
2546 }
2547 *pdata = data;
2548 return 0;
2549 }
2550 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2551
2552 /*
2553 * Read or write a bunch of msrs. All parameters are kernel addresses.
2554 *
2555 * @return number of msrs set successfully.
2556 */
2557 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2558 struct kvm_msr_entry *entries,
2559 int (*do_msr)(struct kvm_vcpu *vcpu,
2560 unsigned index, u64 *data))
2561 {
2562 int i, idx;
2563
2564 idx = srcu_read_lock(&vcpu->kvm->srcu);
2565 for (i = 0; i < msrs->nmsrs; ++i)
2566 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2567 break;
2568 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2569
2570 return i;
2571 }
2572
2573 /*
2574 * Read or write a bunch of msrs. Parameters are user addresses.
2575 *
2576 * @return number of msrs set successfully.
2577 */
2578 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2579 int (*do_msr)(struct kvm_vcpu *vcpu,
2580 unsigned index, u64 *data),
2581 int writeback)
2582 {
2583 struct kvm_msrs msrs;
2584 struct kvm_msr_entry *entries;
2585 int r, n;
2586 unsigned size;
2587
2588 r = -EFAULT;
2589 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2590 goto out;
2591
2592 r = -E2BIG;
2593 if (msrs.nmsrs >= MAX_IO_MSRS)
2594 goto out;
2595
2596 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2597 entries = memdup_user(user_msrs->entries, size);
2598 if (IS_ERR(entries)) {
2599 r = PTR_ERR(entries);
2600 goto out;
2601 }
2602
2603 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2604 if (r < 0)
2605 goto out_free;
2606
2607 r = -EFAULT;
2608 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2609 goto out_free;
2610
2611 r = n;
2612
2613 out_free:
2614 kfree(entries);
2615 out:
2616 return r;
2617 }
2618
2619 int kvm_dev_ioctl_check_extension(long ext)
2620 {
2621 int r;
2622
2623 switch (ext) {
2624 case KVM_CAP_IRQCHIP:
2625 case KVM_CAP_HLT:
2626 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2627 case KVM_CAP_SET_TSS_ADDR:
2628 case KVM_CAP_EXT_CPUID:
2629 case KVM_CAP_EXT_EMUL_CPUID:
2630 case KVM_CAP_CLOCKSOURCE:
2631 case KVM_CAP_PIT:
2632 case KVM_CAP_NOP_IO_DELAY:
2633 case KVM_CAP_MP_STATE:
2634 case KVM_CAP_SYNC_MMU:
2635 case KVM_CAP_USER_NMI:
2636 case KVM_CAP_REINJECT_CONTROL:
2637 case KVM_CAP_IRQ_INJECT_STATUS:
2638 case KVM_CAP_IRQFD:
2639 case KVM_CAP_IOEVENTFD:
2640 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2641 case KVM_CAP_PIT2:
2642 case KVM_CAP_PIT_STATE2:
2643 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2644 case KVM_CAP_XEN_HVM:
2645 case KVM_CAP_ADJUST_CLOCK:
2646 case KVM_CAP_VCPU_EVENTS:
2647 case KVM_CAP_HYPERV:
2648 case KVM_CAP_HYPERV_VAPIC:
2649 case KVM_CAP_HYPERV_SPIN:
2650 case KVM_CAP_PCI_SEGMENT:
2651 case KVM_CAP_DEBUGREGS:
2652 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2653 case KVM_CAP_XSAVE:
2654 case KVM_CAP_ASYNC_PF:
2655 case KVM_CAP_GET_TSC_KHZ:
2656 case KVM_CAP_KVMCLOCK_CTRL:
2657 case KVM_CAP_READONLY_MEM:
2658 case KVM_CAP_HYPERV_TIME:
2659 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2660 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2661 case KVM_CAP_ASSIGN_DEV_IRQ:
2662 case KVM_CAP_PCI_2_3:
2663 #endif
2664 r = 1;
2665 break;
2666 case KVM_CAP_COALESCED_MMIO:
2667 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2668 break;
2669 case KVM_CAP_VAPIC:
2670 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2671 break;
2672 case KVM_CAP_NR_VCPUS:
2673 r = KVM_SOFT_MAX_VCPUS;
2674 break;
2675 case KVM_CAP_MAX_VCPUS:
2676 r = KVM_MAX_VCPUS;
2677 break;
2678 case KVM_CAP_NR_MEMSLOTS:
2679 r = KVM_USER_MEM_SLOTS;
2680 break;
2681 case KVM_CAP_PV_MMU: /* obsolete */
2682 r = 0;
2683 break;
2684 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2685 case KVM_CAP_IOMMU:
2686 r = iommu_present(&pci_bus_type);
2687 break;
2688 #endif
2689 case KVM_CAP_MCE:
2690 r = KVM_MAX_MCE_BANKS;
2691 break;
2692 case KVM_CAP_XCRS:
2693 r = cpu_has_xsave;
2694 break;
2695 case KVM_CAP_TSC_CONTROL:
2696 r = kvm_has_tsc_control;
2697 break;
2698 case KVM_CAP_TSC_DEADLINE_TIMER:
2699 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2700 break;
2701 default:
2702 r = 0;
2703 break;
2704 }
2705 return r;
2706
2707 }
2708
2709 long kvm_arch_dev_ioctl(struct file *filp,
2710 unsigned int ioctl, unsigned long arg)
2711 {
2712 void __user *argp = (void __user *)arg;
2713 long r;
2714
2715 switch (ioctl) {
2716 case KVM_GET_MSR_INDEX_LIST: {
2717 struct kvm_msr_list __user *user_msr_list = argp;
2718 struct kvm_msr_list msr_list;
2719 unsigned n;
2720
2721 r = -EFAULT;
2722 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2723 goto out;
2724 n = msr_list.nmsrs;
2725 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2726 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2727 goto out;
2728 r = -E2BIG;
2729 if (n < msr_list.nmsrs)
2730 goto out;
2731 r = -EFAULT;
2732 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2733 num_msrs_to_save * sizeof(u32)))
2734 goto out;
2735 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2736 &emulated_msrs,
2737 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2738 goto out;
2739 r = 0;
2740 break;
2741 }
2742 case KVM_GET_SUPPORTED_CPUID:
2743 case KVM_GET_EMULATED_CPUID: {
2744 struct kvm_cpuid2 __user *cpuid_arg = argp;
2745 struct kvm_cpuid2 cpuid;
2746
2747 r = -EFAULT;
2748 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2749 goto out;
2750
2751 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2752 ioctl);
2753 if (r)
2754 goto out;
2755
2756 r = -EFAULT;
2757 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2758 goto out;
2759 r = 0;
2760 break;
2761 }
2762 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2763 u64 mce_cap;
2764
2765 mce_cap = KVM_MCE_CAP_SUPPORTED;
2766 r = -EFAULT;
2767 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2768 goto out;
2769 r = 0;
2770 break;
2771 }
2772 default:
2773 r = -EINVAL;
2774 }
2775 out:
2776 return r;
2777 }
2778
2779 static void wbinvd_ipi(void *garbage)
2780 {
2781 wbinvd();
2782 }
2783
2784 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2785 {
2786 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2787 }
2788
2789 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2790 {
2791 /* Address WBINVD may be executed by guest */
2792 if (need_emulate_wbinvd(vcpu)) {
2793 if (kvm_x86_ops->has_wbinvd_exit())
2794 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2795 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2796 smp_call_function_single(vcpu->cpu,
2797 wbinvd_ipi, NULL, 1);
2798 }
2799
2800 kvm_x86_ops->vcpu_load(vcpu, cpu);
2801
2802 /* Apply any externally detected TSC adjustments (due to suspend) */
2803 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2804 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2805 vcpu->arch.tsc_offset_adjustment = 0;
2806 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2807 }
2808
2809 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2810 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2811 native_read_tsc() - vcpu->arch.last_host_tsc;
2812 if (tsc_delta < 0)
2813 mark_tsc_unstable("KVM discovered backwards TSC");
2814 if (check_tsc_unstable()) {
2815 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2816 vcpu->arch.last_guest_tsc);
2817 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2818 vcpu->arch.tsc_catchup = 1;
2819 }
2820 /*
2821 * On a host with synchronized TSC, there is no need to update
2822 * kvmclock on vcpu->cpu migration
2823 */
2824 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2825 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2826 if (vcpu->cpu != cpu)
2827 kvm_migrate_timers(vcpu);
2828 vcpu->cpu = cpu;
2829 }
2830
2831 accumulate_steal_time(vcpu);
2832 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2833 }
2834
2835 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2836 {
2837 kvm_x86_ops->vcpu_put(vcpu);
2838 kvm_put_guest_fpu(vcpu);
2839 vcpu->arch.last_host_tsc = native_read_tsc();
2840 }
2841
2842 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2843 struct kvm_lapic_state *s)
2844 {
2845 kvm_x86_ops->sync_pir_to_irr(vcpu);
2846 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2847
2848 return 0;
2849 }
2850
2851 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2852 struct kvm_lapic_state *s)
2853 {
2854 kvm_apic_post_state_restore(vcpu, s);
2855 update_cr8_intercept(vcpu);
2856
2857 return 0;
2858 }
2859
2860 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2861 struct kvm_interrupt *irq)
2862 {
2863 if (irq->irq >= KVM_NR_INTERRUPTS)
2864 return -EINVAL;
2865 if (irqchip_in_kernel(vcpu->kvm))
2866 return -ENXIO;
2867
2868 kvm_queue_interrupt(vcpu, irq->irq, false);
2869 kvm_make_request(KVM_REQ_EVENT, vcpu);
2870
2871 return 0;
2872 }
2873
2874 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2875 {
2876 kvm_inject_nmi(vcpu);
2877
2878 return 0;
2879 }
2880
2881 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2882 struct kvm_tpr_access_ctl *tac)
2883 {
2884 if (tac->flags)
2885 return -EINVAL;
2886 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2887 return 0;
2888 }
2889
2890 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2891 u64 mcg_cap)
2892 {
2893 int r;
2894 unsigned bank_num = mcg_cap & 0xff, bank;
2895
2896 r = -EINVAL;
2897 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2898 goto out;
2899 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2900 goto out;
2901 r = 0;
2902 vcpu->arch.mcg_cap = mcg_cap;
2903 /* Init IA32_MCG_CTL to all 1s */
2904 if (mcg_cap & MCG_CTL_P)
2905 vcpu->arch.mcg_ctl = ~(u64)0;
2906 /* Init IA32_MCi_CTL to all 1s */
2907 for (bank = 0; bank < bank_num; bank++)
2908 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2909 out:
2910 return r;
2911 }
2912
2913 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2914 struct kvm_x86_mce *mce)
2915 {
2916 u64 mcg_cap = vcpu->arch.mcg_cap;
2917 unsigned bank_num = mcg_cap & 0xff;
2918 u64 *banks = vcpu->arch.mce_banks;
2919
2920 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2921 return -EINVAL;
2922 /*
2923 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2924 * reporting is disabled
2925 */
2926 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2927 vcpu->arch.mcg_ctl != ~(u64)0)
2928 return 0;
2929 banks += 4 * mce->bank;
2930 /*
2931 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2932 * reporting is disabled for the bank
2933 */
2934 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2935 return 0;
2936 if (mce->status & MCI_STATUS_UC) {
2937 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2938 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2939 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2940 return 0;
2941 }
2942 if (banks[1] & MCI_STATUS_VAL)
2943 mce->status |= MCI_STATUS_OVER;
2944 banks[2] = mce->addr;
2945 banks[3] = mce->misc;
2946 vcpu->arch.mcg_status = mce->mcg_status;
2947 banks[1] = mce->status;
2948 kvm_queue_exception(vcpu, MC_VECTOR);
2949 } else if (!(banks[1] & MCI_STATUS_VAL)
2950 || !(banks[1] & MCI_STATUS_UC)) {
2951 if (banks[1] & MCI_STATUS_VAL)
2952 mce->status |= MCI_STATUS_OVER;
2953 banks[2] = mce->addr;
2954 banks[3] = mce->misc;
2955 banks[1] = mce->status;
2956 } else
2957 banks[1] |= MCI_STATUS_OVER;
2958 return 0;
2959 }
2960
2961 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2962 struct kvm_vcpu_events *events)
2963 {
2964 process_nmi(vcpu);
2965 events->exception.injected =
2966 vcpu->arch.exception.pending &&
2967 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2968 events->exception.nr = vcpu->arch.exception.nr;
2969 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2970 events->exception.pad = 0;
2971 events->exception.error_code = vcpu->arch.exception.error_code;
2972
2973 events->interrupt.injected =
2974 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2975 events->interrupt.nr = vcpu->arch.interrupt.nr;
2976 events->interrupt.soft = 0;
2977 events->interrupt.shadow =
2978 kvm_x86_ops->get_interrupt_shadow(vcpu,
2979 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2980
2981 events->nmi.injected = vcpu->arch.nmi_injected;
2982 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2983 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2984 events->nmi.pad = 0;
2985
2986 events->sipi_vector = 0; /* never valid when reporting to user space */
2987
2988 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2989 | KVM_VCPUEVENT_VALID_SHADOW);
2990 memset(&events->reserved, 0, sizeof(events->reserved));
2991 }
2992
2993 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2994 struct kvm_vcpu_events *events)
2995 {
2996 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2997 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2998 | KVM_VCPUEVENT_VALID_SHADOW))
2999 return -EINVAL;
3000
3001 process_nmi(vcpu);
3002 vcpu->arch.exception.pending = events->exception.injected;
3003 vcpu->arch.exception.nr = events->exception.nr;
3004 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3005 vcpu->arch.exception.error_code = events->exception.error_code;
3006
3007 vcpu->arch.interrupt.pending = events->interrupt.injected;
3008 vcpu->arch.interrupt.nr = events->interrupt.nr;
3009 vcpu->arch.interrupt.soft = events->interrupt.soft;
3010 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3011 kvm_x86_ops->set_interrupt_shadow(vcpu,
3012 events->interrupt.shadow);
3013
3014 vcpu->arch.nmi_injected = events->nmi.injected;
3015 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3016 vcpu->arch.nmi_pending = events->nmi.pending;
3017 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3018
3019 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3020 kvm_vcpu_has_lapic(vcpu))
3021 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3022
3023 kvm_make_request(KVM_REQ_EVENT, vcpu);
3024
3025 return 0;
3026 }
3027
3028 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3029 struct kvm_debugregs *dbgregs)
3030 {
3031 unsigned long val;
3032
3033 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3034 _kvm_get_dr(vcpu, 6, &val);
3035 dbgregs->dr6 = val;
3036 dbgregs->dr7 = vcpu->arch.dr7;
3037 dbgregs->flags = 0;
3038 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3039 }
3040
3041 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3042 struct kvm_debugregs *dbgregs)
3043 {
3044 if (dbgregs->flags)
3045 return -EINVAL;
3046
3047 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3048 vcpu->arch.dr6 = dbgregs->dr6;
3049 kvm_update_dr6(vcpu);
3050 vcpu->arch.dr7 = dbgregs->dr7;
3051 kvm_update_dr7(vcpu);
3052
3053 return 0;
3054 }
3055
3056 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3057 struct kvm_xsave *guest_xsave)
3058 {
3059 if (cpu_has_xsave) {
3060 memcpy(guest_xsave->region,
3061 &vcpu->arch.guest_fpu.state->xsave,
3062 vcpu->arch.guest_xstate_size);
3063 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3064 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3065 } else {
3066 memcpy(guest_xsave->region,
3067 &vcpu->arch.guest_fpu.state->fxsave,
3068 sizeof(struct i387_fxsave_struct));
3069 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3070 XSTATE_FPSSE;
3071 }
3072 }
3073
3074 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3075 struct kvm_xsave *guest_xsave)
3076 {
3077 u64 xstate_bv =
3078 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3079
3080 if (cpu_has_xsave) {
3081 /*
3082 * Here we allow setting states that are not present in
3083 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3084 * with old userspace.
3085 */
3086 if (xstate_bv & ~kvm_supported_xcr0())
3087 return -EINVAL;
3088 memcpy(&vcpu->arch.guest_fpu.state->xsave,
3089 guest_xsave->region, vcpu->arch.guest_xstate_size);
3090 } else {
3091 if (xstate_bv & ~XSTATE_FPSSE)
3092 return -EINVAL;
3093 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3094 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3095 }
3096 return 0;
3097 }
3098
3099 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3100 struct kvm_xcrs *guest_xcrs)
3101 {
3102 if (!cpu_has_xsave) {
3103 guest_xcrs->nr_xcrs = 0;
3104 return;
3105 }
3106
3107 guest_xcrs->nr_xcrs = 1;
3108 guest_xcrs->flags = 0;
3109 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3110 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3111 }
3112
3113 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3114 struct kvm_xcrs *guest_xcrs)
3115 {
3116 int i, r = 0;
3117
3118 if (!cpu_has_xsave)
3119 return -EINVAL;
3120
3121 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3122 return -EINVAL;
3123
3124 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3125 /* Only support XCR0 currently */
3126 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3127 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3128 guest_xcrs->xcrs[i].value);
3129 break;
3130 }
3131 if (r)
3132 r = -EINVAL;
3133 return r;
3134 }
3135
3136 /*
3137 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3138 * stopped by the hypervisor. This function will be called from the host only.
3139 * EINVAL is returned when the host attempts to set the flag for a guest that
3140 * does not support pv clocks.
3141 */
3142 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3143 {
3144 if (!vcpu->arch.pv_time_enabled)
3145 return -EINVAL;
3146 vcpu->arch.pvclock_set_guest_stopped_request = true;
3147 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3148 return 0;
3149 }
3150
3151 long kvm_arch_vcpu_ioctl(struct file *filp,
3152 unsigned int ioctl, unsigned long arg)
3153 {
3154 struct kvm_vcpu *vcpu = filp->private_data;
3155 void __user *argp = (void __user *)arg;
3156 int r;
3157 union {
3158 struct kvm_lapic_state *lapic;
3159 struct kvm_xsave *xsave;
3160 struct kvm_xcrs *xcrs;
3161 void *buffer;
3162 } u;
3163
3164 u.buffer = NULL;
3165 switch (ioctl) {
3166 case KVM_GET_LAPIC: {
3167 r = -EINVAL;
3168 if (!vcpu->arch.apic)
3169 goto out;
3170 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3171
3172 r = -ENOMEM;
3173 if (!u.lapic)
3174 goto out;
3175 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3176 if (r)
3177 goto out;
3178 r = -EFAULT;
3179 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3180 goto out;
3181 r = 0;
3182 break;
3183 }
3184 case KVM_SET_LAPIC: {
3185 r = -EINVAL;
3186 if (!vcpu->arch.apic)
3187 goto out;
3188 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3189 if (IS_ERR(u.lapic))
3190 return PTR_ERR(u.lapic);
3191
3192 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3193 break;
3194 }
3195 case KVM_INTERRUPT: {
3196 struct kvm_interrupt irq;
3197
3198 r = -EFAULT;
3199 if (copy_from_user(&irq, argp, sizeof irq))
3200 goto out;
3201 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3202 break;
3203 }
3204 case KVM_NMI: {
3205 r = kvm_vcpu_ioctl_nmi(vcpu);
3206 break;
3207 }
3208 case KVM_SET_CPUID: {
3209 struct kvm_cpuid __user *cpuid_arg = argp;
3210 struct kvm_cpuid cpuid;
3211
3212 r = -EFAULT;
3213 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3214 goto out;
3215 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3216 break;
3217 }
3218 case KVM_SET_CPUID2: {
3219 struct kvm_cpuid2 __user *cpuid_arg = argp;
3220 struct kvm_cpuid2 cpuid;
3221
3222 r = -EFAULT;
3223 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3224 goto out;
3225 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3226 cpuid_arg->entries);
3227 break;
3228 }
3229 case KVM_GET_CPUID2: {
3230 struct kvm_cpuid2 __user *cpuid_arg = argp;
3231 struct kvm_cpuid2 cpuid;
3232
3233 r = -EFAULT;
3234 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3235 goto out;
3236 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3237 cpuid_arg->entries);
3238 if (r)
3239 goto out;
3240 r = -EFAULT;
3241 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3242 goto out;
3243 r = 0;
3244 break;
3245 }
3246 case KVM_GET_MSRS:
3247 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3248 break;
3249 case KVM_SET_MSRS:
3250 r = msr_io(vcpu, argp, do_set_msr, 0);
3251 break;
3252 case KVM_TPR_ACCESS_REPORTING: {
3253 struct kvm_tpr_access_ctl tac;
3254
3255 r = -EFAULT;
3256 if (copy_from_user(&tac, argp, sizeof tac))
3257 goto out;
3258 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3259 if (r)
3260 goto out;
3261 r = -EFAULT;
3262 if (copy_to_user(argp, &tac, sizeof tac))
3263 goto out;
3264 r = 0;
3265 break;
3266 };
3267 case KVM_SET_VAPIC_ADDR: {
3268 struct kvm_vapic_addr va;
3269
3270 r = -EINVAL;
3271 if (!irqchip_in_kernel(vcpu->kvm))
3272 goto out;
3273 r = -EFAULT;
3274 if (copy_from_user(&va, argp, sizeof va))
3275 goto out;
3276 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3277 break;
3278 }
3279 case KVM_X86_SETUP_MCE: {
3280 u64 mcg_cap;
3281
3282 r = -EFAULT;
3283 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3284 goto out;
3285 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3286 break;
3287 }
3288 case KVM_X86_SET_MCE: {
3289 struct kvm_x86_mce mce;
3290
3291 r = -EFAULT;
3292 if (copy_from_user(&mce, argp, sizeof mce))
3293 goto out;
3294 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3295 break;
3296 }
3297 case KVM_GET_VCPU_EVENTS: {
3298 struct kvm_vcpu_events events;
3299
3300 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3301
3302 r = -EFAULT;
3303 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3304 break;
3305 r = 0;
3306 break;
3307 }
3308 case KVM_SET_VCPU_EVENTS: {
3309 struct kvm_vcpu_events events;
3310
3311 r = -EFAULT;
3312 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3313 break;
3314
3315 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3316 break;
3317 }
3318 case KVM_GET_DEBUGREGS: {
3319 struct kvm_debugregs dbgregs;
3320
3321 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3322
3323 r = -EFAULT;
3324 if (copy_to_user(argp, &dbgregs,
3325 sizeof(struct kvm_debugregs)))
3326 break;
3327 r = 0;
3328 break;
3329 }
3330 case KVM_SET_DEBUGREGS: {
3331 struct kvm_debugregs dbgregs;
3332
3333 r = -EFAULT;
3334 if (copy_from_user(&dbgregs, argp,
3335 sizeof(struct kvm_debugregs)))
3336 break;
3337
3338 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3339 break;
3340 }
3341 case KVM_GET_XSAVE: {
3342 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3343 r = -ENOMEM;
3344 if (!u.xsave)
3345 break;
3346
3347 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3348
3349 r = -EFAULT;
3350 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3351 break;
3352 r = 0;
3353 break;
3354 }
3355 case KVM_SET_XSAVE: {
3356 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3357 if (IS_ERR(u.xsave))
3358 return PTR_ERR(u.xsave);
3359
3360 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3361 break;
3362 }
3363 case KVM_GET_XCRS: {
3364 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3365 r = -ENOMEM;
3366 if (!u.xcrs)
3367 break;
3368
3369 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3370
3371 r = -EFAULT;
3372 if (copy_to_user(argp, u.xcrs,
3373 sizeof(struct kvm_xcrs)))
3374 break;
3375 r = 0;
3376 break;
3377 }
3378 case KVM_SET_XCRS: {
3379 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3380 if (IS_ERR(u.xcrs))
3381 return PTR_ERR(u.xcrs);
3382
3383 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3384 break;
3385 }
3386 case KVM_SET_TSC_KHZ: {
3387 u32 user_tsc_khz;
3388
3389 r = -EINVAL;
3390 user_tsc_khz = (u32)arg;
3391
3392 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3393 goto out;
3394
3395 if (user_tsc_khz == 0)
3396 user_tsc_khz = tsc_khz;
3397
3398 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3399
3400 r = 0;
3401 goto out;
3402 }
3403 case KVM_GET_TSC_KHZ: {
3404 r = vcpu->arch.virtual_tsc_khz;
3405 goto out;
3406 }
3407 case KVM_KVMCLOCK_CTRL: {
3408 r = kvm_set_guest_paused(vcpu);
3409 goto out;
3410 }
3411 default:
3412 r = -EINVAL;
3413 }
3414 out:
3415 kfree(u.buffer);
3416 return r;
3417 }
3418
3419 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3420 {
3421 return VM_FAULT_SIGBUS;
3422 }
3423
3424 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3425 {
3426 int ret;
3427
3428 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3429 return -EINVAL;
3430 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3431 return ret;
3432 }
3433
3434 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3435 u64 ident_addr)
3436 {
3437 kvm->arch.ept_identity_map_addr = ident_addr;
3438 return 0;
3439 }
3440
3441 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3442 u32 kvm_nr_mmu_pages)
3443 {
3444 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3445 return -EINVAL;
3446
3447 mutex_lock(&kvm->slots_lock);
3448
3449 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3450 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3451
3452 mutex_unlock(&kvm->slots_lock);
3453 return 0;
3454 }
3455
3456 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3457 {
3458 return kvm->arch.n_max_mmu_pages;
3459 }
3460
3461 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3462 {
3463 int r;
3464
3465 r = 0;
3466 switch (chip->chip_id) {
3467 case KVM_IRQCHIP_PIC_MASTER:
3468 memcpy(&chip->chip.pic,
3469 &pic_irqchip(kvm)->pics[0],
3470 sizeof(struct kvm_pic_state));
3471 break;
3472 case KVM_IRQCHIP_PIC_SLAVE:
3473 memcpy(&chip->chip.pic,
3474 &pic_irqchip(kvm)->pics[1],
3475 sizeof(struct kvm_pic_state));
3476 break;
3477 case KVM_IRQCHIP_IOAPIC:
3478 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3479 break;
3480 default:
3481 r = -EINVAL;
3482 break;
3483 }
3484 return r;
3485 }
3486
3487 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3488 {
3489 int r;
3490
3491 r = 0;
3492 switch (chip->chip_id) {
3493 case KVM_IRQCHIP_PIC_MASTER:
3494 spin_lock(&pic_irqchip(kvm)->lock);
3495 memcpy(&pic_irqchip(kvm)->pics[0],
3496 &chip->chip.pic,
3497 sizeof(struct kvm_pic_state));
3498 spin_unlock(&pic_irqchip(kvm)->lock);
3499 break;
3500 case KVM_IRQCHIP_PIC_SLAVE:
3501 spin_lock(&pic_irqchip(kvm)->lock);
3502 memcpy(&pic_irqchip(kvm)->pics[1],
3503 &chip->chip.pic,
3504 sizeof(struct kvm_pic_state));
3505 spin_unlock(&pic_irqchip(kvm)->lock);
3506 break;
3507 case KVM_IRQCHIP_IOAPIC:
3508 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3509 break;
3510 default:
3511 r = -EINVAL;
3512 break;
3513 }
3514 kvm_pic_update_irq(pic_irqchip(kvm));
3515 return r;
3516 }
3517
3518 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3519 {
3520 int r = 0;
3521
3522 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3523 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3524 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3525 return r;
3526 }
3527
3528 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3529 {
3530 int r = 0;
3531
3532 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3533 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3534 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3535 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3536 return r;
3537 }
3538
3539 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3540 {
3541 int r = 0;
3542
3543 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3544 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3545 sizeof(ps->channels));
3546 ps->flags = kvm->arch.vpit->pit_state.flags;
3547 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3548 memset(&ps->reserved, 0, sizeof(ps->reserved));
3549 return r;
3550 }
3551
3552 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3553 {
3554 int r = 0, start = 0;
3555 u32 prev_legacy, cur_legacy;
3556 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3557 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3558 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3559 if (!prev_legacy && cur_legacy)
3560 start = 1;
3561 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3562 sizeof(kvm->arch.vpit->pit_state.channels));
3563 kvm->arch.vpit->pit_state.flags = ps->flags;
3564 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3565 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3566 return r;
3567 }
3568
3569 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3570 struct kvm_reinject_control *control)
3571 {
3572 if (!kvm->arch.vpit)
3573 return -ENXIO;
3574 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3575 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3576 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3577 return 0;
3578 }
3579
3580 /**
3581 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3582 * @kvm: kvm instance
3583 * @log: slot id and address to which we copy the log
3584 *
3585 * We need to keep it in mind that VCPU threads can write to the bitmap
3586 * concurrently. So, to avoid losing data, we keep the following order for
3587 * each bit:
3588 *
3589 * 1. Take a snapshot of the bit and clear it if needed.
3590 * 2. Write protect the corresponding page.
3591 * 3. Flush TLB's if needed.
3592 * 4. Copy the snapshot to the userspace.
3593 *
3594 * Between 2 and 3, the guest may write to the page using the remaining TLB
3595 * entry. This is not a problem because the page will be reported dirty at
3596 * step 4 using the snapshot taken before and step 3 ensures that successive
3597 * writes will be logged for the next call.
3598 */
3599 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3600 {
3601 int r;
3602 struct kvm_memory_slot *memslot;
3603 unsigned long n, i;
3604 unsigned long *dirty_bitmap;
3605 unsigned long *dirty_bitmap_buffer;
3606 bool is_dirty = false;
3607
3608 mutex_lock(&kvm->slots_lock);
3609
3610 r = -EINVAL;
3611 if (log->slot >= KVM_USER_MEM_SLOTS)
3612 goto out;
3613
3614 memslot = id_to_memslot(kvm->memslots, log->slot);
3615
3616 dirty_bitmap = memslot->dirty_bitmap;
3617 r = -ENOENT;
3618 if (!dirty_bitmap)
3619 goto out;
3620
3621 n = kvm_dirty_bitmap_bytes(memslot);
3622
3623 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3624 memset(dirty_bitmap_buffer, 0, n);
3625
3626 spin_lock(&kvm->mmu_lock);
3627
3628 for (i = 0; i < n / sizeof(long); i++) {
3629 unsigned long mask;
3630 gfn_t offset;
3631
3632 if (!dirty_bitmap[i])
3633 continue;
3634
3635 is_dirty = true;
3636
3637 mask = xchg(&dirty_bitmap[i], 0);
3638 dirty_bitmap_buffer[i] = mask;
3639
3640 offset = i * BITS_PER_LONG;
3641 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3642 }
3643
3644 spin_unlock(&kvm->mmu_lock);
3645
3646 /* See the comments in kvm_mmu_slot_remove_write_access(). */
3647 lockdep_assert_held(&kvm->slots_lock);
3648
3649 /*
3650 * All the TLBs can be flushed out of mmu lock, see the comments in
3651 * kvm_mmu_slot_remove_write_access().
3652 */
3653 if (is_dirty)
3654 kvm_flush_remote_tlbs(kvm);
3655
3656 r = -EFAULT;
3657 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3658 goto out;
3659
3660 r = 0;
3661 out:
3662 mutex_unlock(&kvm->slots_lock);
3663 return r;
3664 }
3665
3666 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3667 bool line_status)
3668 {
3669 if (!irqchip_in_kernel(kvm))
3670 return -ENXIO;
3671
3672 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3673 irq_event->irq, irq_event->level,
3674 line_status);
3675 return 0;
3676 }
3677
3678 long kvm_arch_vm_ioctl(struct file *filp,
3679 unsigned int ioctl, unsigned long arg)
3680 {
3681 struct kvm *kvm = filp->private_data;
3682 void __user *argp = (void __user *)arg;
3683 int r = -ENOTTY;
3684 /*
3685 * This union makes it completely explicit to gcc-3.x
3686 * that these two variables' stack usage should be
3687 * combined, not added together.
3688 */
3689 union {
3690 struct kvm_pit_state ps;
3691 struct kvm_pit_state2 ps2;
3692 struct kvm_pit_config pit_config;
3693 } u;
3694
3695 switch (ioctl) {
3696 case KVM_SET_TSS_ADDR:
3697 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3698 break;
3699 case KVM_SET_IDENTITY_MAP_ADDR: {
3700 u64 ident_addr;
3701
3702 r = -EFAULT;
3703 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3704 goto out;
3705 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3706 break;
3707 }
3708 case KVM_SET_NR_MMU_PAGES:
3709 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3710 break;
3711 case KVM_GET_NR_MMU_PAGES:
3712 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3713 break;
3714 case KVM_CREATE_IRQCHIP: {
3715 struct kvm_pic *vpic;
3716
3717 mutex_lock(&kvm->lock);
3718 r = -EEXIST;
3719 if (kvm->arch.vpic)
3720 goto create_irqchip_unlock;
3721 r = -EINVAL;
3722 if (atomic_read(&kvm->online_vcpus))
3723 goto create_irqchip_unlock;
3724 r = -ENOMEM;
3725 vpic = kvm_create_pic(kvm);
3726 if (vpic) {
3727 r = kvm_ioapic_init(kvm);
3728 if (r) {
3729 mutex_lock(&kvm->slots_lock);
3730 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3731 &vpic->dev_master);
3732 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3733 &vpic->dev_slave);
3734 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3735 &vpic->dev_eclr);
3736 mutex_unlock(&kvm->slots_lock);
3737 kfree(vpic);
3738 goto create_irqchip_unlock;
3739 }
3740 } else
3741 goto create_irqchip_unlock;
3742 smp_wmb();
3743 kvm->arch.vpic = vpic;
3744 smp_wmb();
3745 r = kvm_setup_default_irq_routing(kvm);
3746 if (r) {
3747 mutex_lock(&kvm->slots_lock);
3748 mutex_lock(&kvm->irq_lock);
3749 kvm_ioapic_destroy(kvm);
3750 kvm_destroy_pic(kvm);
3751 mutex_unlock(&kvm->irq_lock);
3752 mutex_unlock(&kvm->slots_lock);
3753 }
3754 create_irqchip_unlock:
3755 mutex_unlock(&kvm->lock);
3756 break;
3757 }
3758 case KVM_CREATE_PIT:
3759 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3760 goto create_pit;
3761 case KVM_CREATE_PIT2:
3762 r = -EFAULT;
3763 if (copy_from_user(&u.pit_config, argp,
3764 sizeof(struct kvm_pit_config)))
3765 goto out;
3766 create_pit:
3767 mutex_lock(&kvm->slots_lock);
3768 r = -EEXIST;
3769 if (kvm->arch.vpit)
3770 goto create_pit_unlock;
3771 r = -ENOMEM;
3772 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3773 if (kvm->arch.vpit)
3774 r = 0;
3775 create_pit_unlock:
3776 mutex_unlock(&kvm->slots_lock);
3777 break;
3778 case KVM_GET_IRQCHIP: {
3779 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3780 struct kvm_irqchip *chip;
3781
3782 chip = memdup_user(argp, sizeof(*chip));
3783 if (IS_ERR(chip)) {
3784 r = PTR_ERR(chip);
3785 goto out;
3786 }
3787
3788 r = -ENXIO;
3789 if (!irqchip_in_kernel(kvm))
3790 goto get_irqchip_out;
3791 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3792 if (r)
3793 goto get_irqchip_out;
3794 r = -EFAULT;
3795 if (copy_to_user(argp, chip, sizeof *chip))
3796 goto get_irqchip_out;
3797 r = 0;
3798 get_irqchip_out:
3799 kfree(chip);
3800 break;
3801 }
3802 case KVM_SET_IRQCHIP: {
3803 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3804 struct kvm_irqchip *chip;
3805
3806 chip = memdup_user(argp, sizeof(*chip));
3807 if (IS_ERR(chip)) {
3808 r = PTR_ERR(chip);
3809 goto out;
3810 }
3811
3812 r = -ENXIO;
3813 if (!irqchip_in_kernel(kvm))
3814 goto set_irqchip_out;
3815 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3816 if (r)
3817 goto set_irqchip_out;
3818 r = 0;
3819 set_irqchip_out:
3820 kfree(chip);
3821 break;
3822 }
3823 case KVM_GET_PIT: {
3824 r = -EFAULT;
3825 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3826 goto out;
3827 r = -ENXIO;
3828 if (!kvm->arch.vpit)
3829 goto out;
3830 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3831 if (r)
3832 goto out;
3833 r = -EFAULT;
3834 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3835 goto out;
3836 r = 0;
3837 break;
3838 }
3839 case KVM_SET_PIT: {
3840 r = -EFAULT;
3841 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3842 goto out;
3843 r = -ENXIO;
3844 if (!kvm->arch.vpit)
3845 goto out;
3846 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3847 break;
3848 }
3849 case KVM_GET_PIT2: {
3850 r = -ENXIO;
3851 if (!kvm->arch.vpit)
3852 goto out;
3853 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3854 if (r)
3855 goto out;
3856 r = -EFAULT;
3857 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3858 goto out;
3859 r = 0;
3860 break;
3861 }
3862 case KVM_SET_PIT2: {
3863 r = -EFAULT;
3864 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3865 goto out;
3866 r = -ENXIO;
3867 if (!kvm->arch.vpit)
3868 goto out;
3869 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3870 break;
3871 }
3872 case KVM_REINJECT_CONTROL: {
3873 struct kvm_reinject_control control;
3874 r = -EFAULT;
3875 if (copy_from_user(&control, argp, sizeof(control)))
3876 goto out;
3877 r = kvm_vm_ioctl_reinject(kvm, &control);
3878 break;
3879 }
3880 case KVM_XEN_HVM_CONFIG: {
3881 r = -EFAULT;
3882 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3883 sizeof(struct kvm_xen_hvm_config)))
3884 goto out;
3885 r = -EINVAL;
3886 if (kvm->arch.xen_hvm_config.flags)
3887 goto out;
3888 r = 0;
3889 break;
3890 }
3891 case KVM_SET_CLOCK: {
3892 struct kvm_clock_data user_ns;
3893 u64 now_ns;
3894 s64 delta;
3895
3896 r = -EFAULT;
3897 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3898 goto out;
3899
3900 r = -EINVAL;
3901 if (user_ns.flags)
3902 goto out;
3903
3904 r = 0;
3905 local_irq_disable();
3906 now_ns = get_kernel_ns();
3907 delta = user_ns.clock - now_ns;
3908 local_irq_enable();
3909 kvm->arch.kvmclock_offset = delta;
3910 kvm_gen_update_masterclock(kvm);
3911 break;
3912 }
3913 case KVM_GET_CLOCK: {
3914 struct kvm_clock_data user_ns;
3915 u64 now_ns;
3916
3917 local_irq_disable();
3918 now_ns = get_kernel_ns();
3919 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3920 local_irq_enable();
3921 user_ns.flags = 0;
3922 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3923
3924 r = -EFAULT;
3925 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3926 goto out;
3927 r = 0;
3928 break;
3929 }
3930
3931 default:
3932 ;
3933 }
3934 out:
3935 return r;
3936 }
3937
3938 static void kvm_init_msr_list(void)
3939 {
3940 u32 dummy[2];
3941 unsigned i, j;
3942
3943 /* skip the first msrs in the list. KVM-specific */
3944 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3945 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3946 continue;
3947
3948 /*
3949 * Even MSRs that are valid in the host may not be exposed
3950 * to the guests in some cases. We could work around this
3951 * in VMX with the generic MSR save/load machinery, but it
3952 * is not really worthwhile since it will really only
3953 * happen with nested virtualization.
3954 */
3955 switch (msrs_to_save[i]) {
3956 case MSR_IA32_BNDCFGS:
3957 if (!kvm_x86_ops->mpx_supported())
3958 continue;
3959 break;
3960 default:
3961 break;
3962 }
3963
3964 if (j < i)
3965 msrs_to_save[j] = msrs_to_save[i];
3966 j++;
3967 }
3968 num_msrs_to_save = j;
3969 }
3970
3971 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3972 const void *v)
3973 {
3974 int handled = 0;
3975 int n;
3976
3977 do {
3978 n = min(len, 8);
3979 if (!(vcpu->arch.apic &&
3980 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3981 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3982 break;
3983 handled += n;
3984 addr += n;
3985 len -= n;
3986 v += n;
3987 } while (len);
3988
3989 return handled;
3990 }
3991
3992 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3993 {
3994 int handled = 0;
3995 int n;
3996
3997 do {
3998 n = min(len, 8);
3999 if (!(vcpu->arch.apic &&
4000 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
4001 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4002 break;
4003 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4004 handled += n;
4005 addr += n;
4006 len -= n;
4007 v += n;
4008 } while (len);
4009
4010 return handled;
4011 }
4012
4013 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4014 struct kvm_segment *var, int seg)
4015 {
4016 kvm_x86_ops->set_segment(vcpu, var, seg);
4017 }
4018
4019 void kvm_get_segment(struct kvm_vcpu *vcpu,
4020 struct kvm_segment *var, int seg)
4021 {
4022 kvm_x86_ops->get_segment(vcpu, var, seg);
4023 }
4024
4025 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
4026 {
4027 gpa_t t_gpa;
4028 struct x86_exception exception;
4029
4030 BUG_ON(!mmu_is_nested(vcpu));
4031
4032 /* NPT walks are always user-walks */
4033 access |= PFERR_USER_MASK;
4034 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
4035
4036 return t_gpa;
4037 }
4038
4039 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4040 struct x86_exception *exception)
4041 {
4042 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4043 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4044 }
4045
4046 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4047 struct x86_exception *exception)
4048 {
4049 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4050 access |= PFERR_FETCH_MASK;
4051 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4052 }
4053
4054 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4055 struct x86_exception *exception)
4056 {
4057 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4058 access |= PFERR_WRITE_MASK;
4059 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4060 }
4061
4062 /* uses this to access any guest's mapped memory without checking CPL */
4063 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4064 struct x86_exception *exception)
4065 {
4066 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4067 }
4068
4069 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4070 struct kvm_vcpu *vcpu, u32 access,
4071 struct x86_exception *exception)
4072 {
4073 void *data = val;
4074 int r = X86EMUL_CONTINUE;
4075
4076 while (bytes) {
4077 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4078 exception);
4079 unsigned offset = addr & (PAGE_SIZE-1);
4080 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4081 int ret;
4082
4083 if (gpa == UNMAPPED_GVA)
4084 return X86EMUL_PROPAGATE_FAULT;
4085 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
4086 if (ret < 0) {
4087 r = X86EMUL_IO_NEEDED;
4088 goto out;
4089 }
4090
4091 bytes -= toread;
4092 data += toread;
4093 addr += toread;
4094 }
4095 out:
4096 return r;
4097 }
4098
4099 /* used for instruction fetching */
4100 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4101 gva_t addr, void *val, unsigned int bytes,
4102 struct x86_exception *exception)
4103 {
4104 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4105 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4106
4107 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
4108 access | PFERR_FETCH_MASK,
4109 exception);
4110 }
4111
4112 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4113 gva_t addr, void *val, unsigned int bytes,
4114 struct x86_exception *exception)
4115 {
4116 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4117 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4118
4119 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4120 exception);
4121 }
4122 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4123
4124 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4125 gva_t addr, void *val, unsigned int bytes,
4126 struct x86_exception *exception)
4127 {
4128 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4129 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4130 }
4131
4132 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4133 gva_t addr, void *val,
4134 unsigned int bytes,
4135 struct x86_exception *exception)
4136 {
4137 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4138 void *data = val;
4139 int r = X86EMUL_CONTINUE;
4140
4141 while (bytes) {
4142 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4143 PFERR_WRITE_MASK,
4144 exception);
4145 unsigned offset = addr & (PAGE_SIZE-1);
4146 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4147 int ret;
4148
4149 if (gpa == UNMAPPED_GVA)
4150 return X86EMUL_PROPAGATE_FAULT;
4151 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4152 if (ret < 0) {
4153 r = X86EMUL_IO_NEEDED;
4154 goto out;
4155 }
4156
4157 bytes -= towrite;
4158 data += towrite;
4159 addr += towrite;
4160 }
4161 out:
4162 return r;
4163 }
4164 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4165
4166 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4167 gpa_t *gpa, struct x86_exception *exception,
4168 bool write)
4169 {
4170 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4171 | (write ? PFERR_WRITE_MASK : 0);
4172
4173 if (vcpu_match_mmio_gva(vcpu, gva)
4174 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4175 vcpu->arch.access, access)) {
4176 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4177 (gva & (PAGE_SIZE - 1));
4178 trace_vcpu_match_mmio(gva, *gpa, write, false);
4179 return 1;
4180 }
4181
4182 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4183
4184 if (*gpa == UNMAPPED_GVA)
4185 return -1;
4186
4187 /* For APIC access vmexit */
4188 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4189 return 1;
4190
4191 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4192 trace_vcpu_match_mmio(gva, *gpa, write, true);
4193 return 1;
4194 }
4195
4196 return 0;
4197 }
4198
4199 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4200 const void *val, int bytes)
4201 {
4202 int ret;
4203
4204 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4205 if (ret < 0)
4206 return 0;
4207 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4208 return 1;
4209 }
4210
4211 struct read_write_emulator_ops {
4212 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4213 int bytes);
4214 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4215 void *val, int bytes);
4216 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4217 int bytes, void *val);
4218 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4219 void *val, int bytes);
4220 bool write;
4221 };
4222
4223 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4224 {
4225 if (vcpu->mmio_read_completed) {
4226 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4227 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4228 vcpu->mmio_read_completed = 0;
4229 return 1;
4230 }
4231
4232 return 0;
4233 }
4234
4235 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4236 void *val, int bytes)
4237 {
4238 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4239 }
4240
4241 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4242 void *val, int bytes)
4243 {
4244 return emulator_write_phys(vcpu, gpa, val, bytes);
4245 }
4246
4247 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4248 {
4249 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4250 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4251 }
4252
4253 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4254 void *val, int bytes)
4255 {
4256 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4257 return X86EMUL_IO_NEEDED;
4258 }
4259
4260 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4261 void *val, int bytes)
4262 {
4263 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4264
4265 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4266 return X86EMUL_CONTINUE;
4267 }
4268
4269 static const struct read_write_emulator_ops read_emultor = {
4270 .read_write_prepare = read_prepare,
4271 .read_write_emulate = read_emulate,
4272 .read_write_mmio = vcpu_mmio_read,
4273 .read_write_exit_mmio = read_exit_mmio,
4274 };
4275
4276 static const struct read_write_emulator_ops write_emultor = {
4277 .read_write_emulate = write_emulate,
4278 .read_write_mmio = write_mmio,
4279 .read_write_exit_mmio = write_exit_mmio,
4280 .write = true,
4281 };
4282
4283 static int emulator_read_write_onepage(unsigned long addr, void *val,
4284 unsigned int bytes,
4285 struct x86_exception *exception,
4286 struct kvm_vcpu *vcpu,
4287 const struct read_write_emulator_ops *ops)
4288 {
4289 gpa_t gpa;
4290 int handled, ret;
4291 bool write = ops->write;
4292 struct kvm_mmio_fragment *frag;
4293
4294 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4295
4296 if (ret < 0)
4297 return X86EMUL_PROPAGATE_FAULT;
4298
4299 /* For APIC access vmexit */
4300 if (ret)
4301 goto mmio;
4302
4303 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4304 return X86EMUL_CONTINUE;
4305
4306 mmio:
4307 /*
4308 * Is this MMIO handled locally?
4309 */
4310 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4311 if (handled == bytes)
4312 return X86EMUL_CONTINUE;
4313
4314 gpa += handled;
4315 bytes -= handled;
4316 val += handled;
4317
4318 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4319 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4320 frag->gpa = gpa;
4321 frag->data = val;
4322 frag->len = bytes;
4323 return X86EMUL_CONTINUE;
4324 }
4325
4326 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4327 void *val, unsigned int bytes,
4328 struct x86_exception *exception,
4329 const struct read_write_emulator_ops *ops)
4330 {
4331 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4332 gpa_t gpa;
4333 int rc;
4334
4335 if (ops->read_write_prepare &&
4336 ops->read_write_prepare(vcpu, val, bytes))
4337 return X86EMUL_CONTINUE;
4338
4339 vcpu->mmio_nr_fragments = 0;
4340
4341 /* Crossing a page boundary? */
4342 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4343 int now;
4344
4345 now = -addr & ~PAGE_MASK;
4346 rc = emulator_read_write_onepage(addr, val, now, exception,
4347 vcpu, ops);
4348
4349 if (rc != X86EMUL_CONTINUE)
4350 return rc;
4351 addr += now;
4352 val += now;
4353 bytes -= now;
4354 }
4355
4356 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4357 vcpu, ops);
4358 if (rc != X86EMUL_CONTINUE)
4359 return rc;
4360
4361 if (!vcpu->mmio_nr_fragments)
4362 return rc;
4363
4364 gpa = vcpu->mmio_fragments[0].gpa;
4365
4366 vcpu->mmio_needed = 1;
4367 vcpu->mmio_cur_fragment = 0;
4368
4369 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4370 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4371 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4372 vcpu->run->mmio.phys_addr = gpa;
4373
4374 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4375 }
4376
4377 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4378 unsigned long addr,
4379 void *val,
4380 unsigned int bytes,
4381 struct x86_exception *exception)
4382 {
4383 return emulator_read_write(ctxt, addr, val, bytes,
4384 exception, &read_emultor);
4385 }
4386
4387 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4388 unsigned long addr,
4389 const void *val,
4390 unsigned int bytes,
4391 struct x86_exception *exception)
4392 {
4393 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4394 exception, &write_emultor);
4395 }
4396
4397 #define CMPXCHG_TYPE(t, ptr, old, new) \
4398 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4399
4400 #ifdef CONFIG_X86_64
4401 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4402 #else
4403 # define CMPXCHG64(ptr, old, new) \
4404 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4405 #endif
4406
4407 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4408 unsigned long addr,
4409 const void *old,
4410 const void *new,
4411 unsigned int bytes,
4412 struct x86_exception *exception)
4413 {
4414 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4415 gpa_t gpa;
4416 struct page *page;
4417 char *kaddr;
4418 bool exchanged;
4419
4420 /* guests cmpxchg8b have to be emulated atomically */
4421 if (bytes > 8 || (bytes & (bytes - 1)))
4422 goto emul_write;
4423
4424 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4425
4426 if (gpa == UNMAPPED_GVA ||
4427 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4428 goto emul_write;
4429
4430 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4431 goto emul_write;
4432
4433 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4434 if (is_error_page(page))
4435 goto emul_write;
4436
4437 kaddr = kmap_atomic(page);
4438 kaddr += offset_in_page(gpa);
4439 switch (bytes) {
4440 case 1:
4441 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4442 break;
4443 case 2:
4444 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4445 break;
4446 case 4:
4447 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4448 break;
4449 case 8:
4450 exchanged = CMPXCHG64(kaddr, old, new);
4451 break;
4452 default:
4453 BUG();
4454 }
4455 kunmap_atomic(kaddr);
4456 kvm_release_page_dirty(page);
4457
4458 if (!exchanged)
4459 return X86EMUL_CMPXCHG_FAILED;
4460
4461 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
4462 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4463
4464 return X86EMUL_CONTINUE;
4465
4466 emul_write:
4467 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4468
4469 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4470 }
4471
4472 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4473 {
4474 /* TODO: String I/O for in kernel device */
4475 int r;
4476
4477 if (vcpu->arch.pio.in)
4478 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4479 vcpu->arch.pio.size, pd);
4480 else
4481 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4482 vcpu->arch.pio.port, vcpu->arch.pio.size,
4483 pd);
4484 return r;
4485 }
4486
4487 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4488 unsigned short port, void *val,
4489 unsigned int count, bool in)
4490 {
4491 vcpu->arch.pio.port = port;
4492 vcpu->arch.pio.in = in;
4493 vcpu->arch.pio.count = count;
4494 vcpu->arch.pio.size = size;
4495
4496 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4497 vcpu->arch.pio.count = 0;
4498 return 1;
4499 }
4500
4501 vcpu->run->exit_reason = KVM_EXIT_IO;
4502 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4503 vcpu->run->io.size = size;
4504 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4505 vcpu->run->io.count = count;
4506 vcpu->run->io.port = port;
4507
4508 return 0;
4509 }
4510
4511 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4512 int size, unsigned short port, void *val,
4513 unsigned int count)
4514 {
4515 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4516 int ret;
4517
4518 if (vcpu->arch.pio.count)
4519 goto data_avail;
4520
4521 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4522 if (ret) {
4523 data_avail:
4524 memcpy(val, vcpu->arch.pio_data, size * count);
4525 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4526 vcpu->arch.pio.count = 0;
4527 return 1;
4528 }
4529
4530 return 0;
4531 }
4532
4533 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4534 int size, unsigned short port,
4535 const void *val, unsigned int count)
4536 {
4537 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4538
4539 memcpy(vcpu->arch.pio_data, val, size * count);
4540 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4541 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4542 }
4543
4544 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4545 {
4546 return kvm_x86_ops->get_segment_base(vcpu, seg);
4547 }
4548
4549 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4550 {
4551 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4552 }
4553
4554 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4555 {
4556 if (!need_emulate_wbinvd(vcpu))
4557 return X86EMUL_CONTINUE;
4558
4559 if (kvm_x86_ops->has_wbinvd_exit()) {
4560 int cpu = get_cpu();
4561
4562 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4563 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4564 wbinvd_ipi, NULL, 1);
4565 put_cpu();
4566 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4567 } else
4568 wbinvd();
4569 return X86EMUL_CONTINUE;
4570 }
4571 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4572
4573 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4574 {
4575 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4576 }
4577
4578 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4579 {
4580 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4581 }
4582
4583 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4584 {
4585
4586 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4587 }
4588
4589 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4590 {
4591 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4592 }
4593
4594 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4595 {
4596 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4597 unsigned long value;
4598
4599 switch (cr) {
4600 case 0:
4601 value = kvm_read_cr0(vcpu);
4602 break;
4603 case 2:
4604 value = vcpu->arch.cr2;
4605 break;
4606 case 3:
4607 value = kvm_read_cr3(vcpu);
4608 break;
4609 case 4:
4610 value = kvm_read_cr4(vcpu);
4611 break;
4612 case 8:
4613 value = kvm_get_cr8(vcpu);
4614 break;
4615 default:
4616 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4617 return 0;
4618 }
4619
4620 return value;
4621 }
4622
4623 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4624 {
4625 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4626 int res = 0;
4627
4628 switch (cr) {
4629 case 0:
4630 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4631 break;
4632 case 2:
4633 vcpu->arch.cr2 = val;
4634 break;
4635 case 3:
4636 res = kvm_set_cr3(vcpu, val);
4637 break;
4638 case 4:
4639 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4640 break;
4641 case 8:
4642 res = kvm_set_cr8(vcpu, val);
4643 break;
4644 default:
4645 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4646 res = -1;
4647 }
4648
4649 return res;
4650 }
4651
4652 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4653 {
4654 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4655 }
4656
4657 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4658 {
4659 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4660 }
4661
4662 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4663 {
4664 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4665 }
4666
4667 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4668 {
4669 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4670 }
4671
4672 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4673 {
4674 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4675 }
4676
4677 static unsigned long emulator_get_cached_segment_base(
4678 struct x86_emulate_ctxt *ctxt, int seg)
4679 {
4680 return get_segment_base(emul_to_vcpu(ctxt), seg);
4681 }
4682
4683 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4684 struct desc_struct *desc, u32 *base3,
4685 int seg)
4686 {
4687 struct kvm_segment var;
4688
4689 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4690 *selector = var.selector;
4691
4692 if (var.unusable) {
4693 memset(desc, 0, sizeof(*desc));
4694 return false;
4695 }
4696
4697 if (var.g)
4698 var.limit >>= 12;
4699 set_desc_limit(desc, var.limit);
4700 set_desc_base(desc, (unsigned long)var.base);
4701 #ifdef CONFIG_X86_64
4702 if (base3)
4703 *base3 = var.base >> 32;
4704 #endif
4705 desc->type = var.type;
4706 desc->s = var.s;
4707 desc->dpl = var.dpl;
4708 desc->p = var.present;
4709 desc->avl = var.avl;
4710 desc->l = var.l;
4711 desc->d = var.db;
4712 desc->g = var.g;
4713
4714 return true;
4715 }
4716
4717 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4718 struct desc_struct *desc, u32 base3,
4719 int seg)
4720 {
4721 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4722 struct kvm_segment var;
4723
4724 var.selector = selector;
4725 var.base = get_desc_base(desc);
4726 #ifdef CONFIG_X86_64
4727 var.base |= ((u64)base3) << 32;
4728 #endif
4729 var.limit = get_desc_limit(desc);
4730 if (desc->g)
4731 var.limit = (var.limit << 12) | 0xfff;
4732 var.type = desc->type;
4733 var.present = desc->p;
4734 var.dpl = desc->dpl;
4735 var.db = desc->d;
4736 var.s = desc->s;
4737 var.l = desc->l;
4738 var.g = desc->g;
4739 var.avl = desc->avl;
4740 var.present = desc->p;
4741 var.unusable = !var.present;
4742 var.padding = 0;
4743
4744 kvm_set_segment(vcpu, &var, seg);
4745 return;
4746 }
4747
4748 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4749 u32 msr_index, u64 *pdata)
4750 {
4751 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4752 }
4753
4754 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4755 u32 msr_index, u64 data)
4756 {
4757 struct msr_data msr;
4758
4759 msr.data = data;
4760 msr.index = msr_index;
4761 msr.host_initiated = false;
4762 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4763 }
4764
4765 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4766 u32 pmc)
4767 {
4768 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4769 }
4770
4771 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4772 u32 pmc, u64 *pdata)
4773 {
4774 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4775 }
4776
4777 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4778 {
4779 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4780 }
4781
4782 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4783 {
4784 preempt_disable();
4785 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4786 /*
4787 * CR0.TS may reference the host fpu state, not the guest fpu state,
4788 * so it may be clear at this point.
4789 */
4790 clts();
4791 }
4792
4793 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4794 {
4795 preempt_enable();
4796 }
4797
4798 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4799 struct x86_instruction_info *info,
4800 enum x86_intercept_stage stage)
4801 {
4802 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4803 }
4804
4805 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4806 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4807 {
4808 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4809 }
4810
4811 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4812 {
4813 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4814 }
4815
4816 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4817 {
4818 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4819 }
4820
4821 static const struct x86_emulate_ops emulate_ops = {
4822 .read_gpr = emulator_read_gpr,
4823 .write_gpr = emulator_write_gpr,
4824 .read_std = kvm_read_guest_virt_system,
4825 .write_std = kvm_write_guest_virt_system,
4826 .fetch = kvm_fetch_guest_virt,
4827 .read_emulated = emulator_read_emulated,
4828 .write_emulated = emulator_write_emulated,
4829 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4830 .invlpg = emulator_invlpg,
4831 .pio_in_emulated = emulator_pio_in_emulated,
4832 .pio_out_emulated = emulator_pio_out_emulated,
4833 .get_segment = emulator_get_segment,
4834 .set_segment = emulator_set_segment,
4835 .get_cached_segment_base = emulator_get_cached_segment_base,
4836 .get_gdt = emulator_get_gdt,
4837 .get_idt = emulator_get_idt,
4838 .set_gdt = emulator_set_gdt,
4839 .set_idt = emulator_set_idt,
4840 .get_cr = emulator_get_cr,
4841 .set_cr = emulator_set_cr,
4842 .cpl = emulator_get_cpl,
4843 .get_dr = emulator_get_dr,
4844 .set_dr = emulator_set_dr,
4845 .set_msr = emulator_set_msr,
4846 .get_msr = emulator_get_msr,
4847 .check_pmc = emulator_check_pmc,
4848 .read_pmc = emulator_read_pmc,
4849 .halt = emulator_halt,
4850 .wbinvd = emulator_wbinvd,
4851 .fix_hypercall = emulator_fix_hypercall,
4852 .get_fpu = emulator_get_fpu,
4853 .put_fpu = emulator_put_fpu,
4854 .intercept = emulator_intercept,
4855 .get_cpuid = emulator_get_cpuid,
4856 };
4857
4858 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4859 {
4860 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4861 /*
4862 * an sti; sti; sequence only disable interrupts for the first
4863 * instruction. So, if the last instruction, be it emulated or
4864 * not, left the system with the INT_STI flag enabled, it
4865 * means that the last instruction is an sti. We should not
4866 * leave the flag on in this case. The same goes for mov ss
4867 */
4868 if (!(int_shadow & mask))
4869 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4870 }
4871
4872 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4873 {
4874 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4875 if (ctxt->exception.vector == PF_VECTOR)
4876 kvm_propagate_fault(vcpu, &ctxt->exception);
4877 else if (ctxt->exception.error_code_valid)
4878 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4879 ctxt->exception.error_code);
4880 else
4881 kvm_queue_exception(vcpu, ctxt->exception.vector);
4882 }
4883
4884 static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4885 {
4886 memset(&ctxt->opcode_len, 0,
4887 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
4888
4889 ctxt->fetch.start = 0;
4890 ctxt->fetch.end = 0;
4891 ctxt->io_read.pos = 0;
4892 ctxt->io_read.end = 0;
4893 ctxt->mem_read.pos = 0;
4894 ctxt->mem_read.end = 0;
4895 }
4896
4897 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4898 {
4899 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4900 int cs_db, cs_l;
4901
4902 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4903
4904 ctxt->eflags = kvm_get_rflags(vcpu);
4905 ctxt->eip = kvm_rip_read(vcpu);
4906 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4907 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4908 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
4909 cs_db ? X86EMUL_MODE_PROT32 :
4910 X86EMUL_MODE_PROT16;
4911 ctxt->guest_mode = is_guest_mode(vcpu);
4912
4913 init_decode_cache(ctxt);
4914 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4915 }
4916
4917 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4918 {
4919 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4920 int ret;
4921
4922 init_emulate_ctxt(vcpu);
4923
4924 ctxt->op_bytes = 2;
4925 ctxt->ad_bytes = 2;
4926 ctxt->_eip = ctxt->eip + inc_eip;
4927 ret = emulate_int_real(ctxt, irq);
4928
4929 if (ret != X86EMUL_CONTINUE)
4930 return EMULATE_FAIL;
4931
4932 ctxt->eip = ctxt->_eip;
4933 kvm_rip_write(vcpu, ctxt->eip);
4934 kvm_set_rflags(vcpu, ctxt->eflags);
4935
4936 if (irq == NMI_VECTOR)
4937 vcpu->arch.nmi_pending = 0;
4938 else
4939 vcpu->arch.interrupt.pending = false;
4940
4941 return EMULATE_DONE;
4942 }
4943 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4944
4945 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4946 {
4947 int r = EMULATE_DONE;
4948
4949 ++vcpu->stat.insn_emulation_fail;
4950 trace_kvm_emulate_insn_failed(vcpu);
4951 if (!is_guest_mode(vcpu)) {
4952 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4953 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4954 vcpu->run->internal.ndata = 0;
4955 r = EMULATE_FAIL;
4956 }
4957 kvm_queue_exception(vcpu, UD_VECTOR);
4958
4959 return r;
4960 }
4961
4962 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4963 bool write_fault_to_shadow_pgtable,
4964 int emulation_type)
4965 {
4966 gpa_t gpa = cr2;
4967 pfn_t pfn;
4968
4969 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4970 return false;
4971
4972 if (!vcpu->arch.mmu.direct_map) {
4973 /*
4974 * Write permission should be allowed since only
4975 * write access need to be emulated.
4976 */
4977 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4978
4979 /*
4980 * If the mapping is invalid in guest, let cpu retry
4981 * it to generate fault.
4982 */
4983 if (gpa == UNMAPPED_GVA)
4984 return true;
4985 }
4986
4987 /*
4988 * Do not retry the unhandleable instruction if it faults on the
4989 * readonly host memory, otherwise it will goto a infinite loop:
4990 * retry instruction -> write #PF -> emulation fail -> retry
4991 * instruction -> ...
4992 */
4993 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4994
4995 /*
4996 * If the instruction failed on the error pfn, it can not be fixed,
4997 * report the error to userspace.
4998 */
4999 if (is_error_noslot_pfn(pfn))
5000 return false;
5001
5002 kvm_release_pfn_clean(pfn);
5003
5004 /* The instructions are well-emulated on direct mmu. */
5005 if (vcpu->arch.mmu.direct_map) {
5006 unsigned int indirect_shadow_pages;
5007
5008 spin_lock(&vcpu->kvm->mmu_lock);
5009 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5010 spin_unlock(&vcpu->kvm->mmu_lock);
5011
5012 if (indirect_shadow_pages)
5013 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5014
5015 return true;
5016 }
5017
5018 /*
5019 * if emulation was due to access to shadowed page table
5020 * and it failed try to unshadow page and re-enter the
5021 * guest to let CPU execute the instruction.
5022 */
5023 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5024
5025 /*
5026 * If the access faults on its page table, it can not
5027 * be fixed by unprotecting shadow page and it should
5028 * be reported to userspace.
5029 */
5030 return !write_fault_to_shadow_pgtable;
5031 }
5032
5033 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5034 unsigned long cr2, int emulation_type)
5035 {
5036 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5037 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5038
5039 last_retry_eip = vcpu->arch.last_retry_eip;
5040 last_retry_addr = vcpu->arch.last_retry_addr;
5041
5042 /*
5043 * If the emulation is caused by #PF and it is non-page_table
5044 * writing instruction, it means the VM-EXIT is caused by shadow
5045 * page protected, we can zap the shadow page and retry this
5046 * instruction directly.
5047 *
5048 * Note: if the guest uses a non-page-table modifying instruction
5049 * on the PDE that points to the instruction, then we will unmap
5050 * the instruction and go to an infinite loop. So, we cache the
5051 * last retried eip and the last fault address, if we meet the eip
5052 * and the address again, we can break out of the potential infinite
5053 * loop.
5054 */
5055 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5056
5057 if (!(emulation_type & EMULTYPE_RETRY))
5058 return false;
5059
5060 if (x86_page_table_writing_insn(ctxt))
5061 return false;
5062
5063 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5064 return false;
5065
5066 vcpu->arch.last_retry_eip = ctxt->eip;
5067 vcpu->arch.last_retry_addr = cr2;
5068
5069 if (!vcpu->arch.mmu.direct_map)
5070 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5071
5072 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5073
5074 return true;
5075 }
5076
5077 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5078 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5079
5080 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5081 unsigned long *db)
5082 {
5083 u32 dr6 = 0;
5084 int i;
5085 u32 enable, rwlen;
5086
5087 enable = dr7;
5088 rwlen = dr7 >> 16;
5089 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5090 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5091 dr6 |= (1 << i);
5092 return dr6;
5093 }
5094
5095 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
5096 {
5097 struct kvm_run *kvm_run = vcpu->run;
5098
5099 /*
5100 * Use the "raw" value to see if TF was passed to the processor.
5101 * Note that the new value of the flags has not been saved yet.
5102 *
5103 * This is correct even for TF set by the guest, because "the
5104 * processor will not generate this exception after the instruction
5105 * that sets the TF flag".
5106 */
5107 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5108
5109 if (unlikely(rflags & X86_EFLAGS_TF)) {
5110 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5111 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5112 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5113 kvm_run->debug.arch.exception = DB_VECTOR;
5114 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5115 *r = EMULATE_USER_EXIT;
5116 } else {
5117 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5118 /*
5119 * "Certain debug exceptions may clear bit 0-3. The
5120 * remaining contents of the DR6 register are never
5121 * cleared by the processor".
5122 */
5123 vcpu->arch.dr6 &= ~15;
5124 vcpu->arch.dr6 |= DR6_BS;
5125 kvm_queue_exception(vcpu, DB_VECTOR);
5126 }
5127 }
5128 }
5129
5130 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5131 {
5132 struct kvm_run *kvm_run = vcpu->run;
5133 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5134 u32 dr6 = 0;
5135
5136 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5137 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5138 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5139 vcpu->arch.guest_debug_dr7,
5140 vcpu->arch.eff_db);
5141
5142 if (dr6 != 0) {
5143 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5144 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5145 get_segment_base(vcpu, VCPU_SREG_CS);
5146
5147 kvm_run->debug.arch.exception = DB_VECTOR;
5148 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5149 *r = EMULATE_USER_EXIT;
5150 return true;
5151 }
5152 }
5153
5154 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5155 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5156 vcpu->arch.dr7,
5157 vcpu->arch.db);
5158
5159 if (dr6 != 0) {
5160 vcpu->arch.dr6 &= ~15;
5161 vcpu->arch.dr6 |= dr6;
5162 kvm_queue_exception(vcpu, DB_VECTOR);
5163 *r = EMULATE_DONE;
5164 return true;
5165 }
5166 }
5167
5168 return false;
5169 }
5170
5171 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5172 unsigned long cr2,
5173 int emulation_type,
5174 void *insn,
5175 int insn_len)
5176 {
5177 int r;
5178 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5179 bool writeback = true;
5180 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5181
5182 /*
5183 * Clear write_fault_to_shadow_pgtable here to ensure it is
5184 * never reused.
5185 */
5186 vcpu->arch.write_fault_to_shadow_pgtable = false;
5187 kvm_clear_exception_queue(vcpu);
5188
5189 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5190 init_emulate_ctxt(vcpu);
5191
5192 /*
5193 * We will reenter on the same instruction since
5194 * we do not set complete_userspace_io. This does not
5195 * handle watchpoints yet, those would be handled in
5196 * the emulate_ops.
5197 */
5198 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5199 return r;
5200
5201 ctxt->interruptibility = 0;
5202 ctxt->have_exception = false;
5203 ctxt->perm_ok = false;
5204
5205 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5206
5207 r = x86_decode_insn(ctxt, insn, insn_len);
5208
5209 trace_kvm_emulate_insn_start(vcpu);
5210 ++vcpu->stat.insn_emulation;
5211 if (r != EMULATION_OK) {
5212 if (emulation_type & EMULTYPE_TRAP_UD)
5213 return EMULATE_FAIL;
5214 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5215 emulation_type))
5216 return EMULATE_DONE;
5217 if (emulation_type & EMULTYPE_SKIP)
5218 return EMULATE_FAIL;
5219 return handle_emulation_failure(vcpu);
5220 }
5221 }
5222
5223 if (emulation_type & EMULTYPE_SKIP) {
5224 kvm_rip_write(vcpu, ctxt->_eip);
5225 return EMULATE_DONE;
5226 }
5227
5228 if (retry_instruction(ctxt, cr2, emulation_type))
5229 return EMULATE_DONE;
5230
5231 /* this is needed for vmware backdoor interface to work since it
5232 changes registers values during IO operation */
5233 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5234 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5235 emulator_invalidate_register_cache(ctxt);
5236 }
5237
5238 restart:
5239 r = x86_emulate_insn(ctxt);
5240
5241 if (r == EMULATION_INTERCEPTED)
5242 return EMULATE_DONE;
5243
5244 if (r == EMULATION_FAILED) {
5245 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5246 emulation_type))
5247 return EMULATE_DONE;
5248
5249 return handle_emulation_failure(vcpu);
5250 }
5251
5252 if (ctxt->have_exception) {
5253 inject_emulated_exception(vcpu);
5254 r = EMULATE_DONE;
5255 } else if (vcpu->arch.pio.count) {
5256 if (!vcpu->arch.pio.in) {
5257 /* FIXME: return into emulator if single-stepping. */
5258 vcpu->arch.pio.count = 0;
5259 } else {
5260 writeback = false;
5261 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5262 }
5263 r = EMULATE_USER_EXIT;
5264 } else if (vcpu->mmio_needed) {
5265 if (!vcpu->mmio_is_write)
5266 writeback = false;
5267 r = EMULATE_USER_EXIT;
5268 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5269 } else if (r == EMULATION_RESTART)
5270 goto restart;
5271 else
5272 r = EMULATE_DONE;
5273
5274 if (writeback) {
5275 toggle_interruptibility(vcpu, ctxt->interruptibility);
5276 kvm_make_request(KVM_REQ_EVENT, vcpu);
5277 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5278 kvm_rip_write(vcpu, ctxt->eip);
5279 if (r == EMULATE_DONE)
5280 kvm_vcpu_check_singlestep(vcpu, &r);
5281 kvm_set_rflags(vcpu, ctxt->eflags);
5282 } else
5283 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5284
5285 return r;
5286 }
5287 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5288
5289 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5290 {
5291 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5292 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5293 size, port, &val, 1);
5294 /* do not return to emulator after return from userspace */
5295 vcpu->arch.pio.count = 0;
5296 return ret;
5297 }
5298 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5299
5300 static void tsc_bad(void *info)
5301 {
5302 __this_cpu_write(cpu_tsc_khz, 0);
5303 }
5304
5305 static void tsc_khz_changed(void *data)
5306 {
5307 struct cpufreq_freqs *freq = data;
5308 unsigned long khz = 0;
5309
5310 if (data)
5311 khz = freq->new;
5312 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5313 khz = cpufreq_quick_get(raw_smp_processor_id());
5314 if (!khz)
5315 khz = tsc_khz;
5316 __this_cpu_write(cpu_tsc_khz, khz);
5317 }
5318
5319 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5320 void *data)
5321 {
5322 struct cpufreq_freqs *freq = data;
5323 struct kvm *kvm;
5324 struct kvm_vcpu *vcpu;
5325 int i, send_ipi = 0;
5326
5327 /*
5328 * We allow guests to temporarily run on slowing clocks,
5329 * provided we notify them after, or to run on accelerating
5330 * clocks, provided we notify them before. Thus time never
5331 * goes backwards.
5332 *
5333 * However, we have a problem. We can't atomically update
5334 * the frequency of a given CPU from this function; it is
5335 * merely a notifier, which can be called from any CPU.
5336 * Changing the TSC frequency at arbitrary points in time
5337 * requires a recomputation of local variables related to
5338 * the TSC for each VCPU. We must flag these local variables
5339 * to be updated and be sure the update takes place with the
5340 * new frequency before any guests proceed.
5341 *
5342 * Unfortunately, the combination of hotplug CPU and frequency
5343 * change creates an intractable locking scenario; the order
5344 * of when these callouts happen is undefined with respect to
5345 * CPU hotplug, and they can race with each other. As such,
5346 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5347 * undefined; you can actually have a CPU frequency change take
5348 * place in between the computation of X and the setting of the
5349 * variable. To protect against this problem, all updates of
5350 * the per_cpu tsc_khz variable are done in an interrupt
5351 * protected IPI, and all callers wishing to update the value
5352 * must wait for a synchronous IPI to complete (which is trivial
5353 * if the caller is on the CPU already). This establishes the
5354 * necessary total order on variable updates.
5355 *
5356 * Note that because a guest time update may take place
5357 * anytime after the setting of the VCPU's request bit, the
5358 * correct TSC value must be set before the request. However,
5359 * to ensure the update actually makes it to any guest which
5360 * starts running in hardware virtualization between the set
5361 * and the acquisition of the spinlock, we must also ping the
5362 * CPU after setting the request bit.
5363 *
5364 */
5365
5366 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5367 return 0;
5368 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5369 return 0;
5370
5371 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5372
5373 spin_lock(&kvm_lock);
5374 list_for_each_entry(kvm, &vm_list, vm_list) {
5375 kvm_for_each_vcpu(i, vcpu, kvm) {
5376 if (vcpu->cpu != freq->cpu)
5377 continue;
5378 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5379 if (vcpu->cpu != smp_processor_id())
5380 send_ipi = 1;
5381 }
5382 }
5383 spin_unlock(&kvm_lock);
5384
5385 if (freq->old < freq->new && send_ipi) {
5386 /*
5387 * We upscale the frequency. Must make the guest
5388 * doesn't see old kvmclock values while running with
5389 * the new frequency, otherwise we risk the guest sees
5390 * time go backwards.
5391 *
5392 * In case we update the frequency for another cpu
5393 * (which might be in guest context) send an interrupt
5394 * to kick the cpu out of guest context. Next time
5395 * guest context is entered kvmclock will be updated,
5396 * so the guest will not see stale values.
5397 */
5398 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5399 }
5400 return 0;
5401 }
5402
5403 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5404 .notifier_call = kvmclock_cpufreq_notifier
5405 };
5406
5407 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5408 unsigned long action, void *hcpu)
5409 {
5410 unsigned int cpu = (unsigned long)hcpu;
5411
5412 switch (action) {
5413 case CPU_ONLINE:
5414 case CPU_DOWN_FAILED:
5415 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5416 break;
5417 case CPU_DOWN_PREPARE:
5418 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5419 break;
5420 }
5421 return NOTIFY_OK;
5422 }
5423
5424 static struct notifier_block kvmclock_cpu_notifier_block = {
5425 .notifier_call = kvmclock_cpu_notifier,
5426 .priority = -INT_MAX
5427 };
5428
5429 static void kvm_timer_init(void)
5430 {
5431 int cpu;
5432
5433 max_tsc_khz = tsc_khz;
5434
5435 cpu_notifier_register_begin();
5436 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5437 #ifdef CONFIG_CPU_FREQ
5438 struct cpufreq_policy policy;
5439 memset(&policy, 0, sizeof(policy));
5440 cpu = get_cpu();
5441 cpufreq_get_policy(&policy, cpu);
5442 if (policy.cpuinfo.max_freq)
5443 max_tsc_khz = policy.cpuinfo.max_freq;
5444 put_cpu();
5445 #endif
5446 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5447 CPUFREQ_TRANSITION_NOTIFIER);
5448 }
5449 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5450 for_each_online_cpu(cpu)
5451 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5452
5453 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5454 cpu_notifier_register_done();
5455
5456 }
5457
5458 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5459
5460 int kvm_is_in_guest(void)
5461 {
5462 return __this_cpu_read(current_vcpu) != NULL;
5463 }
5464
5465 static int kvm_is_user_mode(void)
5466 {
5467 int user_mode = 3;
5468
5469 if (__this_cpu_read(current_vcpu))
5470 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5471
5472 return user_mode != 0;
5473 }
5474
5475 static unsigned long kvm_get_guest_ip(void)
5476 {
5477 unsigned long ip = 0;
5478
5479 if (__this_cpu_read(current_vcpu))
5480 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5481
5482 return ip;
5483 }
5484
5485 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5486 .is_in_guest = kvm_is_in_guest,
5487 .is_user_mode = kvm_is_user_mode,
5488 .get_guest_ip = kvm_get_guest_ip,
5489 };
5490
5491 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5492 {
5493 __this_cpu_write(current_vcpu, vcpu);
5494 }
5495 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5496
5497 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5498 {
5499 __this_cpu_write(current_vcpu, NULL);
5500 }
5501 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5502
5503 static void kvm_set_mmio_spte_mask(void)
5504 {
5505 u64 mask;
5506 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5507
5508 /*
5509 * Set the reserved bits and the present bit of an paging-structure
5510 * entry to generate page fault with PFER.RSV = 1.
5511 */
5512 /* Mask the reserved physical address bits. */
5513 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5514
5515 /* Bit 62 is always reserved for 32bit host. */
5516 mask |= 0x3ull << 62;
5517
5518 /* Set the present bit. */
5519 mask |= 1ull;
5520
5521 #ifdef CONFIG_X86_64
5522 /*
5523 * If reserved bit is not supported, clear the present bit to disable
5524 * mmio page fault.
5525 */
5526 if (maxphyaddr == 52)
5527 mask &= ~1ull;
5528 #endif
5529
5530 kvm_mmu_set_mmio_spte_mask(mask);
5531 }
5532
5533 #ifdef CONFIG_X86_64
5534 static void pvclock_gtod_update_fn(struct work_struct *work)
5535 {
5536 struct kvm *kvm;
5537
5538 struct kvm_vcpu *vcpu;
5539 int i;
5540
5541 spin_lock(&kvm_lock);
5542 list_for_each_entry(kvm, &vm_list, vm_list)
5543 kvm_for_each_vcpu(i, vcpu, kvm)
5544 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5545 atomic_set(&kvm_guest_has_master_clock, 0);
5546 spin_unlock(&kvm_lock);
5547 }
5548
5549 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5550
5551 /*
5552 * Notification about pvclock gtod data update.
5553 */
5554 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5555 void *priv)
5556 {
5557 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5558 struct timekeeper *tk = priv;
5559
5560 update_pvclock_gtod(tk);
5561
5562 /* disable master clock if host does not trust, or does not
5563 * use, TSC clocksource
5564 */
5565 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5566 atomic_read(&kvm_guest_has_master_clock) != 0)
5567 queue_work(system_long_wq, &pvclock_gtod_work);
5568
5569 return 0;
5570 }
5571
5572 static struct notifier_block pvclock_gtod_notifier = {
5573 .notifier_call = pvclock_gtod_notify,
5574 };
5575 #endif
5576
5577 int kvm_arch_init(void *opaque)
5578 {
5579 int r;
5580 struct kvm_x86_ops *ops = opaque;
5581
5582 if (kvm_x86_ops) {
5583 printk(KERN_ERR "kvm: already loaded the other module\n");
5584 r = -EEXIST;
5585 goto out;
5586 }
5587
5588 if (!ops->cpu_has_kvm_support()) {
5589 printk(KERN_ERR "kvm: no hardware support\n");
5590 r = -EOPNOTSUPP;
5591 goto out;
5592 }
5593 if (ops->disabled_by_bios()) {
5594 printk(KERN_ERR "kvm: disabled by bios\n");
5595 r = -EOPNOTSUPP;
5596 goto out;
5597 }
5598
5599 r = -ENOMEM;
5600 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5601 if (!shared_msrs) {
5602 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5603 goto out;
5604 }
5605
5606 r = kvm_mmu_module_init();
5607 if (r)
5608 goto out_free_percpu;
5609
5610 kvm_set_mmio_spte_mask();
5611
5612 kvm_x86_ops = ops;
5613 kvm_init_msr_list();
5614
5615 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5616 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5617
5618 kvm_timer_init();
5619
5620 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5621
5622 if (cpu_has_xsave)
5623 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5624
5625 kvm_lapic_init();
5626 #ifdef CONFIG_X86_64
5627 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5628 #endif
5629
5630 return 0;
5631
5632 out_free_percpu:
5633 free_percpu(shared_msrs);
5634 out:
5635 return r;
5636 }
5637
5638 void kvm_arch_exit(void)
5639 {
5640 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5641
5642 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5643 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5644 CPUFREQ_TRANSITION_NOTIFIER);
5645 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5646 #ifdef CONFIG_X86_64
5647 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5648 #endif
5649 kvm_x86_ops = NULL;
5650 kvm_mmu_module_exit();
5651 free_percpu(shared_msrs);
5652 }
5653
5654 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5655 {
5656 ++vcpu->stat.halt_exits;
5657 if (irqchip_in_kernel(vcpu->kvm)) {
5658 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5659 return 1;
5660 } else {
5661 vcpu->run->exit_reason = KVM_EXIT_HLT;
5662 return 0;
5663 }
5664 }
5665 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5666
5667 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5668 {
5669 u64 param, ingpa, outgpa, ret;
5670 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5671 bool fast, longmode;
5672 int cs_db, cs_l;
5673
5674 /*
5675 * hypercall generates UD from non zero cpl and real mode
5676 * per HYPER-V spec
5677 */
5678 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5679 kvm_queue_exception(vcpu, UD_VECTOR);
5680 return 0;
5681 }
5682
5683 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5684 longmode = is_long_mode(vcpu) && cs_l == 1;
5685
5686 if (!longmode) {
5687 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5688 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5689 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5690 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5691 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5692 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5693 }
5694 #ifdef CONFIG_X86_64
5695 else {
5696 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5697 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5698 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5699 }
5700 #endif
5701
5702 code = param & 0xffff;
5703 fast = (param >> 16) & 0x1;
5704 rep_cnt = (param >> 32) & 0xfff;
5705 rep_idx = (param >> 48) & 0xfff;
5706
5707 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5708
5709 switch (code) {
5710 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5711 kvm_vcpu_on_spin(vcpu);
5712 break;
5713 default:
5714 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5715 break;
5716 }
5717
5718 ret = res | (((u64)rep_done & 0xfff) << 32);
5719 if (longmode) {
5720 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5721 } else {
5722 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5723 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5724 }
5725
5726 return 1;
5727 }
5728
5729 /*
5730 * kvm_pv_kick_cpu_op: Kick a vcpu.
5731 *
5732 * @apicid - apicid of vcpu to be kicked.
5733 */
5734 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5735 {
5736 struct kvm_lapic_irq lapic_irq;
5737
5738 lapic_irq.shorthand = 0;
5739 lapic_irq.dest_mode = 0;
5740 lapic_irq.dest_id = apicid;
5741
5742 lapic_irq.delivery_mode = APIC_DM_REMRD;
5743 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
5744 }
5745
5746 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5747 {
5748 unsigned long nr, a0, a1, a2, a3, ret;
5749 int r = 1;
5750
5751 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5752 return kvm_hv_hypercall(vcpu);
5753
5754 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5755 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5756 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5757 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5758 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5759
5760 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5761
5762 if (!is_long_mode(vcpu)) {
5763 nr &= 0xFFFFFFFF;
5764 a0 &= 0xFFFFFFFF;
5765 a1 &= 0xFFFFFFFF;
5766 a2 &= 0xFFFFFFFF;
5767 a3 &= 0xFFFFFFFF;
5768 }
5769
5770 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5771 ret = -KVM_EPERM;
5772 goto out;
5773 }
5774
5775 switch (nr) {
5776 case KVM_HC_VAPIC_POLL_IRQ:
5777 ret = 0;
5778 break;
5779 case KVM_HC_KICK_CPU:
5780 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5781 ret = 0;
5782 break;
5783 default:
5784 ret = -KVM_ENOSYS;
5785 break;
5786 }
5787 out:
5788 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5789 ++vcpu->stat.hypercalls;
5790 return r;
5791 }
5792 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5793
5794 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5795 {
5796 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5797 char instruction[3];
5798 unsigned long rip = kvm_rip_read(vcpu);
5799
5800 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5801
5802 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5803 }
5804
5805 /*
5806 * Check if userspace requested an interrupt window, and that the
5807 * interrupt window is open.
5808 *
5809 * No need to exit to userspace if we already have an interrupt queued.
5810 */
5811 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5812 {
5813 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5814 vcpu->run->request_interrupt_window &&
5815 kvm_arch_interrupt_allowed(vcpu));
5816 }
5817
5818 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5819 {
5820 struct kvm_run *kvm_run = vcpu->run;
5821
5822 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5823 kvm_run->cr8 = kvm_get_cr8(vcpu);
5824 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5825 if (irqchip_in_kernel(vcpu->kvm))
5826 kvm_run->ready_for_interrupt_injection = 1;
5827 else
5828 kvm_run->ready_for_interrupt_injection =
5829 kvm_arch_interrupt_allowed(vcpu) &&
5830 !kvm_cpu_has_interrupt(vcpu) &&
5831 !kvm_event_needs_reinjection(vcpu);
5832 }
5833
5834 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5835 {
5836 int max_irr, tpr;
5837
5838 if (!kvm_x86_ops->update_cr8_intercept)
5839 return;
5840
5841 if (!vcpu->arch.apic)
5842 return;
5843
5844 if (!vcpu->arch.apic->vapic_addr)
5845 max_irr = kvm_lapic_find_highest_irr(vcpu);
5846 else
5847 max_irr = -1;
5848
5849 if (max_irr != -1)
5850 max_irr >>= 4;
5851
5852 tpr = kvm_lapic_get_cr8(vcpu);
5853
5854 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5855 }
5856
5857 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
5858 {
5859 int r;
5860
5861 /* try to reinject previous events if any */
5862 if (vcpu->arch.exception.pending) {
5863 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5864 vcpu->arch.exception.has_error_code,
5865 vcpu->arch.exception.error_code);
5866 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5867 vcpu->arch.exception.has_error_code,
5868 vcpu->arch.exception.error_code,
5869 vcpu->arch.exception.reinject);
5870 return 0;
5871 }
5872
5873 if (vcpu->arch.nmi_injected) {
5874 kvm_x86_ops->set_nmi(vcpu);
5875 return 0;
5876 }
5877
5878 if (vcpu->arch.interrupt.pending) {
5879 kvm_x86_ops->set_irq(vcpu);
5880 return 0;
5881 }
5882
5883 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5884 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5885 if (r != 0)
5886 return r;
5887 }
5888
5889 /* try to inject new event if pending */
5890 if (vcpu->arch.nmi_pending) {
5891 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5892 --vcpu->arch.nmi_pending;
5893 vcpu->arch.nmi_injected = true;
5894 kvm_x86_ops->set_nmi(vcpu);
5895 }
5896 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5897 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5898 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5899 false);
5900 kvm_x86_ops->set_irq(vcpu);
5901 }
5902 }
5903 return 0;
5904 }
5905
5906 static void process_nmi(struct kvm_vcpu *vcpu)
5907 {
5908 unsigned limit = 2;
5909
5910 /*
5911 * x86 is limited to one NMI running, and one NMI pending after it.
5912 * If an NMI is already in progress, limit further NMIs to just one.
5913 * Otherwise, allow two (and we'll inject the first one immediately).
5914 */
5915 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5916 limit = 1;
5917
5918 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5919 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5920 kvm_make_request(KVM_REQ_EVENT, vcpu);
5921 }
5922
5923 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
5924 {
5925 u64 eoi_exit_bitmap[4];
5926 u32 tmr[8];
5927
5928 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5929 return;
5930
5931 memset(eoi_exit_bitmap, 0, 32);
5932 memset(tmr, 0, 32);
5933
5934 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
5935 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
5936 kvm_apic_update_tmr(vcpu, tmr);
5937 }
5938
5939 /*
5940 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5941 * exiting to the userspace. Otherwise, the value will be returned to the
5942 * userspace.
5943 */
5944 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5945 {
5946 int r;
5947 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5948 vcpu->run->request_interrupt_window;
5949 bool req_immediate_exit = false;
5950
5951 if (vcpu->requests) {
5952 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5953 kvm_mmu_unload(vcpu);
5954 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5955 __kvm_migrate_timers(vcpu);
5956 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5957 kvm_gen_update_masterclock(vcpu->kvm);
5958 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5959 kvm_gen_kvmclock_update(vcpu);
5960 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5961 r = kvm_guest_time_update(vcpu);
5962 if (unlikely(r))
5963 goto out;
5964 }
5965 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5966 kvm_mmu_sync_roots(vcpu);
5967 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5968 kvm_x86_ops->tlb_flush(vcpu);
5969 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5970 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5971 r = 0;
5972 goto out;
5973 }
5974 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5975 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5976 r = 0;
5977 goto out;
5978 }
5979 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5980 vcpu->fpu_active = 0;
5981 kvm_x86_ops->fpu_deactivate(vcpu);
5982 }
5983 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5984 /* Page is swapped out. Do synthetic halt */
5985 vcpu->arch.apf.halted = true;
5986 r = 1;
5987 goto out;
5988 }
5989 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5990 record_steal_time(vcpu);
5991 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5992 process_nmi(vcpu);
5993 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5994 kvm_handle_pmu_event(vcpu);
5995 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5996 kvm_deliver_pmi(vcpu);
5997 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5998 vcpu_scan_ioapic(vcpu);
5999 }
6000
6001 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6002 kvm_apic_accept_events(vcpu);
6003 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6004 r = 1;
6005 goto out;
6006 }
6007
6008 if (inject_pending_event(vcpu, req_int_win) != 0)
6009 req_immediate_exit = true;
6010 /* enable NMI/IRQ window open exits if needed */
6011 else if (vcpu->arch.nmi_pending)
6012 kvm_x86_ops->enable_nmi_window(vcpu);
6013 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6014 kvm_x86_ops->enable_irq_window(vcpu);
6015
6016 if (kvm_lapic_enabled(vcpu)) {
6017 /*
6018 * Update architecture specific hints for APIC
6019 * virtual interrupt delivery.
6020 */
6021 if (kvm_x86_ops->hwapic_irr_update)
6022 kvm_x86_ops->hwapic_irr_update(vcpu,
6023 kvm_lapic_find_highest_irr(vcpu));
6024 update_cr8_intercept(vcpu);
6025 kvm_lapic_sync_to_vapic(vcpu);
6026 }
6027 }
6028
6029 r = kvm_mmu_reload(vcpu);
6030 if (unlikely(r)) {
6031 goto cancel_injection;
6032 }
6033
6034 preempt_disable();
6035
6036 kvm_x86_ops->prepare_guest_switch(vcpu);
6037 if (vcpu->fpu_active)
6038 kvm_load_guest_fpu(vcpu);
6039 kvm_load_guest_xcr0(vcpu);
6040
6041 vcpu->mode = IN_GUEST_MODE;
6042
6043 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6044
6045 /* We should set ->mode before check ->requests,
6046 * see the comment in make_all_cpus_request.
6047 */
6048 smp_mb__after_srcu_read_unlock();
6049
6050 local_irq_disable();
6051
6052 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6053 || need_resched() || signal_pending(current)) {
6054 vcpu->mode = OUTSIDE_GUEST_MODE;
6055 smp_wmb();
6056 local_irq_enable();
6057 preempt_enable();
6058 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6059 r = 1;
6060 goto cancel_injection;
6061 }
6062
6063 if (req_immediate_exit)
6064 smp_send_reschedule(vcpu->cpu);
6065
6066 kvm_guest_enter();
6067
6068 if (unlikely(vcpu->arch.switch_db_regs)) {
6069 set_debugreg(0, 7);
6070 set_debugreg(vcpu->arch.eff_db[0], 0);
6071 set_debugreg(vcpu->arch.eff_db[1], 1);
6072 set_debugreg(vcpu->arch.eff_db[2], 2);
6073 set_debugreg(vcpu->arch.eff_db[3], 3);
6074 set_debugreg(vcpu->arch.dr6, 6);
6075 }
6076
6077 trace_kvm_entry(vcpu->vcpu_id);
6078 kvm_x86_ops->run(vcpu);
6079
6080 /*
6081 * Do this here before restoring debug registers on the host. And
6082 * since we do this before handling the vmexit, a DR access vmexit
6083 * can (a) read the correct value of the debug registers, (b) set
6084 * KVM_DEBUGREG_WONT_EXIT again.
6085 */
6086 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6087 int i;
6088
6089 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6090 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6091 for (i = 0; i < KVM_NR_DB_REGS; i++)
6092 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6093 }
6094
6095 /*
6096 * If the guest has used debug registers, at least dr7
6097 * will be disabled while returning to the host.
6098 * If we don't have active breakpoints in the host, we don't
6099 * care about the messed up debug address registers. But if
6100 * we have some of them active, restore the old state.
6101 */
6102 if (hw_breakpoint_active())
6103 hw_breakpoint_restore();
6104
6105 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6106 native_read_tsc());
6107
6108 vcpu->mode = OUTSIDE_GUEST_MODE;
6109 smp_wmb();
6110
6111 /* Interrupt is enabled by handle_external_intr() */
6112 kvm_x86_ops->handle_external_intr(vcpu);
6113
6114 ++vcpu->stat.exits;
6115
6116 /*
6117 * We must have an instruction between local_irq_enable() and
6118 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6119 * the interrupt shadow. The stat.exits increment will do nicely.
6120 * But we need to prevent reordering, hence this barrier():
6121 */
6122 barrier();
6123
6124 kvm_guest_exit();
6125
6126 preempt_enable();
6127
6128 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6129
6130 /*
6131 * Profile KVM exit RIPs:
6132 */
6133 if (unlikely(prof_on == KVM_PROFILING)) {
6134 unsigned long rip = kvm_rip_read(vcpu);
6135 profile_hit(KVM_PROFILING, (void *)rip);
6136 }
6137
6138 if (unlikely(vcpu->arch.tsc_always_catchup))
6139 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6140
6141 if (vcpu->arch.apic_attention)
6142 kvm_lapic_sync_from_vapic(vcpu);
6143
6144 r = kvm_x86_ops->handle_exit(vcpu);
6145 return r;
6146
6147 cancel_injection:
6148 kvm_x86_ops->cancel_injection(vcpu);
6149 if (unlikely(vcpu->arch.apic_attention))
6150 kvm_lapic_sync_from_vapic(vcpu);
6151 out:
6152 return r;
6153 }
6154
6155
6156 static int __vcpu_run(struct kvm_vcpu *vcpu)
6157 {
6158 int r;
6159 struct kvm *kvm = vcpu->kvm;
6160
6161 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6162
6163 r = 1;
6164 while (r > 0) {
6165 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6166 !vcpu->arch.apf.halted)
6167 r = vcpu_enter_guest(vcpu);
6168 else {
6169 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6170 kvm_vcpu_block(vcpu);
6171 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6172 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6173 kvm_apic_accept_events(vcpu);
6174 switch(vcpu->arch.mp_state) {
6175 case KVM_MP_STATE_HALTED:
6176 vcpu->arch.pv.pv_unhalted = false;
6177 vcpu->arch.mp_state =
6178 KVM_MP_STATE_RUNNABLE;
6179 case KVM_MP_STATE_RUNNABLE:
6180 vcpu->arch.apf.halted = false;
6181 break;
6182 case KVM_MP_STATE_INIT_RECEIVED:
6183 break;
6184 default:
6185 r = -EINTR;
6186 break;
6187 }
6188 }
6189 }
6190
6191 if (r <= 0)
6192 break;
6193
6194 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6195 if (kvm_cpu_has_pending_timer(vcpu))
6196 kvm_inject_pending_timer_irqs(vcpu);
6197
6198 if (dm_request_for_irq_injection(vcpu)) {
6199 r = -EINTR;
6200 vcpu->run->exit_reason = KVM_EXIT_INTR;
6201 ++vcpu->stat.request_irq_exits;
6202 }
6203
6204 kvm_check_async_pf_completion(vcpu);
6205
6206 if (signal_pending(current)) {
6207 r = -EINTR;
6208 vcpu->run->exit_reason = KVM_EXIT_INTR;
6209 ++vcpu->stat.signal_exits;
6210 }
6211 if (need_resched()) {
6212 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6213 cond_resched();
6214 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6215 }
6216 }
6217
6218 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6219
6220 return r;
6221 }
6222
6223 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6224 {
6225 int r;
6226 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6227 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6228 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6229 if (r != EMULATE_DONE)
6230 return 0;
6231 return 1;
6232 }
6233
6234 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6235 {
6236 BUG_ON(!vcpu->arch.pio.count);
6237
6238 return complete_emulated_io(vcpu);
6239 }
6240
6241 /*
6242 * Implements the following, as a state machine:
6243 *
6244 * read:
6245 * for each fragment
6246 * for each mmio piece in the fragment
6247 * write gpa, len
6248 * exit
6249 * copy data
6250 * execute insn
6251 *
6252 * write:
6253 * for each fragment
6254 * for each mmio piece in the fragment
6255 * write gpa, len
6256 * copy data
6257 * exit
6258 */
6259 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6260 {
6261 struct kvm_run *run = vcpu->run;
6262 struct kvm_mmio_fragment *frag;
6263 unsigned len;
6264
6265 BUG_ON(!vcpu->mmio_needed);
6266
6267 /* Complete previous fragment */
6268 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6269 len = min(8u, frag->len);
6270 if (!vcpu->mmio_is_write)
6271 memcpy(frag->data, run->mmio.data, len);
6272
6273 if (frag->len <= 8) {
6274 /* Switch to the next fragment. */
6275 frag++;
6276 vcpu->mmio_cur_fragment++;
6277 } else {
6278 /* Go forward to the next mmio piece. */
6279 frag->data += len;
6280 frag->gpa += len;
6281 frag->len -= len;
6282 }
6283
6284 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6285 vcpu->mmio_needed = 0;
6286
6287 /* FIXME: return into emulator if single-stepping. */
6288 if (vcpu->mmio_is_write)
6289 return 1;
6290 vcpu->mmio_read_completed = 1;
6291 return complete_emulated_io(vcpu);
6292 }
6293
6294 run->exit_reason = KVM_EXIT_MMIO;
6295 run->mmio.phys_addr = frag->gpa;
6296 if (vcpu->mmio_is_write)
6297 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6298 run->mmio.len = min(8u, frag->len);
6299 run->mmio.is_write = vcpu->mmio_is_write;
6300 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6301 return 0;
6302 }
6303
6304
6305 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6306 {
6307 int r;
6308 sigset_t sigsaved;
6309
6310 if (!tsk_used_math(current) && init_fpu(current))
6311 return -ENOMEM;
6312
6313 if (vcpu->sigset_active)
6314 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6315
6316 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6317 kvm_vcpu_block(vcpu);
6318 kvm_apic_accept_events(vcpu);
6319 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6320 r = -EAGAIN;
6321 goto out;
6322 }
6323
6324 /* re-sync apic's tpr */
6325 if (!irqchip_in_kernel(vcpu->kvm)) {
6326 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6327 r = -EINVAL;
6328 goto out;
6329 }
6330 }
6331
6332 if (unlikely(vcpu->arch.complete_userspace_io)) {
6333 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6334 vcpu->arch.complete_userspace_io = NULL;
6335 r = cui(vcpu);
6336 if (r <= 0)
6337 goto out;
6338 } else
6339 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6340
6341 r = __vcpu_run(vcpu);
6342
6343 out:
6344 post_kvm_run_save(vcpu);
6345 if (vcpu->sigset_active)
6346 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6347
6348 return r;
6349 }
6350
6351 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6352 {
6353 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6354 /*
6355 * We are here if userspace calls get_regs() in the middle of
6356 * instruction emulation. Registers state needs to be copied
6357 * back from emulation context to vcpu. Userspace shouldn't do
6358 * that usually, but some bad designed PV devices (vmware
6359 * backdoor interface) need this to work
6360 */
6361 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6362 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6363 }
6364 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6365 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6366 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6367 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6368 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6369 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6370 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6371 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6372 #ifdef CONFIG_X86_64
6373 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6374 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6375 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6376 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6377 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6378 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6379 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6380 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6381 #endif
6382
6383 regs->rip = kvm_rip_read(vcpu);
6384 regs->rflags = kvm_get_rflags(vcpu);
6385
6386 return 0;
6387 }
6388
6389 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6390 {
6391 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6392 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6393
6394 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6395 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6396 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6397 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6398 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6399 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6400 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6401 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6402 #ifdef CONFIG_X86_64
6403 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6404 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6405 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6406 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6407 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6408 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6409 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6410 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6411 #endif
6412
6413 kvm_rip_write(vcpu, regs->rip);
6414 kvm_set_rflags(vcpu, regs->rflags);
6415
6416 vcpu->arch.exception.pending = false;
6417
6418 kvm_make_request(KVM_REQ_EVENT, vcpu);
6419
6420 return 0;
6421 }
6422
6423 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6424 {
6425 struct kvm_segment cs;
6426
6427 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6428 *db = cs.db;
6429 *l = cs.l;
6430 }
6431 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6432
6433 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6434 struct kvm_sregs *sregs)
6435 {
6436 struct desc_ptr dt;
6437
6438 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6439 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6440 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6441 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6442 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6443 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6444
6445 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6446 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6447
6448 kvm_x86_ops->get_idt(vcpu, &dt);
6449 sregs->idt.limit = dt.size;
6450 sregs->idt.base = dt.address;
6451 kvm_x86_ops->get_gdt(vcpu, &dt);
6452 sregs->gdt.limit = dt.size;
6453 sregs->gdt.base = dt.address;
6454
6455 sregs->cr0 = kvm_read_cr0(vcpu);
6456 sregs->cr2 = vcpu->arch.cr2;
6457 sregs->cr3 = kvm_read_cr3(vcpu);
6458 sregs->cr4 = kvm_read_cr4(vcpu);
6459 sregs->cr8 = kvm_get_cr8(vcpu);
6460 sregs->efer = vcpu->arch.efer;
6461 sregs->apic_base = kvm_get_apic_base(vcpu);
6462
6463 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6464
6465 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6466 set_bit(vcpu->arch.interrupt.nr,
6467 (unsigned long *)sregs->interrupt_bitmap);
6468
6469 return 0;
6470 }
6471
6472 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6473 struct kvm_mp_state *mp_state)
6474 {
6475 kvm_apic_accept_events(vcpu);
6476 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6477 vcpu->arch.pv.pv_unhalted)
6478 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6479 else
6480 mp_state->mp_state = vcpu->arch.mp_state;
6481
6482 return 0;
6483 }
6484
6485 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6486 struct kvm_mp_state *mp_state)
6487 {
6488 if (!kvm_vcpu_has_lapic(vcpu) &&
6489 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6490 return -EINVAL;
6491
6492 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6493 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6494 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6495 } else
6496 vcpu->arch.mp_state = mp_state->mp_state;
6497 kvm_make_request(KVM_REQ_EVENT, vcpu);
6498 return 0;
6499 }
6500
6501 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6502 int reason, bool has_error_code, u32 error_code)
6503 {
6504 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6505 int ret;
6506
6507 init_emulate_ctxt(vcpu);
6508
6509 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6510 has_error_code, error_code);
6511
6512 if (ret)
6513 return EMULATE_FAIL;
6514
6515 kvm_rip_write(vcpu, ctxt->eip);
6516 kvm_set_rflags(vcpu, ctxt->eflags);
6517 kvm_make_request(KVM_REQ_EVENT, vcpu);
6518 return EMULATE_DONE;
6519 }
6520 EXPORT_SYMBOL_GPL(kvm_task_switch);
6521
6522 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6523 struct kvm_sregs *sregs)
6524 {
6525 struct msr_data apic_base_msr;
6526 int mmu_reset_needed = 0;
6527 int pending_vec, max_bits, idx;
6528 struct desc_ptr dt;
6529
6530 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6531 return -EINVAL;
6532
6533 dt.size = sregs->idt.limit;
6534 dt.address = sregs->idt.base;
6535 kvm_x86_ops->set_idt(vcpu, &dt);
6536 dt.size = sregs->gdt.limit;
6537 dt.address = sregs->gdt.base;
6538 kvm_x86_ops->set_gdt(vcpu, &dt);
6539
6540 vcpu->arch.cr2 = sregs->cr2;
6541 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6542 vcpu->arch.cr3 = sregs->cr3;
6543 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6544
6545 kvm_set_cr8(vcpu, sregs->cr8);
6546
6547 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6548 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6549 apic_base_msr.data = sregs->apic_base;
6550 apic_base_msr.host_initiated = true;
6551 kvm_set_apic_base(vcpu, &apic_base_msr);
6552
6553 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6554 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6555 vcpu->arch.cr0 = sregs->cr0;
6556
6557 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6558 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6559 if (sregs->cr4 & X86_CR4_OSXSAVE)
6560 kvm_update_cpuid(vcpu);
6561
6562 idx = srcu_read_lock(&vcpu->kvm->srcu);
6563 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6564 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6565 mmu_reset_needed = 1;
6566 }
6567 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6568
6569 if (mmu_reset_needed)
6570 kvm_mmu_reset_context(vcpu);
6571
6572 max_bits = KVM_NR_INTERRUPTS;
6573 pending_vec = find_first_bit(
6574 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6575 if (pending_vec < max_bits) {
6576 kvm_queue_interrupt(vcpu, pending_vec, false);
6577 pr_debug("Set back pending irq %d\n", pending_vec);
6578 }
6579
6580 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6581 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6582 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6583 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6584 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6585 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6586
6587 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6588 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6589
6590 update_cr8_intercept(vcpu);
6591
6592 /* Older userspace won't unhalt the vcpu on reset. */
6593 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6594 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6595 !is_protmode(vcpu))
6596 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6597
6598 kvm_make_request(KVM_REQ_EVENT, vcpu);
6599
6600 return 0;
6601 }
6602
6603 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6604 struct kvm_guest_debug *dbg)
6605 {
6606 unsigned long rflags;
6607 int i, r;
6608
6609 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6610 r = -EBUSY;
6611 if (vcpu->arch.exception.pending)
6612 goto out;
6613 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6614 kvm_queue_exception(vcpu, DB_VECTOR);
6615 else
6616 kvm_queue_exception(vcpu, BP_VECTOR);
6617 }
6618
6619 /*
6620 * Read rflags as long as potentially injected trace flags are still
6621 * filtered out.
6622 */
6623 rflags = kvm_get_rflags(vcpu);
6624
6625 vcpu->guest_debug = dbg->control;
6626 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6627 vcpu->guest_debug = 0;
6628
6629 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6630 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6631 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6632 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6633 } else {
6634 for (i = 0; i < KVM_NR_DB_REGS; i++)
6635 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6636 }
6637 kvm_update_dr7(vcpu);
6638
6639 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6640 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6641 get_segment_base(vcpu, VCPU_SREG_CS);
6642
6643 /*
6644 * Trigger an rflags update that will inject or remove the trace
6645 * flags.
6646 */
6647 kvm_set_rflags(vcpu, rflags);
6648
6649 kvm_x86_ops->update_db_bp_intercept(vcpu);
6650
6651 r = 0;
6652
6653 out:
6654
6655 return r;
6656 }
6657
6658 /*
6659 * Translate a guest virtual address to a guest physical address.
6660 */
6661 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6662 struct kvm_translation *tr)
6663 {
6664 unsigned long vaddr = tr->linear_address;
6665 gpa_t gpa;
6666 int idx;
6667
6668 idx = srcu_read_lock(&vcpu->kvm->srcu);
6669 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6670 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6671 tr->physical_address = gpa;
6672 tr->valid = gpa != UNMAPPED_GVA;
6673 tr->writeable = 1;
6674 tr->usermode = 0;
6675
6676 return 0;
6677 }
6678
6679 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6680 {
6681 struct i387_fxsave_struct *fxsave =
6682 &vcpu->arch.guest_fpu.state->fxsave;
6683
6684 memcpy(fpu->fpr, fxsave->st_space, 128);
6685 fpu->fcw = fxsave->cwd;
6686 fpu->fsw = fxsave->swd;
6687 fpu->ftwx = fxsave->twd;
6688 fpu->last_opcode = fxsave->fop;
6689 fpu->last_ip = fxsave->rip;
6690 fpu->last_dp = fxsave->rdp;
6691 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6692
6693 return 0;
6694 }
6695
6696 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6697 {
6698 struct i387_fxsave_struct *fxsave =
6699 &vcpu->arch.guest_fpu.state->fxsave;
6700
6701 memcpy(fxsave->st_space, fpu->fpr, 128);
6702 fxsave->cwd = fpu->fcw;
6703 fxsave->swd = fpu->fsw;
6704 fxsave->twd = fpu->ftwx;
6705 fxsave->fop = fpu->last_opcode;
6706 fxsave->rip = fpu->last_ip;
6707 fxsave->rdp = fpu->last_dp;
6708 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6709
6710 return 0;
6711 }
6712
6713 int fx_init(struct kvm_vcpu *vcpu)
6714 {
6715 int err;
6716
6717 err = fpu_alloc(&vcpu->arch.guest_fpu);
6718 if (err)
6719 return err;
6720
6721 fpu_finit(&vcpu->arch.guest_fpu);
6722
6723 /*
6724 * Ensure guest xcr0 is valid for loading
6725 */
6726 vcpu->arch.xcr0 = XSTATE_FP;
6727
6728 vcpu->arch.cr0 |= X86_CR0_ET;
6729
6730 return 0;
6731 }
6732 EXPORT_SYMBOL_GPL(fx_init);
6733
6734 static void fx_free(struct kvm_vcpu *vcpu)
6735 {
6736 fpu_free(&vcpu->arch.guest_fpu);
6737 }
6738
6739 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6740 {
6741 if (vcpu->guest_fpu_loaded)
6742 return;
6743
6744 /*
6745 * Restore all possible states in the guest,
6746 * and assume host would use all available bits.
6747 * Guest xcr0 would be loaded later.
6748 */
6749 kvm_put_guest_xcr0(vcpu);
6750 vcpu->guest_fpu_loaded = 1;
6751 __kernel_fpu_begin();
6752 fpu_restore_checking(&vcpu->arch.guest_fpu);
6753 trace_kvm_fpu(1);
6754 }
6755
6756 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6757 {
6758 kvm_put_guest_xcr0(vcpu);
6759
6760 if (!vcpu->guest_fpu_loaded)
6761 return;
6762
6763 vcpu->guest_fpu_loaded = 0;
6764 fpu_save_init(&vcpu->arch.guest_fpu);
6765 __kernel_fpu_end();
6766 ++vcpu->stat.fpu_reload;
6767 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
6768 trace_kvm_fpu(0);
6769 }
6770
6771 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6772 {
6773 kvmclock_reset(vcpu);
6774
6775 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6776 fx_free(vcpu);
6777 kvm_x86_ops->vcpu_free(vcpu);
6778 }
6779
6780 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6781 unsigned int id)
6782 {
6783 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6784 printk_once(KERN_WARNING
6785 "kvm: SMP vm created on host with unstable TSC; "
6786 "guest TSC will not be reliable\n");
6787 return kvm_x86_ops->vcpu_create(kvm, id);
6788 }
6789
6790 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6791 {
6792 int r;
6793
6794 vcpu->arch.mtrr_state.have_fixed = 1;
6795 r = vcpu_load(vcpu);
6796 if (r)
6797 return r;
6798 kvm_vcpu_reset(vcpu);
6799 kvm_mmu_setup(vcpu);
6800 vcpu_put(vcpu);
6801
6802 return r;
6803 }
6804
6805 int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6806 {
6807 int r;
6808 struct msr_data msr;
6809 struct kvm *kvm = vcpu->kvm;
6810
6811 r = vcpu_load(vcpu);
6812 if (r)
6813 return r;
6814 msr.data = 0x0;
6815 msr.index = MSR_IA32_TSC;
6816 msr.host_initiated = true;
6817 kvm_write_tsc(vcpu, &msr);
6818 vcpu_put(vcpu);
6819
6820 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6821 KVMCLOCK_SYNC_PERIOD);
6822
6823 return r;
6824 }
6825
6826 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6827 {
6828 int r;
6829 vcpu->arch.apf.msr_val = 0;
6830
6831 r = vcpu_load(vcpu);
6832 BUG_ON(r);
6833 kvm_mmu_unload(vcpu);
6834 vcpu_put(vcpu);
6835
6836 fx_free(vcpu);
6837 kvm_x86_ops->vcpu_free(vcpu);
6838 }
6839
6840 void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
6841 {
6842 atomic_set(&vcpu->arch.nmi_queued, 0);
6843 vcpu->arch.nmi_pending = 0;
6844 vcpu->arch.nmi_injected = false;
6845
6846 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6847 vcpu->arch.dr6 = DR6_FIXED_1;
6848 kvm_update_dr6(vcpu);
6849 vcpu->arch.dr7 = DR7_FIXED_1;
6850 kvm_update_dr7(vcpu);
6851
6852 kvm_make_request(KVM_REQ_EVENT, vcpu);
6853 vcpu->arch.apf.msr_val = 0;
6854 vcpu->arch.st.msr_val = 0;
6855
6856 kvmclock_reset(vcpu);
6857
6858 kvm_clear_async_pf_completion_queue(vcpu);
6859 kvm_async_pf_hash_reset(vcpu);
6860 vcpu->arch.apf.halted = false;
6861
6862 kvm_pmu_reset(vcpu);
6863
6864 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6865 vcpu->arch.regs_avail = ~0;
6866 vcpu->arch.regs_dirty = ~0;
6867
6868 kvm_x86_ops->vcpu_reset(vcpu);
6869 }
6870
6871 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6872 {
6873 struct kvm_segment cs;
6874
6875 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6876 cs.selector = vector << 8;
6877 cs.base = vector << 12;
6878 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6879 kvm_rip_write(vcpu, 0);
6880 }
6881
6882 int kvm_arch_hardware_enable(void *garbage)
6883 {
6884 struct kvm *kvm;
6885 struct kvm_vcpu *vcpu;
6886 int i;
6887 int ret;
6888 u64 local_tsc;
6889 u64 max_tsc = 0;
6890 bool stable, backwards_tsc = false;
6891
6892 kvm_shared_msr_cpu_online();
6893 ret = kvm_x86_ops->hardware_enable(garbage);
6894 if (ret != 0)
6895 return ret;
6896
6897 local_tsc = native_read_tsc();
6898 stable = !check_tsc_unstable();
6899 list_for_each_entry(kvm, &vm_list, vm_list) {
6900 kvm_for_each_vcpu(i, vcpu, kvm) {
6901 if (!stable && vcpu->cpu == smp_processor_id())
6902 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6903 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6904 backwards_tsc = true;
6905 if (vcpu->arch.last_host_tsc > max_tsc)
6906 max_tsc = vcpu->arch.last_host_tsc;
6907 }
6908 }
6909 }
6910
6911 /*
6912 * Sometimes, even reliable TSCs go backwards. This happens on
6913 * platforms that reset TSC during suspend or hibernate actions, but
6914 * maintain synchronization. We must compensate. Fortunately, we can
6915 * detect that condition here, which happens early in CPU bringup,
6916 * before any KVM threads can be running. Unfortunately, we can't
6917 * bring the TSCs fully up to date with real time, as we aren't yet far
6918 * enough into CPU bringup that we know how much real time has actually
6919 * elapsed; our helper function, get_kernel_ns() will be using boot
6920 * variables that haven't been updated yet.
6921 *
6922 * So we simply find the maximum observed TSC above, then record the
6923 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6924 * the adjustment will be applied. Note that we accumulate
6925 * adjustments, in case multiple suspend cycles happen before some VCPU
6926 * gets a chance to run again. In the event that no KVM threads get a
6927 * chance to run, we will miss the entire elapsed period, as we'll have
6928 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6929 * loose cycle time. This isn't too big a deal, since the loss will be
6930 * uniform across all VCPUs (not to mention the scenario is extremely
6931 * unlikely). It is possible that a second hibernate recovery happens
6932 * much faster than a first, causing the observed TSC here to be
6933 * smaller; this would require additional padding adjustment, which is
6934 * why we set last_host_tsc to the local tsc observed here.
6935 *
6936 * N.B. - this code below runs only on platforms with reliable TSC,
6937 * as that is the only way backwards_tsc is set above. Also note
6938 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6939 * have the same delta_cyc adjustment applied if backwards_tsc
6940 * is detected. Note further, this adjustment is only done once,
6941 * as we reset last_host_tsc on all VCPUs to stop this from being
6942 * called multiple times (one for each physical CPU bringup).
6943 *
6944 * Platforms with unreliable TSCs don't have to deal with this, they
6945 * will be compensated by the logic in vcpu_load, which sets the TSC to
6946 * catchup mode. This will catchup all VCPUs to real time, but cannot
6947 * guarantee that they stay in perfect synchronization.
6948 */
6949 if (backwards_tsc) {
6950 u64 delta_cyc = max_tsc - local_tsc;
6951 backwards_tsc_observed = true;
6952 list_for_each_entry(kvm, &vm_list, vm_list) {
6953 kvm_for_each_vcpu(i, vcpu, kvm) {
6954 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6955 vcpu->arch.last_host_tsc = local_tsc;
6956 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6957 &vcpu->requests);
6958 }
6959
6960 /*
6961 * We have to disable TSC offset matching.. if you were
6962 * booting a VM while issuing an S4 host suspend....
6963 * you may have some problem. Solving this issue is
6964 * left as an exercise to the reader.
6965 */
6966 kvm->arch.last_tsc_nsec = 0;
6967 kvm->arch.last_tsc_write = 0;
6968 }
6969
6970 }
6971 return 0;
6972 }
6973
6974 void kvm_arch_hardware_disable(void *garbage)
6975 {
6976 kvm_x86_ops->hardware_disable(garbage);
6977 drop_user_return_notifiers(garbage);
6978 }
6979
6980 int kvm_arch_hardware_setup(void)
6981 {
6982 return kvm_x86_ops->hardware_setup();
6983 }
6984
6985 void kvm_arch_hardware_unsetup(void)
6986 {
6987 kvm_x86_ops->hardware_unsetup();
6988 }
6989
6990 void kvm_arch_check_processor_compat(void *rtn)
6991 {
6992 kvm_x86_ops->check_processor_compatibility(rtn);
6993 }
6994
6995 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6996 {
6997 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6998 }
6999
7000 struct static_key kvm_no_apic_vcpu __read_mostly;
7001
7002 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7003 {
7004 struct page *page;
7005 struct kvm *kvm;
7006 int r;
7007
7008 BUG_ON(vcpu->kvm == NULL);
7009 kvm = vcpu->kvm;
7010
7011 vcpu->arch.pv.pv_unhalted = false;
7012 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7013 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
7014 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7015 else
7016 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7017
7018 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7019 if (!page) {
7020 r = -ENOMEM;
7021 goto fail;
7022 }
7023 vcpu->arch.pio_data = page_address(page);
7024
7025 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7026
7027 r = kvm_mmu_create(vcpu);
7028 if (r < 0)
7029 goto fail_free_pio_data;
7030
7031 if (irqchip_in_kernel(kvm)) {
7032 r = kvm_create_lapic(vcpu);
7033 if (r < 0)
7034 goto fail_mmu_destroy;
7035 } else
7036 static_key_slow_inc(&kvm_no_apic_vcpu);
7037
7038 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7039 GFP_KERNEL);
7040 if (!vcpu->arch.mce_banks) {
7041 r = -ENOMEM;
7042 goto fail_free_lapic;
7043 }
7044 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7045
7046 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7047 r = -ENOMEM;
7048 goto fail_free_mce_banks;
7049 }
7050
7051 r = fx_init(vcpu);
7052 if (r)
7053 goto fail_free_wbinvd_dirty_mask;
7054
7055 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7056 vcpu->arch.pv_time_enabled = false;
7057
7058 vcpu->arch.guest_supported_xcr0 = 0;
7059 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7060
7061 kvm_async_pf_hash_reset(vcpu);
7062 kvm_pmu_init(vcpu);
7063
7064 return 0;
7065 fail_free_wbinvd_dirty_mask:
7066 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7067 fail_free_mce_banks:
7068 kfree(vcpu->arch.mce_banks);
7069 fail_free_lapic:
7070 kvm_free_lapic(vcpu);
7071 fail_mmu_destroy:
7072 kvm_mmu_destroy(vcpu);
7073 fail_free_pio_data:
7074 free_page((unsigned long)vcpu->arch.pio_data);
7075 fail:
7076 return r;
7077 }
7078
7079 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7080 {
7081 int idx;
7082
7083 kvm_pmu_destroy(vcpu);
7084 kfree(vcpu->arch.mce_banks);
7085 kvm_free_lapic(vcpu);
7086 idx = srcu_read_lock(&vcpu->kvm->srcu);
7087 kvm_mmu_destroy(vcpu);
7088 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7089 free_page((unsigned long)vcpu->arch.pio_data);
7090 if (!irqchip_in_kernel(vcpu->kvm))
7091 static_key_slow_dec(&kvm_no_apic_vcpu);
7092 }
7093
7094 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7095 {
7096 if (type)
7097 return -EINVAL;
7098
7099 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7100 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7101 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7102 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7103
7104 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7105 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7106 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7107 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7108 &kvm->arch.irq_sources_bitmap);
7109
7110 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7111 mutex_init(&kvm->arch.apic_map_lock);
7112 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7113
7114 pvclock_update_vm_gtod_copy(kvm);
7115
7116 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7117 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7118
7119 return 0;
7120 }
7121
7122 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7123 {
7124 int r;
7125 r = vcpu_load(vcpu);
7126 BUG_ON(r);
7127 kvm_mmu_unload(vcpu);
7128 vcpu_put(vcpu);
7129 }
7130
7131 static void kvm_free_vcpus(struct kvm *kvm)
7132 {
7133 unsigned int i;
7134 struct kvm_vcpu *vcpu;
7135
7136 /*
7137 * Unpin any mmu pages first.
7138 */
7139 kvm_for_each_vcpu(i, vcpu, kvm) {
7140 kvm_clear_async_pf_completion_queue(vcpu);
7141 kvm_unload_vcpu_mmu(vcpu);
7142 }
7143 kvm_for_each_vcpu(i, vcpu, kvm)
7144 kvm_arch_vcpu_free(vcpu);
7145
7146 mutex_lock(&kvm->lock);
7147 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7148 kvm->vcpus[i] = NULL;
7149
7150 atomic_set(&kvm->online_vcpus, 0);
7151 mutex_unlock(&kvm->lock);
7152 }
7153
7154 void kvm_arch_sync_events(struct kvm *kvm)
7155 {
7156 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7157 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7158 kvm_free_all_assigned_devices(kvm);
7159 kvm_free_pit(kvm);
7160 }
7161
7162 void kvm_arch_destroy_vm(struct kvm *kvm)
7163 {
7164 if (current->mm == kvm->mm) {
7165 /*
7166 * Free memory regions allocated on behalf of userspace,
7167 * unless the the memory map has changed due to process exit
7168 * or fd copying.
7169 */
7170 struct kvm_userspace_memory_region mem;
7171 memset(&mem, 0, sizeof(mem));
7172 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7173 kvm_set_memory_region(kvm, &mem);
7174
7175 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7176 kvm_set_memory_region(kvm, &mem);
7177
7178 mem.slot = TSS_PRIVATE_MEMSLOT;
7179 kvm_set_memory_region(kvm, &mem);
7180 }
7181 kvm_iommu_unmap_guest(kvm);
7182 kfree(kvm->arch.vpic);
7183 kfree(kvm->arch.vioapic);
7184 kvm_free_vcpus(kvm);
7185 if (kvm->arch.apic_access_page)
7186 put_page(kvm->arch.apic_access_page);
7187 if (kvm->arch.ept_identity_pagetable)
7188 put_page(kvm->arch.ept_identity_pagetable);
7189 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7190 }
7191
7192 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7193 struct kvm_memory_slot *dont)
7194 {
7195 int i;
7196
7197 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7198 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7199 kvm_kvfree(free->arch.rmap[i]);
7200 free->arch.rmap[i] = NULL;
7201 }
7202 if (i == 0)
7203 continue;
7204
7205 if (!dont || free->arch.lpage_info[i - 1] !=
7206 dont->arch.lpage_info[i - 1]) {
7207 kvm_kvfree(free->arch.lpage_info[i - 1]);
7208 free->arch.lpage_info[i - 1] = NULL;
7209 }
7210 }
7211 }
7212
7213 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7214 unsigned long npages)
7215 {
7216 int i;
7217
7218 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7219 unsigned long ugfn;
7220 int lpages;
7221 int level = i + 1;
7222
7223 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7224 slot->base_gfn, level) + 1;
7225
7226 slot->arch.rmap[i] =
7227 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7228 if (!slot->arch.rmap[i])
7229 goto out_free;
7230 if (i == 0)
7231 continue;
7232
7233 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7234 sizeof(*slot->arch.lpage_info[i - 1]));
7235 if (!slot->arch.lpage_info[i - 1])
7236 goto out_free;
7237
7238 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7239 slot->arch.lpage_info[i - 1][0].write_count = 1;
7240 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7241 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7242 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7243 /*
7244 * If the gfn and userspace address are not aligned wrt each
7245 * other, or if explicitly asked to, disable large page
7246 * support for this slot
7247 */
7248 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7249 !kvm_largepages_enabled()) {
7250 unsigned long j;
7251
7252 for (j = 0; j < lpages; ++j)
7253 slot->arch.lpage_info[i - 1][j].write_count = 1;
7254 }
7255 }
7256
7257 return 0;
7258
7259 out_free:
7260 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7261 kvm_kvfree(slot->arch.rmap[i]);
7262 slot->arch.rmap[i] = NULL;
7263 if (i == 0)
7264 continue;
7265
7266 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7267 slot->arch.lpage_info[i - 1] = NULL;
7268 }
7269 return -ENOMEM;
7270 }
7271
7272 void kvm_arch_memslots_updated(struct kvm *kvm)
7273 {
7274 /*
7275 * memslots->generation has been incremented.
7276 * mmio generation may have reached its maximum value.
7277 */
7278 kvm_mmu_invalidate_mmio_sptes(kvm);
7279 }
7280
7281 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7282 struct kvm_memory_slot *memslot,
7283 struct kvm_userspace_memory_region *mem,
7284 enum kvm_mr_change change)
7285 {
7286 /*
7287 * Only private memory slots need to be mapped here since
7288 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
7289 */
7290 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7291 unsigned long userspace_addr;
7292
7293 /*
7294 * MAP_SHARED to prevent internal slot pages from being moved
7295 * by fork()/COW.
7296 */
7297 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7298 PROT_READ | PROT_WRITE,
7299 MAP_SHARED | MAP_ANONYMOUS, 0);
7300
7301 if (IS_ERR((void *)userspace_addr))
7302 return PTR_ERR((void *)userspace_addr);
7303
7304 memslot->userspace_addr = userspace_addr;
7305 }
7306
7307 return 0;
7308 }
7309
7310 void kvm_arch_commit_memory_region(struct kvm *kvm,
7311 struct kvm_userspace_memory_region *mem,
7312 const struct kvm_memory_slot *old,
7313 enum kvm_mr_change change)
7314 {
7315
7316 int nr_mmu_pages = 0;
7317
7318 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
7319 int ret;
7320
7321 ret = vm_munmap(old->userspace_addr,
7322 old->npages * PAGE_SIZE);
7323 if (ret < 0)
7324 printk(KERN_WARNING
7325 "kvm_vm_ioctl_set_memory_region: "
7326 "failed to munmap memory\n");
7327 }
7328
7329 if (!kvm->arch.n_requested_mmu_pages)
7330 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7331
7332 if (nr_mmu_pages)
7333 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7334 /*
7335 * Write protect all pages for dirty logging.
7336 *
7337 * All the sptes including the large sptes which point to this
7338 * slot are set to readonly. We can not create any new large
7339 * spte on this slot until the end of the logging.
7340 *
7341 * See the comments in fast_page_fault().
7342 */
7343 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
7344 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7345 }
7346
7347 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7348 {
7349 kvm_mmu_invalidate_zap_all_pages(kvm);
7350 }
7351
7352 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7353 struct kvm_memory_slot *slot)
7354 {
7355 kvm_mmu_invalidate_zap_all_pages(kvm);
7356 }
7357
7358 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7359 {
7360 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7361 kvm_x86_ops->check_nested_events(vcpu, false);
7362
7363 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7364 !vcpu->arch.apf.halted)
7365 || !list_empty_careful(&vcpu->async_pf.done)
7366 || kvm_apic_has_events(vcpu)
7367 || vcpu->arch.pv.pv_unhalted
7368 || atomic_read(&vcpu->arch.nmi_queued) ||
7369 (kvm_arch_interrupt_allowed(vcpu) &&
7370 kvm_cpu_has_interrupt(vcpu));
7371 }
7372
7373 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7374 {
7375 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7376 }
7377
7378 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7379 {
7380 return kvm_x86_ops->interrupt_allowed(vcpu);
7381 }
7382
7383 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7384 {
7385 unsigned long current_rip = kvm_rip_read(vcpu) +
7386 get_segment_base(vcpu, VCPU_SREG_CS);
7387
7388 return current_rip == linear_rip;
7389 }
7390 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7391
7392 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7393 {
7394 unsigned long rflags;
7395
7396 rflags = kvm_x86_ops->get_rflags(vcpu);
7397 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7398 rflags &= ~X86_EFLAGS_TF;
7399 return rflags;
7400 }
7401 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7402
7403 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7404 {
7405 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7406 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7407 rflags |= X86_EFLAGS_TF;
7408 kvm_x86_ops->set_rflags(vcpu, rflags);
7409 kvm_make_request(KVM_REQ_EVENT, vcpu);
7410 }
7411 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7412
7413 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7414 {
7415 int r;
7416
7417 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7418 work->wakeup_all)
7419 return;
7420
7421 r = kvm_mmu_reload(vcpu);
7422 if (unlikely(r))
7423 return;
7424
7425 if (!vcpu->arch.mmu.direct_map &&
7426 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7427 return;
7428
7429 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7430 }
7431
7432 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7433 {
7434 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7435 }
7436
7437 static inline u32 kvm_async_pf_next_probe(u32 key)
7438 {
7439 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7440 }
7441
7442 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7443 {
7444 u32 key = kvm_async_pf_hash_fn(gfn);
7445
7446 while (vcpu->arch.apf.gfns[key] != ~0)
7447 key = kvm_async_pf_next_probe(key);
7448
7449 vcpu->arch.apf.gfns[key] = gfn;
7450 }
7451
7452 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7453 {
7454 int i;
7455 u32 key = kvm_async_pf_hash_fn(gfn);
7456
7457 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7458 (vcpu->arch.apf.gfns[key] != gfn &&
7459 vcpu->arch.apf.gfns[key] != ~0); i++)
7460 key = kvm_async_pf_next_probe(key);
7461
7462 return key;
7463 }
7464
7465 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7466 {
7467 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7468 }
7469
7470 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7471 {
7472 u32 i, j, k;
7473
7474 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7475 while (true) {
7476 vcpu->arch.apf.gfns[i] = ~0;
7477 do {
7478 j = kvm_async_pf_next_probe(j);
7479 if (vcpu->arch.apf.gfns[j] == ~0)
7480 return;
7481 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7482 /*
7483 * k lies cyclically in ]i,j]
7484 * | i.k.j |
7485 * |....j i.k.| or |.k..j i...|
7486 */
7487 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7488 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7489 i = j;
7490 }
7491 }
7492
7493 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7494 {
7495
7496 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7497 sizeof(val));
7498 }
7499
7500 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7501 struct kvm_async_pf *work)
7502 {
7503 struct x86_exception fault;
7504
7505 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7506 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7507
7508 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7509 (vcpu->arch.apf.send_user_only &&
7510 kvm_x86_ops->get_cpl(vcpu) == 0))
7511 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7512 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7513 fault.vector = PF_VECTOR;
7514 fault.error_code_valid = true;
7515 fault.error_code = 0;
7516 fault.nested_page_fault = false;
7517 fault.address = work->arch.token;
7518 kvm_inject_page_fault(vcpu, &fault);
7519 }
7520 }
7521
7522 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7523 struct kvm_async_pf *work)
7524 {
7525 struct x86_exception fault;
7526
7527 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7528 if (work->wakeup_all)
7529 work->arch.token = ~0; /* broadcast wakeup */
7530 else
7531 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7532
7533 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7534 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7535 fault.vector = PF_VECTOR;
7536 fault.error_code_valid = true;
7537 fault.error_code = 0;
7538 fault.nested_page_fault = false;
7539 fault.address = work->arch.token;
7540 kvm_inject_page_fault(vcpu, &fault);
7541 }
7542 vcpu->arch.apf.halted = false;
7543 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7544 }
7545
7546 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7547 {
7548 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7549 return true;
7550 else
7551 return !kvm_event_needs_reinjection(vcpu) &&
7552 kvm_x86_ops->interrupt_allowed(vcpu);
7553 }
7554
7555 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7556 {
7557 atomic_inc(&kvm->arch.noncoherent_dma_count);
7558 }
7559 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7560
7561 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7562 {
7563 atomic_dec(&kvm->arch.noncoherent_dma_count);
7564 }
7565 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7566
7567 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7568 {
7569 return atomic_read(&kvm->arch.noncoherent_dma_count);
7570 }
7571 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7572
7573 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7574 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7575 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7576 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7577 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
7578 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
7579 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
7580 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
7581 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
7582 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
7583 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
7584 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
7585 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
Linux with added FPC-III support