| blob | 6f95fb618dc30ac2766d7e402ff5ee2b1f5cba20 |
1 /*
2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 *
20 * File: baseband.c
21 *
22 * Purpose: Implement functions to access baseband
23 *
24 * Author: Kyle Hsu
25 *
26 * Date: Aug.22, 2002
27 *
28 * Functions:
29 * BBuGetFrameTime - Calculate data frame transmitting time
30 * BBvCaculateParameter - Caculate PhyLength, PhyService and Phy Signal parameter for baseband Tx
31 * BBbReadEmbedded - Embedded read baseband register via MAC
32 * BBbWriteEmbedded - Embedded write baseband register via MAC
33 * BBbIsRegBitsOn - Test if baseband register bits on
34 * BBbIsRegBitsOff - Test if baseband register bits off
35 * BBbVT3253Init - VIA VT3253 baseband chip init code
36 * BBvReadAllRegs - Read All Baseband Registers
37 * BBvLoopbackOn - Turn on BaseBand Loopback mode
38 * BBvLoopbackOff - Turn off BaseBand Loopback mode
39 *
40 * Revision History:
41 * 06-10-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
42 * 08-07-2003 Bryan YC Fan: Add MAXIM2827/2825 and RFMD2959 support.
43 * 08-26-2003 Kyle Hsu : Modify BBuGetFrameTime() and BBvCalculateParameter().
44 * cancel the setting of MAC_REG_SOFTPWRCTL on BBbVT3253Init().
45 * Add the comments.
46 * 09-01-2003 Bryan YC Fan: RF & BB tables updated.
47 * Modified BBvLoopbackOn & BBvLoopbackOff().
48 *
49 *
50 */
59 /*--------------------- Static Definitions -------------------------*/
60 //static int msglevel =MSG_LEVEL_DEBUG;
63 /*--------------------- Static Classes ----------------------------*/
65 /*--------------------- Static Variables --------------------------*/
67 /*--------------------- Static Functions --------------------------*/
69 /*--------------------- Export Variables --------------------------*/
71 /*--------------------- Static Definitions -------------------------*/
73 /*--------------------- Static Classes ----------------------------*/
75 /*--------------------- Static Variables --------------------------*/
77 #define CB_VT3253_INIT_FOR_RFMD 446
525 };
527 #define CB_VT3253B0_INIT_FOR_RFMD 256
785 };
787 #define CB_VT3253B0_AGC_FOR_RFMD2959 195
788 // For RFMD2959
985 };
987 #define CB_VT3253B0_INIT_FOR_AIROHA2230 256
988 // For AIROHA
1246 };
1248 #define CB_VT3253B0_INIT_FOR_UW2451 256
1249 //For UW2451
1507 };
1509 #define CB_VT3253B0_AGC 193
1510 // For AIROHA
1705 };
1710 /*--------------------- Static Functions --------------------------*/
1712 static
1713 unsigned long
1716 static
1717 void
1719 PSDevice pDevice
1720 );
1722 static
1723 void
1725 PSDevice pDevice
1726 )
1727 {
1732 else
1738 else
1740 }
1747 }
1748 }
1750 /*--------------------- Export Variables --------------------------*/
1751 /*
1752 * Description: Calculate data frame transmitting time
1753 *
1754 * Parameters:
1755 * In:
1756 * byPreambleType - Preamble Type
1757 * byPktType - PK_TYPE_11A, PK_TYPE_11B, PK_TYPE_11GB, PK_TYPE_11GA
1758 * cbFrameLength - Baseband Type
1759 * wRate - Tx Rate
1760 * Out:
1761 *
1762 * Return Value: FrameTime
1763 *
1764 */
1765 unsigned int
1770 unsigned short wRate
1771 )
1772 {
1782 }
1789 else
1795 uFrameTime++;
1802 uFrameTime++;
1809 }
1810 }
1812 /*
1813 * Description: Calculate Length, Service, and Signal fields of Phy for Tx
1814 *
1815 * Parameters:
1816 * In:
1817 * pDevice - Device Structure
1818 * cbFrameLength - Tx Frame Length
1819 * wRate - Tx Rate
1820 * Out:
1821 * pwPhyLen - pointer to Phy Length field
1822 * pbyPhySrv - pointer to Phy Service field
1823 * pbyPhySgn - pointer to Phy Signal field
1824 *
1825 * Return Value: none
1826 *
1827 */
1828 void
1830 PSDevice pDevice,
1837 )
1838 {
1865 cbBitCount++;
1869 cbUsCount++;
1879 cbBitCount++;
1883 cbUsCount++;
1886 }
1898 }
1906 }
1914 }
1922 }
1930 }
1938 }
1946 }
1954 }
1962 }
1964 }
1974 }
1975 }
1977 /*
1978 * Description: Read a byte from BASEBAND, by embedded programming
1979 *
1980 * Parameters:
1981 * In:
1982 * dwIoBase - I/O base address
1983 * byBBAddr - address of register in Baseband
1984 * Out:
1985 * pbyData - data read
1986 *
1987 * Return Value: true if succeeded; false if failed.
1988 *
1989 */
1991 {
1995 // BB reg offset
1998 // turn on REGR
2000 // W_MAX_TIMEOUT is the timeout period
2005 }
2007 // get BB data
2014 }
2016 }
2018 /*
2019 * Description: Write a Byte to BASEBAND, by embedded programming
2020 *
2021 * Parameters:
2022 * In:
2023 * dwIoBase - I/O base address
2024 * byBBAddr - address of register in Baseband
2025 * byData - data to write
2026 * Out:
2027 * none
2028 *
2029 * Return Value: true if succeeded; false if failed.
2030 *
2031 */
2033 {
2037 // BB reg offset
2039 // set BB data
2042 // turn on BBREGCTL_REGW
2044 // W_MAX_TIMEOUT is the timeout period
2049 }
2055 }
2057 }
2059 /*
2060 * Description: Test if all bits are set for the Baseband register
2061 *
2062 * Parameters:
2063 * In:
2064 * dwIoBase - I/O base address
2065 * byBBAddr - address of register in Baseband
2066 * byTestBits - TestBits
2067 * Out:
2068 * none
2069 *
2070 * Return Value: true if all TestBits are set; false otherwise.
2071 *
2072 */
2074 {
2079 }
2081 /*
2082 * Description: Test if all bits are clear for the Baseband register
2083 *
2084 * Parameters:
2085 * In:
2086 * dwIoBase - I/O base address
2087 * byBBAddr - address of register in Baseband
2088 * byTestBits - TestBits
2089 * Out:
2090 * none
2091 *
2092 * Return Value: true if all TestBits are clear; false otherwise.
2093 *
2094 */
2096 {
2101 }
2103 /*
2104 * Description: VIA VT3253 Baseband chip init function
2105 *
2106 * Parameters:
2107 * In:
2108 * dwIoBase - I/O base address
2109 * byRevId - Revision ID
2110 * byRFType - RF type
2111 * Out:
2112 * none
2113 *
2114 * Return Value: true if succeeded; false if failed.
2115 *
2116 */
2119 {
2129 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253InitTab_RFMD[ii][0], byVT3253InitTab_RFMD[ii][1]);
2136 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AGC4_RFMD2959[ii][0], byVT3253B0_AGC4_RFMD2959[ii][1]);
2140 }
2151 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AIROHA2230[ii][0], byVT3253B0_AIROHA2230[ii][1]);
2186 // Init ANT B select,TX Config CR09 = 0x61->0x45, 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2187 //bResult &= BBbWriteEmbedded(dwIoBase,0x09,0x41);
2188 // Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2189 //bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);
2190 // Select VC1/VC2, CR215 = 0x02->0x06
2193 //{{RobertYu:20050125, request by Jack
2196 //}}
2198 //{{RobertYu:20050221, request by Jack
2201 //}}
2215 //}} RobertYu
2219 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AIROHA2230[ii][0], byVT3253B0_AIROHA2230[ii][1]);
2232 // Fix VT3226 DFC system timing issue
2234 //{{ RobertYu: 20050104
2237 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AIROHA2230[ii][0], byVT3253B0_AIROHA2230[ii][1]);
2240 //{{ RobertYu:20050223, request by JerryChung
2241 // Init ANT B select,TX Config CR09 = 0x61->0x45, 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2242 //bResult &= BBbWriteEmbedded(dwIoBase,0x09,0x41);
2243 // Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2244 //bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);
2245 // Select VC1/VC2, CR215 = 0x02->0x06
2247 //}}
2260 //}} RobertYu
2262 // No VGA Table now
2265 }
2270 }
2273 }
2275 /*
2276 * Description: Read All Baseband Registers
2277 *
2278 * Parameters:
2279 * In:
2280 * dwIoBase - I/O base address
2281 * pbyBBRegs - Point to struct that stores Baseband Registers
2282 * Out:
2283 * none
2284 *
2285 * Return Value: none
2286 *
2287 */
2289 {
2295 }
2296 }
2298 /*
2299 * Description: Turn on BaseBand Loopback mode
2300 *
2301 * Parameters:
2302 * In:
2303 * dwIoBase - I/O base address
2304 * bCCK - If CCK is set
2305 * Out:
2306 * none
2307 *
2308 * Return Value: none
2309 *
2310 */
2313 {
2317 //CR C9 = 0x00
2323 //CR 88 = 0x02(CCK), 0x03(OFDM)
2327 // Enable internal digital loopback: CR33 |= 0000 0001
2330 // CR154 = 0x00
2335 // Enable internal digital loopback:CR154 |= 0000 0001
2338 // CR33 = 0x00
2342 }
2344 //CR14 = 0x00
2347 // Disable TX_IQUN
2350 }
2352 /*
2353 * Description: Turn off BaseBand Loopback mode
2354 *
2355 * Parameters:
2356 * In:
2357 * pDevice - Device Structure
2358 *
2359 * Out:
2360 * none
2361 *
2362 * Return Value: none
2363 *
2364 */
2366 {
2376 // Set the CR33 Bit2 to disable internal Loopback.
2382 }
2385 }
2387 /*
2388 * Description: Set ShortSlotTime mode
2389 *
2390 * Parameters:
2391 * In:
2392 * pDevice - Device Structure
2393 * Out:
2394 * none
2395 *
2396 * Return Value: none
2397 *
2398 */
2399 void
2401 {
2409 else
2412 // patch for 3253B0 Baseband with Cardbus module
2418 }
2421 {
2427 // patch for 3253B0 Baseband with Cardbus module
2432 else
2436 }
2438 /*
2439 * Description: Baseband SoftwareReset
2440 *
2441 * Parameters:
2442 * In:
2443 * dwIoBase - I/O base address
2444 * Out:
2445 * none
2446 *
2447 * Return Value: none
2448 *
2449 */
2450 void
2452 {
2457 }
2459 /*
2460 * Description: Baseband Power Save Mode ON
2461 *
2462 * Parameters:
2463 * In:
2464 * dwIoBase - I/O base address
2465 * Out:
2466 * none
2467 *
2468 * Return Value: none
2469 *
2470 */
2471 void
2473 {
2479 }
2481 /*
2482 * Description: Baseband Power Save Mode OFF
2483 *
2484 * Parameters:
2485 * In:
2486 * dwIoBase - I/O base address
2487 * Out:
2488 * none
2489 *
2490 * Return Value: none
2491 *
2492 */
2493 void
2495 {
2501 }
2503 /*
2504 * Description: Set Tx Antenna mode
2505 *
2506 * Parameters:
2507 * In:
2508 * pDevice - Device Structure
2509 * byAntennaMode - Antenna Mode
2510 * Out:
2511 * none
2512 *
2513 * Return Value: none
2514 *
2515 */
2517 void
2519 {
2524 // bit 1 is diversity
2527 // bit 2 is ANTSEL
2532 }
2534 }
2536 /*
2537 * Description: Set Rx Antenna mode
2538 *
2539 * Parameters:
2540 * In:
2541 * pDevice - Device Structure
2542 * byAntennaMode - Antenna Mode
2543 * Out:
2544 * none
2545 *
2546 * Return Value: none
2547 *
2548 */
2550 void
2552 {
2564 }
2566 }
2568 /*
2569 * Description: BBvSetDeepSleep
2570 *
2571 * Parameters:
2572 * In:
2573 * pDevice - Device Structure
2574 * Out:
2575 * none
2576 *
2577 * Return Value: none
2578 *
2579 */
2580 void
2582 {
2585 }
2587 void
2589 {
2592 }
2594 static
2595 unsigned long
2597 {
2602 //This is a thousand-ratio
2608 }
2614 }
2621 }
2628 }
2636 }
2644 }
2652 }
2660 }
2667 }
2674 }
2680 }
2685 }
2688 }
2690 void
2692 {
2698 }
2700 /*
2701 * Description: Antenna Diversity
2702 *
2703 * Parameters:
2704 * In:
2705 * pDevice - Device Structure
2706 * byRSR - RSR from received packet
2707 * bySQ3 - SQ3 value from received packet
2708 * Out:
2709 * none
2710 *
2711 * Return Value: none
2712 *
2713 */
2715 void
2717 {
2732 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "SQ3_State0, rate = [%08x]\n", (int)pDevice->ulRatio_State0);
2750 }
2753 }
2774 }
2777 }
2779 }
2781 /*+
2782 *
2783 * Description:
2784 * Timer for SQ3 antenna diversity
2785 *
2786 * Parameters:
2787 * In:
2788 * Out:
2789 * none
2790 *
2791 * Return Value: none
2792 *
2793 -*/
2795 void
2798 )
2799 {
2805 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "3.[%08x][%08x], %d\n", (int)pDevice->ulRatio_State0, (int)pDevice->ulRatio_State1, (int)pDevice->uDiversityCnt);
2818 }
2820 /*+
2821 *
2822 * Description:
2823 * Timer for SQ3 antenna diversity
2824 *
2825 * Parameters:
2826 * In:
2827 * pvSysSpec1
2828 * hDeviceContext - Pointer to the adapter
2829 * pvSysSpec2
2830 * pvSysSpec3
2831 * Out:
2832 * none
2833 *
2834 * Return Value: none
2835 *
2836 -*/
2838 void
2841 )
2842 {
2871 }
2872 }
2878 }