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KVM: nVMX: Fix returned value of MSR_IA32_VMX_VMCS_ENUM
[linux/fpc-iii.git] / drivers / staging / vt6655 / rf.c
blob99c89a14d89ba557232e767a75723ee8888b21b9
1 /*
2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 *
20 * File: rf.c
21 *
22 * Purpose: rf function code
23 *
24 * Author: Jerry Chen
25 *
26 * Date: Feb. 19, 2004
27 *
28 * Functions:
29 * IFRFbWriteEmbedded - Embedded write RF register via MAC
30 *
31 * Revision History:
32 *
33 */
34
35 #include "mac.h"
36 #include "srom.h"
37 #include "rf.h"
38 #include "baseband.h"
39
40 /*--------------------- Static Definitions -------------------------*/
41
42 #define BY_AL2230_REG_LEN 23 //24bit
43 #define CB_AL2230_INIT_SEQ 15
44 #define SWITCH_CHANNEL_DELAY_AL2230 200 //us
45 #define AL2230_PWR_IDX_LEN 64
46
47 #define BY_AL7230_REG_LEN 23 //24bit
48 #define CB_AL7230_INIT_SEQ 16
49 #define SWITCH_CHANNEL_DELAY_AL7230 200 //us
50 #define AL7230_PWR_IDX_LEN 64
51
52 /*--------------------- Static Classes ----------------------------*/
53
54 /*--------------------- Static Variables --------------------------*/
55
56 static const unsigned long dwAL2230InitTable[CB_AL2230_INIT_SEQ] = {
57 0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
58 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
59 0x01A00200+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
60 0x00FFF300+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
61 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
62 0x0F4DC500+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
63 0x0805B600+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
64 0x0146C700+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
65 0x00068800+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
66 0x0403B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
67 0x00DBBA00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
68 0x00099B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
69 0x0BDFFC00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
70 0x00000D00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
71 0x00580F00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW
72 };
73
74 static const unsigned long dwAL2230ChannelTable0[CB_MAX_CHANNEL] = {
75 0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz
76 0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz
77 0x03E79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz
78 0x03E79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz
79 0x03F7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz
80 0x03F7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz
81 0x03E7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz
82 0x03E7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz
83 0x03F7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz
84 0x03F7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz
85 0x03E7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz
86 0x03E7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz
87 0x03F7C000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz
88 0x03E7C000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW // channel = 14, Tf = 2412M
89 };
90
91 static const unsigned long dwAL2230ChannelTable1[CB_MAX_CHANNEL] = {
92 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz
93 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz
94 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz
95 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz
96 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz
97 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz
98 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz
99 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz
100 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz
101 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz
102 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz
103 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz
104 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz
105 0x06666100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW // channel = 14, Tf = 2412M
106 };
107
108 static unsigned long dwAL2230PowerTable[AL2230_PWR_IDX_LEN] = {
109 0x04040900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
110 0x04041900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
111 0x04042900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
112 0x04043900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
113 0x04044900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
114 0x04045900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
115 0x04046900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
116 0x04047900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
117 0x04048900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
118 0x04049900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
119 0x0404A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
120 0x0404B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
121 0x0404C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
122 0x0404D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
123 0x0404E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
124 0x0404F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
125 0x04050900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
126 0x04051900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
127 0x04052900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
128 0x04053900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
129 0x04054900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
130 0x04055900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
131 0x04056900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
132 0x04057900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
133 0x04058900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
134 0x04059900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
135 0x0405A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
136 0x0405B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
137 0x0405C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
138 0x0405D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
139 0x0405E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
140 0x0405F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
141 0x04060900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
142 0x04061900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
143 0x04062900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
144 0x04063900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
145 0x04064900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
146 0x04065900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
147 0x04066900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
148 0x04067900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
149 0x04068900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
150 0x04069900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
151 0x0406A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
152 0x0406B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
153 0x0406C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
154 0x0406D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
155 0x0406E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
156 0x0406F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
157 0x04070900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
158 0x04071900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
159 0x04072900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
160 0x04073900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
161 0x04074900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
162 0x04075900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
163 0x04076900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
164 0x04077900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
165 0x04078900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
166 0x04079900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
167 0x0407A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
168 0x0407B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
169 0x0407C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
170 0x0407D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
171 0x0407E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
172 0x0407F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW
173 };
174
175 //{{ RobertYu:20050104
176 // 40MHz reference frequency
177 // Need to Pull PLLON(PE3) low when writing channel registers through 3-wire.
178 static const unsigned long dwAL7230InitTable[CB_AL7230_INIT_SEQ] = {
179 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel1 // Need modify for 11a
180 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel1 // Need modify for 11a
181 0x841FF200+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 451FE2
182 0x3FDFA300+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 5FDFA3
183 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // 11b/g // Need modify for 11a
184 // RoberYu:20050113, Rev0.47 Regsiter Setting Guide
185 0x802B5500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 8D1B55
186 0x56AF3600+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
187 0xCE020700+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 860207
188 0x6EBC0800+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
189 0x221BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
190 0xE0000A00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: E0600A
191 0x08031B00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10)
192 // RoberYu:20050113, Rev0.47 Regsiter Setting Guide
193 0x000A3C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 00143C
194 0xFFFFFD00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
195 0x00000E00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
196 0x1ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // Need modify for 11a: 12BACF
197 };
198
199 static const unsigned long dwAL7230InitTableAMode[CB_AL7230_INIT_SEQ] = {
200 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel184 // Need modify for 11b/g
201 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel184 // Need modify for 11b/g
202 0x451FE200+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g
203 0x5FDFA300+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g
204 0x67F78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // 11a // Need modify for 11b/g
205 0x853F5500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g, RoberYu:20050113
206 0x56AF3600+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
207 0xCE020700+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g
208 0x6EBC0800+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
209 0x221BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
210 0xE0600A00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g
211 0x08031B00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10)
212 0x00147C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g
213 0xFFFFFD00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
214 0x00000E00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
215 0x12BACF00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // Need modify for 11b/g
216 };
217
218 static const unsigned long dwAL7230ChannelTable0[CB_MAX_CHANNEL] = {
219 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz
220 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz
221 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz
222 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz
223 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz
224 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz
225 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz
226 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz //RobertYu: 20050218, update for APNode 0.49
227 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz //RobertYu: 20050218, update for APNode 0.49
228 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz //RobertYu: 20050218, update for APNode 0.49
229 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz //RobertYu: 20050218, update for APNode 0.49
230 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz //RobertYu: 20050218, update for APNode 0.49
231 0x0037C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz //RobertYu: 20050218, update for APNode 0.49
232 0x0037C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 14, Tf = 2484MHz
233
234 // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22)
235 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 183, Tf = 4915MHz (15)
236 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 184, Tf = 4920MHz (16)
237 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 185, Tf = 4925MHz (17)
238 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 187, Tf = 4935MHz (18)
239 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 188, Tf = 4940MHz (19)
240 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 189, Tf = 4945MHz (20)
241 0x0FF53000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 192, Tf = 4960MHz (21)
242 0x0FF53000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 196, Tf = 4980MHz (22)
243
244 // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
245 // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56)
246
247 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 5035MHz (23)
248 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 5040MHz (24)
249 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 5045MHz (25)
250 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 5055MHz (26)
251 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 5060MHz (27)
252 0x0FF55000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 16, Tf = 5080MHz (28)
253 0x0FF56000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 34, Tf = 5170MHz (29)
254 0x0FF56000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 36, Tf = 5180MHz (30)
255 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 38, Tf = 5190MHz (31) //RobertYu: 20050218, update for APNode 0.49
256 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 40, Tf = 5200MHz (32)
257 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 42, Tf = 5210MHz (33)
258 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 44, Tf = 5220MHz (34)
259 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 46, Tf = 5230MHz (35)
260 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 48, Tf = 5240MHz (36)
261 0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 52, Tf = 5260MHz (37)
262 0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 56, Tf = 5280MHz (38)
263 0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 60, Tf = 5300MHz (39)
264 0x0FF59000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 64, Tf = 5320MHz (40)
265
266 0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 100, Tf = 5500MHz (41)
267 0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 104, Tf = 5520MHz (42)
268 0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 108, Tf = 5540MHz (43)
269 0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 112, Tf = 5560MHz (44)
270 0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 116, Tf = 5580MHz (45)
271 0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 120, Tf = 5600MHz (46)
272 0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 124, Tf = 5620MHz (47)
273 0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 128, Tf = 5640MHz (48)
274 0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 132, Tf = 5660MHz (49)
275 0x0FF5F000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 136, Tf = 5680MHz (50)
276 0x0FF5F000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 140, Tf = 5700MHz (51)
277 0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 149, Tf = 5745MHz (52)
278 0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 153, Tf = 5765MHz (53)
279 0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 157, Tf = 5785MHz (54)
280 0x0FF61000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 161, Tf = 5805MHz (55)
281 0x0FF61000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // channel = 165, Tf = 5825MHz (56)
282 };
283
284 static const unsigned long dwAL7230ChannelTable1[CB_MAX_CHANNEL] = {
285 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz
286 0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz
287 0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz
288 0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz
289 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz
290 0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz
291 0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz
292 0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz
293 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz
294 0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz
295 0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz
296 0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz
297 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz
298 0x06666100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 14, Tf = 2484MHz
299
300 // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22)
301 0x1D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 183, Tf = 4915MHz (15)
302 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 184, Tf = 4920MHz (16)
303 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 185, Tf = 4925MHz (17)
304 0x08000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 187, Tf = 4935MHz (18)
305 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 188, Tf = 4940MHz (19)
306 0x0D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 189, Tf = 4945MHz (20)
307 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 192, Tf = 4960MHz (21)
308 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 196, Tf = 4980MHz (22)
309
310 // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
311 // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56)
312 0x1D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 5035MHz (23)
313 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 5040MHz (24)
314 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 5045MHz (25)
315 0x08000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 5055MHz (26)
316 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 5060MHz (27)
317 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 16, Tf = 5080MHz (28)
318 0x05555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 34, Tf = 5170MHz (29)
319 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 36, Tf = 5180MHz (30)
320 0x10000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 38, Tf = 5190MHz (31)
321 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 40, Tf = 5200MHz (32)
322 0x1AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 42, Tf = 5210MHz (33)
323 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 44, Tf = 5220MHz (34)
324 0x05555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 46, Tf = 5230MHz (35)
325 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 48, Tf = 5240MHz (36)
326 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 52, Tf = 5260MHz (37)
327 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 56, Tf = 5280MHz (38)
328 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 60, Tf = 5300MHz (39)
329 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 64, Tf = 5320MHz (40)
330 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 100, Tf = 5500MHz (41)
331 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 104, Tf = 5520MHz (42)
332 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 108, Tf = 5540MHz (43)
333 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 112, Tf = 5560MHz (44)
334 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 116, Tf = 5580MHz (45)
335 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 120, Tf = 5600MHz (46)
336 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 124, Tf = 5620MHz (47)
337 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 128, Tf = 5640MHz (48)
338 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 132, Tf = 5660MHz (49)
339 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 136, Tf = 5680MHz (50)
340 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 140, Tf = 5700MHz (51)
341 0x18000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 149, Tf = 5745MHz (52)
342 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 153, Tf = 5765MHz (53)
343 0x0D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 157, Tf = 5785MHz (54)
344 0x18000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 161, Tf = 5805MHz (55)
345 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // channel = 165, Tf = 5825MHz (56)
346 };
347
348 static const unsigned long dwAL7230ChannelTable2[CB_MAX_CHANNEL] = {
349 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz
350 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz
351 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz
352 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz
353 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz
354 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz
355 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz
356 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz
357 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz
358 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz
359 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz
360 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz
361 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz
362 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 14, Tf = 2484MHz
363
364 // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22)
365 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 183, Tf = 4915MHz (15)
366 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 184, Tf = 4920MHz (16)
367 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 185, Tf = 4925MHz (17)
368 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 187, Tf = 4935MHz (18)
369 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 188, Tf = 4940MHz (19)
370 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 189, Tf = 4945MHz (20)
371 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 192, Tf = 4960MHz (21)
372 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 196, Tf = 4980MHz (22)
373
374 // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
375 // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56)
376 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 5035MHz (23)
377 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 5040MHz (24)
378 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 5045MHz (25)
379 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 5055MHz (26)
380 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 5060MHz (27)
381 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 16, Tf = 5080MHz (28)
382 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 34, Tf = 5170MHz (29)
383 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 36, Tf = 5180MHz (30)
384 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 38, Tf = 5190MHz (31)
385 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 40, Tf = 5200MHz (32)
386 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 42, Tf = 5210MHz (33)
387 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 44, Tf = 5220MHz (34)
388 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 46, Tf = 5230MHz (35)
389 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 48, Tf = 5240MHz (36)
390 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 52, Tf = 5260MHz (37)
391 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 56, Tf = 5280MHz (38)
392 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 60, Tf = 5300MHz (39)
393 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 64, Tf = 5320MHz (40)
394 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 100, Tf = 5500MHz (41)
395 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 104, Tf = 5520MHz (42)
396 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 108, Tf = 5540MHz (43)
397 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 112, Tf = 5560MHz (44)
398 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 116, Tf = 5580MHz (45)
399 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 120, Tf = 5600MHz (46)
400 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 124, Tf = 5620MHz (47)
401 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 128, Tf = 5640MHz (48)
402 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 132, Tf = 5660MHz (49)
403 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 136, Tf = 5680MHz (50)
404 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 140, Tf = 5700MHz (51)
405 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 149, Tf = 5745MHz (52)
406 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 153, Tf = 5765MHz (53)
407 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 157, Tf = 5785MHz (54)
408 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 161, Tf = 5805MHz (55)
409 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // channel = 165, Tf = 5825MHz (56)
410 };
411 //}} RobertYu
412
413 /*--------------------- Static Functions --------------------------*/
414
415 /*
416 * Description: AIROHA IFRF chip init function
417 *
418 * Parameters:
419 * In:
420 * dwIoBase - I/O base address
421 * Out:
422 * none
423 *
424 * Return Value: true if succeeded; false if failed.
425 *
426 */
427 static bool s_bAL7230Init(unsigned long dwIoBase)
428 {
429 int ii;
430 bool bResult;
431
432 bResult = true;
433
434 //3-wire control for normal mode
435 VNSvOutPortB(dwIoBase + MAC_REG_SOFTPWRCTL, 0);
436
437 MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI |
438 SOFTPWRCTL_TXPEINV));
439 BBvPowerSaveModeOFF(dwIoBase); //RobertYu:20050106, have DC value for Calibration
440
441 for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++)
442 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[ii]);
443
444 // PLL On
445 MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
446
447 //Calibration
448 MACvTimer0MicroSDelay(dwIoBase, 150);//150us
449 bResult &= IFRFbWriteEmbedded(dwIoBase, (0x9ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW)); //TXDCOC:active, RCK:disable
450 MACvTimer0MicroSDelay(dwIoBase, 30);//30us
451 bResult &= IFRFbWriteEmbedded(dwIoBase, (0x3ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW)); //TXDCOC:disable, RCK:active
452 MACvTimer0MicroSDelay(dwIoBase, 30);//30us
453 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[CB_AL7230_INIT_SEQ-1]); //TXDCOC:disable, RCK:disable
454
455 MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 |
456 SOFTPWRCTL_SWPE2 |
457 SOFTPWRCTL_SWPECTI |
458 SOFTPWRCTL_TXPEINV));
459
460 BBvPowerSaveModeON(dwIoBase); // RobertYu:20050106
461
462 // PE1: TX_ON, PE2: RX_ON, PE3: PLLON
463 //3-wire control for power saving mode
464 VNSvOutPortB(dwIoBase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); //1100 0000
465
466 return bResult;
467 }
468
469 // Need to Pull PLLON low when writing channel registers through 3-wire interface
470 static bool s_bAL7230SelectChannel(unsigned long dwIoBase, unsigned char byChannel)
471 {
472 bool bResult;
473
474 bResult = true;
475
476 // PLLON Off
477 MACvWordRegBitsOff(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
478
479 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230ChannelTable0[byChannel - 1]); //Reg0
480 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230ChannelTable1[byChannel - 1]); //Reg1
481 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230ChannelTable2[byChannel - 1]); //Reg4
482
483 // PLLOn On
484 MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
485
486 // Set Channel[7] = 0 to tell H/W channel is changing now.
487 VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel & 0x7F));
488 MACvTimer0MicroSDelay(dwIoBase, SWITCH_CHANNEL_DELAY_AL7230);
489 // Set Channel[7] = 1 to tell H/W channel change is done.
490 VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel | 0x80));
491
492 return bResult;
493 }
494
495 /*
496 * Description: Select channel with UW2452 chip
497 *
498 * Parameters:
499 * In:
500 * dwIoBase - I/O base address
501 * uChannel - Channel number
502 * Out:
503 * none
504 *
505 * Return Value: true if succeeded; false if failed.
506 *
507 */
508
509 //{{ RobertYu: 20041210
510 /*
511 * Description: UW2452 IFRF chip init function
512 *
513 * Parameters:
514 * In:
515 * dwIoBase - I/O base address
516 * Out:
517 * none
518 *
519 * Return Value: true if succeeded; false if failed.
520 *
521 */
522
523 //}} RobertYu
524 ////////////////////////////////////////////////////////////////////////////////
525
526 /*
527 * Description: VT3226 IFRF chip init function
528 *
529 * Parameters:
530 * In:
531 * dwIoBase - I/O base address
532 * Out:
533 * none
534 *
535 * Return Value: true if succeeded; false if failed.
536 *
537 */
538
539 /*
540 * Description: Select channel with VT3226 chip
541 *
542 * Parameters:
543 * In:
544 * dwIoBase - I/O base address
545 * uChannel - Channel number
546 * Out:
547 * none
548 *
549 * Return Value: true if succeeded; false if failed.
550 *
551 */
552
553 /*--------------------- Export Variables --------------------------*/
554
555 /*--------------------- Export Functions --------------------------*/
556
557 /*
558 * Description: Write to IF/RF, by embedded programming
559 *
560 * Parameters:
561 * In:
562 * dwIoBase - I/O base address
563 * dwData - data to write
564 * Out:
565 * none
566 *
567 * Return Value: true if succeeded; false if failed.
568 *
569 */
570 bool IFRFbWriteEmbedded(unsigned long dwIoBase, unsigned long dwData)
571 {
572 unsigned short ww;
573 unsigned long dwValue;
574
575 VNSvOutPortD(dwIoBase + MAC_REG_IFREGCTL, dwData);
576
577 // W_MAX_TIMEOUT is the timeout period
578 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
579 VNSvInPortD(dwIoBase + MAC_REG_IFREGCTL, &dwValue);
580 if (dwValue & IFREGCTL_DONE)
581 break;
582 }
583
584 if (ww == W_MAX_TIMEOUT)
585 return false;
586
587 return true;
588 }
589
590 /*
591 * Description: RFMD RF2959 IFRF chip init function
592 *
593 * Parameters:
594 * In:
595 * dwIoBase - I/O base address
596 * Out:
597 * none
598 *
599 * Return Value: true if succeeded; false if failed.
600 *
601 */
602
603 /*
604 * Description: Select channel with RFMD 2959 chip
605 *
606 * Parameters:
607 * In:
608 * dwIoBase - I/O base address
609 * uChannel - Channel number
610 * Out:
611 * none
612 *
613 * Return Value: true if succeeded; false if failed.
614 *
615 */
616
617 /*
618 * Description: AIROHA IFRF chip init function
619 *
620 * Parameters:
621 * In:
622 * dwIoBase - I/O base address
623 * Out:
624 * none
625 *
626 * Return Value: true if succeeded; false if failed.
627 *
628 */
629 static bool RFbAL2230Init(unsigned long dwIoBase)
630 {
631 int ii;
632 bool bResult;
633
634 bResult = true;
635
636 //3-wire control for normal mode
637 VNSvOutPortB(dwIoBase + MAC_REG_SOFTPWRCTL, 0);
638
639 MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI |
640 SOFTPWRCTL_TXPEINV));
641 //2008-8-21 chester <add>
642 // PLL Off
643
644 MACvWordRegBitsOff(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
645
646 //patch abnormal AL2230 frequency output
647 //2008-8-21 chester <add>
648 IFRFbWriteEmbedded(dwIoBase, (0x07168700+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW));
649
650 for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++)
651 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL2230InitTable[ii]);
652 //2008-8-21 chester <add>
653 MACvTimer0MicroSDelay(dwIoBase, 30); //delay 30 us
654
655 // PLL On
656 MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
657
658 MACvTimer0MicroSDelay(dwIoBase, 150);//150us
659 bResult &= IFRFbWriteEmbedded(dwIoBase, (0x00d80f00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW));
660 MACvTimer0MicroSDelay(dwIoBase, 30);//30us
661 bResult &= IFRFbWriteEmbedded(dwIoBase, (0x00780f00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW));
662 MACvTimer0MicroSDelay(dwIoBase, 30);//30us
663 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL2230InitTable[CB_AL2230_INIT_SEQ-1]);
664
665 MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 |
666 SOFTPWRCTL_SWPE2 |
667 SOFTPWRCTL_SWPECTI |
668 SOFTPWRCTL_TXPEINV));
669
670 //3-wire control for power saving mode
671 VNSvOutPortB(dwIoBase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); //1100 0000
672
673 return bResult;
674 }
675
676 static bool RFbAL2230SelectChannel(unsigned long dwIoBase, unsigned char byChannel)
677 {
678 bool bResult;
679
680 bResult = true;
681
682 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL2230ChannelTable0[byChannel - 1]);
683 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL2230ChannelTable1[byChannel - 1]);
684
685 // Set Channel[7] = 0 to tell H/W channel is changing now.
686 VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel & 0x7F));
687 MACvTimer0MicroSDelay(dwIoBase, SWITCH_CHANNEL_DELAY_AL2230);
688 // Set Channel[7] = 1 to tell H/W channel change is done.
689 VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel | 0x80));
690
691 return bResult;
692 }
693
694 /*
695 * Description: UW2451 IFRF chip init function
696 *
697 * Parameters:
698 * In:
699 * dwIoBase - I/O base address
700 * Out:
701 * none
702 *
703 * Return Value: true if succeeded; false if failed.
704 *
705 */
706
707 /*
708 * Description: Select channel with UW2451 chip
709 *
710 * Parameters:
711 * In:
712 * dwIoBase - I/O base address
713 * uChannel - Channel number
714 * Out:
715 * none
716 *
717 * Return Value: true if succeeded; false if failed.
718 *
719 */
720
721 /*
722 * Description: Set sleep mode to UW2451 chip
723 *
724 * Parameters:
725 * In:
726 * dwIoBase - I/O base address
727 * uChannel - Channel number
728 * Out:
729 * none
730 *
731 * Return Value: true if succeeded; false if failed.
732 *
733 */
734
735 /*
736 * Description: RF init function
737 *
738 * Parameters:
739 * In:
740 * byBBType
741 * byRFType
742 * Out:
743 * none
744 *
745 * Return Value: true if succeeded; false if failed.
746 *
747 */
748 bool RFbInit(
749 PSDevice pDevice
750 )
751 {
752 bool bResult = true;
753 switch (pDevice->byRFType) {
754 case RF_AIROHA:
755 case RF_AL2230S:
756 pDevice->byMaxPwrLevel = AL2230_PWR_IDX_LEN;
757 bResult = RFbAL2230Init(pDevice->PortOffset);
758 break;
759 case RF_AIROHA7230:
760 pDevice->byMaxPwrLevel = AL7230_PWR_IDX_LEN;
761 bResult = s_bAL7230Init(pDevice->PortOffset);
762 break;
763 case RF_NOTHING:
764 bResult = true;
765 break;
766 default:
767 bResult = false;
768 break;
769 }
770 return bResult;
771 }
772
773 /*
774 * Description: Select channel
775 *
776 * Parameters:
777 * In:
778 * byRFType
779 * byChannel - Channel number
780 * Out:
781 * none
782 *
783 * Return Value: true if succeeded; false if failed.
784 *
785 */
786 bool RFbSelectChannel(unsigned long dwIoBase, unsigned char byRFType, unsigned char byChannel)
787 {
788 bool bResult = true;
789 switch (byRFType) {
790 case RF_AIROHA:
791 case RF_AL2230S:
792 bResult = RFbAL2230SelectChannel(dwIoBase, byChannel);
793 break;
794 //{{ RobertYu: 20050104
795 case RF_AIROHA7230:
796 bResult = s_bAL7230SelectChannel(dwIoBase, byChannel);
797 break;
798 //}} RobertYu
799 case RF_NOTHING:
800 bResult = true;
801 break;
802 default:
803 bResult = false;
804 break;
805 }
806 return bResult;
807 }
808
809 /*
810 * Description: Write WakeProgSyn
811 *
812 * Parameters:
813 * In:
814 * dwIoBase - I/O base address
815 * uChannel - channel number
816 * bySleepCnt - SleepProgSyn count
817 *
818 * Return Value: None.
819 *
820 */
821 bool RFvWriteWakeProgSyn(unsigned long dwIoBase, unsigned char byRFType, unsigned int uChannel)
822 {
823 int ii;
824 unsigned char byInitCount = 0;
825 unsigned char bySleepCount = 0;
826
827 VNSvOutPortW(dwIoBase + MAC_REG_MISCFFNDEX, 0);
828 switch (byRFType) {
829 case RF_AIROHA:
830 case RF_AL2230S:
831
832 if (uChannel > CB_MAX_CHANNEL_24G)
833 return false;
834
835 byInitCount = CB_AL2230_INIT_SEQ + 2; // Init Reg + Channel Reg (2)
836 bySleepCount = 0;
837 if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount))
838 return false;
839
840 for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++)
841 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230InitTable[ii]);
842
843 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable0[uChannel-1]);
844 ii++;
845 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable1[uChannel-1]);
846 break;
847
848 //{{ RobertYu: 20050104
849 // Need to check, PLLON need to be low for channel setting
850 case RF_AIROHA7230:
851 byInitCount = CB_AL7230_INIT_SEQ + 3; // Init Reg + Channel Reg (3)
852 bySleepCount = 0;
853 if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount))
854 return false;
855
856 if (uChannel <= CB_MAX_CHANNEL_24G) {
857 for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++)
858 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTable[ii]);
859 } else {
860 for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++)
861 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTableAMode[ii]);
862 }
863
864 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable0[uChannel-1]);
865 ii++;
866 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable1[uChannel-1]);
867 ii++;
868 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable2[uChannel-1]);
869 break;
870 //}} RobertYu
871
872 case RF_NOTHING:
873 return true;
874 break;
875
876 default:
877 return false;
878 break;
879 }
880
881 MACvSetMISCFifo(dwIoBase, MISCFIFO_SYNINFO_IDX, (unsigned long)MAKEWORD(bySleepCount, byInitCount));
882
883 return true;
884 }
885
886 /*
887 * Description: Set Tx power
888 *
889 * Parameters:
890 * In:
891 * dwIoBase - I/O base address
892 * dwRFPowerTable - RF Tx Power Setting
893 * Out:
894 * none
895 *
896 * Return Value: true if succeeded; false if failed.
897 *
898 */
899 bool RFbSetPower(
900 PSDevice pDevice,
901 unsigned int uRATE,
902 unsigned int uCH
903 )
904 {
905 bool bResult = true;
906 unsigned char byPwr = 0;
907 unsigned char byDec = 0;
908 unsigned char byPwrdBm = 0;
909
910 if (pDevice->dwDiagRefCount != 0)
911 return true;
912
913 if ((uCH < 1) || (uCH > CB_MAX_CHANNEL))
914 return false;
915
916 switch (uRATE) {
917 case RATE_1M:
918 case RATE_2M:
919 case RATE_5M:
920 case RATE_11M:
921 byPwr = pDevice->abyCCKPwrTbl[uCH];
922 byPwrdBm = pDevice->abyCCKDefaultPwr[uCH];
923 break;
924 case RATE_6M:
925 case RATE_9M:
926 case RATE_18M:
927 byPwr = pDevice->abyOFDMPwrTbl[uCH];
928 if (pDevice->byRFType == RF_UW2452)
929 byDec = byPwr + 14;
930 else
931 byDec = byPwr + 10;
932
933 if (byDec >= pDevice->byMaxPwrLevel)
934 byDec = pDevice->byMaxPwrLevel-1;
935
936 if (pDevice->byRFType == RF_UW2452) {
937 byPwrdBm = byDec - byPwr;
938 byPwrdBm /= 3;
939 } else {
940 byPwrdBm = byDec - byPwr;
941 byPwrdBm >>= 1;
942 }
943
944 byPwrdBm += pDevice->abyOFDMDefaultPwr[uCH];
945 byPwr = byDec;
946 break;
947 case RATE_24M:
948 case RATE_36M:
949 case RATE_48M:
950 case RATE_54M:
951 byPwr = pDevice->abyOFDMPwrTbl[uCH];
952 byPwrdBm = pDevice->abyOFDMDefaultPwr[uCH];
953 break;
954 }
955
956 if (pDevice->byCurPwr == byPwr)
957 return true;
958
959 bResult = RFbRawSetPower(pDevice, byPwr, uRATE);
960 if (bResult)
961 pDevice->byCurPwr = byPwr;
962
963 return bResult;
964 }
965
966 /*
967 * Description: Set Tx power
968 *
969 * Parameters:
970 * In:
971 * dwIoBase - I/O base address
972 * dwRFPowerTable - RF Tx Power Setting
973 * Out:
974 * none
975 *
976 * Return Value: true if succeeded; false if failed.
977 *
978 */
979
980 bool RFbRawSetPower(
981 PSDevice pDevice,
982 unsigned char byPwr,
983 unsigned int uRATE
984 )
985 {
986 bool bResult = true;
987 unsigned long dwMax7230Pwr = 0;
988
989 if (byPwr >= pDevice->byMaxPwrLevel)
990 return false;
991
992 switch (pDevice->byRFType) {
993 case RF_AIROHA:
994 bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, dwAL2230PowerTable[byPwr]);
995 if (uRATE <= RATE_11M)
996 bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, 0x0001B400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
997 else
998 bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
999
1000 break;
1001
1002 case RF_AL2230S:
1003 bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, dwAL2230PowerTable[byPwr]);
1004 if (uRATE <= RATE_11M) {
1005 bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, 0x040C1400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
1006 bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, 0x00299B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
1007 } else {
1008 bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
1009 bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, 0x00099B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
1010 }
1011
1012 break;
1013
1014 case RF_AIROHA7230:
1015 // 0x080F1B00 for 3 wire control TxGain(D10) and 0x31 as TX Gain value
1016 dwMax7230Pwr = 0x080C0B00 | ((byPwr) << 12) |
1017 (BY_AL7230_REG_LEN << 3) | IFREGCTL_REGW;
1018
1019 bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, dwMax7230Pwr);
1020 break;
1021
1022 default:
1023 break;
1024 }
1025 return bResult;
1026 }
1027
1028 /*+
1029 *
1030 * Routine Description:
1031 * Translate RSSI to dBm
1032 *
1033 * Parameters:
1034 * In:
1035 * pDevice - The adapter to be translated
1036 * byCurrRSSI - RSSI to be translated
1037 * Out:
1038 * pdwdbm - Translated dbm number
1039 *
1040 * Return Value: none
1041 *
1042 -*/
1043 void
1044 RFvRSSITodBm(
1045 PSDevice pDevice,
1046 unsigned char byCurrRSSI,
1047 long *pldBm
1048 )
1049 {
1050 unsigned char byIdx = (((byCurrRSSI & 0xC0) >> 6) & 0x03);
1051 long b = (byCurrRSSI & 0x3F);
1052 long a = 0;
1053 unsigned char abyAIROHARF[4] = {0, 18, 0, 40};
1054
1055 switch (pDevice->byRFType) {
1056 case RF_AIROHA:
1057 case RF_AL2230S:
1058 case RF_AIROHA7230: //RobertYu: 20040104
1059 a = abyAIROHARF[byIdx];
1060 break;
1061 default:
1062 break;
1063 }
1064
1065 *pldBm = -1 * (a + b * 2);
1066 }
1067
1068 ////////////////////////////////////////////////////////////////////////////////
1069 //{{ RobertYu: 20050104
1070
1071 // Post processing for the 11b/g and 11a.
1072 // for save time on changing Reg2,3,5,7,10,12,15
1073 bool RFbAL7230SelectChannelPostProcess(unsigned long dwIoBase, unsigned char byOldChannel, unsigned char byNewChannel)
1074 {
1075 bool bResult;
1076
1077 bResult = true;
1078
1079 // if change between 11 b/g and 11a need to update the following register
1080 // Channel Index 1~14
1081
1082 if ((byOldChannel <= CB_MAX_CHANNEL_24G) && (byNewChannel > CB_MAX_CHANNEL_24G)) {
1083 // Change from 2.4G to 5G
1084 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[2]); //Reg2
1085 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[3]); //Reg3
1086 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[5]); //Reg5
1087 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[7]); //Reg7
1088 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[10]);//Reg10
1089 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[12]);//Reg12
1090 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[15]);//Reg15
1091 } else if ((byOldChannel > CB_MAX_CHANNEL_24G) && (byNewChannel <= CB_MAX_CHANNEL_24G)) {
1092 // change from 5G to 2.4G
1093 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[2]); //Reg2
1094 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[3]); //Reg3
1095 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[5]); //Reg5
1096 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[7]); //Reg7
1097 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[10]);//Reg10
1098 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[12]);//Reg12
1099 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[15]);//Reg15
1100 }
1101
1102 return bResult;
1103 }
1104
1105 //}} RobertYu
1106 ////////////////////////////////////////////////////////////////////////////////
Linux with added FPC-III support