drivers/usb/dwc2/core.c

   1 /*
   2  * core.c - DesignWare HS OTG Controller common routines
   3  *
   4  * Copyright (C) 2004-2013 Synopsys, Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 /*
  38  * The Core code provides basic services for accessing and managing the
  39  * DWC_otg hardware. These services are used by both the Host Controller
  40  * Driver and the Peripheral Controller Driver.
  41  */
  42 #include <linux/kernel.h>
  43 #include <linux/module.h>
  44 #include <linux/moduleparam.h>
  45 #include <linux/spinlock.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/dma-mapping.h>
  48 #include <linux/delay.h>
  49 #include <linux/io.h>
  50 #include <linux/slab.h>
  51 #include <linux/usb.h>
  52
  53 #include <linux/usb/hcd.h>
  54 #include <linux/usb/ch11.h>
  55
  56 #include "core.h"
  57 #include "hcd.h"
  58
  59 /**
  60  * dwc2_backup_global_registers() - Backup global controller registers.
  61  * When suspending usb bus, registers needs to be backuped
  62  * if controller power is disabled once suspended.
  63  *
  64  * @hsotg: Programming view of the DWC_otg controller
  65  */
  66 static int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
  67 {
  68         struct dwc2_gregs_backup *gr;
  69         int i;
  70
  71         /* Backup global regs */
  72         gr = &hsotg->gr_backup;
  73
  74         gr->gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
  75         gr->gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
  76         gr->gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
  77         gr->gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
  78         gr->grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
  79         gr->gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
  80         gr->hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
  81         gr->gdfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
  82         for (i = 0; i < MAX_EPS_CHANNELS; i++)
  83                 gr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
  84
  85         gr->valid = true;
  86         return 0;
  87 }
  88
  89 /**
  90  * dwc2_restore_global_registers() - Restore controller global registers.
  91  * When resuming usb bus, device registers needs to be restored
  92  * if controller power were disabled.
  93  *
  94  * @hsotg: Programming view of the DWC_otg controller
  95  */
  96 static int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
  97 {
  98         struct dwc2_gregs_backup *gr;
  99         int i;
 100
 101         dev_dbg(hsotg->dev, "%s\n", __func__);
 102
 103         /* Restore global regs */
 104         gr = &hsotg->gr_backup;
 105         if (!gr->valid) {
 106                 dev_err(hsotg->dev, "%s: no global registers to restore\n",
 107                         __func__);
 108                 return -EINVAL;
 109         }
 110         gr->valid = false;
 111
 112         dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
 113         dwc2_writel(gr->gotgctl, hsotg->regs + GOTGCTL);
 114         dwc2_writel(gr->gintmsk, hsotg->regs + GINTMSK);
 115         dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG);
 116         dwc2_writel(gr->gahbcfg, hsotg->regs + GAHBCFG);
 117         dwc2_writel(gr->grxfsiz, hsotg->regs + GRXFSIZ);
 118         dwc2_writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ);
 119         dwc2_writel(gr->hptxfsiz, hsotg->regs + HPTXFSIZ);
 120         dwc2_writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG);
 121         for (i = 0; i < MAX_EPS_CHANNELS; i++)
 122                 dwc2_writel(gr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i));
 123
 124         return 0;
 125 }
 126
 127 /**
 128  * dwc2_exit_hibernation() - Exit controller from Partial Power Down.
 129  *
 130  * @hsotg: Programming view of the DWC_otg controller
 131  * @restore: Controller registers need to be restored
 132  */
 133 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore)
 134 {
 135         u32 pcgcctl;
 136         int ret = 0;
 137
 138         if (!hsotg->params.hibernation)
 139                 return -ENOTSUPP;
 140
 141         pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
 142         pcgcctl &= ~PCGCTL_STOPPCLK;
 143         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 144
 145         pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
 146         pcgcctl &= ~PCGCTL_PWRCLMP;
 147         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 148
 149         pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
 150         pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
 151         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 152
 153         udelay(100);
 154         if (restore) {
 155                 ret = dwc2_restore_global_registers(hsotg);
 156                 if (ret) {
 157                         dev_err(hsotg->dev, "%s: failed to restore registers\n",
 158                                 __func__);
 159                         return ret;
 160                 }
 161                 if (dwc2_is_host_mode(hsotg)) {
 162                         ret = dwc2_restore_host_registers(hsotg);
 163                         if (ret) {
 164                                 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
 165                                         __func__);
 166                                 return ret;
 167                         }
 168                 } else {
 169                         ret = dwc2_restore_device_registers(hsotg);
 170                         if (ret) {
 171                                 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
 172                                         __func__);
 173                                 return ret;
 174                         }
 175                 }
 176         }
 177
 178         return ret;
 179 }
 180
 181 /**
 182  * dwc2_enter_hibernation() - Put controller in Partial Power Down.
 183  *
 184  * @hsotg: Programming view of the DWC_otg controller
 185  */
 186 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg)
 187 {
 188         u32 pcgcctl;
 189         int ret = 0;
 190
 191         if (!hsotg->params.hibernation)
 192                 return -ENOTSUPP;
 193
 194         /* Backup all registers */
 195         ret = dwc2_backup_global_registers(hsotg);
 196         if (ret) {
 197                 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
 198                         __func__);
 199                 return ret;
 200         }
 201
 202         if (dwc2_is_host_mode(hsotg)) {
 203                 ret = dwc2_backup_host_registers(hsotg);
 204                 if (ret) {
 205                         dev_err(hsotg->dev, "%s: failed to backup host registers\n",
 206                                 __func__);
 207                         return ret;
 208                 }
 209         } else {
 210                 ret = dwc2_backup_device_registers(hsotg);
 211                 if (ret) {
 212                         dev_err(hsotg->dev, "%s: failed to backup device registers\n",
 213                                 __func__);
 214                         return ret;
 215                 }
 216         }
 217
 218         /*
 219          * Clear any pending interrupts since dwc2 will not be able to
 220          * clear them after entering hibernation.
 221          */
 222         dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
 223
 224         /* Put the controller in low power state */
 225         pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
 226
 227         pcgcctl |= PCGCTL_PWRCLMP;
 228         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 229         ndelay(20);
 230
 231         pcgcctl |= PCGCTL_RSTPDWNMODULE;
 232         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 233         ndelay(20);
 234
 235         pcgcctl |= PCGCTL_STOPPCLK;
 236         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 237
 238         return ret;
 239 }
 240
 241 /**
 242  * dwc2_wait_for_mode() - Waits for the controller mode.
 243  * @hsotg:      Programming view of the DWC_otg controller.
 244  * @host_mode:  If true, waits for host mode, otherwise device mode.
 245  */
 246 static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg,
 247                                bool host_mode)
 248 {
 249         ktime_t start;
 250         ktime_t end;
 251         unsigned int timeout = 110;
 252
 253         dev_vdbg(hsotg->dev, "Waiting for %s mode\n",
 254                  host_mode ? "host" : "device");
 255
 256         start = ktime_get();
 257
 258         while (1) {
 259                 s64 ms;
 260
 261                 if (dwc2_is_host_mode(hsotg) == host_mode) {
 262                         dev_vdbg(hsotg->dev, "%s mode set\n",
 263                                  host_mode ? "Host" : "Device");
 264                         break;
 265                 }
 266
 267                 end = ktime_get();
 268                 ms = ktime_to_ms(ktime_sub(end, start));
 269
 270                 if (ms >= (s64)timeout) {
 271                         dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n",
 272                                  __func__, host_mode ? "host" : "device");
 273                         break;
 274                 }
 275
 276                 usleep_range(1000, 2000);
 277         }
 278 }
 279
 280 /**
 281  * dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce
 282  * filter is enabled.
 283  */
 284 static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg)
 285 {
 286         u32 gsnpsid;
 287         u32 ghwcfg4;
 288
 289         if (!dwc2_hw_is_otg(hsotg))
 290                 return false;
 291
 292         /* Check if core configuration includes the IDDIG filter. */
 293         ghwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4);
 294         if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN))
 295                 return false;
 296
 297         /*
 298          * Check if the IDDIG debounce filter is bypassed. Available
 299          * in core version >= 3.10a.
 300          */
 301         gsnpsid = dwc2_readl(hsotg->regs + GSNPSID);
 302         if (gsnpsid >= DWC2_CORE_REV_3_10a) {
 303                 u32 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
 304
 305                 if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS)
 306                         return false;
 307         }
 308
 309         return true;
 310 }
 311
 312 /*
 313  * Do core a soft reset of the core.  Be careful with this because it
 314  * resets all the internal state machines of the core.
 315  */
 316 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
 317 {
 318         u32 greset;
 319         int count = 0;
 320         bool wait_for_host_mode = false;
 321
 322         dev_vdbg(hsotg->dev, "%s()\n", __func__);
 323
 324         /*
 325          * If the current mode is host, either due to the force mode
 326          * bit being set (which persists after core reset) or the
 327          * connector id pin, a core soft reset will temporarily reset
 328          * the mode to device. A delay from the IDDIG debounce filter
 329          * will occur before going back to host mode.
 330          *
 331          * Determine whether we will go back into host mode after a
 332          * reset and account for this delay after the reset.
 333          */
 334         if (dwc2_iddig_filter_enabled(hsotg)) {
 335                 u32 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
 336                 u32 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 337
 338                 if (!(gotgctl & GOTGCTL_CONID_B) ||
 339                     (gusbcfg & GUSBCFG_FORCEHOSTMODE)) {
 340                         wait_for_host_mode = true;
 341                 }
 342         }
 343
 344         /* Core Soft Reset */
 345         greset = dwc2_readl(hsotg->regs + GRSTCTL);
 346         greset |= GRSTCTL_CSFTRST;
 347         dwc2_writel(greset, hsotg->regs + GRSTCTL);
 348         do {
 349                 udelay(1);
 350                 greset = dwc2_readl(hsotg->regs + GRSTCTL);
 351                 if (++count > 50) {
 352                         dev_warn(hsotg->dev,
 353                                  "%s() HANG! Soft Reset GRSTCTL=%0x\n",
 354                                  __func__, greset);
 355                         return -EBUSY;
 356                 }
 357         } while (greset & GRSTCTL_CSFTRST);
 358
 359         /* Wait for AHB master IDLE state */
 360         count = 0;
 361         do {
 362                 udelay(1);
 363                 greset = dwc2_readl(hsotg->regs + GRSTCTL);
 364                 if (++count > 50) {
 365                         dev_warn(hsotg->dev,
 366                                  "%s() HANG! AHB Idle GRSTCTL=%0x\n",
 367                                  __func__, greset);
 368                         return -EBUSY;
 369                 }
 370         } while (!(greset & GRSTCTL_AHBIDLE));
 371
 372         if (wait_for_host_mode && !skip_wait)
 373                 dwc2_wait_for_mode(hsotg, true);
 374
 375         return 0;
 376 }
 377
 378 /*
 379  * Force the mode of the controller.
 380  *
 381  * Forcing the mode is needed for two cases:
 382  *
 383  * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the
 384  * controller to stay in a particular mode regardless of ID pin
 385  * changes. We do this usually after a core reset.
 386  *
 387  * 2) During probe we want to read reset values of the hw
 388  * configuration registers that are only available in either host or
 389  * device mode. We may need to force the mode if the current mode does
 390  * not allow us to access the register in the mode that we want.
 391  *
 392  * In either case it only makes sense to force the mode if the
 393  * controller hardware is OTG capable.
 394  *
 395  * Checks are done in this function to determine whether doing a force
 396  * would be valid or not.
 397  *
 398  * If a force is done, it requires a IDDIG debounce filter delay if
 399  * the filter is configured and enabled. We poll the current mode of
 400  * the controller to account for this delay.
 401  */
 402 static bool dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
 403 {
 404         u32 gusbcfg;
 405         u32 set;
 406         u32 clear;
 407
 408         dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device");
 409
 410         /*
 411          * Force mode has no effect if the hardware is not OTG.
 412          */
 413         if (!dwc2_hw_is_otg(hsotg))
 414                 return false;
 415
 416         /*
 417          * If dr_mode is either peripheral or host only, there is no
 418          * need to ever force the mode to the opposite mode.
 419          */
 420         if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL))
 421                 return false;
 422
 423         if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST))
 424                 return false;
 425
 426         gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 427
 428         set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE;
 429         clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE;
 430
 431         gusbcfg &= ~clear;
 432         gusbcfg |= set;
 433         dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
 434
 435         dwc2_wait_for_mode(hsotg, host);
 436         return true;
 437 }
 438
 439 /**
 440  * dwc2_clear_force_mode() - Clears the force mode bits.
 441  *
 442  * After clearing the bits, wait up to 100 ms to account for any
 443  * potential IDDIG filter delay. We can't know if we expect this delay
 444  * or not because the value of the connector ID status is affected by
 445  * the force mode. We only need to call this once during probe if
 446  * dr_mode == OTG.
 447  */
 448 void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
 449 {
 450         u32 gusbcfg;
 451
 452         gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 453         gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
 454         gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
 455         dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
 456
 457         if (dwc2_iddig_filter_enabled(hsotg))
 458                 msleep(100);
 459 }
 460
 461 /*
 462  * Sets or clears force mode based on the dr_mode parameter.
 463  */
 464 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
 465 {
 466         bool ret;
 467
 468         switch (hsotg->dr_mode) {
 469         case USB_DR_MODE_HOST:
 470                 ret = dwc2_force_mode(hsotg, true);
 471                 /*
 472                  * NOTE: This is required for some rockchip soc based
 473                  * platforms on their host-only dwc2.
 474                  */
 475                 if (!ret)
 476                         msleep(50);
 477
 478                 break;
 479         case USB_DR_MODE_PERIPHERAL:
 480                 dwc2_force_mode(hsotg, false);
 481                 break;
 482         case USB_DR_MODE_OTG:
 483                 dwc2_clear_force_mode(hsotg);
 484                 break;
 485         default:
 486                 dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n",
 487                          __func__, hsotg->dr_mode);
 488                 break;
 489         }
 490 }
 491
 492 /*
 493  * Do core a soft reset of the core.  Be careful with this because it
 494  * resets all the internal state machines of the core.
 495  *
 496  * Additionally this will apply force mode as per the hsotg->dr_mode
 497  * parameter.
 498  */
 499 int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg)
 500 {
 501         int retval;
 502
 503         retval = dwc2_core_reset(hsotg, false);
 504         if (retval)
 505                 return retval;
 506
 507         dwc2_force_dr_mode(hsotg);
 508         return 0;
 509 }
 510
 511 /**
 512  * dwc2_dump_host_registers() - Prints the host registers
 513  *
 514  * @hsotg: Programming view of DWC_otg controller
 515  *
 516  * NOTE: This function will be removed once the peripheral controller code
 517  * is integrated and the driver is stable
 518  */
 519 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
 520 {
 521 #ifdef DEBUG
 522         u32 __iomem *addr;
 523         int i;
 524
 525         dev_dbg(hsotg->dev, "Host Global Registers\n");
 526         addr = hsotg->regs + HCFG;
 527         dev_dbg(hsotg->dev, "HCFG        @0x%08lX : 0x%08X\n",
 528                 (unsigned long)addr, dwc2_readl(addr));
 529         addr = hsotg->regs + HFIR;
 530         dev_dbg(hsotg->dev, "HFIR        @0x%08lX : 0x%08X\n",
 531                 (unsigned long)addr, dwc2_readl(addr));
 532         addr = hsotg->regs + HFNUM;
 533         dev_dbg(hsotg->dev, "HFNUM       @0x%08lX : 0x%08X\n",
 534                 (unsigned long)addr, dwc2_readl(addr));
 535         addr = hsotg->regs + HPTXSTS;
 536         dev_dbg(hsotg->dev, "HPTXSTS     @0x%08lX : 0x%08X\n",
 537                 (unsigned long)addr, dwc2_readl(addr));
 538         addr = hsotg->regs + HAINT;
 539         dev_dbg(hsotg->dev, "HAINT       @0x%08lX : 0x%08X\n",
 540                 (unsigned long)addr, dwc2_readl(addr));
 541         addr = hsotg->regs + HAINTMSK;
 542         dev_dbg(hsotg->dev, "HAINTMSK    @0x%08lX : 0x%08X\n",
 543                 (unsigned long)addr, dwc2_readl(addr));
 544         if (hsotg->params.dma_desc_enable) {
 545                 addr = hsotg->regs + HFLBADDR;
 546                 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
 547                         (unsigned long)addr, dwc2_readl(addr));
 548         }
 549
 550         addr = hsotg->regs + HPRT0;
 551         dev_dbg(hsotg->dev, "HPRT0       @0x%08lX : 0x%08X\n",
 552                 (unsigned long)addr, dwc2_readl(addr));
 553
 554         for (i = 0; i < hsotg->params.host_channels; i++) {
 555                 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
 556                 addr = hsotg->regs + HCCHAR(i);
 557                 dev_dbg(hsotg->dev, "HCCHAR      @0x%08lX : 0x%08X\n",
 558                         (unsigned long)addr, dwc2_readl(addr));
 559                 addr = hsotg->regs + HCSPLT(i);
 560                 dev_dbg(hsotg->dev, "HCSPLT      @0x%08lX : 0x%08X\n",
 561                         (unsigned long)addr, dwc2_readl(addr));
 562                 addr = hsotg->regs + HCINT(i);
 563                 dev_dbg(hsotg->dev, "HCINT       @0x%08lX : 0x%08X\n",
 564                         (unsigned long)addr, dwc2_readl(addr));
 565                 addr = hsotg->regs + HCINTMSK(i);
 566                 dev_dbg(hsotg->dev, "HCINTMSK    @0x%08lX : 0x%08X\n",
 567                         (unsigned long)addr, dwc2_readl(addr));
 568                 addr = hsotg->regs + HCTSIZ(i);
 569                 dev_dbg(hsotg->dev, "HCTSIZ      @0x%08lX : 0x%08X\n",
 570                         (unsigned long)addr, dwc2_readl(addr));
 571                 addr = hsotg->regs + HCDMA(i);
 572                 dev_dbg(hsotg->dev, "HCDMA       @0x%08lX : 0x%08X\n",
 573                         (unsigned long)addr, dwc2_readl(addr));
 574                 if (hsotg->params.dma_desc_enable) {
 575                         addr = hsotg->regs + HCDMAB(i);
 576                         dev_dbg(hsotg->dev, "HCDMAB      @0x%08lX : 0x%08X\n",
 577                                 (unsigned long)addr, dwc2_readl(addr));
 578                 }
 579         }
 580 #endif
 581 }
 582
 583 /**
 584  * dwc2_dump_global_registers() - Prints the core global registers
 585  *
 586  * @hsotg: Programming view of DWC_otg controller
 587  *
 588  * NOTE: This function will be removed once the peripheral controller code
 589  * is integrated and the driver is stable
 590  */
 591 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
 592 {
 593 #ifdef DEBUG
 594         u32 __iomem *addr;
 595
 596         dev_dbg(hsotg->dev, "Core Global Registers\n");
 597         addr = hsotg->regs + GOTGCTL;
 598         dev_dbg(hsotg->dev, "GOTGCTL     @0x%08lX : 0x%08X\n",
 599                 (unsigned long)addr, dwc2_readl(addr));
 600         addr = hsotg->regs + GOTGINT;
 601         dev_dbg(hsotg->dev, "GOTGINT     @0x%08lX : 0x%08X\n",
 602                 (unsigned long)addr, dwc2_readl(addr));
 603         addr = hsotg->regs + GAHBCFG;
 604         dev_dbg(hsotg->dev, "GAHBCFG     @0x%08lX : 0x%08X\n",
 605                 (unsigned long)addr, dwc2_readl(addr));
 606         addr = hsotg->regs + GUSBCFG;
 607         dev_dbg(hsotg->dev, "GUSBCFG     @0x%08lX : 0x%08X\n",
 608                 (unsigned long)addr, dwc2_readl(addr));
 609         addr = hsotg->regs + GRSTCTL;
 610         dev_dbg(hsotg->dev, "GRSTCTL     @0x%08lX : 0x%08X\n",
 611                 (unsigned long)addr, dwc2_readl(addr));
 612         addr = hsotg->regs + GINTSTS;
 613         dev_dbg(hsotg->dev, "GINTSTS     @0x%08lX : 0x%08X\n",
 614                 (unsigned long)addr, dwc2_readl(addr));
 615         addr = hsotg->regs + GINTMSK;
 616         dev_dbg(hsotg->dev, "GINTMSK     @0x%08lX : 0x%08X\n",
 617                 (unsigned long)addr, dwc2_readl(addr));
 618         addr = hsotg->regs + GRXSTSR;
 619         dev_dbg(hsotg->dev, "GRXSTSR     @0x%08lX : 0x%08X\n",
 620                 (unsigned long)addr, dwc2_readl(addr));
 621         addr = hsotg->regs + GRXFSIZ;
 622         dev_dbg(hsotg->dev, "GRXFSIZ     @0x%08lX : 0x%08X\n",
 623                 (unsigned long)addr, dwc2_readl(addr));
 624         addr = hsotg->regs + GNPTXFSIZ;
 625         dev_dbg(hsotg->dev, "GNPTXFSIZ   @0x%08lX : 0x%08X\n",
 626                 (unsigned long)addr, dwc2_readl(addr));
 627         addr = hsotg->regs + GNPTXSTS;
 628         dev_dbg(hsotg->dev, "GNPTXSTS    @0x%08lX : 0x%08X\n",
 629                 (unsigned long)addr, dwc2_readl(addr));
 630         addr = hsotg->regs + GI2CCTL;
 631         dev_dbg(hsotg->dev, "GI2CCTL     @0x%08lX : 0x%08X\n",
 632                 (unsigned long)addr, dwc2_readl(addr));
 633         addr = hsotg->regs + GPVNDCTL;
 634         dev_dbg(hsotg->dev, "GPVNDCTL    @0x%08lX : 0x%08X\n",
 635                 (unsigned long)addr, dwc2_readl(addr));
 636         addr = hsotg->regs + GGPIO;
 637         dev_dbg(hsotg->dev, "GGPIO       @0x%08lX : 0x%08X\n",
 638                 (unsigned long)addr, dwc2_readl(addr));
 639         addr = hsotg->regs + GUID;
 640         dev_dbg(hsotg->dev, "GUID        @0x%08lX : 0x%08X\n",
 641                 (unsigned long)addr, dwc2_readl(addr));
 642         addr = hsotg->regs + GSNPSID;
 643         dev_dbg(hsotg->dev, "GSNPSID     @0x%08lX : 0x%08X\n",
 644                 (unsigned long)addr, dwc2_readl(addr));
 645         addr = hsotg->regs + GHWCFG1;
 646         dev_dbg(hsotg->dev, "GHWCFG1     @0x%08lX : 0x%08X\n",
 647                 (unsigned long)addr, dwc2_readl(addr));
 648         addr = hsotg->regs + GHWCFG2;
 649         dev_dbg(hsotg->dev, "GHWCFG2     @0x%08lX : 0x%08X\n",
 650                 (unsigned long)addr, dwc2_readl(addr));
 651         addr = hsotg->regs + GHWCFG3;
 652         dev_dbg(hsotg->dev, "GHWCFG3     @0x%08lX : 0x%08X\n",
 653                 (unsigned long)addr, dwc2_readl(addr));
 654         addr = hsotg->regs + GHWCFG4;
 655         dev_dbg(hsotg->dev, "GHWCFG4     @0x%08lX : 0x%08X\n",
 656                 (unsigned long)addr, dwc2_readl(addr));
 657         addr = hsotg->regs + GLPMCFG;
 658         dev_dbg(hsotg->dev, "GLPMCFG     @0x%08lX : 0x%08X\n",
 659                 (unsigned long)addr, dwc2_readl(addr));
 660         addr = hsotg->regs + GPWRDN;
 661         dev_dbg(hsotg->dev, "GPWRDN      @0x%08lX : 0x%08X\n",
 662                 (unsigned long)addr, dwc2_readl(addr));
 663         addr = hsotg->regs + GDFIFOCFG;
 664         dev_dbg(hsotg->dev, "GDFIFOCFG   @0x%08lX : 0x%08X\n",
 665                 (unsigned long)addr, dwc2_readl(addr));
 666         addr = hsotg->regs + HPTXFSIZ;
 667         dev_dbg(hsotg->dev, "HPTXFSIZ    @0x%08lX : 0x%08X\n",
 668                 (unsigned long)addr, dwc2_readl(addr));
 669
 670         addr = hsotg->regs + PCGCTL;
 671         dev_dbg(hsotg->dev, "PCGCTL      @0x%08lX : 0x%08X\n",
 672                 (unsigned long)addr, dwc2_readl(addr));
 673 #endif
 674 }
 675
 676 /**
 677  * dwc2_flush_tx_fifo() - Flushes a Tx FIFO
 678  *
 679  * @hsotg: Programming view of DWC_otg controller
 680  * @num:   Tx FIFO to flush
 681  */
 682 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
 683 {
 684         u32 greset;
 685         int count = 0;
 686
 687         dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
 688
 689         greset = GRSTCTL_TXFFLSH;
 690         greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
 691         dwc2_writel(greset, hsotg->regs + GRSTCTL);
 692
 693         do {
 694                 greset = dwc2_readl(hsotg->regs + GRSTCTL);
 695                 if (++count > 10000) {
 696                         dev_warn(hsotg->dev,
 697                                  "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
 698                                  __func__, greset,
 699                                  dwc2_readl(hsotg->regs + GNPTXSTS));
 700                         break;
 701                 }
 702                 udelay(1);
 703         } while (greset & GRSTCTL_TXFFLSH);
 704
 705         /* Wait for at least 3 PHY Clocks */
 706         udelay(1);
 707 }
 708
 709 /**
 710  * dwc2_flush_rx_fifo() - Flushes the Rx FIFO
 711  *
 712  * @hsotg: Programming view of DWC_otg controller
 713  */
 714 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
 715 {
 716         u32 greset;
 717         int count = 0;
 718
 719         dev_vdbg(hsotg->dev, "%s()\n", __func__);
 720
 721         greset = GRSTCTL_RXFFLSH;
 722         dwc2_writel(greset, hsotg->regs + GRSTCTL);
 723
 724         do {
 725                 greset = dwc2_readl(hsotg->regs + GRSTCTL);
 726                 if (++count > 10000) {
 727                         dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n",
 728                                  __func__, greset);
 729                         break;
 730                 }
 731                 udelay(1);
 732         } while (greset & GRSTCTL_RXFFLSH);
 733
 734         /* Wait for at least 3 PHY Clocks */
 735         udelay(1);
 736 }
 737
 738 /*
 739  * Forces either host or device mode if the controller is not
 740  * currently in that mode.
 741  *
 742  * Returns true if the mode was forced.
 743  */
 744 bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host)
 745 {
 746         if (host && dwc2_is_host_mode(hsotg))
 747                 return false;
 748         else if (!host && dwc2_is_device_mode(hsotg))
 749                 return false;
 750
 751         return dwc2_force_mode(hsotg, host);
 752 }
 753
 754 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
 755 {
 756         if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff)
 757                 return false;
 758         else
 759                 return true;
 760 }
 761
 762 /**
 763  * dwc2_enable_global_interrupts() - Enables the controller's Global
 764  * Interrupt in the AHB Config register
 765  *
 766  * @hsotg: Programming view of DWC_otg controller
 767  */
 768 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
 769 {
 770         u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
 771
 772         ahbcfg |= GAHBCFG_GLBL_INTR_EN;
 773         dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
 774 }
 775
 776 /**
 777  * dwc2_disable_global_interrupts() - Disables the controller's Global
 778  * Interrupt in the AHB Config register
 779  *
 780  * @hsotg: Programming view of DWC_otg controller
 781  */
 782 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
 783 {
 784         u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
 785
 786         ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
 787         dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
 788 }
 789
 790 /* Returns the controller's GHWCFG2.OTG_MODE. */
 791 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg)
 792 {
 793         u32 ghwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
 794
 795         return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >>
 796                 GHWCFG2_OP_MODE_SHIFT;
 797 }
 798
 799 /* Returns true if the controller is capable of DRD. */
 800 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg)
 801 {
 802         unsigned int op_mode = dwc2_op_mode(hsotg);
 803
 804         return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) ||
 805                 (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) ||
 806                 (op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE);
 807 }
 808
 809 /* Returns true if the controller is host-only. */
 810 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
 811 {
 812         unsigned int op_mode = dwc2_op_mode(hsotg);
 813
 814         return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
 815                 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST);
 816 }
 817
 818 /* Returns true if the controller is device-only. */
 819 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg)
 820 {
 821         unsigned int op_mode = dwc2_op_mode(hsotg);
 822
 823         return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
 824                 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE);
 825 }
 826
 827 MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
 828 MODULE_AUTHOR("Synopsys, Inc.");
 829 MODULE_LICENSE("Dual BSD/GPL");