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Merge 4.11-rc4 into tty-next
[linux/fpc-iii.git] / drivers / usb / gadget / udc / udc-xilinx.c
blob588e2531b8b81e05365f0d85fabd1e90452540a4
1 /*
2 * Xilinx USB peripheral controller driver
3 *
4 * Copyright (C) 2004 by Thomas Rathbone
5 * Copyright (C) 2005 by HP Labs
6 * Copyright (C) 2005 by David Brownell
7 * Copyright (C) 2010 - 2014 Xilinx, Inc.
8 *
9 * Some parts of this driver code is based on the driver for at91-series
10 * USB peripheral controller (at91_udc.c).
11 *
12 * This program is free software; you can redistribute it
13 * and/or modify it under the terms of the GNU General Public
14 * License as published by the Free Software Foundation;
15 * either version 2 of the License, or (at your option) any
16 * later version.
17 */
18
19 #include <linux/delay.h>
20 #include <linux/device.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/interrupt.h>
23 #include <linux/io.h>
24 #include <linux/module.h>
25 #include <linux/of_address.h>
26 #include <linux/of_device.h>
27 #include <linux/of_platform.h>
28 #include <linux/of_irq.h>
29 #include <linux/prefetch.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32
33 /* Register offsets for the USB device.*/
34 #define XUSB_EP0_CONFIG_OFFSET 0x0000 /* EP0 Config Reg Offset */
35 #define XUSB_SETUP_PKT_ADDR_OFFSET 0x0080 /* Setup Packet Address */
36 #define XUSB_ADDRESS_OFFSET 0x0100 /* Address Register */
37 #define XUSB_CONTROL_OFFSET 0x0104 /* Control Register */
38 #define XUSB_STATUS_OFFSET 0x0108 /* Status Register */
39 #define XUSB_FRAMENUM_OFFSET 0x010C /* Frame Number Register */
40 #define XUSB_IER_OFFSET 0x0110 /* Interrupt Enable Register */
41 #define XUSB_BUFFREADY_OFFSET 0x0114 /* Buffer Ready Register */
42 #define XUSB_TESTMODE_OFFSET 0x0118 /* Test Mode Register */
43 #define XUSB_DMA_RESET_OFFSET 0x0200 /* DMA Soft Reset Register */
44 #define XUSB_DMA_CONTROL_OFFSET 0x0204 /* DMA Control Register */
45 #define XUSB_DMA_DSAR_ADDR_OFFSET 0x0208 /* DMA source Address Reg */
46 #define XUSB_DMA_DDAR_ADDR_OFFSET 0x020C /* DMA destination Addr Reg */
47 #define XUSB_DMA_LENGTH_OFFSET 0x0210 /* DMA Length Register */
48 #define XUSB_DMA_STATUS_OFFSET 0x0214 /* DMA Status Register */
49
50 /* Endpoint Configuration Space offsets */
51 #define XUSB_EP_CFGSTATUS_OFFSET 0x00 /* Endpoint Config Status */
52 #define XUSB_EP_BUF0COUNT_OFFSET 0x08 /* Buffer 0 Count */
53 #define XUSB_EP_BUF1COUNT_OFFSET 0x0C /* Buffer 1 Count */
54
55 #define XUSB_CONTROL_USB_READY_MASK 0x80000000 /* USB ready Mask */
56 #define XUSB_CONTROL_USB_RMTWAKE_MASK 0x40000000 /* Remote wake up mask */
57
58 /* Interrupt register related masks.*/
59 #define XUSB_STATUS_GLOBAL_INTR_MASK 0x80000000 /* Global Intr Enable */
60 #define XUSB_STATUS_DMADONE_MASK 0x04000000 /* DMA done Mask */
61 #define XUSB_STATUS_DMAERR_MASK 0x02000000 /* DMA Error Mask */
62 #define XUSB_STATUS_DMABUSY_MASK 0x80000000 /* DMA Error Mask */
63 #define XUSB_STATUS_RESUME_MASK 0x01000000 /* USB Resume Mask */
64 #define XUSB_STATUS_RESET_MASK 0x00800000 /* USB Reset Mask */
65 #define XUSB_STATUS_SUSPEND_MASK 0x00400000 /* USB Suspend Mask */
66 #define XUSB_STATUS_DISCONNECT_MASK 0x00200000 /* USB Disconnect Mask */
67 #define XUSB_STATUS_FIFO_BUFF_RDY_MASK 0x00100000 /* FIFO Buff Ready Mask */
68 #define XUSB_STATUS_FIFO_BUFF_FREE_MASK 0x00080000 /* FIFO Buff Free Mask */
69 #define XUSB_STATUS_SETUP_PACKET_MASK 0x00040000 /* Setup packet received */
70 #define XUSB_STATUS_EP1_BUFF2_COMP_MASK 0x00000200 /* EP 1 Buff 2 Processed */
71 #define XUSB_STATUS_EP1_BUFF1_COMP_MASK 0x00000002 /* EP 1 Buff 1 Processed */
72 #define XUSB_STATUS_EP0_BUFF2_COMP_MASK 0x00000100 /* EP 0 Buff 2 Processed */
73 #define XUSB_STATUS_EP0_BUFF1_COMP_MASK 0x00000001 /* EP 0 Buff 1 Processed */
74 #define XUSB_STATUS_HIGH_SPEED_MASK 0x00010000 /* USB Speed Mask */
75 /* Suspend,Reset,Suspend and Disconnect Mask */
76 #define XUSB_STATUS_INTR_EVENT_MASK 0x01E00000
77 /* Buffers completion Mask */
78 #define XUSB_STATUS_INTR_BUFF_COMP_ALL_MASK 0x0000FEFF
79 /* Mask for buffer 0 and buffer 1 completion for all Endpoints */
80 #define XUSB_STATUS_INTR_BUFF_COMP_SHIFT_MASK 0x00000101
81 #define XUSB_STATUS_EP_BUFF2_SHIFT 8 /* EP buffer offset */
82
83 /* Endpoint Configuration Status Register */
84 #define XUSB_EP_CFG_VALID_MASK 0x80000000 /* Endpoint Valid bit */
85 #define XUSB_EP_CFG_STALL_MASK 0x40000000 /* Endpoint Stall bit */
86 #define XUSB_EP_CFG_DATA_TOGGLE_MASK 0x08000000 /* Endpoint Data toggle */
87
88 /* USB device specific global configuration constants.*/
89 #define XUSB_MAX_ENDPOINTS 8 /* Maximum End Points */
90 #define XUSB_EP_NUMBER_ZERO 0 /* End point Zero */
91 /* DPRAM is the source address for DMA transfer */
92 #define XUSB_DMA_READ_FROM_DPRAM 0x80000000
93 #define XUSB_DMA_DMASR_BUSY 0x80000000 /* DMA busy */
94 #define XUSB_DMA_DMASR_ERROR 0x40000000 /* DMA Error */
95 /*
96 * When this bit is set, the DMA buffer ready bit is set by hardware upon
97 * DMA transfer completion.
98 */
99 #define XUSB_DMA_BRR_CTRL 0x40000000 /* DMA bufready ctrl bit */
100 /* Phase States */
101 #define SETUP_PHASE 0x0000 /* Setup Phase */
102 #define DATA_PHASE 0x0001 /* Data Phase */
103 #define STATUS_PHASE 0x0002 /* Status Phase */
104
105 #define EP0_MAX_PACKET 64 /* Endpoint 0 maximum packet length */
106 #define STATUSBUFF_SIZE 2 /* Buffer size for GET_STATUS command */
107 #define EPNAME_SIZE 4 /* Buffer size for endpoint name */
108
109 /* container_of helper macros */
110 #define to_udc(g) container_of((g), struct xusb_udc, gadget)
111 #define to_xusb_ep(ep) container_of((ep), struct xusb_ep, ep_usb)
112 #define to_xusb_req(req) container_of((req), struct xusb_req, usb_req)
113
114 /**
115 * struct xusb_req - Xilinx USB device request structure
116 * @usb_req: Linux usb request structure
117 * @queue: usb device request queue
118 * @ep: pointer to xusb_endpoint structure
119 */
120 struct xusb_req {
121 struct usb_request usb_req;
122 struct list_head queue;
123 struct xusb_ep *ep;
124 };
125
126 /**
127 * struct xusb_ep - USB end point structure.
128 * @ep_usb: usb endpoint instance
129 * @queue: endpoint message queue
130 * @udc: xilinx usb peripheral driver instance pointer
131 * @desc: pointer to the usb endpoint descriptor
132 * @rambase: the endpoint buffer address
133 * @offset: the endpoint register offset value
134 * @name: name of the endpoint
135 * @epnumber: endpoint number
136 * @maxpacket: maximum packet size the endpoint can store
137 * @buffer0count: the size of the packet recieved in the first buffer
138 * @buffer1count: the size of the packet received in the second buffer
139 * @curbufnum: current buffer of endpoint that will be processed next
140 * @buffer0ready: the busy state of first buffer
141 * @buffer1ready: the busy state of second buffer
142 * @is_in: endpoint direction (IN or OUT)
143 * @is_iso: endpoint type(isochronous or non isochronous)
144 */
145 struct xusb_ep {
146 struct usb_ep ep_usb;
147 struct list_head queue;
148 struct xusb_udc *udc;
149 const struct usb_endpoint_descriptor *desc;
150 u32 rambase;
151 u32 offset;
152 char name[4];
153 u16 epnumber;
154 u16 maxpacket;
155 u16 buffer0count;
156 u16 buffer1count;
157 u8 curbufnum;
158 bool buffer0ready;
159 bool buffer1ready;
160 bool is_in;
161 bool is_iso;
162 };
163
164 /**
165 * struct xusb_udc - USB peripheral driver structure
166 * @gadget: USB gadget driver instance
167 * @ep: an array of endpoint structures
168 * @driver: pointer to the usb gadget driver instance
169 * @setup: usb_ctrlrequest structure for control requests
170 * @req: pointer to dummy request for get status command
171 * @dev: pointer to device structure in gadget
172 * @usb_state: device in suspended state or not
173 * @remote_wkp: remote wakeup enabled by host
174 * @setupseqtx: tx status
175 * @setupseqrx: rx status
176 * @addr: the usb device base address
177 * @lock: instance of spinlock
178 * @dma_enabled: flag indicating whether the dma is included in the system
179 * @read_fn: function pointer to read device registers
180 * @write_fn: function pointer to write to device registers
181 */
182 struct xusb_udc {
183 struct usb_gadget gadget;
184 struct xusb_ep ep[8];
185 struct usb_gadget_driver *driver;
186 struct usb_ctrlrequest setup;
187 struct xusb_req *req;
188 struct device *dev;
189 u32 usb_state;
190 u32 remote_wkp;
191 u32 setupseqtx;
192 u32 setupseqrx;
193 void __iomem *addr;
194 spinlock_t lock;
195 bool dma_enabled;
196
197 unsigned int (*read_fn)(void __iomem *);
198 void (*write_fn)(void __iomem *, u32, u32);
199 };
200
201 /* Endpoint buffer start addresses in the core */
202 static u32 rambase[8] = { 0x22, 0x1000, 0x1100, 0x1200, 0x1300, 0x1400, 0x1500,
203 0x1600 };
204
205 static const char driver_name[] = "xilinx-udc";
206 static const char ep0name[] = "ep0";
207
208 /* Control endpoint configuration.*/
209 static const struct usb_endpoint_descriptor config_bulk_out_desc = {
210 .bLength = USB_DT_ENDPOINT_SIZE,
211 .bDescriptorType = USB_DT_ENDPOINT,
212 .bEndpointAddress = USB_DIR_OUT,
213 .bmAttributes = USB_ENDPOINT_XFER_BULK,
214 .wMaxPacketSize = cpu_to_le16(EP0_MAX_PACKET),
215 };
216
217 /**
218 * xudc_write32 - little endian write to device registers
219 * @addr: base addr of device registers
220 * @offset: register offset
221 * @val: data to be written
222 */
223 static void xudc_write32(void __iomem *addr, u32 offset, u32 val)
224 {
225 iowrite32(val, addr + offset);
226 }
227
228 /**
229 * xudc_read32 - little endian read from device registers
230 * @addr: addr of device register
231 * Return: value at addr
232 */
233 static unsigned int xudc_read32(void __iomem *addr)
234 {
235 return ioread32(addr);
236 }
237
238 /**
239 * xudc_write32_be - big endian write to device registers
240 * @addr: base addr of device registers
241 * @offset: register offset
242 * @val: data to be written
243 */
244 static void xudc_write32_be(void __iomem *addr, u32 offset, u32 val)
245 {
246 iowrite32be(val, addr + offset);
247 }
248
249 /**
250 * xudc_read32_be - big endian read from device registers
251 * @addr: addr of device register
252 * Return: value at addr
253 */
254 static unsigned int xudc_read32_be(void __iomem *addr)
255 {
256 return ioread32be(addr);
257 }
258
259 /**
260 * xudc_wrstatus - Sets up the usb device status stages.
261 * @udc: pointer to the usb device controller structure.
262 */
263 static void xudc_wrstatus(struct xusb_udc *udc)
264 {
265 struct xusb_ep *ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO];
266 u32 epcfgreg;
267
268 epcfgreg = udc->read_fn(udc->addr + ep0->offset)|
269 XUSB_EP_CFG_DATA_TOGGLE_MASK;
270 udc->write_fn(udc->addr, ep0->offset, epcfgreg);
271 udc->write_fn(udc->addr, ep0->offset + XUSB_EP_BUF0COUNT_OFFSET, 0);
272 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1);
273 }
274
275 /**
276 * xudc_epconfig - Configures the given endpoint.
277 * @ep: pointer to the usb device endpoint structure.
278 * @udc: pointer to the usb peripheral controller structure.
279 *
280 * This function configures a specific endpoint with the given configuration
281 * data.
282 */
283 static void xudc_epconfig(struct xusb_ep *ep, struct xusb_udc *udc)
284 {
285 u32 epcfgreg;
286
287 /*
288 * Configure the end point direction, type, Max Packet Size and the
289 * EP buffer location.
290 */
291 epcfgreg = ((ep->is_in << 29) | (ep->is_iso << 28) |
292 (ep->ep_usb.maxpacket << 15) | (ep->rambase));
293 udc->write_fn(udc->addr, ep->offset, epcfgreg);
294
295 /* Set the Buffer count and the Buffer ready bits.*/
296 udc->write_fn(udc->addr, ep->offset + XUSB_EP_BUF0COUNT_OFFSET,
297 ep->buffer0count);
298 udc->write_fn(udc->addr, ep->offset + XUSB_EP_BUF1COUNT_OFFSET,
299 ep->buffer1count);
300 if (ep->buffer0ready)
301 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET,
302 1 << ep->epnumber);
303 if (ep->buffer1ready)
304 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET,
305 1 << (ep->epnumber + XUSB_STATUS_EP_BUFF2_SHIFT));
306 }
307
308 /**
309 * xudc_start_dma - Starts DMA transfer.
310 * @ep: pointer to the usb device endpoint structure.
311 * @src: DMA source address.
312 * @dst: DMA destination address.
313 * @length: number of bytes to transfer.
314 *
315 * Return: 0 on success, error code on failure
316 *
317 * This function starts DMA transfer by writing to DMA source,
318 * destination and lenth registers.
319 */
320 static int xudc_start_dma(struct xusb_ep *ep, dma_addr_t src,
321 dma_addr_t dst, u32 length)
322 {
323 struct xusb_udc *udc = ep->udc;
324 int rc = 0;
325 u32 timeout = 500;
326 u32 reg;
327
328 /*
329 * Set the addresses in the DMA source and
330 * destination registers and then set the length
331 * into the DMA length register.
332 */
333 udc->write_fn(udc->addr, XUSB_DMA_DSAR_ADDR_OFFSET, src);
334 udc->write_fn(udc->addr, XUSB_DMA_DDAR_ADDR_OFFSET, dst);
335 udc->write_fn(udc->addr, XUSB_DMA_LENGTH_OFFSET, length);
336
337 /*
338 * Wait till DMA transaction is complete and
339 * check whether the DMA transaction was
340 * successful.
341 */
342 do {
343 reg = udc->read_fn(udc->addr + XUSB_DMA_STATUS_OFFSET);
344 if (!(reg & XUSB_DMA_DMASR_BUSY))
345 break;
346
347 /*
348 * We can't sleep here, because it's also called from
349 * interrupt context.
350 */
351 timeout--;
352 if (!timeout) {
353 dev_err(udc->dev, "DMA timeout\n");
354 return -ETIMEDOUT;
355 }
356 udelay(1);
357 } while (1);
358
359 if ((udc->read_fn(udc->addr + XUSB_DMA_STATUS_OFFSET) &
360 XUSB_DMA_DMASR_ERROR) == XUSB_DMA_DMASR_ERROR){
361 dev_err(udc->dev, "DMA Error\n");
362 rc = -EINVAL;
363 }
364
365 return rc;
366 }
367
368 /**
369 * xudc_dma_send - Sends IN data using DMA.
370 * @ep: pointer to the usb device endpoint structure.
371 * @req: pointer to the usb request structure.
372 * @buffer: pointer to data to be sent.
373 * @length: number of bytes to send.
374 *
375 * Return: 0 on success, -EAGAIN if no buffer is free and error
376 * code on failure.
377 *
378 * This function sends data using DMA.
379 */
380 static int xudc_dma_send(struct xusb_ep *ep, struct xusb_req *req,
381 u8 *buffer, u32 length)
382 {
383 u32 *eprambase;
384 dma_addr_t src;
385 dma_addr_t dst;
386 struct xusb_udc *udc = ep->udc;
387
388 src = req->usb_req.dma + req->usb_req.actual;
389 if (req->usb_req.length)
390 dma_sync_single_for_device(udc->dev, src,
391 length, DMA_TO_DEVICE);
392 if (!ep->curbufnum && !ep->buffer0ready) {
393 /* Get the Buffer address and copy the transmit data.*/
394 eprambase = (u32 __force *)(udc->addr + ep->rambase);
395 dst = virt_to_phys(eprambase);
396 udc->write_fn(udc->addr, ep->offset +
397 XUSB_EP_BUF0COUNT_OFFSET, length);
398 udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET,
399 XUSB_DMA_BRR_CTRL | (1 << ep->epnumber));
400 ep->buffer0ready = 1;
401 ep->curbufnum = 1;
402 } else if (ep->curbufnum && !ep->buffer1ready) {
403 /* Get the Buffer address and copy the transmit data.*/
404 eprambase = (u32 __force *)(udc->addr + ep->rambase +
405 ep->ep_usb.maxpacket);
406 dst = virt_to_phys(eprambase);
407 udc->write_fn(udc->addr, ep->offset +
408 XUSB_EP_BUF1COUNT_OFFSET, length);
409 udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET,
410 XUSB_DMA_BRR_CTRL | (1 << (ep->epnumber +
411 XUSB_STATUS_EP_BUFF2_SHIFT)));
412 ep->buffer1ready = 1;
413 ep->curbufnum = 0;
414 } else {
415 /* None of ping pong buffers are ready currently .*/
416 return -EAGAIN;
417 }
418
419 return xudc_start_dma(ep, src, dst, length);
420 }
421
422 /**
423 * xudc_dma_receive - Receives OUT data using DMA.
424 * @ep: pointer to the usb device endpoint structure.
425 * @req: pointer to the usb request structure.
426 * @buffer: pointer to storage buffer of received data.
427 * @length: number of bytes to receive.
428 *
429 * Return: 0 on success, -EAGAIN if no buffer is free and error
430 * code on failure.
431 *
432 * This function receives data using DMA.
433 */
434 static int xudc_dma_receive(struct xusb_ep *ep, struct xusb_req *req,
435 u8 *buffer, u32 length)
436 {
437 u32 *eprambase;
438 dma_addr_t src;
439 dma_addr_t dst;
440 struct xusb_udc *udc = ep->udc;
441
442 dst = req->usb_req.dma + req->usb_req.actual;
443 if (!ep->curbufnum && !ep->buffer0ready) {
444 /* Get the Buffer address and copy the transmit data */
445 eprambase = (u32 __force *)(udc->addr + ep->rambase);
446 src = virt_to_phys(eprambase);
447 udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET,
448 XUSB_DMA_BRR_CTRL | XUSB_DMA_READ_FROM_DPRAM |
449 (1 << ep->epnumber));
450 ep->buffer0ready = 1;
451 ep->curbufnum = 1;
452 } else if (ep->curbufnum && !ep->buffer1ready) {
453 /* Get the Buffer address and copy the transmit data */
454 eprambase = (u32 __force *)(udc->addr +
455 ep->rambase + ep->ep_usb.maxpacket);
456 src = virt_to_phys(eprambase);
457 udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET,
458 XUSB_DMA_BRR_CTRL | XUSB_DMA_READ_FROM_DPRAM |
459 (1 << (ep->epnumber +
460 XUSB_STATUS_EP_BUFF2_SHIFT)));
461 ep->buffer1ready = 1;
462 ep->curbufnum = 0;
463 } else {
464 /* None of the ping-pong buffers are ready currently */
465 return -EAGAIN;
466 }
467
468 return xudc_start_dma(ep, src, dst, length);
469 }
470
471 /**
472 * xudc_eptxrx - Transmits or receives data to or from an endpoint.
473 * @ep: pointer to the usb endpoint configuration structure.
474 * @req: pointer to the usb request structure.
475 * @bufferptr: pointer to buffer containing the data to be sent.
476 * @bufferlen: The number of data bytes to be sent.
477 *
478 * Return: 0 on success, -EAGAIN if no buffer is free.
479 *
480 * This function copies the transmit/receive data to/from the end point buffer
481 * and enables the buffer for transmission/reception.
482 */
483 static int xudc_eptxrx(struct xusb_ep *ep, struct xusb_req *req,
484 u8 *bufferptr, u32 bufferlen)
485 {
486 u32 *eprambase;
487 u32 bytestosend;
488 int rc = 0;
489 struct xusb_udc *udc = ep->udc;
490
491 bytestosend = bufferlen;
492 if (udc->dma_enabled) {
493 if (ep->is_in)
494 rc = xudc_dma_send(ep, req, bufferptr, bufferlen);
495 else
496 rc = xudc_dma_receive(ep, req, bufferptr, bufferlen);
497 return rc;
498 }
499 /* Put the transmit buffer into the correct ping-pong buffer.*/
500 if (!ep->curbufnum && !ep->buffer0ready) {
501 /* Get the Buffer address and copy the transmit data.*/
502 eprambase = (u32 __force *)(udc->addr + ep->rambase);
503 if (ep->is_in) {
504 memcpy(eprambase, bufferptr, bytestosend);
505 udc->write_fn(udc->addr, ep->offset +
506 XUSB_EP_BUF0COUNT_OFFSET, bufferlen);
507 } else {
508 memcpy(bufferptr, eprambase, bytestosend);
509 }
510 /*
511 * Enable the buffer for transmission.
512 */
513 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET,
514 1 << ep->epnumber);
515 ep->buffer0ready = 1;
516 ep->curbufnum = 1;
517 } else if (ep->curbufnum && !ep->buffer1ready) {
518 /* Get the Buffer address and copy the transmit data.*/
519 eprambase = (u32 __force *)(udc->addr + ep->rambase +
520 ep->ep_usb.maxpacket);
521 if (ep->is_in) {
522 memcpy(eprambase, bufferptr, bytestosend);
523 udc->write_fn(udc->addr, ep->offset +
524 XUSB_EP_BUF1COUNT_OFFSET, bufferlen);
525 } else {
526 memcpy(bufferptr, eprambase, bytestosend);
527 }
528 /*
529 * Enable the buffer for transmission.
530 */
531 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET,
532 1 << (ep->epnumber + XUSB_STATUS_EP_BUFF2_SHIFT));
533 ep->buffer1ready = 1;
534 ep->curbufnum = 0;
535 } else {
536 /* None of the ping-pong buffers are ready currently */
537 return -EAGAIN;
538 }
539 return rc;
540 }
541
542 /**
543 * xudc_done - Exeutes the endpoint data transfer completion tasks.
544 * @ep: pointer to the usb device endpoint structure.
545 * @req: pointer to the usb request structure.
546 * @status: Status of the data transfer.
547 *
548 * Deletes the message from the queue and updates data transfer completion
549 * status.
550 */
551 static void xudc_done(struct xusb_ep *ep, struct xusb_req *req, int status)
552 {
553 struct xusb_udc *udc = ep->udc;
554
555 list_del_init(&req->queue);
556
557 if (req->usb_req.status == -EINPROGRESS)
558 req->usb_req.status = status;
559 else
560 status = req->usb_req.status;
561
562 if (status && status != -ESHUTDOWN)
563 dev_dbg(udc->dev, "%s done %p, status %d\n",
564 ep->ep_usb.name, req, status);
565 /* unmap request if DMA is present*/
566 if (udc->dma_enabled && ep->epnumber && req->usb_req.length)
567 usb_gadget_unmap_request(&udc->gadget, &req->usb_req,
568 ep->is_in);
569
570 if (req->usb_req.complete) {
571 spin_unlock(&udc->lock);
572 req->usb_req.complete(&ep->ep_usb, &req->usb_req);
573 spin_lock(&udc->lock);
574 }
575 }
576
577 /**
578 * xudc_read_fifo - Reads the data from the given endpoint buffer.
579 * @ep: pointer to the usb device endpoint structure.
580 * @req: pointer to the usb request structure.
581 *
582 * Return: 0 if request is completed and -EAGAIN if not completed.
583 *
584 * Pulls OUT packet data from the endpoint buffer.
585 */
586 static int xudc_read_fifo(struct xusb_ep *ep, struct xusb_req *req)
587 {
588 u8 *buf;
589 u32 is_short, count, bufferspace;
590 u8 bufoffset;
591 u8 two_pkts = 0;
592 int ret;
593 int retval = -EAGAIN;
594 struct xusb_udc *udc = ep->udc;
595
596 if (ep->buffer0ready && ep->buffer1ready) {
597 dev_dbg(udc->dev, "Packet NOT ready!\n");
598 return retval;
599 }
600 top:
601 if (ep->curbufnum)
602 bufoffset = XUSB_EP_BUF1COUNT_OFFSET;
603 else
604 bufoffset = XUSB_EP_BUF0COUNT_OFFSET;
605
606 count = udc->read_fn(udc->addr + ep->offset + bufoffset);
607
608 if (!ep->buffer0ready && !ep->buffer1ready)
609 two_pkts = 1;
610
611 buf = req->usb_req.buf + req->usb_req.actual;
612 prefetchw(buf);
613 bufferspace = req->usb_req.length - req->usb_req.actual;
614 is_short = count < ep->ep_usb.maxpacket;
615
616 if (unlikely(!bufferspace)) {
617 /*
618 * This happens when the driver's buffer
619 * is smaller than what the host sent.
620 * discard the extra data.
621 */
622 if (req->usb_req.status != -EOVERFLOW)
623 dev_dbg(udc->dev, "%s overflow %d\n",
624 ep->ep_usb.name, count);
625 req->usb_req.status = -EOVERFLOW;
626 xudc_done(ep, req, -EOVERFLOW);
627 return 0;
628 }
629
630 ret = xudc_eptxrx(ep, req, buf, count);
631 switch (ret) {
632 case 0:
633 req->usb_req.actual += min(count, bufferspace);
634 dev_dbg(udc->dev, "read %s, %d bytes%s req %p %d/%d\n",
635 ep->ep_usb.name, count, is_short ? "/S" : "", req,
636 req->usb_req.actual, req->usb_req.length);
637 bufferspace -= count;
638 /* Completion */
639 if ((req->usb_req.actual == req->usb_req.length) || is_short) {
640 if (udc->dma_enabled && req->usb_req.length)
641 dma_sync_single_for_cpu(udc->dev,
642 req->usb_req.dma,
643 req->usb_req.actual,
644 DMA_FROM_DEVICE);
645 xudc_done(ep, req, 0);
646 return 0;
647 }
648 if (two_pkts) {
649 two_pkts = 0;
650 goto top;
651 }
652 break;
653 case -EAGAIN:
654 dev_dbg(udc->dev, "receive busy\n");
655 break;
656 case -EINVAL:
657 case -ETIMEDOUT:
658 /* DMA error, dequeue the request */
659 xudc_done(ep, req, -ECONNRESET);
660 retval = 0;
661 break;
662 }
663
664 return retval;
665 }
666
667 /**
668 * xudc_write_fifo - Writes data into the given endpoint buffer.
669 * @ep: pointer to the usb device endpoint structure.
670 * @req: pointer to the usb request structure.
671 *
672 * Return: 0 if request is completed and -EAGAIN if not completed.
673 *
674 * Loads endpoint buffer for an IN packet.
675 */
676 static int xudc_write_fifo(struct xusb_ep *ep, struct xusb_req *req)
677 {
678 u32 max;
679 u32 length;
680 int ret;
681 int retval = -EAGAIN;
682 struct xusb_udc *udc = ep->udc;
683 int is_last, is_short = 0;
684 u8 *buf;
685
686 max = le16_to_cpu(ep->desc->wMaxPacketSize);
687 buf = req->usb_req.buf + req->usb_req.actual;
688 prefetch(buf);
689 length = req->usb_req.length - req->usb_req.actual;
690 length = min(length, max);
691
692 ret = xudc_eptxrx(ep, req, buf, length);
693 switch (ret) {
694 case 0:
695 req->usb_req.actual += length;
696 if (unlikely(length != max)) {
697 is_last = is_short = 1;
698 } else {
699 if (likely(req->usb_req.length !=
700 req->usb_req.actual) || req->usb_req.zero)
701 is_last = 0;
702 else
703 is_last = 1;
704 }
705 dev_dbg(udc->dev, "%s: wrote %s %d bytes%s%s %d left %p\n",
706 __func__, ep->ep_usb.name, length, is_last ? "/L" : "",
707 is_short ? "/S" : "",
708 req->usb_req.length - req->usb_req.actual, req);
709 /* completion */
710 if (is_last) {
711 xudc_done(ep, req, 0);
712 retval = 0;
713 }
714 break;
715 case -EAGAIN:
716 dev_dbg(udc->dev, "Send busy\n");
717 break;
718 case -EINVAL:
719 case -ETIMEDOUT:
720 /* DMA error, dequeue the request */
721 xudc_done(ep, req, -ECONNRESET);
722 retval = 0;
723 break;
724 }
725
726 return retval;
727 }
728
729 /**
730 * xudc_nuke - Cleans up the data transfer message list.
731 * @ep: pointer to the usb device endpoint structure.
732 * @status: Status of the data transfer.
733 */
734 static void xudc_nuke(struct xusb_ep *ep, int status)
735 {
736 struct xusb_req *req;
737
738 while (!list_empty(&ep->queue)) {
739 req = list_first_entry(&ep->queue, struct xusb_req, queue);
740 xudc_done(ep, req, status);
741 }
742 }
743
744 /**
745 * xudc_ep_set_halt - Stalls/unstalls the given endpoint.
746 * @_ep: pointer to the usb device endpoint structure.
747 * @value: value to indicate stall/unstall.
748 *
749 * Return: 0 for success and error value on failure
750 */
751 static int xudc_ep_set_halt(struct usb_ep *_ep, int value)
752 {
753 struct xusb_ep *ep = to_xusb_ep(_ep);
754 struct xusb_udc *udc;
755 unsigned long flags;
756 u32 epcfgreg;
757
758 if (!_ep || (!ep->desc && ep->epnumber)) {
759 pr_debug("%s: bad ep or descriptor\n", __func__);
760 return -EINVAL;
761 }
762 udc = ep->udc;
763
764 if (ep->is_in && (!list_empty(&ep->queue)) && value) {
765 dev_dbg(udc->dev, "requests pending can't halt\n");
766 return -EAGAIN;
767 }
768
769 if (ep->buffer0ready || ep->buffer1ready) {
770 dev_dbg(udc->dev, "HW buffers busy can't halt\n");
771 return -EAGAIN;
772 }
773
774 spin_lock_irqsave(&udc->lock, flags);
775
776 if (value) {
777 /* Stall the device.*/
778 epcfgreg = udc->read_fn(udc->addr + ep->offset);
779 epcfgreg |= XUSB_EP_CFG_STALL_MASK;
780 udc->write_fn(udc->addr, ep->offset, epcfgreg);
781 } else {
782 /* Unstall the device.*/
783 epcfgreg = udc->read_fn(udc->addr + ep->offset);
784 epcfgreg &= ~XUSB_EP_CFG_STALL_MASK;
785 udc->write_fn(udc->addr, ep->offset, epcfgreg);
786 if (ep->epnumber) {
787 /* Reset the toggle bit.*/
788 epcfgreg = udc->read_fn(ep->udc->addr + ep->offset);
789 epcfgreg &= ~XUSB_EP_CFG_DATA_TOGGLE_MASK;
790 udc->write_fn(udc->addr, ep->offset, epcfgreg);
791 }
792 }
793
794 spin_unlock_irqrestore(&udc->lock, flags);
795 return 0;
796 }
797
798 /**
799 * xudc_ep_enable - Enables the given endpoint.
800 * @ep: pointer to the xusb endpoint structure.
801 * @desc: pointer to usb endpoint descriptor.
802 *
803 * Return: 0 for success and error value on failure
804 */
805 static int __xudc_ep_enable(struct xusb_ep *ep,
806 const struct usb_endpoint_descriptor *desc)
807 {
808 struct xusb_udc *udc = ep->udc;
809 u32 tmp;
810 u32 epcfg;
811 u32 ier;
812 u16 maxpacket;
813
814 ep->is_in = ((desc->bEndpointAddress & USB_DIR_IN) != 0);
815 /* Bit 3...0:endpoint number */
816 ep->epnumber = (desc->bEndpointAddress & 0x0f);
817 ep->desc = desc;
818 ep->ep_usb.desc = desc;
819 tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
820 ep->ep_usb.maxpacket = maxpacket = le16_to_cpu(desc->wMaxPacketSize);
821
822 switch (tmp) {
823 case USB_ENDPOINT_XFER_CONTROL:
824 dev_dbg(udc->dev, "only one control endpoint\n");
825 /* NON- ISO */
826 ep->is_iso = 0;
827 return -EINVAL;
828 case USB_ENDPOINT_XFER_INT:
829 /* NON- ISO */
830 ep->is_iso = 0;
831 if (maxpacket > 64) {
832 dev_dbg(udc->dev, "bogus maxpacket %d\n", maxpacket);
833 return -EINVAL;
834 }
835 break;
836 case USB_ENDPOINT_XFER_BULK:
837 /* NON- ISO */
838 ep->is_iso = 0;
839 if (!(is_power_of_2(maxpacket) && maxpacket >= 8 &&
840 maxpacket <= 512)) {
841 dev_dbg(udc->dev, "bogus maxpacket %d\n", maxpacket);
842 return -EINVAL;
843 }
844 break;
845 case USB_ENDPOINT_XFER_ISOC:
846 /* ISO */
847 ep->is_iso = 1;
848 break;
849 }
850
851 ep->buffer0ready = 0;
852 ep->buffer1ready = 0;
853 ep->curbufnum = 0;
854 ep->rambase = rambase[ep->epnumber];
855 xudc_epconfig(ep, udc);
856
857 dev_dbg(udc->dev, "Enable Endpoint %d max pkt is %d\n",
858 ep->epnumber, maxpacket);
859
860 /* Enable the End point.*/
861 epcfg = udc->read_fn(udc->addr + ep->offset);
862 epcfg |= XUSB_EP_CFG_VALID_MASK;
863 udc->write_fn(udc->addr, ep->offset, epcfg);
864 if (ep->epnumber)
865 ep->rambase <<= 2;
866
867 /* Enable buffer completion interrupts for endpoint */
868 ier = udc->read_fn(udc->addr + XUSB_IER_OFFSET);
869 ier |= (XUSB_STATUS_INTR_BUFF_COMP_SHIFT_MASK << ep->epnumber);
870 udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier);
871
872 /* for OUT endpoint set buffers ready to receive */
873 if (ep->epnumber && !ep->is_in) {
874 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET,
875 1 << ep->epnumber);
876 ep->buffer0ready = 1;
877 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET,
878 (1 << (ep->epnumber +
879 XUSB_STATUS_EP_BUFF2_SHIFT)));
880 ep->buffer1ready = 1;
881 }
882
883 return 0;
884 }
885
886 /**
887 * xudc_ep_enable - Enables the given endpoint.
888 * @_ep: pointer to the usb endpoint structure.
889 * @desc: pointer to usb endpoint descriptor.
890 *
891 * Return: 0 for success and error value on failure
892 */
893 static int xudc_ep_enable(struct usb_ep *_ep,
894 const struct usb_endpoint_descriptor *desc)
895 {
896 struct xusb_ep *ep;
897 struct xusb_udc *udc;
898 unsigned long flags;
899 int ret;
900
901 if (!_ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
902 pr_debug("%s: bad ep or descriptor\n", __func__);
903 return -EINVAL;
904 }
905
906 ep = to_xusb_ep(_ep);
907 udc = ep->udc;
908
909 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
910 dev_dbg(udc->dev, "bogus device state\n");
911 return -ESHUTDOWN;
912 }
913
914 spin_lock_irqsave(&udc->lock, flags);
915 ret = __xudc_ep_enable(ep, desc);
916 spin_unlock_irqrestore(&udc->lock, flags);
917
918 return ret;
919 }
920
921 /**
922 * xudc_ep_disable - Disables the given endpoint.
923 * @_ep: pointer to the usb endpoint structure.
924 *
925 * Return: 0 for success and error value on failure
926 */
927 static int xudc_ep_disable(struct usb_ep *_ep)
928 {
929 struct xusb_ep *ep;
930 unsigned long flags;
931 u32 epcfg;
932 struct xusb_udc *udc;
933
934 if (!_ep) {
935 pr_debug("%s: invalid ep\n", __func__);
936 return -EINVAL;
937 }
938
939 ep = to_xusb_ep(_ep);
940 udc = ep->udc;
941
942 spin_lock_irqsave(&udc->lock, flags);
943
944 xudc_nuke(ep, -ESHUTDOWN);
945
946 /* Restore the endpoint's pristine config */
947 ep->desc = NULL;
948 ep->ep_usb.desc = NULL;
949
950 dev_dbg(udc->dev, "USB Ep %d disable\n ", ep->epnumber);
951 /* Disable the endpoint.*/
952 epcfg = udc->read_fn(udc->addr + ep->offset);
953 epcfg &= ~XUSB_EP_CFG_VALID_MASK;
954 udc->write_fn(udc->addr, ep->offset, epcfg);
955
956 spin_unlock_irqrestore(&udc->lock, flags);
957 return 0;
958 }
959
960 /**
961 * xudc_ep_alloc_request - Initializes the request queue.
962 * @_ep: pointer to the usb endpoint structure.
963 * @gfp_flags: Flags related to the request call.
964 *
965 * Return: pointer to request structure on success and a NULL on failure.
966 */
967 static struct usb_request *xudc_ep_alloc_request(struct usb_ep *_ep,
968 gfp_t gfp_flags)
969 {
970 struct xusb_ep *ep = to_xusb_ep(_ep);
971 struct xusb_udc *udc;
972 struct xusb_req *req;
973
974 udc = ep->udc;
975 req = kzalloc(sizeof(*req), gfp_flags);
976 if (!req)
977 return NULL;
978
979 req->ep = ep;
980 INIT_LIST_HEAD(&req->queue);
981 return &req->usb_req;
982 }
983
984 /**
985 * xudc_free_request - Releases the request from queue.
986 * @_ep: pointer to the usb device endpoint structure.
987 * @_req: pointer to the usb request structure.
988 */
989 static void xudc_free_request(struct usb_ep *_ep, struct usb_request *_req)
990 {
991 struct xusb_req *req = to_xusb_req(_req);
992
993 kfree(req);
994 }
995
996 /**
997 * xudc_ep0_queue - Adds the request to endpoint 0 queue.
998 * @ep0: pointer to the xusb endpoint 0 structure.
999 * @req: pointer to the xusb request structure.
1000 *
1001 * Return: 0 for success and error value on failure
1002 */
1003 static int __xudc_ep0_queue(struct xusb_ep *ep0, struct xusb_req *req)
1004 {
1005 struct xusb_udc *udc = ep0->udc;
1006 u32 length;
1007 u8 *corebuf;
1008
1009 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
1010 dev_dbg(udc->dev, "%s, bogus device state\n", __func__);
1011 return -EINVAL;
1012 }
1013 if (!list_empty(&ep0->queue)) {
1014 dev_dbg(udc->dev, "%s:ep0 busy\n", __func__);
1015 return -EBUSY;
1016 }
1017
1018 req->usb_req.status = -EINPROGRESS;
1019 req->usb_req.actual = 0;
1020
1021 list_add_tail(&req->queue, &ep0->queue);
1022
1023 if (udc->setup.bRequestType & USB_DIR_IN) {
1024 prefetch(req->usb_req.buf);
1025 length = req->usb_req.length;
1026 corebuf = (void __force *) ((ep0->rambase << 2) +
1027 udc->addr);
1028 length = req->usb_req.actual = min_t(u32, length,
1029 EP0_MAX_PACKET);
1030 memcpy(corebuf, req->usb_req.buf, length);
1031 udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, length);
1032 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1);
1033 } else {
1034 if (udc->setup.wLength) {
1035 /* Enable EP0 buffer to receive data */
1036 udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, 0);
1037 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1);
1038 } else {
1039 xudc_wrstatus(udc);
1040 }
1041 }
1042
1043 return 0;
1044 }
1045
1046 /**
1047 * xudc_ep0_queue - Adds the request to endpoint 0 queue.
1048 * @_ep: pointer to the usb endpoint 0 structure.
1049 * @_req: pointer to the usb request structure.
1050 * @gfp_flags: Flags related to the request call.
1051 *
1052 * Return: 0 for success and error value on failure
1053 */
1054 static int xudc_ep0_queue(struct usb_ep *_ep, struct usb_request *_req,
1055 gfp_t gfp_flags)
1056 {
1057 struct xusb_req *req = to_xusb_req(_req);
1058 struct xusb_ep *ep0 = to_xusb_ep(_ep);
1059 struct xusb_udc *udc = ep0->udc;
1060 unsigned long flags;
1061 int ret;
1062
1063 spin_lock_irqsave(&udc->lock, flags);
1064 ret = __xudc_ep0_queue(ep0, req);
1065 spin_unlock_irqrestore(&udc->lock, flags);
1066
1067 return ret;
1068 }
1069
1070 /**
1071 * xudc_ep_queue - Adds the request to endpoint queue.
1072 * @_ep: pointer to the usb endpoint structure.
1073 * @_req: pointer to the usb request structure.
1074 * @gfp_flags: Flags related to the request call.
1075 *
1076 * Return: 0 for success and error value on failure
1077 */
1078 static int xudc_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
1079 gfp_t gfp_flags)
1080 {
1081 struct xusb_req *req = to_xusb_req(_req);
1082 struct xusb_ep *ep = to_xusb_ep(_ep);
1083 struct xusb_udc *udc = ep->udc;
1084 int ret;
1085 unsigned long flags;
1086
1087 if (!ep->desc) {
1088 dev_dbg(udc->dev, "%s:queing request to disabled %s\n",
1089 __func__, ep->name);
1090 return -ESHUTDOWN;
1091 }
1092
1093 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
1094 dev_dbg(udc->dev, "%s, bogus device state\n", __func__);
1095 return -EINVAL;
1096 }
1097
1098 spin_lock_irqsave(&udc->lock, flags);
1099
1100 _req->status = -EINPROGRESS;
1101 _req->actual = 0;
1102
1103 if (udc->dma_enabled) {
1104 ret = usb_gadget_map_request(&udc->gadget, &req->usb_req,
1105 ep->is_in);
1106 if (ret) {
1107 dev_dbg(udc->dev, "gadget_map failed ep%d\n",
1108 ep->epnumber);
1109 spin_unlock_irqrestore(&udc->lock, flags);
1110 return -EAGAIN;
1111 }
1112 }
1113
1114 if (list_empty(&ep->queue)) {
1115 if (ep->is_in) {
1116 dev_dbg(udc->dev, "xudc_write_fifo from ep_queue\n");
1117 if (!xudc_write_fifo(ep, req))
1118 req = NULL;
1119 } else {
1120 dev_dbg(udc->dev, "xudc_read_fifo from ep_queue\n");
1121 if (!xudc_read_fifo(ep, req))
1122 req = NULL;
1123 }
1124 }
1125
1126 if (req != NULL)
1127 list_add_tail(&req->queue, &ep->queue);
1128
1129 spin_unlock_irqrestore(&udc->lock, flags);
1130 return 0;
1131 }
1132
1133 /**
1134 * xudc_ep_dequeue - Removes the request from the queue.
1135 * @_ep: pointer to the usb device endpoint structure.
1136 * @_req: pointer to the usb request structure.
1137 *
1138 * Return: 0 for success and error value on failure
1139 */
1140 static int xudc_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1141 {
1142 struct xusb_ep *ep = to_xusb_ep(_ep);
1143 struct xusb_req *req = to_xusb_req(_req);
1144 struct xusb_udc *udc = ep->udc;
1145 unsigned long flags;
1146
1147 spin_lock_irqsave(&udc->lock, flags);
1148 /* Make sure it's actually queued on this endpoint */
1149 list_for_each_entry(req, &ep->queue, queue) {
1150 if (&req->usb_req == _req)
1151 break;
1152 }
1153 if (&req->usb_req != _req) {
1154 spin_unlock_irqrestore(&ep->udc->lock, flags);
1155 return -EINVAL;
1156 }
1157 xudc_done(ep, req, -ECONNRESET);
1158 spin_unlock_irqrestore(&udc->lock, flags);
1159
1160 return 0;
1161 }
1162
1163 /**
1164 * xudc_ep0_enable - Enables the given endpoint.
1165 * @ep: pointer to the usb endpoint structure.
1166 * @desc: pointer to usb endpoint descriptor.
1167 *
1168 * Return: error always.
1169 *
1170 * endpoint 0 enable should not be called by gadget layer.
1171 */
1172 static int xudc_ep0_enable(struct usb_ep *ep,
1173 const struct usb_endpoint_descriptor *desc)
1174 {
1175 return -EINVAL;
1176 }
1177
1178 /**
1179 * xudc_ep0_disable - Disables the given endpoint.
1180 * @ep: pointer to the usb endpoint structure.
1181 *
1182 * Return: error always.
1183 *
1184 * endpoint 0 disable should not be called by gadget layer.
1185 */
1186 static int xudc_ep0_disable(struct usb_ep *ep)
1187 {
1188 return -EINVAL;
1189 }
1190
1191 static const struct usb_ep_ops xusb_ep0_ops = {
1192 .enable = xudc_ep0_enable,
1193 .disable = xudc_ep0_disable,
1194 .alloc_request = xudc_ep_alloc_request,
1195 .free_request = xudc_free_request,
1196 .queue = xudc_ep0_queue,
1197 .dequeue = xudc_ep_dequeue,
1198 .set_halt = xudc_ep_set_halt,
1199 };
1200
1201 static const struct usb_ep_ops xusb_ep_ops = {
1202 .enable = xudc_ep_enable,
1203 .disable = xudc_ep_disable,
1204 .alloc_request = xudc_ep_alloc_request,
1205 .free_request = xudc_free_request,
1206 .queue = xudc_ep_queue,
1207 .dequeue = xudc_ep_dequeue,
1208 .set_halt = xudc_ep_set_halt,
1209 };
1210
1211 /**
1212 * xudc_get_frame - Reads the current usb frame number.
1213 * @gadget: pointer to the usb gadget structure.
1214 *
1215 * Return: current frame number for success and error value on failure.
1216 */
1217 static int xudc_get_frame(struct usb_gadget *gadget)
1218 {
1219 struct xusb_udc *udc;
1220 int frame;
1221
1222 if (!gadget)
1223 return -ENODEV;
1224
1225 udc = to_udc(gadget);
1226 frame = udc->read_fn(udc->addr + XUSB_FRAMENUM_OFFSET);
1227 return frame;
1228 }
1229
1230 /**
1231 * xudc_wakeup - Send remote wakeup signal to host
1232 * @gadget: pointer to the usb gadget structure.
1233 *
1234 * Return: 0 on success and error on failure
1235 */
1236 static int xudc_wakeup(struct usb_gadget *gadget)
1237 {
1238 struct xusb_udc *udc = to_udc(gadget);
1239 u32 crtlreg;
1240 int status = -EINVAL;
1241 unsigned long flags;
1242
1243 spin_lock_irqsave(&udc->lock, flags);
1244
1245 /* Remote wake up not enabled by host */
1246 if (!udc->remote_wkp)
1247 goto done;
1248
1249 crtlreg = udc->read_fn(udc->addr + XUSB_CONTROL_OFFSET);
1250 crtlreg |= XUSB_CONTROL_USB_RMTWAKE_MASK;
1251 /* set remote wake up bit */
1252 udc->write_fn(udc->addr, XUSB_CONTROL_OFFSET, crtlreg);
1253 /*
1254 * wait for a while and reset remote wake up bit since this bit
1255 * is not cleared by HW after sending remote wakeup to host.
1256 */
1257 mdelay(2);
1258
1259 crtlreg &= ~XUSB_CONTROL_USB_RMTWAKE_MASK;
1260 udc->write_fn(udc->addr, XUSB_CONTROL_OFFSET, crtlreg);
1261 status = 0;
1262 done:
1263 spin_unlock_irqrestore(&udc->lock, flags);
1264 return status;
1265 }
1266
1267 /**
1268 * xudc_pullup - start/stop USB traffic
1269 * @gadget: pointer to the usb gadget structure.
1270 * @is_on: flag to start or stop
1271 *
1272 * Return: 0 always
1273 *
1274 * This function starts/stops SIE engine of IP based on is_on.
1275 */
1276 static int xudc_pullup(struct usb_gadget *gadget, int is_on)
1277 {
1278 struct xusb_udc *udc = to_udc(gadget);
1279 unsigned long flags;
1280 u32 crtlreg;
1281
1282 spin_lock_irqsave(&udc->lock, flags);
1283
1284 crtlreg = udc->read_fn(udc->addr + XUSB_CONTROL_OFFSET);
1285 if (is_on)
1286 crtlreg |= XUSB_CONTROL_USB_READY_MASK;
1287 else
1288 crtlreg &= ~XUSB_CONTROL_USB_READY_MASK;
1289
1290 udc->write_fn(udc->addr, XUSB_CONTROL_OFFSET, crtlreg);
1291
1292 spin_unlock_irqrestore(&udc->lock, flags);
1293
1294 return 0;
1295 }
1296
1297 /**
1298 * xudc_eps_init - initialize endpoints.
1299 * @udc: pointer to the usb device controller structure.
1300 */
1301 static void xudc_eps_init(struct xusb_udc *udc)
1302 {
1303 u32 ep_number;
1304
1305 INIT_LIST_HEAD(&udc->gadget.ep_list);
1306
1307 for (ep_number = 0; ep_number < XUSB_MAX_ENDPOINTS; ep_number++) {
1308 struct xusb_ep *ep = &udc->ep[ep_number];
1309
1310 if (ep_number) {
1311 list_add_tail(&ep->ep_usb.ep_list,
1312 &udc->gadget.ep_list);
1313 usb_ep_set_maxpacket_limit(&ep->ep_usb,
1314 (unsigned short) ~0);
1315 snprintf(ep->name, EPNAME_SIZE, "ep%d", ep_number);
1316 ep->ep_usb.name = ep->name;
1317 ep->ep_usb.ops = &xusb_ep_ops;
1318
1319 ep->ep_usb.caps.type_iso = true;
1320 ep->ep_usb.caps.type_bulk = true;
1321 ep->ep_usb.caps.type_int = true;
1322 } else {
1323 ep->ep_usb.name = ep0name;
1324 usb_ep_set_maxpacket_limit(&ep->ep_usb, EP0_MAX_PACKET);
1325 ep->ep_usb.ops = &xusb_ep0_ops;
1326
1327 ep->ep_usb.caps.type_control = true;
1328 }
1329
1330 ep->ep_usb.caps.dir_in = true;
1331 ep->ep_usb.caps.dir_out = true;
1332
1333 ep->udc = udc;
1334 ep->epnumber = ep_number;
1335 ep->desc = NULL;
1336 /*
1337 * The configuration register address offset between
1338 * each endpoint is 0x10.
1339 */
1340 ep->offset = XUSB_EP0_CONFIG_OFFSET + (ep_number * 0x10);
1341 ep->is_in = 0;
1342 ep->is_iso = 0;
1343 ep->maxpacket = 0;
1344 xudc_epconfig(ep, udc);
1345
1346 /* Initialize one queue per endpoint */
1347 INIT_LIST_HEAD(&ep->queue);
1348 }
1349 }
1350
1351 /**
1352 * xudc_stop_activity - Stops any further activity on the device.
1353 * @udc: pointer to the usb device controller structure.
1354 */
1355 static void xudc_stop_activity(struct xusb_udc *udc)
1356 {
1357 int i;
1358 struct xusb_ep *ep;
1359
1360 for (i = 0; i < XUSB_MAX_ENDPOINTS; i++) {
1361 ep = &udc->ep[i];
1362 xudc_nuke(ep, -ESHUTDOWN);
1363 }
1364 }
1365
1366 /**
1367 * xudc_start - Starts the device.
1368 * @gadget: pointer to the usb gadget structure
1369 * @driver: pointer to gadget driver structure
1370 *
1371 * Return: zero on success and error on failure
1372 */
1373 static int xudc_start(struct usb_gadget *gadget,
1374 struct usb_gadget_driver *driver)
1375 {
1376 struct xusb_udc *udc = to_udc(gadget);
1377 struct xusb_ep *ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO];
1378 const struct usb_endpoint_descriptor *desc = &config_bulk_out_desc;
1379 unsigned long flags;
1380 int ret = 0;
1381
1382 spin_lock_irqsave(&udc->lock, flags);
1383
1384 if (udc->driver) {
1385 dev_err(udc->dev, "%s is already bound to %s\n",
1386 udc->gadget.name, udc->driver->driver.name);
1387 ret = -EBUSY;
1388 goto err;
1389 }
1390
1391 /* hook up the driver */
1392 udc->driver = driver;
1393 udc->gadget.speed = driver->max_speed;
1394
1395 /* Enable the control endpoint. */
1396 ret = __xudc_ep_enable(ep0, desc);
1397
1398 /* Set device address and remote wakeup to 0 */
1399 udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0);
1400 udc->remote_wkp = 0;
1401 err:
1402 spin_unlock_irqrestore(&udc->lock, flags);
1403 return ret;
1404 }
1405
1406 /**
1407 * xudc_stop - stops the device.
1408 * @gadget: pointer to the usb gadget structure
1409 * @driver: pointer to usb gadget driver structure
1410 *
1411 * Return: zero always
1412 */
1413 static int xudc_stop(struct usb_gadget *gadget)
1414 {
1415 struct xusb_udc *udc = to_udc(gadget);
1416 unsigned long flags;
1417
1418 spin_lock_irqsave(&udc->lock, flags);
1419
1420 udc->gadget.speed = USB_SPEED_UNKNOWN;
1421 udc->driver = NULL;
1422
1423 /* Set device address and remote wakeup to 0 */
1424 udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0);
1425 udc->remote_wkp = 0;
1426
1427 xudc_stop_activity(udc);
1428
1429 spin_unlock_irqrestore(&udc->lock, flags);
1430
1431 return 0;
1432 }
1433
1434 static const struct usb_gadget_ops xusb_udc_ops = {
1435 .get_frame = xudc_get_frame,
1436 .wakeup = xudc_wakeup,
1437 .pullup = xudc_pullup,
1438 .udc_start = xudc_start,
1439 .udc_stop = xudc_stop,
1440 };
1441
1442 /**
1443 * xudc_clear_stall_all_ep - clears stall of every endpoint.
1444 * @udc: pointer to the udc structure.
1445 */
1446 static void xudc_clear_stall_all_ep(struct xusb_udc *udc)
1447 {
1448 struct xusb_ep *ep;
1449 u32 epcfgreg;
1450 int i;
1451
1452 for (i = 0; i < XUSB_MAX_ENDPOINTS; i++) {
1453 ep = &udc->ep[i];
1454 epcfgreg = udc->read_fn(udc->addr + ep->offset);
1455 epcfgreg &= ~XUSB_EP_CFG_STALL_MASK;
1456 udc->write_fn(udc->addr, ep->offset, epcfgreg);
1457 if (ep->epnumber) {
1458 /* Reset the toggle bit.*/
1459 epcfgreg = udc->read_fn(udc->addr + ep->offset);
1460 epcfgreg &= ~XUSB_EP_CFG_DATA_TOGGLE_MASK;
1461 udc->write_fn(udc->addr, ep->offset, epcfgreg);
1462 }
1463 }
1464 }
1465
1466 /**
1467 * xudc_startup_handler - The usb device controller interrupt handler.
1468 * @udc: pointer to the udc structure.
1469 * @intrstatus: The mask value containing the interrupt sources.
1470 *
1471 * This function handles the RESET,SUSPEND,RESUME and DISCONNECT interrupts.
1472 */
1473 static void xudc_startup_handler(struct xusb_udc *udc, u32 intrstatus)
1474 {
1475 u32 intrreg;
1476
1477 if (intrstatus & XUSB_STATUS_RESET_MASK) {
1478
1479 dev_dbg(udc->dev, "Reset\n");
1480
1481 if (intrstatus & XUSB_STATUS_HIGH_SPEED_MASK)
1482 udc->gadget.speed = USB_SPEED_HIGH;
1483 else
1484 udc->gadget.speed = USB_SPEED_FULL;
1485
1486 xudc_stop_activity(udc);
1487 xudc_clear_stall_all_ep(udc);
1488 udc->write_fn(udc->addr, XUSB_TESTMODE_OFFSET, 0);
1489
1490 /* Set device address and remote wakeup to 0 */
1491 udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0);
1492 udc->remote_wkp = 0;
1493
1494 /* Enable the suspend, resume and disconnect */
1495 intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET);
1496 intrreg |= XUSB_STATUS_SUSPEND_MASK | XUSB_STATUS_RESUME_MASK |
1497 XUSB_STATUS_DISCONNECT_MASK;
1498 udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg);
1499 }
1500 if (intrstatus & XUSB_STATUS_SUSPEND_MASK) {
1501
1502 dev_dbg(udc->dev, "Suspend\n");
1503
1504 /* Enable the reset, resume and disconnect */
1505 intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET);
1506 intrreg |= XUSB_STATUS_RESET_MASK | XUSB_STATUS_RESUME_MASK |
1507 XUSB_STATUS_DISCONNECT_MASK;
1508 udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg);
1509
1510 udc->usb_state = USB_STATE_SUSPENDED;
1511
1512 if (udc->driver->suspend) {
1513 spin_unlock(&udc->lock);
1514 udc->driver->suspend(&udc->gadget);
1515 spin_lock(&udc->lock);
1516 }
1517 }
1518 if (intrstatus & XUSB_STATUS_RESUME_MASK) {
1519 bool condition = (udc->usb_state != USB_STATE_SUSPENDED);
1520
1521 dev_WARN_ONCE(udc->dev, condition,
1522 "Resume IRQ while not suspended\n");
1523
1524 dev_dbg(udc->dev, "Resume\n");
1525
1526 /* Enable the reset, suspend and disconnect */
1527 intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET);
1528 intrreg |= XUSB_STATUS_RESET_MASK | XUSB_STATUS_SUSPEND_MASK |
1529 XUSB_STATUS_DISCONNECT_MASK;
1530 udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg);
1531
1532 udc->usb_state = 0;
1533
1534 if (udc->driver->resume) {
1535 spin_unlock(&udc->lock);
1536 udc->driver->resume(&udc->gadget);
1537 spin_lock(&udc->lock);
1538 }
1539 }
1540 if (intrstatus & XUSB_STATUS_DISCONNECT_MASK) {
1541
1542 dev_dbg(udc->dev, "Disconnect\n");
1543
1544 /* Enable the reset, resume and suspend */
1545 intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET);
1546 intrreg |= XUSB_STATUS_RESET_MASK | XUSB_STATUS_RESUME_MASK |
1547 XUSB_STATUS_SUSPEND_MASK;
1548 udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg);
1549
1550 if (udc->driver && udc->driver->disconnect) {
1551 spin_unlock(&udc->lock);
1552 udc->driver->disconnect(&udc->gadget);
1553 spin_lock(&udc->lock);
1554 }
1555 }
1556 }
1557
1558 /**
1559 * xudc_ep0_stall - Stall endpoint zero.
1560 * @udc: pointer to the udc structure.
1561 *
1562 * This function stalls endpoint zero.
1563 */
1564 static void xudc_ep0_stall(struct xusb_udc *udc)
1565 {
1566 u32 epcfgreg;
1567 struct xusb_ep *ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO];
1568
1569 epcfgreg = udc->read_fn(udc->addr + ep0->offset);
1570 epcfgreg |= XUSB_EP_CFG_STALL_MASK;
1571 udc->write_fn(udc->addr, ep0->offset, epcfgreg);
1572 }
1573
1574 /**
1575 * xudc_setaddress - executes SET_ADDRESS command
1576 * @udc: pointer to the udc structure.
1577 *
1578 * This function executes USB SET_ADDRESS command
1579 */
1580 static void xudc_setaddress(struct xusb_udc *udc)
1581 {
1582 struct xusb_ep *ep0 = &udc->ep[0];
1583 struct xusb_req *req = udc->req;
1584 int ret;
1585
1586 req->usb_req.length = 0;
1587 ret = __xudc_ep0_queue(ep0, req);
1588 if (ret == 0)
1589 return;
1590
1591 dev_err(udc->dev, "Can't respond to SET ADDRESS request\n");
1592 xudc_ep0_stall(udc);
1593 }
1594
1595 /**
1596 * xudc_getstatus - executes GET_STATUS command
1597 * @udc: pointer to the udc structure.
1598 *
1599 * This function executes USB GET_STATUS command
1600 */
1601 static void xudc_getstatus(struct xusb_udc *udc)
1602 {
1603 struct xusb_ep *ep0 = &udc->ep[0];
1604 struct xusb_req *req = udc->req;
1605 struct xusb_ep *target_ep;
1606 u16 status = 0;
1607 u32 epcfgreg;
1608 int epnum;
1609 u32 halt;
1610 int ret;
1611
1612 switch (udc->setup.bRequestType & USB_RECIP_MASK) {
1613 case USB_RECIP_DEVICE:
1614 /* Get device status */
1615 status = 1 << USB_DEVICE_SELF_POWERED;
1616 if (udc->remote_wkp)
1617 status |= (1 << USB_DEVICE_REMOTE_WAKEUP);
1618 break;
1619 case USB_RECIP_INTERFACE:
1620 break;
1621 case USB_RECIP_ENDPOINT:
1622 epnum = udc->setup.wIndex & USB_ENDPOINT_NUMBER_MASK;
1623 target_ep = &udc->ep[epnum];
1624 epcfgreg = udc->read_fn(udc->addr + target_ep->offset);
1625 halt = epcfgreg & XUSB_EP_CFG_STALL_MASK;
1626 if (udc->setup.wIndex & USB_DIR_IN) {
1627 if (!target_ep->is_in)
1628 goto stall;
1629 } else {
1630 if (target_ep->is_in)
1631 goto stall;
1632 }
1633 if (halt)
1634 status = 1 << USB_ENDPOINT_HALT;
1635 break;
1636 default:
1637 goto stall;
1638 }
1639
1640 req->usb_req.length = 2;
1641 *(u16 *)req->usb_req.buf = cpu_to_le16(status);
1642 ret = __xudc_ep0_queue(ep0, req);
1643 if (ret == 0)
1644 return;
1645 stall:
1646 dev_err(udc->dev, "Can't respond to getstatus request\n");
1647 xudc_ep0_stall(udc);
1648 }
1649
1650 /**
1651 * xudc_set_clear_feature - Executes the set feature and clear feature commands.
1652 * @udc: pointer to the usb device controller structure.
1653 *
1654 * Processes the SET_FEATURE and CLEAR_FEATURE commands.
1655 */
1656 static void xudc_set_clear_feature(struct xusb_udc *udc)
1657 {
1658 struct xusb_ep *ep0 = &udc->ep[0];
1659 struct xusb_req *req = udc->req;
1660 struct xusb_ep *target_ep;
1661 u8 endpoint;
1662 u8 outinbit;
1663 u32 epcfgreg;
1664 int flag = (udc->setup.bRequest == USB_REQ_SET_FEATURE ? 1 : 0);
1665 int ret;
1666
1667 switch (udc->setup.bRequestType) {
1668 case USB_RECIP_DEVICE:
1669 switch (udc->setup.wValue) {
1670 case USB_DEVICE_TEST_MODE:
1671 /*
1672 * The Test Mode will be executed
1673 * after the status phase.
1674 */
1675 break;
1676 case USB_DEVICE_REMOTE_WAKEUP:
1677 if (flag)
1678 udc->remote_wkp = 1;
1679 else
1680 udc->remote_wkp = 0;
1681 break;
1682 default:
1683 xudc_ep0_stall(udc);
1684 break;
1685 }
1686 break;
1687 case USB_RECIP_ENDPOINT:
1688 if (!udc->setup.wValue) {
1689 endpoint = udc->setup.wIndex & USB_ENDPOINT_NUMBER_MASK;
1690 target_ep = &udc->ep[endpoint];
1691 outinbit = udc->setup.wIndex & USB_ENDPOINT_DIR_MASK;
1692 outinbit = outinbit >> 7;
1693
1694 /* Make sure direction matches.*/
1695 if (outinbit != target_ep->is_in) {
1696 xudc_ep0_stall(udc);
1697 return;
1698 }
1699 epcfgreg = udc->read_fn(udc->addr + target_ep->offset);
1700 if (!endpoint) {
1701 /* Clear the stall.*/
1702 epcfgreg &= ~XUSB_EP_CFG_STALL_MASK;
1703 udc->write_fn(udc->addr,
1704 target_ep->offset, epcfgreg);
1705 } else {
1706 if (flag) {
1707 epcfgreg |= XUSB_EP_CFG_STALL_MASK;
1708 udc->write_fn(udc->addr,
1709 target_ep->offset,
1710 epcfgreg);
1711 } else {
1712 /* Unstall the endpoint.*/
1713 epcfgreg &= ~(XUSB_EP_CFG_STALL_MASK |
1714 XUSB_EP_CFG_DATA_TOGGLE_MASK);
1715 udc->write_fn(udc->addr,
1716 target_ep->offset,
1717 epcfgreg);
1718 }
1719 }
1720 }
1721 break;
1722 default:
1723 xudc_ep0_stall(udc);
1724 return;
1725 }
1726
1727 req->usb_req.length = 0;
1728 ret = __xudc_ep0_queue(ep0, req);
1729 if (ret == 0)
1730 return;
1731
1732 dev_err(udc->dev, "Can't respond to SET/CLEAR FEATURE\n");
1733 xudc_ep0_stall(udc);
1734 }
1735
1736 /**
1737 * xudc_handle_setup - Processes the setup packet.
1738 * @udc: pointer to the usb device controller structure.
1739 *
1740 * Process setup packet and delegate to gadget layer.
1741 */
1742 static void xudc_handle_setup(struct xusb_udc *udc)
1743 {
1744 struct xusb_ep *ep0 = &udc->ep[0];
1745 struct usb_ctrlrequest setup;
1746 u32 *ep0rambase;
1747
1748 /* Load up the chapter 9 command buffer.*/
1749 ep0rambase = (u32 __force *) (udc->addr + XUSB_SETUP_PKT_ADDR_OFFSET);
1750 memcpy(&setup, ep0rambase, 8);
1751
1752 udc->setup = setup;
1753 udc->setup.wValue = cpu_to_le16(setup.wValue);
1754 udc->setup.wIndex = cpu_to_le16(setup.wIndex);
1755 udc->setup.wLength = cpu_to_le16(setup.wLength);
1756
1757 /* Clear previous requests */
1758 xudc_nuke(ep0, -ECONNRESET);
1759
1760 if (udc->setup.bRequestType & USB_DIR_IN) {
1761 /* Execute the get command.*/
1762 udc->setupseqrx = STATUS_PHASE;
1763 udc->setupseqtx = DATA_PHASE;
1764 } else {
1765 /* Execute the put command.*/
1766 udc->setupseqrx = DATA_PHASE;
1767 udc->setupseqtx = STATUS_PHASE;
1768 }
1769
1770 switch (udc->setup.bRequest) {
1771 case USB_REQ_GET_STATUS:
1772 /* Data+Status phase form udc */
1773 if ((udc->setup.bRequestType &
1774 (USB_DIR_IN | USB_TYPE_MASK)) !=
1775 (USB_DIR_IN | USB_TYPE_STANDARD))
1776 break;
1777 xudc_getstatus(udc);
1778 return;
1779 case USB_REQ_SET_ADDRESS:
1780 /* Status phase from udc */
1781 if (udc->setup.bRequestType != (USB_DIR_OUT |
1782 USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1783 break;
1784 xudc_setaddress(udc);
1785 return;
1786 case USB_REQ_CLEAR_FEATURE:
1787 case USB_REQ_SET_FEATURE:
1788 /* Requests with no data phase, status phase from udc */
1789 if ((udc->setup.bRequestType & USB_TYPE_MASK)
1790 != USB_TYPE_STANDARD)
1791 break;
1792 xudc_set_clear_feature(udc);
1793 return;
1794 default:
1795 break;
1796 }
1797
1798 spin_unlock(&udc->lock);
1799 if (udc->driver->setup(&udc->gadget, &setup) < 0)
1800 xudc_ep0_stall(udc);
1801 spin_lock(&udc->lock);
1802 }
1803
1804 /**
1805 * xudc_ep0_out - Processes the endpoint 0 OUT token.
1806 * @udc: pointer to the usb device controller structure.
1807 */
1808 static void xudc_ep0_out(struct xusb_udc *udc)
1809 {
1810 struct xusb_ep *ep0 = &udc->ep[0];
1811 struct xusb_req *req;
1812 u8 *ep0rambase;
1813 unsigned int bytes_to_rx;
1814 void *buffer;
1815
1816 req = list_first_entry(&ep0->queue, struct xusb_req, queue);
1817
1818 switch (udc->setupseqrx) {
1819 case STATUS_PHASE:
1820 /*
1821 * This resets both state machines for the next
1822 * Setup packet.
1823 */
1824 udc->setupseqrx = SETUP_PHASE;
1825 udc->setupseqtx = SETUP_PHASE;
1826 req->usb_req.actual = req->usb_req.length;
1827 xudc_done(ep0, req, 0);
1828 break;
1829 case DATA_PHASE:
1830 bytes_to_rx = udc->read_fn(udc->addr +
1831 XUSB_EP_BUF0COUNT_OFFSET);
1832 /* Copy the data to be received from the DPRAM. */
1833 ep0rambase = (u8 __force *) (udc->addr +
1834 (ep0->rambase << 2));
1835 buffer = req->usb_req.buf + req->usb_req.actual;
1836 req->usb_req.actual = req->usb_req.actual + bytes_to_rx;
1837 memcpy(buffer, ep0rambase, bytes_to_rx);
1838
1839 if (req->usb_req.length == req->usb_req.actual) {
1840 /* Data transfer completed get ready for Status stage */
1841 xudc_wrstatus(udc);
1842 } else {
1843 /* Enable EP0 buffer to receive data */
1844 udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, 0);
1845 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1);
1846 }
1847 break;
1848 default:
1849 break;
1850 }
1851 }
1852
1853 /**
1854 * xudc_ep0_in - Processes the endpoint 0 IN token.
1855 * @udc: pointer to the usb device controller structure.
1856 */
1857 static void xudc_ep0_in(struct xusb_udc *udc)
1858 {
1859 struct xusb_ep *ep0 = &udc->ep[0];
1860 struct xusb_req *req;
1861 unsigned int bytes_to_tx;
1862 void *buffer;
1863 u32 epcfgreg;
1864 u16 count = 0;
1865 u16 length;
1866 u8 *ep0rambase;
1867 u8 test_mode = udc->setup.wIndex >> 8;
1868
1869 req = list_first_entry(&ep0->queue, struct xusb_req, queue);
1870 bytes_to_tx = req->usb_req.length - req->usb_req.actual;
1871
1872 switch (udc->setupseqtx) {
1873 case STATUS_PHASE:
1874 switch (udc->setup.bRequest) {
1875 case USB_REQ_SET_ADDRESS:
1876 /* Set the address of the device.*/
1877 udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET,
1878 udc->setup.wValue);
1879 break;
1880 case USB_REQ_SET_FEATURE:
1881 if (udc->setup.bRequestType ==
1882 USB_RECIP_DEVICE) {
1883 if (udc->setup.wValue ==
1884 USB_DEVICE_TEST_MODE)
1885 udc->write_fn(udc->addr,
1886 XUSB_TESTMODE_OFFSET,
1887 test_mode);
1888 }
1889 break;
1890 }
1891 req->usb_req.actual = req->usb_req.length;
1892 xudc_done(ep0, req, 0);
1893 break;
1894 case DATA_PHASE:
1895 if (!bytes_to_tx) {
1896 /*
1897 * We're done with data transfer, next
1898 * will be zero length OUT with data toggle of
1899 * 1. Setup data_toggle.
1900 */
1901 epcfgreg = udc->read_fn(udc->addr + ep0->offset);
1902 epcfgreg |= XUSB_EP_CFG_DATA_TOGGLE_MASK;
1903 udc->write_fn(udc->addr, ep0->offset, epcfgreg);
1904 udc->setupseqtx = STATUS_PHASE;
1905 } else {
1906 length = count = min_t(u32, bytes_to_tx,
1907 EP0_MAX_PACKET);
1908 /* Copy the data to be transmitted into the DPRAM. */
1909 ep0rambase = (u8 __force *) (udc->addr +
1910 (ep0->rambase << 2));
1911 buffer = req->usb_req.buf + req->usb_req.actual;
1912 req->usb_req.actual = req->usb_req.actual + length;
1913 memcpy(ep0rambase, buffer, length);
1914 }
1915 udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, count);
1916 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1);
1917 break;
1918 default:
1919 break;
1920 }
1921 }
1922
1923 /**
1924 * xudc_ctrl_ep_handler - Endpoint 0 interrupt handler.
1925 * @udc: pointer to the udc structure.
1926 * @intrstatus: It's the mask value for the interrupt sources on endpoint 0.
1927 *
1928 * Processes the commands received during enumeration phase.
1929 */
1930 static void xudc_ctrl_ep_handler(struct xusb_udc *udc, u32 intrstatus)
1931 {
1932
1933 if (intrstatus & XUSB_STATUS_SETUP_PACKET_MASK) {
1934 xudc_handle_setup(udc);
1935 } else {
1936 if (intrstatus & XUSB_STATUS_FIFO_BUFF_RDY_MASK)
1937 xudc_ep0_out(udc);
1938 else if (intrstatus & XUSB_STATUS_FIFO_BUFF_FREE_MASK)
1939 xudc_ep0_in(udc);
1940 }
1941 }
1942
1943 /**
1944 * xudc_nonctrl_ep_handler - Non control endpoint interrupt handler.
1945 * @udc: pointer to the udc structure.
1946 * @epnum: End point number for which the interrupt is to be processed
1947 * @intrstatus: mask value for interrupt sources of endpoints other
1948 * than endpoint 0.
1949 *
1950 * Processes the buffer completion interrupts.
1951 */
1952 static void xudc_nonctrl_ep_handler(struct xusb_udc *udc, u8 epnum,
1953 u32 intrstatus)
1954 {
1955
1956 struct xusb_req *req;
1957 struct xusb_ep *ep;
1958
1959 ep = &udc->ep[epnum];
1960 /* Process the End point interrupts.*/
1961 if (intrstatus & (XUSB_STATUS_EP0_BUFF1_COMP_MASK << epnum))
1962 ep->buffer0ready = 0;
1963 if (intrstatus & (XUSB_STATUS_EP0_BUFF2_COMP_MASK << epnum))
1964 ep->buffer1ready = 0;
1965
1966 if (list_empty(&ep->queue))
1967 return;
1968
1969 req = list_first_entry(&ep->queue, struct xusb_req, queue);
1970
1971 if (ep->is_in)
1972 xudc_write_fifo(ep, req);
1973 else
1974 xudc_read_fifo(ep, req);
1975 }
1976
1977 /**
1978 * xudc_irq - The main interrupt handler.
1979 * @irq: The interrupt number.
1980 * @_udc: pointer to the usb device controller structure.
1981 *
1982 * Return: IRQ_HANDLED after the interrupt is handled.
1983 */
1984 static irqreturn_t xudc_irq(int irq, void *_udc)
1985 {
1986 struct xusb_udc *udc = _udc;
1987 u32 intrstatus;
1988 u32 ier;
1989 u8 index;
1990 u32 bufintr;
1991 unsigned long flags;
1992
1993 spin_lock_irqsave(&udc->lock, flags);
1994
1995 /*
1996 * Event interrupts are level sensitive hence first disable
1997 * IER, read ISR and figure out active interrupts.
1998 */
1999 ier = udc->read_fn(udc->addr + XUSB_IER_OFFSET);
2000 ier &= ~XUSB_STATUS_INTR_EVENT_MASK;
2001 udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier);
2002
2003 /* Read the Interrupt Status Register.*/
2004 intrstatus = udc->read_fn(udc->addr + XUSB_STATUS_OFFSET);
2005
2006 /* Call the handler for the event interrupt.*/
2007 if (intrstatus & XUSB_STATUS_INTR_EVENT_MASK) {
2008 /*
2009 * Check if there is any action to be done for :
2010 * - USB Reset received {XUSB_STATUS_RESET_MASK}
2011 * - USB Suspend received {XUSB_STATUS_SUSPEND_MASK}
2012 * - USB Resume received {XUSB_STATUS_RESUME_MASK}
2013 * - USB Disconnect received {XUSB_STATUS_DISCONNECT_MASK}
2014 */
2015 xudc_startup_handler(udc, intrstatus);
2016 }
2017
2018 /* Check the buffer completion interrupts */
2019 if (intrstatus & XUSB_STATUS_INTR_BUFF_COMP_ALL_MASK) {
2020 /* Enable Reset, Suspend, Resume and Disconnect */
2021 ier = udc->read_fn(udc->addr + XUSB_IER_OFFSET);
2022 ier |= XUSB_STATUS_INTR_EVENT_MASK;
2023 udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier);
2024
2025 if (intrstatus & XUSB_STATUS_EP0_BUFF1_COMP_MASK)
2026 xudc_ctrl_ep_handler(udc, intrstatus);
2027
2028 for (index = 1; index < 8; index++) {
2029 bufintr = ((intrstatus &
2030 (XUSB_STATUS_EP1_BUFF1_COMP_MASK <<
2031 (index - 1))) || (intrstatus &
2032 (XUSB_STATUS_EP1_BUFF2_COMP_MASK <<
2033 (index - 1))));
2034 if (bufintr) {
2035 xudc_nonctrl_ep_handler(udc, index,
2036 intrstatus);
2037 }
2038 }
2039 }
2040
2041 spin_unlock_irqrestore(&udc->lock, flags);
2042 return IRQ_HANDLED;
2043 }
2044
2045 /**
2046 * xudc_probe - The device probe function for driver initialization.
2047 * @pdev: pointer to the platform device structure.
2048 *
2049 * Return: 0 for success and error value on failure
2050 */
2051 static int xudc_probe(struct platform_device *pdev)
2052 {
2053 struct device_node *np = pdev->dev.of_node;
2054 struct resource *res;
2055 struct xusb_udc *udc;
2056 int irq;
2057 int ret;
2058 u32 ier;
2059 u8 *buff;
2060
2061 udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL);
2062 if (!udc)
2063 return -ENOMEM;
2064
2065 /* Create a dummy request for GET_STATUS, SET_ADDRESS */
2066 udc->req = devm_kzalloc(&pdev->dev, sizeof(struct xusb_req),
2067 GFP_KERNEL);
2068 if (!udc->req)
2069 return -ENOMEM;
2070
2071 buff = devm_kzalloc(&pdev->dev, STATUSBUFF_SIZE, GFP_KERNEL);
2072 if (!buff)
2073 return -ENOMEM;
2074
2075 udc->req->usb_req.buf = buff;
2076
2077 /* Map the registers */
2078 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2079 udc->addr = devm_ioremap_resource(&pdev->dev, res);
2080 if (IS_ERR(udc->addr))
2081 return PTR_ERR(udc->addr);
2082
2083 irq = platform_get_irq(pdev, 0);
2084 if (irq < 0) {
2085 dev_err(&pdev->dev, "unable to get irq\n");
2086 return irq;
2087 }
2088 ret = devm_request_irq(&pdev->dev, irq, xudc_irq, 0,
2089 dev_name(&pdev->dev), udc);
2090 if (ret < 0) {
2091 dev_dbg(&pdev->dev, "unable to request irq %d", irq);
2092 goto fail;
2093 }
2094
2095 udc->dma_enabled = of_property_read_bool(np, "xlnx,has-builtin-dma");
2096
2097 /* Setup gadget structure */
2098 udc->gadget.ops = &xusb_udc_ops;
2099 udc->gadget.max_speed = USB_SPEED_HIGH;
2100 udc->gadget.speed = USB_SPEED_UNKNOWN;
2101 udc->gadget.ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO].ep_usb;
2102 udc->gadget.name = driver_name;
2103
2104 spin_lock_init(&udc->lock);
2105
2106 /* Check for IP endianness */
2107 udc->write_fn = xudc_write32_be;
2108 udc->read_fn = xudc_read32_be;
2109 udc->write_fn(udc->addr, XUSB_TESTMODE_OFFSET, TEST_J);
2110 if ((udc->read_fn(udc->addr + XUSB_TESTMODE_OFFSET))
2111 != TEST_J) {
2112 udc->write_fn = xudc_write32;
2113 udc->read_fn = xudc_read32;
2114 }
2115 udc->write_fn(udc->addr, XUSB_TESTMODE_OFFSET, 0);
2116
2117 xudc_eps_init(udc);
2118
2119 /* Set device address to 0.*/
2120 udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0);
2121
2122 ret = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
2123 if (ret)
2124 goto fail;
2125
2126 udc->dev = &udc->gadget.dev;
2127
2128 /* Enable the interrupts.*/
2129 ier = XUSB_STATUS_GLOBAL_INTR_MASK | XUSB_STATUS_INTR_EVENT_MASK |
2130 XUSB_STATUS_FIFO_BUFF_RDY_MASK | XUSB_STATUS_FIFO_BUFF_FREE_MASK |
2131 XUSB_STATUS_SETUP_PACKET_MASK |
2132 XUSB_STATUS_INTR_BUFF_COMP_ALL_MASK;
2133
2134 udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier);
2135
2136 platform_set_drvdata(pdev, udc);
2137
2138 dev_vdbg(&pdev->dev, "%s at 0x%08X mapped to %p %s\n",
2139 driver_name, (u32)res->start, udc->addr,
2140 udc->dma_enabled ? "with DMA" : "without DMA");
2141
2142 return 0;
2143 fail:
2144 dev_err(&pdev->dev, "probe failed, %d\n", ret);
2145 return ret;
2146 }
2147
2148 /**
2149 * xudc_remove - Releases the resources allocated during the initialization.
2150 * @pdev: pointer to the platform device structure.
2151 *
2152 * Return: 0 always
2153 */
2154 static int xudc_remove(struct platform_device *pdev)
2155 {
2156 struct xusb_udc *udc = platform_get_drvdata(pdev);
2157
2158 usb_del_gadget_udc(&udc->gadget);
2159
2160 return 0;
2161 }
2162
2163 /* Match table for of_platform binding */
2164 static const struct of_device_id usb_of_match[] = {
2165 { .compatible = "xlnx,usb2-device-4.00.a", },
2166 { /* end of list */ },
2167 };
2168 MODULE_DEVICE_TABLE(of, usb_of_match);
2169
2170 static struct platform_driver xudc_driver = {
2171 .driver = {
2172 .name = driver_name,
2173 .of_match_table = usb_of_match,
2174 },
2175 .probe = xudc_probe,
2176 .remove = xudc_remove,
2177 };
2178
2179 module_platform_driver(xudc_driver);
2180
2181 MODULE_DESCRIPTION("Xilinx udc driver");
2182 MODULE_AUTHOR("Xilinx, Inc");
2183 MODULE_LICENSE("GPL");
Linux with added FPC-III support