drivers/usb/host/xhci-pci.c

   1 /*
   2  * xHCI host controller driver PCI Bus Glue.
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/pci.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/acpi.h>
  27
  28 #include "xhci.h"
  29 #include "xhci-trace.h"
  30
  31 #define SSIC_PORT_NUM           2
  32 #define SSIC_PORT_CFG2          0x880c
  33 #define SSIC_PORT_CFG2_OFFSET   0x30
  34 #define PROG_DONE               (1 << 30)
  35 #define SSIC_PORT_UNUSED        (1 << 31)
  36
  37 /* Device for a quirk */
  38 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  39 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  40 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  41 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  42
  43 #define PCI_VENDOR_ID_ETRON             0x1b6f
  44 #define PCI_DEVICE_ID_EJ168             0x7023
  45
  46 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  47 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  48 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  49 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  50 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  51 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  52 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  53 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  54 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  55
  56 static const char hcd_name[] = "xhci_hcd";
  57
  58 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  59
  60 static int xhci_pci_setup(struct usb_hcd *hcd);
  61
  62 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  63         .reset = xhci_pci_setup,
  64 };
  65
  66 /* called after powerup, by probe or system-pm "wakeup" */
  67 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  68 {
  69         /*
  70          * TODO: Implement finding debug ports later.
  71          * TODO: see if there are any quirks that need to be added to handle
  72          * new extended capabilities.
  73          */
  74
  75         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  76         if (!pci_set_mwi(pdev))
  77                 xhci_dbg(xhci, "MWI active\n");
  78
  79         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  80         return 0;
  81 }
  82
  83 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  84 {
  85         struct pci_dev          *pdev = to_pci_dev(dev);
  86
  87         /* Look for vendor-specific quirks */
  88         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
  89                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
  90                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
  91                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  92                                 pdev->revision == 0x0) {
  93                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
  94                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  95                                 "QUIRK: Fresco Logic xHC needs configure"
  96                                 " endpoint cmd after reset endpoint");
  97                 }
  98                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  99                                 pdev->revision == 0x4) {
 100                         xhci->quirks |= XHCI_SLOW_SUSPEND;
 101                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 102                                 "QUIRK: Fresco Logic xHC revision %u"
 103                                 "must be suspended extra slowly",
 104                                 pdev->revision);
 105                 }
 106                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 107                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 108                 /* Fresco Logic confirms: all revisions of this chip do not
 109                  * support MSI, even though some of them claim to in their PCI
 110                  * capabilities.
 111                  */
 112                 xhci->quirks |= XHCI_BROKEN_MSI;
 113                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 114                                 "QUIRK: Fresco Logic revision %u "
 115                                 "has broken MSI implementation",
 116                                 pdev->revision);
 117                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 118         }
 119
 120         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 121                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 122                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 123
 124         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 125                 xhci->quirks |= XHCI_NEC_HOST;
 126
 127         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 128                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 129
 130         /* AMD PLL quirk */
 131         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
 132                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 133
 134         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 135                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 136
 137         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 138                 xhci->quirks |= XHCI_LPM_SUPPORT;
 139                 xhci->quirks |= XHCI_INTEL_HOST;
 140                 xhci->quirks |= XHCI_AVOID_BEI;
 141         }
 142         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 143                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 144                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 145                 xhci->limit_active_eps = 64;
 146                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 147                 /*
 148                  * PPT desktop boards DH77EB and DH77DF will power back on after
 149                  * a few seconds of being shutdown.  The fix for this is to
 150                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 151                  * DMI information to find those particular boards (since each
 152                  * vendor will change the board name), so we have to key off all
 153                  * PPT chipsets.
 154                  */
 155                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 156         }
 157         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 158                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 159                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 160                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 161                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 162         }
 163         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 164                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 165                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 166                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 167                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 168                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 169                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI)) {
 170                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 171         }
 172         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 173                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
 174                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 175         }
 176         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 177             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 178              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
 179                 xhci->quirks |= XHCI_MISSING_CAS;
 180
 181         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 182                         pdev->device == PCI_DEVICE_ID_EJ168) {
 183                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 184                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 185                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 186         }
 187         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 188                         pdev->device == 0x0015)
 189                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 190         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 191                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 192
 193         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 194         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 195                         pdev->device == 0x3432)
 196                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 197
 198         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 199                         pdev->device == 0x1042)
 200                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 201
 202         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 203                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 204                                 "QUIRK: Resetting on resume");
 205 }
 206
 207 #ifdef CONFIG_ACPI
 208 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 209 {
 210         static const u8 intel_dsm_uuid[] = {
 211                 0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45,
 212                 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23,
 213         };
 214         union acpi_object *obj;
 215
 216         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1,
 217                                 NULL);
 218         ACPI_FREE(obj);
 219 }
 220 #else
 221 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 222 #endif /* CONFIG_ACPI */
 223
 224 /* called during probe() after chip reset completes */
 225 static int xhci_pci_setup(struct usb_hcd *hcd)
 226 {
 227         struct xhci_hcd         *xhci;
 228         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 229         int                     retval;
 230
 231         xhci = hcd_to_xhci(hcd);
 232         if (!xhci->sbrn)
 233                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 234
 235         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 236         if (retval)
 237                 return retval;
 238
 239         if (!usb_hcd_is_primary_hcd(hcd))
 240                 return 0;
 241
 242         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 243
 244         /* Find any debug ports */
 245         return xhci_pci_reinit(xhci, pdev);
 246 }
 247
 248 /*
 249  * We need to register our own PCI probe function (instead of the USB core's
 250  * function) in order to create a second roothub under xHCI.
 251  */
 252 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 253 {
 254         int retval;
 255         struct xhci_hcd *xhci;
 256         struct hc_driver *driver;
 257         struct usb_hcd *hcd;
 258
 259         driver = (struct hc_driver *)id->driver_data;
 260
 261         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 262         pm_runtime_get_noresume(&dev->dev);
 263
 264         /* Register the USB 2.0 roothub.
 265          * FIXME: USB core must know to register the USB 2.0 roothub first.
 266          * This is sort of silly, because we could just set the HCD driver flags
 267          * to say USB 2.0, but I'm not sure what the implications would be in
 268          * the other parts of the HCD code.
 269          */
 270         retval = usb_hcd_pci_probe(dev, id);
 271
 272         if (retval)
 273                 goto put_runtime_pm;
 274
 275         /* USB 2.0 roothub is stored in the PCI device now. */
 276         hcd = dev_get_drvdata(&dev->dev);
 277         xhci = hcd_to_xhci(hcd);
 278         xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
 279                                 pci_name(dev), hcd);
 280         if (!xhci->shared_hcd) {
 281                 retval = -ENOMEM;
 282                 goto dealloc_usb2_hcd;
 283         }
 284
 285         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 286                         IRQF_SHARED);
 287         if (retval)
 288                 goto put_usb3_hcd;
 289         /* Roothub already marked as USB 3.0 speed */
 290
 291         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 292                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 293                 xhci->shared_hcd->can_do_streams = 1;
 294
 295         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 296                 xhci_pme_acpi_rtd3_enable(dev);
 297
 298         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 299         pm_runtime_put_noidle(&dev->dev);
 300
 301         return 0;
 302
 303 put_usb3_hcd:
 304         usb_put_hcd(xhci->shared_hcd);
 305 dealloc_usb2_hcd:
 306         usb_hcd_pci_remove(dev);
 307 put_runtime_pm:
 308         pm_runtime_put_noidle(&dev->dev);
 309         return retval;
 310 }
 311
 312 static void xhci_pci_remove(struct pci_dev *dev)
 313 {
 314         struct xhci_hcd *xhci;
 315
 316         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 317         xhci->xhc_state |= XHCI_STATE_REMOVING;
 318         if (xhci->shared_hcd) {
 319                 usb_remove_hcd(xhci->shared_hcd);
 320                 usb_put_hcd(xhci->shared_hcd);
 321         }
 322
 323         /* Workaround for spurious wakeups at shutdown with HSW */
 324         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 325                 pci_set_power_state(dev, PCI_D3hot);
 326
 327         usb_hcd_pci_remove(dev);
 328 }
 329
 330 #ifdef CONFIG_PM
 331 /*
 332  * In some Intel xHCI controllers, in order to get D3 working,
 333  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 334  * SSIC PORT need to be marked as "unused" before putting xHCI
 335  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 336  * Without this change, xHCI might not enter D3 state.
 337  */
 338 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 339 {
 340         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 341         u32 val;
 342         void __iomem *reg;
 343         int i;
 344
 345         for (i = 0; i < SSIC_PORT_NUM; i++) {
 346                 reg = (void __iomem *) xhci->cap_regs +
 347                                 SSIC_PORT_CFG2 +
 348                                 i * SSIC_PORT_CFG2_OFFSET;
 349
 350                 /* Notify SSIC that SSIC profile programming is not done. */
 351                 val = readl(reg) & ~PROG_DONE;
 352                 writel(val, reg);
 353
 354                 /* Mark SSIC port as unused(suspend) or used(resume) */
 355                 val = readl(reg);
 356                 if (suspend)
 357                         val |= SSIC_PORT_UNUSED;
 358                 else
 359                         val &= ~SSIC_PORT_UNUSED;
 360                 writel(val, reg);
 361
 362                 /* Notify SSIC that SSIC profile programming is done */
 363                 val = readl(reg) | PROG_DONE;
 364                 writel(val, reg);
 365                 readl(reg);
 366         }
 367 }
 368
 369 /*
 370  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 371  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 372  */
 373 static void xhci_pme_quirk(struct usb_hcd *hcd)
 374 {
 375         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 376         void __iomem *reg;
 377         u32 val;
 378
 379         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 380         val = readl(reg);
 381         writel(val | BIT(28), reg);
 382         readl(reg);
 383 }
 384
 385 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 386 {
 387         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 388         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 389         int                     ret;
 390
 391         /*
 392          * Systems with the TI redriver that loses port status change events
 393          * need to have the registers polled during D3, so avoid D3cold.
 394          */
 395         if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
 396                 pci_d3cold_disable(pdev);
 397
 398         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 399                 xhci_pme_quirk(hcd);
 400
 401         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 402                 xhci_ssic_port_unused_quirk(hcd, true);
 403
 404         ret = xhci_suspend(xhci, do_wakeup);
 405         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 406                 xhci_ssic_port_unused_quirk(hcd, false);
 407
 408         return ret;
 409 }
 410
 411 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 412 {
 413         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 414         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 415         int                     retval = 0;
 416
 417         /* The BIOS on systems with the Intel Panther Point chipset may or may
 418          * not support xHCI natively.  That means that during system resume, it
 419          * may switch the ports back to EHCI so that users can use their
 420          * keyboard to select a kernel from GRUB after resume from hibernate.
 421          *
 422          * The BIOS is supposed to remember whether the OS had xHCI ports
 423          * enabled before resume, and switch the ports back to xHCI when the
 424          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 425          * writers.
 426          *
 427          * Unconditionally switch the ports back to xHCI after a system resume.
 428          * It should not matter whether the EHCI or xHCI controller is
 429          * resumed first. It's enough to do the switchover in xHCI because
 430          * USB core won't notice anything as the hub driver doesn't start
 431          * running again until after all the devices (including both EHCI and
 432          * xHCI host controllers) have been resumed.
 433          */
 434
 435         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 436                 usb_enable_intel_xhci_ports(pdev);
 437
 438         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 439                 xhci_ssic_port_unused_quirk(hcd, false);
 440
 441         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 442                 xhci_pme_quirk(hcd);
 443
 444         retval = xhci_resume(xhci, hibernated);
 445         return retval;
 446 }
 447 #endif /* CONFIG_PM */
 448
 449 /*-------------------------------------------------------------------------*/
 450
 451 /* PCI driver selection metadata; PCI hotplugging uses this */
 452 static const struct pci_device_id pci_ids[] = { {
 453         /* handle any USB 3.0 xHCI controller */
 454         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 455         .driver_data =  (unsigned long) &xhci_pci_hc_driver,
 456         },
 457         { /* end: all zeroes */ }
 458 };
 459 MODULE_DEVICE_TABLE(pci, pci_ids);
 460
 461 /* pci driver glue; this is a "new style" PCI driver module */
 462 static struct pci_driver xhci_pci_driver = {
 463         .name =         (char *) hcd_name,
 464         .id_table =     pci_ids,
 465
 466         .probe =        xhci_pci_probe,
 467         .remove =       xhci_pci_remove,
 468         /* suspend and resume implemented later */
 469
 470         .shutdown =     usb_hcd_pci_shutdown,
 471 #ifdef CONFIG_PM
 472         .driver = {
 473                 .pm = &usb_hcd_pci_pm_ops
 474         },
 475 #endif
 476 };
 477
 478 static int __init xhci_pci_init(void)
 479 {
 480         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 481 #ifdef CONFIG_PM
 482         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 483         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 484 #endif
 485         return pci_register_driver(&xhci_pci_driver);
 486 }
 487 module_init(xhci_pci_init);
 488
 489 static void __exit xhci_pci_exit(void)
 490 {
 491         pci_unregister_driver(&xhci_pci_driver);
 492 }
 493 module_exit(xhci_pci_exit);
 494
 495 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 496 MODULE_LICENSE("GPL");