drivers/ata/ahci_qoriq.c

   1 /*
   2  * Freescale QorIQ AHCI SATA platform driver
   3  *
   4  * Copyright 2015 Freescale, Inc.
   5  *   Tang Yuantian <Yuantian.Tang@freescale.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2, or (at your option)
  10  * any later version.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/pm.h>
  16 #include <linux/ahci_platform.h>
  17 #include <linux/device.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/libata.h>
  23 #include "ahci.h"
  24
  25 #define DRV_NAME "ahci-qoriq"
  26
  27 /* port register definition */
  28 #define PORT_PHY1       0xA8
  29 #define PORT_PHY2       0xAC
  30 #define PORT_PHY3       0xB0
  31 #define PORT_PHY4       0xB4
  32 #define PORT_PHY5       0xB8
  33 #define PORT_AXICC      0xBC
  34 #define PORT_TRANS      0xC8
  35
  36 /* port register default value */
  37 #define AHCI_PORT_PHY_1_CFG     0xa003fffe
  38 #define AHCI_PORT_TRANS_CFG     0x08000029
  39 #define AHCI_PORT_AXICC_CFG     0x3fffffff
  40
  41 /* for ls1021a */
  42 #define LS1021A_PORT_PHY2       0x28183414
  43 #define LS1021A_PORT_PHY3       0x0e080e06
  44 #define LS1021A_PORT_PHY4       0x064a080b
  45 #define LS1021A_PORT_PHY5       0x2aa86470
  46 #define LS1021A_AXICC_ADDR      0xC0
  47
  48 #define SATA_ECC_DISABLE        0x00020000
  49
  50 enum ahci_qoriq_type {
  51         AHCI_LS1021A,
  52         AHCI_LS1043A,
  53         AHCI_LS2080A,
  54 };
  55
  56 struct ahci_qoriq_priv {
  57         struct ccsr_ahci *reg_base;
  58         enum ahci_qoriq_type type;
  59         void __iomem *ecc_addr;
  60 };
  61
  62 static const struct of_device_id ahci_qoriq_of_match[] = {
  63         { .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
  64         { .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
  65         { .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
  66         {},
  67 };
  68 MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
  69
  70 static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
  71                           unsigned long deadline)
  72 {
  73         const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
  74         void __iomem *port_mmio = ahci_port_base(link->ap);
  75         u32 px_cmd, px_is, px_val;
  76         struct ata_port *ap = link->ap;
  77         struct ahci_port_priv *pp = ap->private_data;
  78         struct ahci_host_priv *hpriv = ap->host->private_data;
  79         struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
  80         u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
  81         struct ata_taskfile tf;
  82         bool online;
  83         int rc;
  84         bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);
  85
  86         DPRINTK("ENTER\n");
  87
  88         ahci_stop_engine(ap);
  89
  90         /*
  91          * There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
  92          * A-009042: The device detection initialization sequence
  93          * mistakenly resets some registers.
  94          *
  95          * Workaround for this is:
  96          * The software should read and store PxCMD and PxIS values
  97          * before issuing the device detection initialization sequence.
  98          * After the sequence is complete, software should restore the
  99          * PxCMD and PxIS with the stored values.
 100          */
 101         if (ls1021a_workaround) {
 102                 px_cmd = readl(port_mmio + PORT_CMD);
 103                 px_is = readl(port_mmio + PORT_IRQ_STAT);
 104         }
 105
 106         /* clear D2H reception area to properly wait for D2H FIS */
 107         ata_tf_init(link->device, &tf);
 108         tf.command = ATA_BUSY;
 109         ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 110
 111         rc = sata_link_hardreset(link, timing, deadline, &online,
 112                                  ahci_check_ready);
 113
 114         /* restore the PxCMD and PxIS on ls1021 */
 115         if (ls1021a_workaround) {
 116                 px_val = readl(port_mmio + PORT_CMD);
 117                 if (px_val != px_cmd)
 118                         writel(px_cmd, port_mmio + PORT_CMD);
 119
 120                 px_val = readl(port_mmio + PORT_IRQ_STAT);
 121                 if (px_val != px_is)
 122                         writel(px_is, port_mmio + PORT_IRQ_STAT);
 123         }
 124
 125         hpriv->start_engine(ap);
 126
 127         if (online)
 128                 *class = ahci_dev_classify(ap);
 129
 130         DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
 131         return rc;
 132 }
 133
 134 static struct ata_port_operations ahci_qoriq_ops = {
 135         .inherits       = &ahci_ops,
 136         .hardreset      = ahci_qoriq_hardreset,
 137 };
 138
 139 static const struct ata_port_info ahci_qoriq_port_info = {
 140         .flags          = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
 141         .pio_mask       = ATA_PIO4,
 142         .udma_mask      = ATA_UDMA6,
 143         .port_ops       = &ahci_qoriq_ops,
 144 };
 145
 146 static struct scsi_host_template ahci_qoriq_sht = {
 147         AHCI_SHT(DRV_NAME),
 148 };
 149
 150 static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
 151 {
 152         struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
 153         void __iomem *reg_base = hpriv->mmio;
 154
 155         switch (qpriv->type) {
 156         case AHCI_LS1021A:
 157                 writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
 158                 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
 159                 writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
 160                 writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
 161                 writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
 162                 writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
 163                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
 164                 writel(AHCI_PORT_AXICC_CFG, reg_base + LS1021A_AXICC_ADDR);
 165                 break;
 166
 167         case AHCI_LS1043A:
 168                 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
 169                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
 170                 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
 171                 break;
 172
 173         case AHCI_LS2080A:
 174                 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
 175                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
 176                 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
 177                 break;
 178         }
 179
 180         return 0;
 181 }
 182
 183 static int ahci_qoriq_probe(struct platform_device *pdev)
 184 {
 185         struct device_node *np = pdev->dev.of_node;
 186         struct device *dev = &pdev->dev;
 187         struct ahci_host_priv *hpriv;
 188         struct ahci_qoriq_priv *qoriq_priv;
 189         const struct of_device_id *of_id;
 190         struct resource *res;
 191         int rc;
 192
 193         hpriv = ahci_platform_get_resources(pdev);
 194         if (IS_ERR(hpriv))
 195                 return PTR_ERR(hpriv);
 196
 197         of_id = of_match_node(ahci_qoriq_of_match, np);
 198         if (!of_id)
 199                 return -ENODEV;
 200
 201         qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
 202         if (!qoriq_priv)
 203                 return -ENOMEM;
 204
 205         qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;
 206
 207         if (qoriq_priv->type == AHCI_LS1021A) {
 208                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 209                                 "sata-ecc");
 210                 qoriq_priv->ecc_addr = devm_ioremap_resource(dev, res);
 211                 if (IS_ERR(qoriq_priv->ecc_addr))
 212                         return PTR_ERR(qoriq_priv->ecc_addr);
 213         }
 214
 215         rc = ahci_platform_enable_resources(hpriv);
 216         if (rc)
 217                 return rc;
 218
 219         hpriv->plat_data = qoriq_priv;
 220         rc = ahci_qoriq_phy_init(hpriv);
 221         if (rc)
 222                 goto disable_resources;
 223
 224         rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
 225                                      &ahci_qoriq_sht);
 226         if (rc)
 227                 goto disable_resources;
 228
 229         return 0;
 230
 231 disable_resources:
 232         ahci_platform_disable_resources(hpriv);
 233
 234         return rc;
 235 }
 236
 237 #ifdef CONFIG_PM_SLEEP
 238 static int ahci_qoriq_resume(struct device *dev)
 239 {
 240         struct ata_host *host = dev_get_drvdata(dev);
 241         struct ahci_host_priv *hpriv = host->private_data;
 242         int rc;
 243
 244         rc = ahci_platform_enable_resources(hpriv);
 245         if (rc)
 246                 return rc;
 247
 248         rc = ahci_qoriq_phy_init(hpriv);
 249         if (rc)
 250                 goto disable_resources;
 251
 252         rc = ahci_platform_resume_host(dev);
 253         if (rc)
 254                 goto disable_resources;
 255
 256         /* We resumed so update PM runtime state */
 257         pm_runtime_disable(dev);
 258         pm_runtime_set_active(dev);
 259         pm_runtime_enable(dev);
 260
 261         return 0;
 262
 263 disable_resources:
 264         ahci_platform_disable_resources(hpriv);
 265
 266         return rc;
 267 }
 268 #endif
 269
 270 static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
 271                          ahci_qoriq_resume);
 272
 273 static struct platform_driver ahci_qoriq_driver = {
 274         .probe = ahci_qoriq_probe,
 275         .remove = ata_platform_remove_one,
 276         .driver = {
 277                 .name = DRV_NAME,
 278                 .of_match_table = ahci_qoriq_of_match,
 279                 .pm = &ahci_qoriq_pm_ops,
 280         },
 281 };
 282 module_platform_driver(ahci_qoriq_driver);
 283
 284 MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
 285 MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
 286 MODULE_LICENSE("GPL");