drivers/gpu/drm/cirrus/cirrus_mode.c

   1
   2 /*
   3  * Copyright 2012 Red Hat
   4  *
   5  * This file is subject to the terms and conditions of the GNU General
   6  * Public License version 2. See the file COPYING in the main
   7  * directory of this archive for more details.
   8  *
   9  * Authors: Matthew Garrett
  10  *          Dave Airlie
  11  *
  12  * Portions of this code derived from cirrusfb.c:
  13  * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
  14  *
  15  * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
  16  */
  17 #include <drm/drmP.h>
  18 #include <drm/drm_crtc_helper.h>
  19 #include <drm/drm_plane_helper.h>
  20
  21 #include <video/cirrus.h>
  22
  23 #include "cirrus_drv.h"
  24
  25 #define CIRRUS_LUT_SIZE 256
  26
  27 #define PALETTE_INDEX 0x8
  28 #define PALETTE_DATA 0x9
  29
  30 /*
  31  * This file contains setup code for the CRTC.
  32  */
  33
  34 /*
  35  * The DRM core requires DPMS functions, but they make little sense in our
  36  * case and so are just stubs
  37  */
  38
  39 static void cirrus_crtc_dpms(struct drm_crtc *crtc, int mode)
  40 {
  41         struct drm_device *dev = crtc->dev;
  42         struct cirrus_device *cdev = dev->dev_private;
  43         u8 sr01, gr0e;
  44
  45         switch (mode) {
  46         case DRM_MODE_DPMS_ON:
  47                 sr01 = 0x00;
  48                 gr0e = 0x00;
  49                 break;
  50         case DRM_MODE_DPMS_STANDBY:
  51                 sr01 = 0x20;
  52                 gr0e = 0x02;
  53                 break;
  54         case DRM_MODE_DPMS_SUSPEND:
  55                 sr01 = 0x20;
  56                 gr0e = 0x04;
  57                 break;
  58         case DRM_MODE_DPMS_OFF:
  59                 sr01 = 0x20;
  60                 gr0e = 0x06;
  61                 break;
  62         default:
  63                 return;
  64         }
  65
  66         WREG8(SEQ_INDEX, 0x1);
  67         sr01 |= RREG8(SEQ_DATA) & ~0x20;
  68         WREG_SEQ(0x1, sr01);
  69
  70         WREG8(GFX_INDEX, 0xe);
  71         gr0e |= RREG8(GFX_DATA) & ~0x06;
  72         WREG_GFX(0xe, gr0e);
  73 }
  74
  75 static void cirrus_set_start_address(struct drm_crtc *crtc, unsigned offset)
  76 {
  77         struct cirrus_device *cdev = crtc->dev->dev_private;
  78         u32 addr;
  79         u8 tmp;
  80
  81         addr = offset >> 2;
  82         WREG_CRT(0x0c, (u8)((addr >> 8) & 0xff));
  83         WREG_CRT(0x0d, (u8)(addr & 0xff));
  84
  85         WREG8(CRT_INDEX, 0x1b);
  86         tmp = RREG8(CRT_DATA);
  87         tmp &= 0xf2;
  88         tmp |= (addr >> 16) & 0x01;
  89         tmp |= (addr >> 15) & 0x0c;
  90         WREG_CRT(0x1b, tmp);
  91         WREG8(CRT_INDEX, 0x1d);
  92         tmp = RREG8(CRT_DATA);
  93         tmp &= 0x7f;
  94         tmp |= (addr >> 12) & 0x80;
  95         WREG_CRT(0x1d, tmp);
  96 }
  97
  98 /* cirrus is different - we will force move buffers out of VRAM */
  99 static int cirrus_crtc_do_set_base(struct drm_crtc *crtc,
 100                                 struct drm_framebuffer *fb,
 101                                 int x, int y, int atomic)
 102 {
 103         struct cirrus_device *cdev = crtc->dev->dev_private;
 104         struct cirrus_bo *bo;
 105         int ret;
 106         u64 gpu_addr;
 107
 108         /* push the previous fb to system ram */
 109         if (!atomic && fb) {
 110                 bo = gem_to_cirrus_bo(fb->obj[0]);
 111                 ret = cirrus_bo_reserve(bo, false);
 112                 if (ret)
 113                         return ret;
 114                 cirrus_bo_push_sysram(bo);
 115                 cirrus_bo_unreserve(bo);
 116         }
 117
 118         bo = gem_to_cirrus_bo(crtc->primary->fb->obj[0]);
 119
 120         ret = cirrus_bo_reserve(bo, false);
 121         if (ret)
 122                 return ret;
 123
 124         ret = cirrus_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
 125         if (ret) {
 126                 cirrus_bo_unreserve(bo);
 127                 return ret;
 128         }
 129
 130         if (cdev->mode_info.gfbdev->gfb == crtc->primary->fb) {
 131                 /* if pushing console in kmap it */
 132                 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
 133                 if (ret)
 134                         DRM_ERROR("failed to kmap fbcon\n");
 135         }
 136         cirrus_bo_unreserve(bo);
 137
 138         cirrus_set_start_address(crtc, (u32)gpu_addr);
 139         return 0;
 140 }
 141
 142 static int cirrus_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 143                              struct drm_framebuffer *old_fb)
 144 {
 145         return cirrus_crtc_do_set_base(crtc, old_fb, x, y, 0);
 146 }
 147
 148 /*
 149  * The meat of this driver. The core passes us a mode and we have to program
 150  * it. The modesetting here is the bare minimum required to satisfy the qemu
 151  * emulation of this hardware, and running this against a real device is
 152  * likely to result in an inadequately programmed mode. We've already had
 153  * the opportunity to modify the mode, so whatever we receive here should
 154  * be something that can be correctly programmed and displayed
 155  */
 156 static int cirrus_crtc_mode_set(struct drm_crtc *crtc,
 157                                 struct drm_display_mode *mode,
 158                                 struct drm_display_mode *adjusted_mode,
 159                                 int x, int y, struct drm_framebuffer *old_fb)
 160 {
 161         struct drm_device *dev = crtc->dev;
 162         struct cirrus_device *cdev = dev->dev_private;
 163         const struct drm_framebuffer *fb = crtc->primary->fb;
 164         int hsyncstart, hsyncend, htotal, hdispend;
 165         int vtotal, vdispend;
 166         int tmp;
 167         int sr07 = 0, hdr = 0;
 168
 169         htotal = mode->htotal / 8;
 170         hsyncend = mode->hsync_end / 8;
 171         hsyncstart = mode->hsync_start / 8;
 172         hdispend = mode->hdisplay / 8;
 173
 174         vtotal = mode->vtotal;
 175         vdispend = mode->vdisplay;
 176
 177         vdispend -= 1;
 178         vtotal -= 2;
 179
 180         htotal -= 5;
 181         hdispend -= 1;
 182         hsyncstart += 1;
 183         hsyncend += 1;
 184
 185         WREG_CRT(VGA_CRTC_V_SYNC_END, 0x20);
 186         WREG_CRT(VGA_CRTC_H_TOTAL, htotal);
 187         WREG_CRT(VGA_CRTC_H_DISP, hdispend);
 188         WREG_CRT(VGA_CRTC_H_SYNC_START, hsyncstart);
 189         WREG_CRT(VGA_CRTC_H_SYNC_END, hsyncend);
 190         WREG_CRT(VGA_CRTC_V_TOTAL, vtotal & 0xff);
 191         WREG_CRT(VGA_CRTC_V_DISP_END, vdispend & 0xff);
 192
 193         tmp = 0x40;
 194         if ((vdispend + 1) & 512)
 195                 tmp |= 0x20;
 196         WREG_CRT(VGA_CRTC_MAX_SCAN, tmp);
 197
 198         /*
 199          * Overflow bits for values that don't fit in the standard registers
 200          */
 201         tmp = 16;
 202         if (vtotal & 256)
 203                 tmp |= 1;
 204         if (vdispend & 256)
 205                 tmp |= 2;
 206         if ((vdispend + 1) & 256)
 207                 tmp |= 8;
 208         if (vtotal & 512)
 209                 tmp |= 32;
 210         if (vdispend & 512)
 211                 tmp |= 64;
 212         WREG_CRT(VGA_CRTC_OVERFLOW, tmp);
 213
 214         tmp = 0;
 215
 216         /* More overflow bits */
 217
 218         if ((htotal + 5) & 64)
 219                 tmp |= 16;
 220         if ((htotal + 5) & 128)
 221                 tmp |= 32;
 222         if (vtotal & 256)
 223                 tmp |= 64;
 224         if (vtotal & 512)
 225                 tmp |= 128;
 226
 227         WREG_CRT(CL_CRT1A, tmp);
 228
 229         /* Disable Hercules/CGA compatibility */
 230         WREG_CRT(VGA_CRTC_MODE, 0x03);
 231
 232         WREG8(SEQ_INDEX, 0x7);
 233         sr07 = RREG8(SEQ_DATA);
 234         sr07 &= 0xe0;
 235         hdr = 0;
 236         switch (fb->format->cpp[0] * 8) {
 237         case 8:
 238                 sr07 |= 0x11;
 239                 break;
 240         case 16:
 241                 sr07 |= 0x17;
 242                 hdr = 0xc1;
 243                 break;
 244         case 24:
 245                 sr07 |= 0x15;
 246                 hdr = 0xc5;
 247                 break;
 248         case 32:
 249                 sr07 |= 0x19;
 250                 hdr = 0xc5;
 251                 break;
 252         default:
 253                 return -1;
 254         }
 255
 256         WREG_SEQ(0x7, sr07);
 257
 258         /* Program the pitch */
 259         tmp = fb->pitches[0] / 8;
 260         WREG_CRT(VGA_CRTC_OFFSET, tmp);
 261
 262         /* Enable extended blanking and pitch bits, and enable full memory */
 263         tmp = 0x22;
 264         tmp |= (fb->pitches[0] >> 7) & 0x10;
 265         tmp |= (fb->pitches[0] >> 6) & 0x40;
 266         WREG_CRT(0x1b, tmp);
 267
 268         /* Enable high-colour modes */
 269         WREG_GFX(VGA_GFX_MODE, 0x40);
 270
 271         /* And set graphics mode */
 272         WREG_GFX(VGA_GFX_MISC, 0x01);
 273
 274         WREG_HDR(hdr);
 275         cirrus_crtc_do_set_base(crtc, old_fb, x, y, 0);
 276
 277         /* Unblank (needed on S3 resume, vgabios doesn't do it then) */
 278         outb(0x20, 0x3c0);
 279         return 0;
 280 }
 281
 282 /*
 283  * This is called before a mode is programmed. A typical use might be to
 284  * enable DPMS during the programming to avoid seeing intermediate stages,
 285  * but that's not relevant to us
 286  */
 287 static void cirrus_crtc_prepare(struct drm_crtc *crtc)
 288 {
 289 }
 290
 291 static void cirrus_crtc_load_lut(struct drm_crtc *crtc)
 292 {
 293         struct drm_device *dev = crtc->dev;
 294         struct cirrus_device *cdev = dev->dev_private;
 295         u16 *r, *g, *b;
 296         int i;
 297
 298         if (!crtc->enabled)
 299                 return;
 300
 301         r = crtc->gamma_store;
 302         g = r + crtc->gamma_size;
 303         b = g + crtc->gamma_size;
 304
 305         for (i = 0; i < CIRRUS_LUT_SIZE; i++) {
 306                 /* VGA registers */
 307                 WREG8(PALETTE_INDEX, i);
 308                 WREG8(PALETTE_DATA, *r++ >> 8);
 309                 WREG8(PALETTE_DATA, *g++ >> 8);
 310                 WREG8(PALETTE_DATA, *b++ >> 8);
 311         }
 312 }
 313
 314 /*
 315  * This is called after a mode is programmed. It should reverse anything done
 316  * by the prepare function
 317  */
 318 static void cirrus_crtc_commit(struct drm_crtc *crtc)
 319 {
 320         cirrus_crtc_load_lut(crtc);
 321 }
 322
 323 /*
 324  * The core can pass us a set of gamma values to program. We actually only
 325  * use this for 8-bit mode so can't perform smooth fades on deeper modes,
 326  * but it's a requirement that we provide the function
 327  */
 328 static int cirrus_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 329                                  u16 *blue, uint32_t size,
 330                                  struct drm_modeset_acquire_ctx *ctx)
 331 {
 332         cirrus_crtc_load_lut(crtc);
 333
 334         return 0;
 335 }
 336
 337 /* Simple cleanup function */
 338 static void cirrus_crtc_destroy(struct drm_crtc *crtc)
 339 {
 340         struct cirrus_crtc *cirrus_crtc = to_cirrus_crtc(crtc);
 341
 342         drm_crtc_cleanup(crtc);
 343         kfree(cirrus_crtc);
 344 }
 345
 346 /* These provide the minimum set of functions required to handle a CRTC */
 347 static const struct drm_crtc_funcs cirrus_crtc_funcs = {
 348         .gamma_set = cirrus_crtc_gamma_set,
 349         .set_config = drm_crtc_helper_set_config,
 350         .destroy = cirrus_crtc_destroy,
 351 };
 352
 353 static const struct drm_crtc_helper_funcs cirrus_helper_funcs = {
 354         .dpms = cirrus_crtc_dpms,
 355         .mode_set = cirrus_crtc_mode_set,
 356         .mode_set_base = cirrus_crtc_mode_set_base,
 357         .prepare = cirrus_crtc_prepare,
 358         .commit = cirrus_crtc_commit,
 359 };
 360
 361 /* CRTC setup */
 362 static void cirrus_crtc_init(struct drm_device *dev)
 363 {
 364         struct cirrus_device *cdev = dev->dev_private;
 365         struct cirrus_crtc *cirrus_crtc;
 366
 367         cirrus_crtc = kzalloc(sizeof(struct cirrus_crtc) +
 368                               (CIRRUSFB_CONN_LIMIT * sizeof(struct drm_connector *)),
 369                               GFP_KERNEL);
 370
 371         if (cirrus_crtc == NULL)
 372                 return;
 373
 374         drm_crtc_init(dev, &cirrus_crtc->base, &cirrus_crtc_funcs);
 375
 376         drm_mode_crtc_set_gamma_size(&cirrus_crtc->base, CIRRUS_LUT_SIZE);
 377         cdev->mode_info.crtc = cirrus_crtc;
 378
 379         drm_crtc_helper_add(&cirrus_crtc->base, &cirrus_helper_funcs);
 380 }
 381
 382 static void cirrus_encoder_mode_set(struct drm_encoder *encoder,
 383                                 struct drm_display_mode *mode,
 384                                 struct drm_display_mode *adjusted_mode)
 385 {
 386 }
 387
 388 static void cirrus_encoder_dpms(struct drm_encoder *encoder, int state)
 389 {
 390         return;
 391 }
 392
 393 static void cirrus_encoder_prepare(struct drm_encoder *encoder)
 394 {
 395 }
 396
 397 static void cirrus_encoder_commit(struct drm_encoder *encoder)
 398 {
 399 }
 400
 401 static void cirrus_encoder_destroy(struct drm_encoder *encoder)
 402 {
 403         struct cirrus_encoder *cirrus_encoder = to_cirrus_encoder(encoder);
 404         drm_encoder_cleanup(encoder);
 405         kfree(cirrus_encoder);
 406 }
 407
 408 static const struct drm_encoder_helper_funcs cirrus_encoder_helper_funcs = {
 409         .dpms = cirrus_encoder_dpms,
 410         .mode_set = cirrus_encoder_mode_set,
 411         .prepare = cirrus_encoder_prepare,
 412         .commit = cirrus_encoder_commit,
 413 };
 414
 415 static const struct drm_encoder_funcs cirrus_encoder_encoder_funcs = {
 416         .destroy = cirrus_encoder_destroy,
 417 };
 418
 419 static struct drm_encoder *cirrus_encoder_init(struct drm_device *dev)
 420 {
 421         struct drm_encoder *encoder;
 422         struct cirrus_encoder *cirrus_encoder;
 423
 424         cirrus_encoder = kzalloc(sizeof(struct cirrus_encoder), GFP_KERNEL);
 425         if (!cirrus_encoder)
 426                 return NULL;
 427
 428         encoder = &cirrus_encoder->base;
 429         encoder->possible_crtcs = 0x1;
 430
 431         drm_encoder_init(dev, encoder, &cirrus_encoder_encoder_funcs,
 432                          DRM_MODE_ENCODER_DAC, NULL);
 433         drm_encoder_helper_add(encoder, &cirrus_encoder_helper_funcs);
 434
 435         return encoder;
 436 }
 437
 438
 439 static int cirrus_vga_get_modes(struct drm_connector *connector)
 440 {
 441         int count;
 442
 443         /* Just add a static list of modes */
 444         if (cirrus_bpp <= 24) {
 445                 count = drm_add_modes_noedid(connector, 1280, 1024);
 446                 drm_set_preferred_mode(connector, 1024, 768);
 447         } else {
 448                 count = drm_add_modes_noedid(connector, 800, 600);
 449                 drm_set_preferred_mode(connector, 800, 600);
 450         }
 451         return count;
 452 }
 453
 454 static struct drm_encoder *cirrus_connector_best_encoder(struct drm_connector
 455                                                   *connector)
 456 {
 457         int enc_id = connector->encoder_ids[0];
 458         /* pick the encoder ids */
 459         if (enc_id)
 460                 return drm_encoder_find(connector->dev, NULL, enc_id);
 461         return NULL;
 462 }
 463
 464 static void cirrus_connector_destroy(struct drm_connector *connector)
 465 {
 466         drm_connector_cleanup(connector);
 467         kfree(connector);
 468 }
 469
 470 static const struct drm_connector_helper_funcs cirrus_vga_connector_helper_funcs = {
 471         .get_modes = cirrus_vga_get_modes,
 472         .best_encoder = cirrus_connector_best_encoder,
 473 };
 474
 475 static const struct drm_connector_funcs cirrus_vga_connector_funcs = {
 476         .dpms = drm_helper_connector_dpms,
 477         .fill_modes = drm_helper_probe_single_connector_modes,
 478         .destroy = cirrus_connector_destroy,
 479 };
 480
 481 static struct drm_connector *cirrus_vga_init(struct drm_device *dev)
 482 {
 483         struct drm_connector *connector;
 484         struct cirrus_connector *cirrus_connector;
 485
 486         cirrus_connector = kzalloc(sizeof(struct cirrus_connector), GFP_KERNEL);
 487         if (!cirrus_connector)
 488                 return NULL;
 489
 490         connector = &cirrus_connector->base;
 491
 492         drm_connector_init(dev, connector,
 493                            &cirrus_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA);
 494
 495         drm_connector_helper_add(connector, &cirrus_vga_connector_helper_funcs);
 496
 497         drm_connector_register(connector);
 498         return connector;
 499 }
 500
 501
 502 int cirrus_modeset_init(struct cirrus_device *cdev)
 503 {
 504         struct drm_encoder *encoder;
 505         struct drm_connector *connector;
 506         int ret;
 507
 508         drm_mode_config_init(cdev->dev);
 509         cdev->mode_info.mode_config_initialized = true;
 510
 511         cdev->dev->mode_config.max_width = CIRRUS_MAX_FB_WIDTH;
 512         cdev->dev->mode_config.max_height = CIRRUS_MAX_FB_HEIGHT;
 513
 514         cdev->dev->mode_config.fb_base = cdev->mc.vram_base;
 515         cdev->dev->mode_config.preferred_depth = 24;
 516         /* don't prefer a shadow on virt GPU */
 517         cdev->dev->mode_config.prefer_shadow = 0;
 518
 519         cirrus_crtc_init(cdev->dev);
 520
 521         encoder = cirrus_encoder_init(cdev->dev);
 522         if (!encoder) {
 523                 DRM_ERROR("cirrus_encoder_init failed\n");
 524                 return -1;
 525         }
 526
 527         connector = cirrus_vga_init(cdev->dev);
 528         if (!connector) {
 529                 DRM_ERROR("cirrus_vga_init failed\n");
 530                 return -1;
 531         }
 532
 533         drm_connector_attach_encoder(connector, encoder);
 534
 535         ret = cirrus_fbdev_init(cdev);
 536         if (ret) {
 537                 DRM_ERROR("cirrus_fbdev_init failed\n");
 538                 return ret;
 539         }
 540
 541         return 0;
 542 }
 543
 544 void cirrus_modeset_fini(struct cirrus_device *cdev)
 545 {
 546         cirrus_fbdev_fini(cdev);
 547
 548         if (cdev->mode_info.mode_config_initialized) {
 549                 drm_mode_config_cleanup(cdev->dev);
 550                 cdev->mode_info.mode_config_initialized = false;
 551         }
 552 }