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vt: vt_ioctl: fix VT_DISALLOCATE freeing in-use virtual console
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / intel_ddi.c
blobb4b1f9ca05b68307be26172b17b5d0b4d85c8820
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <drm/drm_scdc_helper.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31
32 struct ddi_buf_trans {
33 u32 trans1; /* balance leg enable, de-emph level */
34 u32 trans2; /* vref sel, vswing */
35 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
36 };
37
38 static const u8 index_to_dp_signal_levels[] = {
39 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
40 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
41 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
42 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
43 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
44 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
45 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
46 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
47 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
48 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
49 };
50
51 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
52 * them for both DP and FDI transports, allowing those ports to
53 * automatically adapt to HDMI connections as well
54 */
55 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
56 { 0x00FFFFFF, 0x0006000E, 0x0 },
57 { 0x00D75FFF, 0x0005000A, 0x0 },
58 { 0x00C30FFF, 0x00040006, 0x0 },
59 { 0x80AAAFFF, 0x000B0000, 0x0 },
60 { 0x00FFFFFF, 0x0005000A, 0x0 },
61 { 0x00D75FFF, 0x000C0004, 0x0 },
62 { 0x80C30FFF, 0x000B0000, 0x0 },
63 { 0x00FFFFFF, 0x00040006, 0x0 },
64 { 0x80D75FFF, 0x000B0000, 0x0 },
65 };
66
67 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
68 { 0x00FFFFFF, 0x0007000E, 0x0 },
69 { 0x00D75FFF, 0x000F000A, 0x0 },
70 { 0x00C30FFF, 0x00060006, 0x0 },
71 { 0x00AAAFFF, 0x001E0000, 0x0 },
72 { 0x00FFFFFF, 0x000F000A, 0x0 },
73 { 0x00D75FFF, 0x00160004, 0x0 },
74 { 0x00C30FFF, 0x001E0000, 0x0 },
75 { 0x00FFFFFF, 0x00060006, 0x0 },
76 { 0x00D75FFF, 0x001E0000, 0x0 },
77 };
78
79 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
80 /* Idx NT mV d T mV d db */
81 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
82 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
83 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
84 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
85 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
86 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
87 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
88 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
89 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
90 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
91 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
92 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
93 };
94
95 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
96 { 0x00FFFFFF, 0x00000012, 0x0 },
97 { 0x00EBAFFF, 0x00020011, 0x0 },
98 { 0x00C71FFF, 0x0006000F, 0x0 },
99 { 0x00AAAFFF, 0x000E000A, 0x0 },
100 { 0x00FFFFFF, 0x00020011, 0x0 },
101 { 0x00DB6FFF, 0x0005000F, 0x0 },
102 { 0x00BEEFFF, 0x000A000C, 0x0 },
103 { 0x00FFFFFF, 0x0005000F, 0x0 },
104 { 0x00DB6FFF, 0x000A000C, 0x0 },
105 };
106
107 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
108 { 0x00FFFFFF, 0x0007000E, 0x0 },
109 { 0x00D75FFF, 0x000E000A, 0x0 },
110 { 0x00BEFFFF, 0x00140006, 0x0 },
111 { 0x80B2CFFF, 0x001B0002, 0x0 },
112 { 0x00FFFFFF, 0x000E000A, 0x0 },
113 { 0x00DB6FFF, 0x00160005, 0x0 },
114 { 0x80C71FFF, 0x001A0002, 0x0 },
115 { 0x00F7DFFF, 0x00180004, 0x0 },
116 { 0x80D75FFF, 0x001B0002, 0x0 },
117 };
118
119 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
120 { 0x00FFFFFF, 0x0001000E, 0x0 },
121 { 0x00D75FFF, 0x0004000A, 0x0 },
122 { 0x00C30FFF, 0x00070006, 0x0 },
123 { 0x00AAAFFF, 0x000C0000, 0x0 },
124 { 0x00FFFFFF, 0x0004000A, 0x0 },
125 { 0x00D75FFF, 0x00090004, 0x0 },
126 { 0x00C30FFF, 0x000C0000, 0x0 },
127 { 0x00FFFFFF, 0x00070006, 0x0 },
128 { 0x00D75FFF, 0x000C0000, 0x0 },
129 };
130
131 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
132 /* Idx NT mV d T mV df db */
133 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
134 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
135 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
136 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
137 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
138 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
139 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
140 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
141 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
142 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
143 };
144
145 /* Skylake H and S */
146 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
147 { 0x00002016, 0x000000A0, 0x0 },
148 { 0x00005012, 0x0000009B, 0x0 },
149 { 0x00007011, 0x00000088, 0x0 },
150 { 0x80009010, 0x000000C0, 0x1 },
151 { 0x00002016, 0x0000009B, 0x0 },
152 { 0x00005012, 0x00000088, 0x0 },
153 { 0x80007011, 0x000000C0, 0x1 },
154 { 0x00002016, 0x000000DF, 0x0 },
155 { 0x80005012, 0x000000C0, 0x1 },
156 };
157
158 /* Skylake U */
159 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
160 { 0x0000201B, 0x000000A2, 0x0 },
161 { 0x00005012, 0x00000088, 0x0 },
162 { 0x80007011, 0x000000CD, 0x1 },
163 { 0x80009010, 0x000000C0, 0x1 },
164 { 0x0000201B, 0x0000009D, 0x0 },
165 { 0x80005012, 0x000000C0, 0x1 },
166 { 0x80007011, 0x000000C0, 0x1 },
167 { 0x00002016, 0x00000088, 0x0 },
168 { 0x80005012, 0x000000C0, 0x1 },
169 };
170
171 /* Skylake Y */
172 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
173 { 0x00000018, 0x000000A2, 0x0 },
174 { 0x00005012, 0x00000088, 0x0 },
175 { 0x80007011, 0x000000CD, 0x3 },
176 { 0x80009010, 0x000000C0, 0x3 },
177 { 0x00000018, 0x0000009D, 0x0 },
178 { 0x80005012, 0x000000C0, 0x3 },
179 { 0x80007011, 0x000000C0, 0x3 },
180 { 0x00000018, 0x00000088, 0x0 },
181 { 0x80005012, 0x000000C0, 0x3 },
182 };
183
184 /* Kabylake H and S */
185 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
186 { 0x00002016, 0x000000A0, 0x0 },
187 { 0x00005012, 0x0000009B, 0x0 },
188 { 0x00007011, 0x00000088, 0x0 },
189 { 0x80009010, 0x000000C0, 0x1 },
190 { 0x00002016, 0x0000009B, 0x0 },
191 { 0x00005012, 0x00000088, 0x0 },
192 { 0x80007011, 0x000000C0, 0x1 },
193 { 0x00002016, 0x00000097, 0x0 },
194 { 0x80005012, 0x000000C0, 0x1 },
195 };
196
197 /* Kabylake U */
198 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
199 { 0x0000201B, 0x000000A1, 0x0 },
200 { 0x00005012, 0x00000088, 0x0 },
201 { 0x80007011, 0x000000CD, 0x3 },
202 { 0x80009010, 0x000000C0, 0x3 },
203 { 0x0000201B, 0x0000009D, 0x0 },
204 { 0x80005012, 0x000000C0, 0x3 },
205 { 0x80007011, 0x000000C0, 0x3 },
206 { 0x00002016, 0x0000004F, 0x0 },
207 { 0x80005012, 0x000000C0, 0x3 },
208 };
209
210 /* Kabylake Y */
211 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
212 { 0x00001017, 0x000000A1, 0x0 },
213 { 0x00005012, 0x00000088, 0x0 },
214 { 0x80007011, 0x000000CD, 0x3 },
215 { 0x8000800F, 0x000000C0, 0x3 },
216 { 0x00001017, 0x0000009D, 0x0 },
217 { 0x80005012, 0x000000C0, 0x3 },
218 { 0x80007011, 0x000000C0, 0x3 },
219 { 0x00001017, 0x0000004C, 0x0 },
220 { 0x80005012, 0x000000C0, 0x3 },
221 };
222
223 /*
224 * Skylake/Kabylake H and S
225 * eDP 1.4 low vswing translation parameters
226 */
227 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
228 { 0x00000018, 0x000000A8, 0x0 },
229 { 0x00004013, 0x000000A9, 0x0 },
230 { 0x00007011, 0x000000A2, 0x0 },
231 { 0x00009010, 0x0000009C, 0x0 },
232 { 0x00000018, 0x000000A9, 0x0 },
233 { 0x00006013, 0x000000A2, 0x0 },
234 { 0x00007011, 0x000000A6, 0x0 },
235 { 0x00000018, 0x000000AB, 0x0 },
236 { 0x00007013, 0x0000009F, 0x0 },
237 { 0x00000018, 0x000000DF, 0x0 },
238 };
239
240 /*
241 * Skylake/Kabylake U
242 * eDP 1.4 low vswing translation parameters
243 */
244 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
245 { 0x00000018, 0x000000A8, 0x0 },
246 { 0x00004013, 0x000000A9, 0x0 },
247 { 0x00007011, 0x000000A2, 0x0 },
248 { 0x00009010, 0x0000009C, 0x0 },
249 { 0x00000018, 0x000000A9, 0x0 },
250 { 0x00006013, 0x000000A2, 0x0 },
251 { 0x00007011, 0x000000A6, 0x0 },
252 { 0x00002016, 0x000000AB, 0x0 },
253 { 0x00005013, 0x0000009F, 0x0 },
254 { 0x00000018, 0x000000DF, 0x0 },
255 };
256
257 /*
258 * Skylake/Kabylake Y
259 * eDP 1.4 low vswing translation parameters
260 */
261 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
262 { 0x00000018, 0x000000A8, 0x0 },
263 { 0x00004013, 0x000000AB, 0x0 },
264 { 0x00007011, 0x000000A4, 0x0 },
265 { 0x00009010, 0x000000DF, 0x0 },
266 { 0x00000018, 0x000000AA, 0x0 },
267 { 0x00006013, 0x000000A4, 0x0 },
268 { 0x00007011, 0x0000009D, 0x0 },
269 { 0x00000018, 0x000000A0, 0x0 },
270 { 0x00006012, 0x000000DF, 0x0 },
271 { 0x00000018, 0x0000008A, 0x0 },
272 };
273
274 /* Skylake/Kabylake U, H and S */
275 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
276 { 0x00000018, 0x000000AC, 0x0 },
277 { 0x00005012, 0x0000009D, 0x0 },
278 { 0x00007011, 0x00000088, 0x0 },
279 { 0x00000018, 0x000000A1, 0x0 },
280 { 0x00000018, 0x00000098, 0x0 },
281 { 0x00004013, 0x00000088, 0x0 },
282 { 0x80006012, 0x000000CD, 0x1 },
283 { 0x00000018, 0x000000DF, 0x0 },
284 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
285 { 0x80003015, 0x000000C0, 0x1 },
286 { 0x80000018, 0x000000C0, 0x1 },
287 };
288
289 /* Skylake/Kabylake Y */
290 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
291 { 0x00000018, 0x000000A1, 0x0 },
292 { 0x00005012, 0x000000DF, 0x0 },
293 { 0x80007011, 0x000000CB, 0x3 },
294 { 0x00000018, 0x000000A4, 0x0 },
295 { 0x00000018, 0x0000009D, 0x0 },
296 { 0x00004013, 0x00000080, 0x0 },
297 { 0x80006013, 0x000000C0, 0x3 },
298 { 0x00000018, 0x0000008A, 0x0 },
299 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
300 { 0x80003015, 0x000000C0, 0x3 },
301 { 0x80000018, 0x000000C0, 0x3 },
302 };
303
304 struct bxt_ddi_buf_trans {
305 u8 margin; /* swing value */
306 u8 scale; /* scale value */
307 u8 enable; /* scale enable */
308 u8 deemphasis;
309 };
310
311 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
312 /* Idx NT mV diff db */
313 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
314 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */
315 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */
316 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */
317 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
318 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */
319 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */
320 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
321 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */
322 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
323 };
324
325 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
326 /* Idx NT mV diff db */
327 { 26, 0, 0, 128, }, /* 0: 200 0 */
328 { 38, 0, 0, 112, }, /* 1: 200 1.5 */
329 { 48, 0, 0, 96, }, /* 2: 200 4 */
330 { 54, 0, 0, 69, }, /* 3: 200 6 */
331 { 32, 0, 0, 128, }, /* 4: 250 0 */
332 { 48, 0, 0, 104, }, /* 5: 250 1.5 */
333 { 54, 0, 0, 85, }, /* 6: 250 4 */
334 { 43, 0, 0, 128, }, /* 7: 300 0 */
335 { 54, 0, 0, 101, }, /* 8: 300 1.5 */
336 { 48, 0, 0, 128, }, /* 9: 300 0 */
337 };
338
339 /* BSpec has 2 recommended values - entries 0 and 8.
340 * Using the entry with higher vswing.
341 */
342 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
343 /* Idx NT mV diff db */
344 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
345 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */
346 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */
347 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */
348 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
349 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */
350 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */
351 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
352 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */
353 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
354 };
355
356 struct cnl_ddi_buf_trans {
357 u8 dw2_swing_sel;
358 u8 dw7_n_scalar;
359 u8 dw4_cursor_coeff;
360 u8 dw4_post_cursor_2;
361 u8 dw4_post_cursor_1;
362 };
363
364 /* Voltage Swing Programming for VccIO 0.85V for DP */
365 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
366 /* NT mV Trans mV db */
367 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
368 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
369 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
370 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
371 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
372 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
373 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
374 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
375 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
376 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
377 };
378
379 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
380 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
381 /* NT mV Trans mV db */
382 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
383 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
384 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
385 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
386 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
387 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
388 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
389 };
390
391 /* Voltage Swing Programming for VccIO 0.85V for eDP */
392 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
393 /* NT mV Trans mV db */
394 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
395 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
396 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
397 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
398 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
399 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
400 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
401 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
402 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
403 };
404
405 /* Voltage Swing Programming for VccIO 0.95V for DP */
406 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
407 /* NT mV Trans mV db */
408 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
409 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
410 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
411 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
412 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
413 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
414 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
415 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
416 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
417 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
418 };
419
420 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
421 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
422 /* NT mV Trans mV db */
423 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
424 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
425 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
426 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
427 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
428 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
429 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
430 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
431 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
432 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
433 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
434 };
435
436 /* Voltage Swing Programming for VccIO 0.95V for eDP */
437 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
438 /* NT mV Trans mV db */
439 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
440 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
441 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
442 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
443 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
444 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
445 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
446 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
447 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
448 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
449 };
450
451 /* Voltage Swing Programming for VccIO 1.05V for DP */
452 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
453 /* NT mV Trans mV db */
454 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
455 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
456 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
457 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
458 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
459 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
460 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
461 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
462 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
463 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
464 };
465
466 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
467 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
468 /* NT mV Trans mV db */
469 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
470 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
471 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
472 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
473 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
474 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
475 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
476 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
477 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
478 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
479 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
480 };
481
482 /* Voltage Swing Programming for VccIO 1.05V for eDP */
483 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
484 /* NT mV Trans mV db */
485 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
486 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
487 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
488 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
489 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
490 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
491 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
492 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
493 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
494 };
495
496 struct icl_combo_phy_ddi_buf_trans {
497 u32 dw2_swing_select;
498 u32 dw2_swing_scalar;
499 u32 dw4_scaling;
500 };
501
502 /* Voltage Swing Programming for VccIO 0.85V for DP */
503 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
504 /* Voltage mV db */
505 { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
506 { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
507 { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
508 { 0x2, 0x98, 0x900F }, /* 400 9.5 */
509 { 0xB, 0x70, 0x0018 }, /* 600 0.0 */
510 { 0xB, 0x70, 0x3015 }, /* 600 3.5 */
511 { 0xB, 0x70, 0x6012 }, /* 600 6.0 */
512 { 0x5, 0x00, 0x0018 }, /* 800 0.0 */
513 { 0x5, 0x00, 0x3015 }, /* 800 3.5 */
514 { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
515 };
516
517 /* FIXME - After table is updated in Bspec */
518 /* Voltage Swing Programming for VccIO 0.85V for eDP */
519 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
520 /* Voltage mV db */
521 { 0x0, 0x00, 0x00 }, /* 200 0.0 */
522 { 0x0, 0x00, 0x00 }, /* 200 1.5 */
523 { 0x0, 0x00, 0x00 }, /* 200 4.0 */
524 { 0x0, 0x00, 0x00 }, /* 200 6.0 */
525 { 0x0, 0x00, 0x00 }, /* 250 0.0 */
526 { 0x0, 0x00, 0x00 }, /* 250 1.5 */
527 { 0x0, 0x00, 0x00 }, /* 250 4.0 */
528 { 0x0, 0x00, 0x00 }, /* 300 0.0 */
529 { 0x0, 0x00, 0x00 }, /* 300 1.5 */
530 { 0x0, 0x00, 0x00 }, /* 350 0.0 */
531 };
532
533 /* Voltage Swing Programming for VccIO 0.95V for DP */
534 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
535 /* Voltage mV db */
536 { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
537 { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
538 { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
539 { 0x2, 0x98, 0x900F }, /* 400 9.5 */
540 { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
541 { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
542 { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
543 { 0x5, 0x76, 0x0018 }, /* 800 0.0 */
544 { 0x5, 0x76, 0x3015 }, /* 800 3.5 */
545 { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
546 };
547
548 /* FIXME - After table is updated in Bspec */
549 /* Voltage Swing Programming for VccIO 0.95V for eDP */
550 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
551 /* Voltage mV db */
552 { 0x0, 0x00, 0x00 }, /* 200 0.0 */
553 { 0x0, 0x00, 0x00 }, /* 200 1.5 */
554 { 0x0, 0x00, 0x00 }, /* 200 4.0 */
555 { 0x0, 0x00, 0x00 }, /* 200 6.0 */
556 { 0x0, 0x00, 0x00 }, /* 250 0.0 */
557 { 0x0, 0x00, 0x00 }, /* 250 1.5 */
558 { 0x0, 0x00, 0x00 }, /* 250 4.0 */
559 { 0x0, 0x00, 0x00 }, /* 300 0.0 */
560 { 0x0, 0x00, 0x00 }, /* 300 1.5 */
561 { 0x0, 0x00, 0x00 }, /* 350 0.0 */
562 };
563
564 /* Voltage Swing Programming for VccIO 1.05V for DP */
565 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
566 /* Voltage mV db */
567 { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
568 { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
569 { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
570 { 0x2, 0x98, 0x900F }, /* 400 9.5 */
571 { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
572 { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
573 { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
574 { 0x5, 0x71, 0x0018 }, /* 800 0.0 */
575 { 0x5, 0x71, 0x3015 }, /* 800 3.5 */
576 { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
577 };
578
579 /* FIXME - After table is updated in Bspec */
580 /* Voltage Swing Programming for VccIO 1.05V for eDP */
581 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
582 /* Voltage mV db */
583 { 0x0, 0x00, 0x00 }, /* 200 0.0 */
584 { 0x0, 0x00, 0x00 }, /* 200 1.5 */
585 { 0x0, 0x00, 0x00 }, /* 200 4.0 */
586 { 0x0, 0x00, 0x00 }, /* 200 6.0 */
587 { 0x0, 0x00, 0x00 }, /* 250 0.0 */
588 { 0x0, 0x00, 0x00 }, /* 250 1.5 */
589 { 0x0, 0x00, 0x00 }, /* 250 4.0 */
590 { 0x0, 0x00, 0x00 }, /* 300 0.0 */
591 { 0x0, 0x00, 0x00 }, /* 300 1.5 */
592 { 0x0, 0x00, 0x00 }, /* 350 0.0 */
593 };
594
595 struct icl_mg_phy_ddi_buf_trans {
596 u32 cri_txdeemph_override_5_0;
597 u32 cri_txdeemph_override_11_6;
598 u32 cri_txdeemph_override_17_12;
599 };
600
601 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
602 /* Voltage swing pre-emphasis */
603 { 0x0, 0x1B, 0x00 }, /* 0 0 */
604 { 0x0, 0x23, 0x08 }, /* 0 1 */
605 { 0x0, 0x2D, 0x12 }, /* 0 2 */
606 { 0x0, 0x00, 0x00 }, /* 0 3 */
607 { 0x0, 0x23, 0x00 }, /* 1 0 */
608 { 0x0, 0x2B, 0x09 }, /* 1 1 */
609 { 0x0, 0x2E, 0x11 }, /* 1 2 */
610 { 0x0, 0x2F, 0x00 }, /* 2 0 */
611 { 0x0, 0x33, 0x0C }, /* 2 1 */
612 { 0x0, 0x00, 0x00 }, /* 3 0 */
613 };
614
615 static const struct ddi_buf_trans *
616 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
617 {
618 if (dev_priv->vbt.edp.low_vswing) {
619 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
620 return bdw_ddi_translations_edp;
621 } else {
622 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
623 return bdw_ddi_translations_dp;
624 }
625 }
626
627 static const struct ddi_buf_trans *
628 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
629 {
630 if (IS_SKL_ULX(dev_priv)) {
631 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
632 return skl_y_ddi_translations_dp;
633 } else if (IS_SKL_ULT(dev_priv)) {
634 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
635 return skl_u_ddi_translations_dp;
636 } else {
637 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
638 return skl_ddi_translations_dp;
639 }
640 }
641
642 static const struct ddi_buf_trans *
643 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
644 {
645 if (IS_KBL_ULX(dev_priv)) {
646 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
647 return kbl_y_ddi_translations_dp;
648 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
649 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
650 return kbl_u_ddi_translations_dp;
651 } else {
652 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
653 return kbl_ddi_translations_dp;
654 }
655 }
656
657 static const struct ddi_buf_trans *
658 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
659 {
660 if (dev_priv->vbt.edp.low_vswing) {
661 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
662 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
663 return skl_y_ddi_translations_edp;
664 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
665 IS_CFL_ULT(dev_priv)) {
666 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
667 return skl_u_ddi_translations_edp;
668 } else {
669 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
670 return skl_ddi_translations_edp;
671 }
672 }
673
674 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
675 return kbl_get_buf_trans_dp(dev_priv, n_entries);
676 else
677 return skl_get_buf_trans_dp(dev_priv, n_entries);
678 }
679
680 static const struct ddi_buf_trans *
681 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
682 {
683 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
684 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
685 return skl_y_ddi_translations_hdmi;
686 } else {
687 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
688 return skl_ddi_translations_hdmi;
689 }
690 }
691
692 static int skl_buf_trans_num_entries(enum port port, int n_entries)
693 {
694 /* Only DDIA and DDIE can select the 10th register with DP */
695 if (port == PORT_A || port == PORT_E)
696 return min(n_entries, 10);
697 else
698 return min(n_entries, 9);
699 }
700
701 static const struct ddi_buf_trans *
702 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
703 enum port port, int *n_entries)
704 {
705 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
706 const struct ddi_buf_trans *ddi_translations =
707 kbl_get_buf_trans_dp(dev_priv, n_entries);
708 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
709 return ddi_translations;
710 } else if (IS_SKYLAKE(dev_priv)) {
711 const struct ddi_buf_trans *ddi_translations =
712 skl_get_buf_trans_dp(dev_priv, n_entries);
713 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
714 return ddi_translations;
715 } else if (IS_BROADWELL(dev_priv)) {
716 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
717 return bdw_ddi_translations_dp;
718 } else if (IS_HASWELL(dev_priv)) {
719 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
720 return hsw_ddi_translations_dp;
721 }
722
723 *n_entries = 0;
724 return NULL;
725 }
726
727 static const struct ddi_buf_trans *
728 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
729 enum port port, int *n_entries)
730 {
731 if (IS_GEN9_BC(dev_priv)) {
732 const struct ddi_buf_trans *ddi_translations =
733 skl_get_buf_trans_edp(dev_priv, n_entries);
734 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
735 return ddi_translations;
736 } else if (IS_BROADWELL(dev_priv)) {
737 return bdw_get_buf_trans_edp(dev_priv, n_entries);
738 } else if (IS_HASWELL(dev_priv)) {
739 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
740 return hsw_ddi_translations_dp;
741 }
742
743 *n_entries = 0;
744 return NULL;
745 }
746
747 static const struct ddi_buf_trans *
748 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
749 int *n_entries)
750 {
751 if (IS_BROADWELL(dev_priv)) {
752 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
753 return bdw_ddi_translations_fdi;
754 } else if (IS_HASWELL(dev_priv)) {
755 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
756 return hsw_ddi_translations_fdi;
757 }
758
759 *n_entries = 0;
760 return NULL;
761 }
762
763 static const struct ddi_buf_trans *
764 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
765 int *n_entries)
766 {
767 if (IS_GEN9_BC(dev_priv)) {
768 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
769 } else if (IS_BROADWELL(dev_priv)) {
770 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
771 return bdw_ddi_translations_hdmi;
772 } else if (IS_HASWELL(dev_priv)) {
773 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
774 return hsw_ddi_translations_hdmi;
775 }
776
777 *n_entries = 0;
778 return NULL;
779 }
780
781 static const struct bxt_ddi_buf_trans *
782 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
783 {
784 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
785 return bxt_ddi_translations_dp;
786 }
787
788 static const struct bxt_ddi_buf_trans *
789 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
790 {
791 if (dev_priv->vbt.edp.low_vswing) {
792 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
793 return bxt_ddi_translations_edp;
794 }
795
796 return bxt_get_buf_trans_dp(dev_priv, n_entries);
797 }
798
799 static const struct bxt_ddi_buf_trans *
800 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
801 {
802 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
803 return bxt_ddi_translations_hdmi;
804 }
805
806 static const struct cnl_ddi_buf_trans *
807 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
808 {
809 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
810
811 if (voltage == VOLTAGE_INFO_0_85V) {
812 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
813 return cnl_ddi_translations_hdmi_0_85V;
814 } else if (voltage == VOLTAGE_INFO_0_95V) {
815 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
816 return cnl_ddi_translations_hdmi_0_95V;
817 } else if (voltage == VOLTAGE_INFO_1_05V) {
818 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
819 return cnl_ddi_translations_hdmi_1_05V;
820 } else {
821 *n_entries = 1; /* shut up gcc */
822 MISSING_CASE(voltage);
823 }
824 return NULL;
825 }
826
827 static const struct cnl_ddi_buf_trans *
828 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
829 {
830 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
831
832 if (voltage == VOLTAGE_INFO_0_85V) {
833 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
834 return cnl_ddi_translations_dp_0_85V;
835 } else if (voltage == VOLTAGE_INFO_0_95V) {
836 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
837 return cnl_ddi_translations_dp_0_95V;
838 } else if (voltage == VOLTAGE_INFO_1_05V) {
839 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
840 return cnl_ddi_translations_dp_1_05V;
841 } else {
842 *n_entries = 1; /* shut up gcc */
843 MISSING_CASE(voltage);
844 }
845 return NULL;
846 }
847
848 static const struct cnl_ddi_buf_trans *
849 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
850 {
851 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
852
853 if (dev_priv->vbt.edp.low_vswing) {
854 if (voltage == VOLTAGE_INFO_0_85V) {
855 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
856 return cnl_ddi_translations_edp_0_85V;
857 } else if (voltage == VOLTAGE_INFO_0_95V) {
858 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
859 return cnl_ddi_translations_edp_0_95V;
860 } else if (voltage == VOLTAGE_INFO_1_05V) {
861 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
862 return cnl_ddi_translations_edp_1_05V;
863 } else {
864 *n_entries = 1; /* shut up gcc */
865 MISSING_CASE(voltage);
866 }
867 return NULL;
868 } else {
869 return cnl_get_buf_trans_dp(dev_priv, n_entries);
870 }
871 }
872
873 static const struct icl_combo_phy_ddi_buf_trans *
874 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
875 int type, int *n_entries)
876 {
877 u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
878
879 if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
880 switch (voltage) {
881 case VOLTAGE_INFO_0_85V:
882 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
883 return icl_combo_phy_ddi_translations_edp_0_85V;
884 case VOLTAGE_INFO_0_95V:
885 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
886 return icl_combo_phy_ddi_translations_edp_0_95V;
887 case VOLTAGE_INFO_1_05V:
888 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
889 return icl_combo_phy_ddi_translations_edp_1_05V;
890 default:
891 MISSING_CASE(voltage);
892 return NULL;
893 }
894 } else {
895 switch (voltage) {
896 case VOLTAGE_INFO_0_85V:
897 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
898 return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
899 case VOLTAGE_INFO_0_95V:
900 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
901 return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
902 case VOLTAGE_INFO_1_05V:
903 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
904 return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
905 default:
906 MISSING_CASE(voltage);
907 return NULL;
908 }
909 }
910 }
911
912 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
913 {
914 int n_entries, level, default_entry;
915
916 level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
917
918 if (IS_ICELAKE(dev_priv)) {
919 if (port == PORT_A || port == PORT_B)
920 icl_get_combo_buf_trans(dev_priv, port,
921 INTEL_OUTPUT_HDMI, &n_entries);
922 else
923 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
924 default_entry = n_entries - 1;
925 } else if (IS_CANNONLAKE(dev_priv)) {
926 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
927 default_entry = n_entries - 1;
928 } else if (IS_GEN9_LP(dev_priv)) {
929 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
930 default_entry = n_entries - 1;
931 } else if (IS_GEN9_BC(dev_priv)) {
932 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
933 default_entry = 8;
934 } else if (IS_BROADWELL(dev_priv)) {
935 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
936 default_entry = 7;
937 } else if (IS_HASWELL(dev_priv)) {
938 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
939 default_entry = 6;
940 } else {
941 WARN(1, "ddi translation table missing\n");
942 return 0;
943 }
944
945 /* Choose a good default if VBT is badly populated */
946 if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
947 level = default_entry;
948
949 if (WARN_ON_ONCE(n_entries == 0))
950 return 0;
951 if (WARN_ON_ONCE(level >= n_entries))
952 level = n_entries - 1;
953
954 return level;
955 }
956
957 /*
958 * Starting with Haswell, DDI port buffers must be programmed with correct
959 * values in advance. This function programs the correct values for
960 * DP/eDP/FDI use cases.
961 */
962 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
963 const struct intel_crtc_state *crtc_state)
964 {
965 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
966 u32 iboost_bit = 0;
967 int i, n_entries;
968 enum port port = encoder->port;
969 const struct ddi_buf_trans *ddi_translations;
970
971 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
972 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
973 &n_entries);
974 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
975 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
976 &n_entries);
977 else
978 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
979 &n_entries);
980
981 /* If we're boosting the current, set bit 31 of trans1 */
982 if (IS_GEN9_BC(dev_priv) &&
983 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
984 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
985
986 for (i = 0; i < n_entries; i++) {
987 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
988 ddi_translations[i].trans1 | iboost_bit);
989 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
990 ddi_translations[i].trans2);
991 }
992 }
993
994 /*
995 * Starting with Haswell, DDI port buffers must be programmed with correct
996 * values in advance. This function programs the correct values for
997 * HDMI/DVI use cases.
998 */
999 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
1000 int level)
1001 {
1002 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1003 u32 iboost_bit = 0;
1004 int n_entries;
1005 enum port port = encoder->port;
1006 const struct ddi_buf_trans *ddi_translations;
1007
1008 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1009
1010 if (WARN_ON_ONCE(!ddi_translations))
1011 return;
1012 if (WARN_ON_ONCE(level >= n_entries))
1013 level = n_entries - 1;
1014
1015 /* If we're boosting the current, set bit 31 of trans1 */
1016 if (IS_GEN9_BC(dev_priv) &&
1017 dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
1018 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1019
1020 /* Entry 9 is for HDMI: */
1021 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
1022 ddi_translations[level].trans1 | iboost_bit);
1023 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
1024 ddi_translations[level].trans2);
1025 }
1026
1027 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1028 enum port port)
1029 {
1030 i915_reg_t reg = DDI_BUF_CTL(port);
1031 int i;
1032
1033 for (i = 0; i < 16; i++) {
1034 udelay(1);
1035 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
1036 return;
1037 }
1038 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
1039 }
1040
1041 static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
1042 {
1043 switch (pll->info->id) {
1044 case DPLL_ID_WRPLL1:
1045 return PORT_CLK_SEL_WRPLL1;
1046 case DPLL_ID_WRPLL2:
1047 return PORT_CLK_SEL_WRPLL2;
1048 case DPLL_ID_SPLL:
1049 return PORT_CLK_SEL_SPLL;
1050 case DPLL_ID_LCPLL_810:
1051 return PORT_CLK_SEL_LCPLL_810;
1052 case DPLL_ID_LCPLL_1350:
1053 return PORT_CLK_SEL_LCPLL_1350;
1054 case DPLL_ID_LCPLL_2700:
1055 return PORT_CLK_SEL_LCPLL_2700;
1056 default:
1057 MISSING_CASE(pll->info->id);
1058 return PORT_CLK_SEL_NONE;
1059 }
1060 }
1061
1062 static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
1063 const struct intel_shared_dpll *pll)
1064 {
1065 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1066 int clock = crtc->config->port_clock;
1067 const enum intel_dpll_id id = pll->info->id;
1068
1069 switch (id) {
1070 default:
1071 MISSING_CASE(id);
1072 /* fall through */
1073 case DPLL_ID_ICL_DPLL0:
1074 case DPLL_ID_ICL_DPLL1:
1075 return DDI_CLK_SEL_NONE;
1076 case DPLL_ID_ICL_TBTPLL:
1077 switch (clock) {
1078 case 162000:
1079 return DDI_CLK_SEL_TBT_162;
1080 case 270000:
1081 return DDI_CLK_SEL_TBT_270;
1082 case 540000:
1083 return DDI_CLK_SEL_TBT_540;
1084 case 810000:
1085 return DDI_CLK_SEL_TBT_810;
1086 default:
1087 MISSING_CASE(clock);
1088 return DDI_CLK_SEL_NONE;
1089 }
1090 case DPLL_ID_ICL_MGPLL1:
1091 case DPLL_ID_ICL_MGPLL2:
1092 case DPLL_ID_ICL_MGPLL3:
1093 case DPLL_ID_ICL_MGPLL4:
1094 return DDI_CLK_SEL_MG;
1095 }
1096 }
1097
1098 /* Starting with Haswell, different DDI ports can work in FDI mode for
1099 * connection to the PCH-located connectors. For this, it is necessary to train
1100 * both the DDI port and PCH receiver for the desired DDI buffer settings.
1101 *
1102 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1103 * please note that when FDI mode is active on DDI E, it shares 2 lines with
1104 * DDI A (which is used for eDP)
1105 */
1106
1107 void hsw_fdi_link_train(struct intel_crtc *crtc,
1108 const struct intel_crtc_state *crtc_state)
1109 {
1110 struct drm_device *dev = crtc->base.dev;
1111 struct drm_i915_private *dev_priv = to_i915(dev);
1112 struct intel_encoder *encoder;
1113 u32 temp, i, rx_ctl_val, ddi_pll_sel;
1114
1115 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1116 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
1117 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1118 }
1119
1120 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1121 * mode set "sequence for CRT port" document:
1122 * - TP1 to TP2 time with the default value
1123 * - FDI delay to 90h
1124 *
1125 * WaFDIAutoLinkSetTimingOverrride:hsw
1126 */
1127 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1128 FDI_RX_PWRDN_LANE0_VAL(2) |
1129 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1130
1131 /* Enable the PCH Receiver FDI PLL */
1132 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1133 FDI_RX_PLL_ENABLE |
1134 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1135 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1136 POSTING_READ(FDI_RX_CTL(PIPE_A));
1137 udelay(220);
1138
1139 /* Switch from Rawclk to PCDclk */
1140 rx_ctl_val |= FDI_PCDCLK;
1141 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1142
1143 /* Configure Port Clock Select */
1144 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1145 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1146 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1147
1148 /* Start the training iterating through available voltages and emphasis,
1149 * testing each value twice. */
1150 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1151 /* Configure DP_TP_CTL with auto-training */
1152 I915_WRITE(DP_TP_CTL(PORT_E),
1153 DP_TP_CTL_FDI_AUTOTRAIN |
1154 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1155 DP_TP_CTL_LINK_TRAIN_PAT1 |
1156 DP_TP_CTL_ENABLE);
1157
1158 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1159 * DDI E does not support port reversal, the functionality is
1160 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1161 * port reversal bit */
1162 I915_WRITE(DDI_BUF_CTL(PORT_E),
1163 DDI_BUF_CTL_ENABLE |
1164 ((crtc_state->fdi_lanes - 1) << 1) |
1165 DDI_BUF_TRANS_SELECT(i / 2));
1166 POSTING_READ(DDI_BUF_CTL(PORT_E));
1167
1168 udelay(600);
1169
1170 /* Program PCH FDI Receiver TU */
1171 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1172
1173 /* Enable PCH FDI Receiver with auto-training */
1174 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1175 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1176 POSTING_READ(FDI_RX_CTL(PIPE_A));
1177
1178 /* Wait for FDI receiver lane calibration */
1179 udelay(30);
1180
1181 /* Unset FDI_RX_MISC pwrdn lanes */
1182 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1183 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1184 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1185 POSTING_READ(FDI_RX_MISC(PIPE_A));
1186
1187 /* Wait for FDI auto training time */
1188 udelay(5);
1189
1190 temp = I915_READ(DP_TP_STATUS(PORT_E));
1191 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1192 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1193 break;
1194 }
1195
1196 /*
1197 * Leave things enabled even if we failed to train FDI.
1198 * Results in less fireworks from the state checker.
1199 */
1200 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1201 DRM_ERROR("FDI link training failed!\n");
1202 break;
1203 }
1204
1205 rx_ctl_val &= ~FDI_RX_ENABLE;
1206 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1207 POSTING_READ(FDI_RX_CTL(PIPE_A));
1208
1209 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1210 temp &= ~DDI_BUF_CTL_ENABLE;
1211 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1212 POSTING_READ(DDI_BUF_CTL(PORT_E));
1213
1214 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1215 temp = I915_READ(DP_TP_CTL(PORT_E));
1216 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1217 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1218 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1219 POSTING_READ(DP_TP_CTL(PORT_E));
1220
1221 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1222
1223 /* Reset FDI_RX_MISC pwrdn lanes */
1224 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1225 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1226 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1227 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1228 POSTING_READ(FDI_RX_MISC(PIPE_A));
1229 }
1230
1231 /* Enable normal pixel sending for FDI */
1232 I915_WRITE(DP_TP_CTL(PORT_E),
1233 DP_TP_CTL_FDI_AUTOTRAIN |
1234 DP_TP_CTL_LINK_TRAIN_NORMAL |
1235 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1236 DP_TP_CTL_ENABLE);
1237 }
1238
1239 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1240 {
1241 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1242 struct intel_digital_port *intel_dig_port =
1243 enc_to_dig_port(&encoder->base);
1244
1245 intel_dp->DP = intel_dig_port->saved_port_bits |
1246 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1247 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1248 }
1249
1250 static struct intel_encoder *
1251 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1252 {
1253 struct drm_device *dev = crtc->base.dev;
1254 struct intel_encoder *encoder, *ret = NULL;
1255 int num_encoders = 0;
1256
1257 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1258 ret = encoder;
1259 num_encoders++;
1260 }
1261
1262 if (num_encoders != 1)
1263 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1264 pipe_name(crtc->pipe));
1265
1266 BUG_ON(ret == NULL);
1267 return ret;
1268 }
1269
1270 #define LC_FREQ 2700
1271
1272 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1273 i915_reg_t reg)
1274 {
1275 int refclk = LC_FREQ;
1276 int n, p, r;
1277 u32 wrpll;
1278
1279 wrpll = I915_READ(reg);
1280 switch (wrpll & WRPLL_PLL_REF_MASK) {
1281 case WRPLL_PLL_SSC:
1282 case WRPLL_PLL_NON_SSC:
1283 /*
1284 * We could calculate spread here, but our checking
1285 * code only cares about 5% accuracy, and spread is a max of
1286 * 0.5% downspread.
1287 */
1288 refclk = 135;
1289 break;
1290 case WRPLL_PLL_LCPLL:
1291 refclk = LC_FREQ;
1292 break;
1293 default:
1294 WARN(1, "bad wrpll refclk\n");
1295 return 0;
1296 }
1297
1298 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1299 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1300 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1301
1302 /* Convert to KHz, p & r have a fixed point portion */
1303 return (refclk * n * 100) / (p * r);
1304 }
1305
1306 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1307 enum intel_dpll_id pll_id)
1308 {
1309 i915_reg_t cfgcr1_reg, cfgcr2_reg;
1310 uint32_t cfgcr1_val, cfgcr2_val;
1311 uint32_t p0, p1, p2, dco_freq;
1312
1313 cfgcr1_reg = DPLL_CFGCR1(pll_id);
1314 cfgcr2_reg = DPLL_CFGCR2(pll_id);
1315
1316 cfgcr1_val = I915_READ(cfgcr1_reg);
1317 cfgcr2_val = I915_READ(cfgcr2_reg);
1318
1319 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1320 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1321
1322 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
1323 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1324 else
1325 p1 = 1;
1326
1327
1328 switch (p0) {
1329 case DPLL_CFGCR2_PDIV_1:
1330 p0 = 1;
1331 break;
1332 case DPLL_CFGCR2_PDIV_2:
1333 p0 = 2;
1334 break;
1335 case DPLL_CFGCR2_PDIV_3:
1336 p0 = 3;
1337 break;
1338 case DPLL_CFGCR2_PDIV_7:
1339 p0 = 7;
1340 break;
1341 }
1342
1343 switch (p2) {
1344 case DPLL_CFGCR2_KDIV_5:
1345 p2 = 5;
1346 break;
1347 case DPLL_CFGCR2_KDIV_2:
1348 p2 = 2;
1349 break;
1350 case DPLL_CFGCR2_KDIV_3:
1351 p2 = 3;
1352 break;
1353 case DPLL_CFGCR2_KDIV_1:
1354 p2 = 1;
1355 break;
1356 }
1357
1358 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1359
1360 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1361 1000) / 0x8000;
1362
1363 return dco_freq / (p0 * p1 * p2 * 5);
1364 }
1365
1366 static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1367 enum intel_dpll_id pll_id)
1368 {
1369 uint32_t cfgcr0, cfgcr1;
1370 uint32_t p0, p1, p2, dco_freq, ref_clock;
1371
1372 if (INTEL_GEN(dev_priv) >= 11) {
1373 cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
1374 cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
1375 } else {
1376 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1377 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1378 }
1379
1380 p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1381 p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1382
1383 if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1384 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1385 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1386 else
1387 p1 = 1;
1388
1389
1390 switch (p0) {
1391 case DPLL_CFGCR1_PDIV_2:
1392 p0 = 2;
1393 break;
1394 case DPLL_CFGCR1_PDIV_3:
1395 p0 = 3;
1396 break;
1397 case DPLL_CFGCR1_PDIV_5:
1398 p0 = 5;
1399 break;
1400 case DPLL_CFGCR1_PDIV_7:
1401 p0 = 7;
1402 break;
1403 }
1404
1405 switch (p2) {
1406 case DPLL_CFGCR1_KDIV_1:
1407 p2 = 1;
1408 break;
1409 case DPLL_CFGCR1_KDIV_2:
1410 p2 = 2;
1411 break;
1412 case DPLL_CFGCR1_KDIV_4:
1413 p2 = 4;
1414 break;
1415 }
1416
1417 ref_clock = dev_priv->cdclk.hw.ref;
1418
1419 dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1420
1421 dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1422 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1423
1424 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1425 return 0;
1426
1427 return dco_freq / (p0 * p1 * p2 * 5);
1428 }
1429
1430 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1431 {
1432 int dotclock;
1433
1434 if (pipe_config->has_pch_encoder)
1435 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1436 &pipe_config->fdi_m_n);
1437 else if (intel_crtc_has_dp_encoder(pipe_config))
1438 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1439 &pipe_config->dp_m_n);
1440 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1441 dotclock = pipe_config->port_clock * 2 / 3;
1442 else
1443 dotclock = pipe_config->port_clock;
1444
1445 if (pipe_config->ycbcr420)
1446 dotclock *= 2;
1447
1448 if (pipe_config->pixel_multiplier)
1449 dotclock /= pipe_config->pixel_multiplier;
1450
1451 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1452 }
1453
1454 static void icl_ddi_clock_get(struct intel_encoder *encoder,
1455 struct intel_crtc_state *pipe_config)
1456 {
1457 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1458 enum port port = encoder->port;
1459 int link_clock = 0;
1460 uint32_t pll_id;
1461
1462 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1463 if (port == PORT_A || port == PORT_B) {
1464 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
1465 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1466 else
1467 link_clock = icl_calc_dp_combo_pll_link(dev_priv,
1468 pll_id);
1469 } else {
1470 /* FIXME - Add for MG PLL */
1471 WARN(1, "MG PLL clock_get code not implemented yet\n");
1472 }
1473
1474 pipe_config->port_clock = link_clock;
1475 ddi_dotclock_get(pipe_config);
1476 }
1477
1478 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1479 struct intel_crtc_state *pipe_config)
1480 {
1481 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1482 int link_clock = 0;
1483 uint32_t cfgcr0;
1484 enum intel_dpll_id pll_id;
1485
1486 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1487
1488 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1489
1490 if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1491 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1492 } else {
1493 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1494
1495 switch (link_clock) {
1496 case DPLL_CFGCR0_LINK_RATE_810:
1497 link_clock = 81000;
1498 break;
1499 case DPLL_CFGCR0_LINK_RATE_1080:
1500 link_clock = 108000;
1501 break;
1502 case DPLL_CFGCR0_LINK_RATE_1350:
1503 link_clock = 135000;
1504 break;
1505 case DPLL_CFGCR0_LINK_RATE_1620:
1506 link_clock = 162000;
1507 break;
1508 case DPLL_CFGCR0_LINK_RATE_2160:
1509 link_clock = 216000;
1510 break;
1511 case DPLL_CFGCR0_LINK_RATE_2700:
1512 link_clock = 270000;
1513 break;
1514 case DPLL_CFGCR0_LINK_RATE_3240:
1515 link_clock = 324000;
1516 break;
1517 case DPLL_CFGCR0_LINK_RATE_4050:
1518 link_clock = 405000;
1519 break;
1520 default:
1521 WARN(1, "Unsupported link rate\n");
1522 break;
1523 }
1524 link_clock *= 2;
1525 }
1526
1527 pipe_config->port_clock = link_clock;
1528
1529 ddi_dotclock_get(pipe_config);
1530 }
1531
1532 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1533 struct intel_crtc_state *pipe_config)
1534 {
1535 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1536 int link_clock = 0;
1537 uint32_t dpll_ctl1;
1538 enum intel_dpll_id pll_id;
1539
1540 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1541
1542 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1543
1544 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(pll_id)) {
1545 link_clock = skl_calc_wrpll_link(dev_priv, pll_id);
1546 } else {
1547 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(pll_id);
1548 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(pll_id);
1549
1550 switch (link_clock) {
1551 case DPLL_CTRL1_LINK_RATE_810:
1552 link_clock = 81000;
1553 break;
1554 case DPLL_CTRL1_LINK_RATE_1080:
1555 link_clock = 108000;
1556 break;
1557 case DPLL_CTRL1_LINK_RATE_1350:
1558 link_clock = 135000;
1559 break;
1560 case DPLL_CTRL1_LINK_RATE_1620:
1561 link_clock = 162000;
1562 break;
1563 case DPLL_CTRL1_LINK_RATE_2160:
1564 link_clock = 216000;
1565 break;
1566 case DPLL_CTRL1_LINK_RATE_2700:
1567 link_clock = 270000;
1568 break;
1569 default:
1570 WARN(1, "Unsupported link rate\n");
1571 break;
1572 }
1573 link_clock *= 2;
1574 }
1575
1576 pipe_config->port_clock = link_clock;
1577
1578 ddi_dotclock_get(pipe_config);
1579 }
1580
1581 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1582 struct intel_crtc_state *pipe_config)
1583 {
1584 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1585 int link_clock = 0;
1586 u32 val, pll;
1587
1588 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1589 switch (val & PORT_CLK_SEL_MASK) {
1590 case PORT_CLK_SEL_LCPLL_810:
1591 link_clock = 81000;
1592 break;
1593 case PORT_CLK_SEL_LCPLL_1350:
1594 link_clock = 135000;
1595 break;
1596 case PORT_CLK_SEL_LCPLL_2700:
1597 link_clock = 270000;
1598 break;
1599 case PORT_CLK_SEL_WRPLL1:
1600 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1601 break;
1602 case PORT_CLK_SEL_WRPLL2:
1603 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1604 break;
1605 case PORT_CLK_SEL_SPLL:
1606 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1607 if (pll == SPLL_PLL_FREQ_810MHz)
1608 link_clock = 81000;
1609 else if (pll == SPLL_PLL_FREQ_1350MHz)
1610 link_clock = 135000;
1611 else if (pll == SPLL_PLL_FREQ_2700MHz)
1612 link_clock = 270000;
1613 else {
1614 WARN(1, "bad spll freq\n");
1615 return;
1616 }
1617 break;
1618 default:
1619 WARN(1, "bad port clock sel\n");
1620 return;
1621 }
1622
1623 pipe_config->port_clock = link_clock * 2;
1624
1625 ddi_dotclock_get(pipe_config);
1626 }
1627
1628 static int bxt_calc_pll_link(struct intel_crtc_state *crtc_state)
1629 {
1630 struct intel_dpll_hw_state *state;
1631 struct dpll clock;
1632
1633 /* For DDI ports we always use a shared PLL. */
1634 if (WARN_ON(!crtc_state->shared_dpll))
1635 return 0;
1636
1637 state = &crtc_state->dpll_hw_state;
1638
1639 clock.m1 = 2;
1640 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1641 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1642 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1643 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1644 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1645 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1646
1647 return chv_calc_dpll_params(100000, &clock);
1648 }
1649
1650 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1651 struct intel_crtc_state *pipe_config)
1652 {
1653 pipe_config->port_clock = bxt_calc_pll_link(pipe_config);
1654
1655 ddi_dotclock_get(pipe_config);
1656 }
1657
1658 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1659 struct intel_crtc_state *pipe_config)
1660 {
1661 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1662
1663 if (INTEL_GEN(dev_priv) <= 8)
1664 hsw_ddi_clock_get(encoder, pipe_config);
1665 else if (IS_GEN9_BC(dev_priv))
1666 skl_ddi_clock_get(encoder, pipe_config);
1667 else if (IS_GEN9_LP(dev_priv))
1668 bxt_ddi_clock_get(encoder, pipe_config);
1669 else if (IS_CANNONLAKE(dev_priv))
1670 cnl_ddi_clock_get(encoder, pipe_config);
1671 else if (IS_ICELAKE(dev_priv))
1672 icl_ddi_clock_get(encoder, pipe_config);
1673 }
1674
1675 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1676 {
1677 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1678 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1679 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1680 u32 temp;
1681
1682 if (!intel_crtc_has_dp_encoder(crtc_state))
1683 return;
1684
1685 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1686
1687 temp = TRANS_MSA_SYNC_CLK;
1688
1689 if (crtc_state->limited_color_range)
1690 temp |= TRANS_MSA_CEA_RANGE;
1691
1692 switch (crtc_state->pipe_bpp) {
1693 case 18:
1694 temp |= TRANS_MSA_6_BPC;
1695 break;
1696 case 24:
1697 temp |= TRANS_MSA_8_BPC;
1698 break;
1699 case 30:
1700 temp |= TRANS_MSA_10_BPC;
1701 break;
1702 case 36:
1703 temp |= TRANS_MSA_12_BPC;
1704 break;
1705 default:
1706 MISSING_CASE(crtc_state->pipe_bpp);
1707 break;
1708 }
1709
1710 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1711 }
1712
1713 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1714 bool state)
1715 {
1716 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1717 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1718 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1719 uint32_t temp;
1720
1721 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1722 if (state == true)
1723 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1724 else
1725 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1726 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1727 }
1728
1729 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1730 {
1731 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1732 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1733 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1734 enum pipe pipe = crtc->pipe;
1735 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1736 enum port port = encoder->port;
1737 uint32_t temp;
1738
1739 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1740 temp = TRANS_DDI_FUNC_ENABLE;
1741 temp |= TRANS_DDI_SELECT_PORT(port);
1742
1743 switch (crtc_state->pipe_bpp) {
1744 case 18:
1745 temp |= TRANS_DDI_BPC_6;
1746 break;
1747 case 24:
1748 temp |= TRANS_DDI_BPC_8;
1749 break;
1750 case 30:
1751 temp |= TRANS_DDI_BPC_10;
1752 break;
1753 case 36:
1754 temp |= TRANS_DDI_BPC_12;
1755 break;
1756 default:
1757 BUG();
1758 }
1759
1760 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1761 temp |= TRANS_DDI_PVSYNC;
1762 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1763 temp |= TRANS_DDI_PHSYNC;
1764
1765 if (cpu_transcoder == TRANSCODER_EDP) {
1766 switch (pipe) {
1767 case PIPE_A:
1768 /* On Haswell, can only use the always-on power well for
1769 * eDP when not using the panel fitter, and when not
1770 * using motion blur mitigation (which we don't
1771 * support). */
1772 if (IS_HASWELL(dev_priv) &&
1773 (crtc_state->pch_pfit.enabled ||
1774 crtc_state->pch_pfit.force_thru))
1775 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1776 else
1777 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1778 break;
1779 case PIPE_B:
1780 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1781 break;
1782 case PIPE_C:
1783 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1784 break;
1785 default:
1786 BUG();
1787 break;
1788 }
1789 }
1790
1791 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1792 if (crtc_state->has_hdmi_sink)
1793 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1794 else
1795 temp |= TRANS_DDI_MODE_SELECT_DVI;
1796
1797 if (crtc_state->hdmi_scrambling)
1798 temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1799 if (crtc_state->hdmi_high_tmds_clock_ratio)
1800 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1801 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1802 temp |= TRANS_DDI_MODE_SELECT_FDI;
1803 temp |= (crtc_state->fdi_lanes - 1) << 1;
1804 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1805 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1806 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1807 } else {
1808 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1809 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1810 }
1811
1812 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1813 }
1814
1815 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1816 {
1817 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1818 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1819 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1820 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1821 uint32_t val = I915_READ(reg);
1822
1823 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1824 val |= TRANS_DDI_PORT_NONE;
1825 I915_WRITE(reg, val);
1826
1827 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1828 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1829 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1830 /* Quirk time at 100ms for reliable operation */
1831 msleep(100);
1832 }
1833 }
1834
1835 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1836 bool enable)
1837 {
1838 struct drm_device *dev = intel_encoder->base.dev;
1839 struct drm_i915_private *dev_priv = to_i915(dev);
1840 enum pipe pipe = 0;
1841 int ret = 0;
1842 uint32_t tmp;
1843
1844 if (WARN_ON(!intel_display_power_get_if_enabled(dev_priv,
1845 intel_encoder->power_domain)))
1846 return -ENXIO;
1847
1848 if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1849 ret = -EIO;
1850 goto out;
1851 }
1852
1853 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1854 if (enable)
1855 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1856 else
1857 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1858 I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1859 out:
1860 intel_display_power_put(dev_priv, intel_encoder->power_domain);
1861 return ret;
1862 }
1863
1864 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1865 {
1866 struct drm_device *dev = intel_connector->base.dev;
1867 struct drm_i915_private *dev_priv = to_i915(dev);
1868 struct intel_encoder *encoder = intel_connector->encoder;
1869 int type = intel_connector->base.connector_type;
1870 enum port port = encoder->port;
1871 enum pipe pipe = 0;
1872 enum transcoder cpu_transcoder;
1873 uint32_t tmp;
1874 bool ret;
1875
1876 if (!intel_display_power_get_if_enabled(dev_priv,
1877 encoder->power_domain))
1878 return false;
1879
1880 if (!encoder->get_hw_state(encoder, &pipe)) {
1881 ret = false;
1882 goto out;
1883 }
1884
1885 if (port == PORT_A)
1886 cpu_transcoder = TRANSCODER_EDP;
1887 else
1888 cpu_transcoder = (enum transcoder) pipe;
1889
1890 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1891
1892 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1893 case TRANS_DDI_MODE_SELECT_HDMI:
1894 case TRANS_DDI_MODE_SELECT_DVI:
1895 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1896 break;
1897
1898 case TRANS_DDI_MODE_SELECT_DP_SST:
1899 ret = type == DRM_MODE_CONNECTOR_eDP ||
1900 type == DRM_MODE_CONNECTOR_DisplayPort;
1901 break;
1902
1903 case TRANS_DDI_MODE_SELECT_DP_MST:
1904 /* if the transcoder is in MST state then
1905 * connector isn't connected */
1906 ret = false;
1907 break;
1908
1909 case TRANS_DDI_MODE_SELECT_FDI:
1910 ret = type == DRM_MODE_CONNECTOR_VGA;
1911 break;
1912
1913 default:
1914 ret = false;
1915 break;
1916 }
1917
1918 out:
1919 intel_display_power_put(dev_priv, encoder->power_domain);
1920
1921 return ret;
1922 }
1923
1924 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1925 enum pipe *pipe)
1926 {
1927 struct drm_device *dev = encoder->base.dev;
1928 struct drm_i915_private *dev_priv = to_i915(dev);
1929 enum port port = encoder->port;
1930 enum pipe p;
1931 u32 tmp;
1932 bool ret;
1933
1934 if (!intel_display_power_get_if_enabled(dev_priv,
1935 encoder->power_domain))
1936 return false;
1937
1938 ret = false;
1939
1940 tmp = I915_READ(DDI_BUF_CTL(port));
1941
1942 if (!(tmp & DDI_BUF_CTL_ENABLE))
1943 goto out;
1944
1945 if (port == PORT_A) {
1946 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1947
1948 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1949 case TRANS_DDI_EDP_INPUT_A_ON:
1950 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1951 *pipe = PIPE_A;
1952 break;
1953 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1954 *pipe = PIPE_B;
1955 break;
1956 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1957 *pipe = PIPE_C;
1958 break;
1959 }
1960
1961 ret = true;
1962
1963 goto out;
1964 }
1965
1966 for_each_pipe(dev_priv, p) {
1967 enum transcoder cpu_transcoder = (enum transcoder) p;
1968
1969 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1970
1971 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1972 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1973 TRANS_DDI_MODE_SELECT_DP_MST)
1974 goto out;
1975
1976 *pipe = p;
1977 ret = true;
1978
1979 goto out;
1980 }
1981 }
1982
1983 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1984
1985 out:
1986 if (ret && IS_GEN9_LP(dev_priv)) {
1987 tmp = I915_READ(BXT_PHY_CTL(port));
1988 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
1989 BXT_PHY_LANE_POWERDOWN_ACK |
1990 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1991 DRM_ERROR("Port %c enabled but PHY powered down? "
1992 "(PHY_CTL %08x)\n", port_name(port), tmp);
1993 }
1994
1995 intel_display_power_put(dev_priv, encoder->power_domain);
1996
1997 return ret;
1998 }
1999
2000 static inline enum intel_display_power_domain
2001 intel_ddi_main_link_aux_domain(struct intel_dp *intel_dp)
2002 {
2003 /* CNL HW requires corresponding AUX IOs to be powered up for PSR with
2004 * DC states enabled at the same time, while for driver initiated AUX
2005 * transfers we need the same AUX IOs to be powered but with DC states
2006 * disabled. Accordingly use the AUX power domain here which leaves DC
2007 * states enabled.
2008 * However, for non-A AUX ports the corresponding non-EDP transcoders
2009 * would have already enabled power well 2 and DC_OFF. This means we can
2010 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2011 * specific AUX_IO reference without powering up any extra wells.
2012 * Note that PSR is enabled only on Port A even though this function
2013 * returns the correct domain for other ports too.
2014 */
2015 return intel_dp->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2016 intel_dp->aux_power_domain;
2017 }
2018
2019 static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder,
2020 struct intel_crtc_state *crtc_state)
2021 {
2022 struct intel_digital_port *dig_port;
2023 u64 domains;
2024
2025 /*
2026 * TODO: Add support for MST encoders. Atm, the following should never
2027 * happen since fake-MST encoders don't set their get_power_domains()
2028 * hook.
2029 */
2030 if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2031 return 0;
2032
2033 dig_port = enc_to_dig_port(&encoder->base);
2034 domains = BIT_ULL(dig_port->ddi_io_power_domain);
2035
2036 /* AUX power is only needed for (e)DP mode, not for HDMI. */
2037 if (intel_crtc_has_dp_encoder(crtc_state)) {
2038 struct intel_dp *intel_dp = &dig_port->dp;
2039
2040 domains |= BIT_ULL(intel_ddi_main_link_aux_domain(intel_dp));
2041 }
2042
2043 return domains;
2044 }
2045
2046 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
2047 {
2048 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2049 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2050 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
2051 enum port port = encoder->port;
2052 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2053
2054 if (cpu_transcoder != TRANSCODER_EDP)
2055 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2056 TRANS_CLK_SEL_PORT(port));
2057 }
2058
2059 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2060 {
2061 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2062 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2063
2064 if (cpu_transcoder != TRANSCODER_EDP)
2065 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2066 TRANS_CLK_SEL_DISABLED);
2067 }
2068
2069 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2070 enum port port, uint8_t iboost)
2071 {
2072 u32 tmp;
2073
2074 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2075 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2076 if (iboost)
2077 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2078 else
2079 tmp |= BALANCE_LEG_DISABLE(port);
2080 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2081 }
2082
2083 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2084 int level, enum intel_output_type type)
2085 {
2086 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2087 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2088 enum port port = encoder->port;
2089 uint8_t iboost;
2090
2091 if (type == INTEL_OUTPUT_HDMI)
2092 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2093 else
2094 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2095
2096 if (iboost == 0) {
2097 const struct ddi_buf_trans *ddi_translations;
2098 int n_entries;
2099
2100 if (type == INTEL_OUTPUT_HDMI)
2101 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2102 else if (type == INTEL_OUTPUT_EDP)
2103 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2104 else
2105 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2106
2107 if (WARN_ON_ONCE(!ddi_translations))
2108 return;
2109 if (WARN_ON_ONCE(level >= n_entries))
2110 level = n_entries - 1;
2111
2112 iboost = ddi_translations[level].i_boost;
2113 }
2114
2115 /* Make sure that the requested I_boost is valid */
2116 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2117 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2118 return;
2119 }
2120
2121 _skl_ddi_set_iboost(dev_priv, port, iboost);
2122
2123 if (port == PORT_A && intel_dig_port->max_lanes == 4)
2124 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2125 }
2126
2127 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2128 int level, enum intel_output_type type)
2129 {
2130 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2131 const struct bxt_ddi_buf_trans *ddi_translations;
2132 enum port port = encoder->port;
2133 int n_entries;
2134
2135 if (type == INTEL_OUTPUT_HDMI)
2136 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2137 else if (type == INTEL_OUTPUT_EDP)
2138 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2139 else
2140 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2141
2142 if (WARN_ON_ONCE(!ddi_translations))
2143 return;
2144 if (WARN_ON_ONCE(level >= n_entries))
2145 level = n_entries - 1;
2146
2147 bxt_ddi_phy_set_signal_level(dev_priv, port,
2148 ddi_translations[level].margin,
2149 ddi_translations[level].scale,
2150 ddi_translations[level].enable,
2151 ddi_translations[level].deemphasis);
2152 }
2153
2154 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2155 {
2156 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2157 enum port port = encoder->port;
2158 int n_entries;
2159
2160 if (IS_ICELAKE(dev_priv)) {
2161 if (port == PORT_A || port == PORT_B)
2162 icl_get_combo_buf_trans(dev_priv, port, encoder->type,
2163 &n_entries);
2164 else
2165 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2166 } else if (IS_CANNONLAKE(dev_priv)) {
2167 if (encoder->type == INTEL_OUTPUT_EDP)
2168 cnl_get_buf_trans_edp(dev_priv, &n_entries);
2169 else
2170 cnl_get_buf_trans_dp(dev_priv, &n_entries);
2171 } else if (IS_GEN9_LP(dev_priv)) {
2172 if (encoder->type == INTEL_OUTPUT_EDP)
2173 bxt_get_buf_trans_edp(dev_priv, &n_entries);
2174 else
2175 bxt_get_buf_trans_dp(dev_priv, &n_entries);
2176 } else {
2177 if (encoder->type == INTEL_OUTPUT_EDP)
2178 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2179 else
2180 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2181 }
2182
2183 if (WARN_ON(n_entries < 1))
2184 n_entries = 1;
2185 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2186 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2187
2188 return index_to_dp_signal_levels[n_entries - 1] &
2189 DP_TRAIN_VOLTAGE_SWING_MASK;
2190 }
2191
2192 /*
2193 * We assume that the full set of pre-emphasis values can be
2194 * used on all DDI platforms. Should that change we need to
2195 * rethink this code.
2196 */
2197 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2198 {
2199 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2200 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2201 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2202 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2203 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2204 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2205 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2206 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2207 default:
2208 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2209 }
2210 }
2211
2212 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2213 int level, enum intel_output_type type)
2214 {
2215 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2216 const struct cnl_ddi_buf_trans *ddi_translations;
2217 enum port port = encoder->port;
2218 int n_entries, ln;
2219 u32 val;
2220
2221 if (type == INTEL_OUTPUT_HDMI)
2222 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2223 else if (type == INTEL_OUTPUT_EDP)
2224 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2225 else
2226 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2227
2228 if (WARN_ON_ONCE(!ddi_translations))
2229 return;
2230 if (WARN_ON_ONCE(level >= n_entries))
2231 level = n_entries - 1;
2232
2233 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2234 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2235 val &= ~SCALING_MODE_SEL_MASK;
2236 val |= SCALING_MODE_SEL(2);
2237 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2238
2239 /* Program PORT_TX_DW2 */
2240 val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2241 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2242 RCOMP_SCALAR_MASK);
2243 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2244 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2245 /* Rcomp scalar is fixed as 0x98 for every table entry */
2246 val |= RCOMP_SCALAR(0x98);
2247 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2248
2249 /* Program PORT_TX_DW4 */
2250 /* We cannot write to GRP. It would overrite individual loadgen */
2251 for (ln = 0; ln < 4; ln++) {
2252 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2253 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2254 CURSOR_COEFF_MASK);
2255 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2256 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2257 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2258 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2259 }
2260
2261 /* Program PORT_TX_DW5 */
2262 /* All DW5 values are fixed for every table entry */
2263 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2264 val &= ~RTERM_SELECT_MASK;
2265 val |= RTERM_SELECT(6);
2266 val |= TAP3_DISABLE;
2267 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2268
2269 /* Program PORT_TX_DW7 */
2270 val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2271 val &= ~N_SCALAR_MASK;
2272 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2273 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2274 }
2275
2276 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2277 int level, enum intel_output_type type)
2278 {
2279 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2280 enum port port = encoder->port;
2281 int width, rate, ln;
2282 u32 val;
2283
2284 if (type == INTEL_OUTPUT_HDMI) {
2285 width = 4;
2286 rate = 0; /* Rate is always < than 6GHz for HDMI */
2287 } else {
2288 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2289
2290 width = intel_dp->lane_count;
2291 rate = intel_dp->link_rate;
2292 }
2293
2294 /*
2295 * 1. If port type is eDP or DP,
2296 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2297 * else clear to 0b.
2298 */
2299 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2300 if (type != INTEL_OUTPUT_HDMI)
2301 val |= COMMON_KEEPER_EN;
2302 else
2303 val &= ~COMMON_KEEPER_EN;
2304 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2305
2306 /* 2. Program loadgen select */
2307 /*
2308 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2309 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2310 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2311 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2312 */
2313 for (ln = 0; ln <= 3; ln++) {
2314 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2315 val &= ~LOADGEN_SELECT;
2316
2317 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2318 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2319 val |= LOADGEN_SELECT;
2320 }
2321 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2322 }
2323
2324 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2325 val = I915_READ(CNL_PORT_CL1CM_DW5);
2326 val |= SUS_CLOCK_CONFIG;
2327 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2328
2329 /* 4. Clear training enable to change swing values */
2330 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2331 val &= ~TX_TRAINING_EN;
2332 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2333
2334 /* 5. Program swing and de-emphasis */
2335 cnl_ddi_vswing_program(encoder, level, type);
2336
2337 /* 6. Set training enable to trigger update */
2338 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2339 val |= TX_TRAINING_EN;
2340 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2341 }
2342
2343 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2344 u32 level, enum port port, int type)
2345 {
2346 const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
2347 u32 n_entries, val;
2348 int ln;
2349
2350 ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
2351 &n_entries);
2352 if (!ddi_translations)
2353 return;
2354
2355 if (level >= n_entries) {
2356 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2357 level = n_entries - 1;
2358 }
2359
2360 /* Set PORT_TX_DW5 Rterm Sel to 110b. */
2361 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2362 val &= ~RTERM_SELECT_MASK;
2363 val |= RTERM_SELECT(0x6);
2364 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2365
2366 /* Program PORT_TX_DW5 */
2367 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2368 /* Set DisableTap2 and DisableTap3 if MIPI DSI
2369 * Clear DisableTap2 and DisableTap3 for all other Ports
2370 */
2371 if (type == INTEL_OUTPUT_DSI) {
2372 val |= TAP2_DISABLE;
2373 val |= TAP3_DISABLE;
2374 } else {
2375 val &= ~TAP2_DISABLE;
2376 val &= ~TAP3_DISABLE;
2377 }
2378 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2379
2380 /* Program PORT_TX_DW2 */
2381 val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
2382 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2383 RCOMP_SCALAR_MASK);
2384 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
2385 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
2386 /* Program Rcomp scalar for every table entry */
2387 val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
2388 I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
2389
2390 /* Program PORT_TX_DW4 */
2391 /* We cannot write to GRP. It would overwrite individual loadgen. */
2392 for (ln = 0; ln <= 3; ln++) {
2393 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2394 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2395 CURSOR_COEFF_MASK);
2396 val |= ddi_translations[level].dw4_scaling;
2397 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2398 }
2399 }
2400
2401 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2402 u32 level,
2403 enum intel_output_type type)
2404 {
2405 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2406 enum port port = encoder->port;
2407 int width = 0;
2408 int rate = 0;
2409 u32 val;
2410 int ln = 0;
2411
2412 if (type == INTEL_OUTPUT_HDMI) {
2413 width = 4;
2414 /* Rate is always < than 6GHz for HDMI */
2415 } else {
2416 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2417
2418 width = intel_dp->lane_count;
2419 rate = intel_dp->link_rate;
2420 }
2421
2422 /*
2423 * 1. If port type is eDP or DP,
2424 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2425 * else clear to 0b.
2426 */
2427 val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
2428 if (type == INTEL_OUTPUT_HDMI)
2429 val &= ~COMMON_KEEPER_EN;
2430 else
2431 val |= COMMON_KEEPER_EN;
2432 I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
2433
2434 /* 2. Program loadgen select */
2435 /*
2436 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2437 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2438 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2439 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2440 */
2441 for (ln = 0; ln <= 3; ln++) {
2442 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2443 val &= ~LOADGEN_SELECT;
2444
2445 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2446 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2447 val |= LOADGEN_SELECT;
2448 }
2449 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2450 }
2451
2452 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2453 val = I915_READ(ICL_PORT_CL_DW5(port));
2454 val |= SUS_CLOCK_CONFIG;
2455 I915_WRITE(ICL_PORT_CL_DW5(port), val);
2456
2457 /* 4. Clear training enable to change swing values */
2458 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2459 val &= ~TX_TRAINING_EN;
2460 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2461
2462 /* 5. Program swing and de-emphasis */
2463 icl_ddi_combo_vswing_program(dev_priv, level, port, type);
2464
2465 /* 6. Set training enable to trigger update */
2466 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2467 val |= TX_TRAINING_EN;
2468 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2469 }
2470
2471 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level,
2472 enum intel_output_type type)
2473 {
2474 enum port port = encoder->port;
2475
2476 if (port == PORT_A || port == PORT_B)
2477 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2478 else
2479 /* Not Implemented Yet */
2480 WARN_ON(1);
2481 }
2482
2483 static uint32_t translate_signal_level(int signal_levels)
2484 {
2485 int i;
2486
2487 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2488 if (index_to_dp_signal_levels[i] == signal_levels)
2489 return i;
2490 }
2491
2492 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2493 signal_levels);
2494
2495 return 0;
2496 }
2497
2498 static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
2499 {
2500 uint8_t train_set = intel_dp->train_set[0];
2501 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2502 DP_TRAIN_PRE_EMPHASIS_MASK);
2503
2504 return translate_signal_level(signal_levels);
2505 }
2506
2507 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2508 {
2509 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2510 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2511 struct intel_encoder *encoder = &dport->base;
2512 int level = intel_ddi_dp_level(intel_dp);
2513
2514 if (IS_ICELAKE(dev_priv))
2515 icl_ddi_vswing_sequence(encoder, level, encoder->type);
2516 else if (IS_CANNONLAKE(dev_priv))
2517 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2518 else
2519 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2520
2521 return 0;
2522 }
2523
2524 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2525 {
2526 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2527 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2528 struct intel_encoder *encoder = &dport->base;
2529 int level = intel_ddi_dp_level(intel_dp);
2530
2531 if (IS_GEN9_BC(dev_priv))
2532 skl_ddi_set_iboost(encoder, level, encoder->type);
2533
2534 return DDI_BUF_TRANS_SELECT(level);
2535 }
2536
2537 void icl_map_plls_to_ports(struct drm_crtc *crtc,
2538 struct intel_crtc_state *crtc_state,
2539 struct drm_atomic_state *old_state)
2540 {
2541 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2542 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2543 struct drm_connector_state *conn_state;
2544 struct drm_connector *conn;
2545 int i;
2546
2547 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
2548 struct intel_encoder *encoder =
2549 to_intel_encoder(conn_state->best_encoder);
2550 enum port port;
2551 uint32_t val;
2552
2553 if (conn_state->crtc != crtc)
2554 continue;
2555
2556 port = encoder->port;
2557 mutex_lock(&dev_priv->dpll_lock);
2558
2559 val = I915_READ(DPCLKA_CFGCR0_ICL);
2560 WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
2561
2562 if (port == PORT_A || port == PORT_B) {
2563 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2564 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2565 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2566 POSTING_READ(DPCLKA_CFGCR0_ICL);
2567 }
2568
2569 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2570 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2571
2572 mutex_unlock(&dev_priv->dpll_lock);
2573 }
2574 }
2575
2576 void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
2577 struct intel_crtc_state *crtc_state,
2578 struct drm_atomic_state *old_state)
2579 {
2580 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2581 struct drm_connector_state *old_conn_state;
2582 struct drm_connector *conn;
2583 int i;
2584
2585 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
2586 struct intel_encoder *encoder =
2587 to_intel_encoder(old_conn_state->best_encoder);
2588 enum port port;
2589
2590 if (old_conn_state->crtc != crtc)
2591 continue;
2592
2593 port = encoder->port;
2594 mutex_lock(&dev_priv->dpll_lock);
2595 I915_WRITE(DPCLKA_CFGCR0_ICL,
2596 I915_READ(DPCLKA_CFGCR0_ICL) |
2597 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2598 mutex_unlock(&dev_priv->dpll_lock);
2599 }
2600 }
2601
2602 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2603 const struct intel_shared_dpll *pll)
2604 {
2605 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2606 enum port port = encoder->port;
2607 uint32_t val;
2608
2609 if (WARN_ON(!pll))
2610 return;
2611
2612 mutex_lock(&dev_priv->dpll_lock);
2613
2614 if (IS_ICELAKE(dev_priv)) {
2615 if (port >= PORT_C)
2616 I915_WRITE(DDI_CLK_SEL(port),
2617 icl_pll_to_ddi_pll_sel(encoder, pll));
2618 } else if (IS_CANNONLAKE(dev_priv)) {
2619 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2620 val = I915_READ(DPCLKA_CFGCR0);
2621 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2622 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2623 I915_WRITE(DPCLKA_CFGCR0, val);
2624
2625 /*
2626 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2627 * This step and the step before must be done with separate
2628 * register writes.
2629 */
2630 val = I915_READ(DPCLKA_CFGCR0);
2631 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2632 I915_WRITE(DPCLKA_CFGCR0, val);
2633 } else if (IS_GEN9_BC(dev_priv)) {
2634 /* DDI -> PLL mapping */
2635 val = I915_READ(DPLL_CTRL2);
2636
2637 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2638 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2639 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
2640 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2641
2642 I915_WRITE(DPLL_CTRL2, val);
2643
2644 } else if (INTEL_GEN(dev_priv) < 9) {
2645 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2646 }
2647
2648 mutex_unlock(&dev_priv->dpll_lock);
2649 }
2650
2651 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2652 {
2653 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2654 enum port port = encoder->port;
2655
2656 if (IS_ICELAKE(dev_priv)) {
2657 if (port >= PORT_C)
2658 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2659 } else if (IS_CANNONLAKE(dev_priv)) {
2660 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2661 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2662 } else if (IS_GEN9_BC(dev_priv)) {
2663 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2664 DPLL_CTRL2_DDI_CLK_OFF(port));
2665 } else if (INTEL_GEN(dev_priv) < 9) {
2666 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2667 }
2668 }
2669
2670 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
2671 const struct intel_crtc_state *crtc_state,
2672 const struct drm_connector_state *conn_state)
2673 {
2674 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2675 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2676 enum port port = encoder->port;
2677 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2678 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2679 int level = intel_ddi_dp_level(intel_dp);
2680
2681 WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
2682
2683 intel_display_power_get(dev_priv,
2684 intel_ddi_main_link_aux_domain(intel_dp));
2685
2686 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
2687 crtc_state->lane_count, is_mst);
2688
2689 intel_edp_panel_on(intel_dp);
2690
2691 intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
2692
2693 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2694
2695 if (IS_ICELAKE(dev_priv))
2696 icl_ddi_vswing_sequence(encoder, level, encoder->type);
2697 else if (IS_CANNONLAKE(dev_priv))
2698 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2699 else if (IS_GEN9_LP(dev_priv))
2700 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2701 else
2702 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
2703
2704 intel_ddi_init_dp_buf_reg(encoder);
2705 if (!is_mst)
2706 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2707 intel_dp_start_link_train(intel_dp);
2708 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
2709 intel_dp_stop_link_train(intel_dp);
2710
2711 if (!is_mst)
2712 intel_ddi_enable_pipe_clock(crtc_state);
2713 }
2714
2715 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
2716 const struct intel_crtc_state *crtc_state,
2717 const struct drm_connector_state *conn_state)
2718 {
2719 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2720 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2721 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2722 enum port port = encoder->port;
2723 int level = intel_ddi_hdmi_level(dev_priv, port);
2724 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2725
2726 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2727 intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
2728
2729 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2730
2731 if (IS_ICELAKE(dev_priv))
2732 icl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2733 else if (IS_CANNONLAKE(dev_priv))
2734 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2735 else if (IS_GEN9_LP(dev_priv))
2736 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2737 else
2738 intel_prepare_hdmi_ddi_buffers(encoder, level);
2739
2740 if (IS_GEN9_BC(dev_priv))
2741 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
2742
2743 intel_ddi_enable_pipe_clock(crtc_state);
2744
2745 intel_dig_port->set_infoframes(&encoder->base,
2746 crtc_state->has_infoframe,
2747 crtc_state, conn_state);
2748 }
2749
2750 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
2751 const struct intel_crtc_state *crtc_state,
2752 const struct drm_connector_state *conn_state)
2753 {
2754 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2755 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2756 enum pipe pipe = crtc->pipe;
2757
2758 /*
2759 * When called from DP MST code:
2760 * - conn_state will be NULL
2761 * - encoder will be the main encoder (ie. mst->primary)
2762 * - the main connector associated with this port
2763 * won't be active or linked to a crtc
2764 * - crtc_state will be the state of the first stream to
2765 * be activated on this port, and it may not be the same
2766 * stream that will be deactivated last, but each stream
2767 * should have a state that is identical when it comes to
2768 * the DP link parameteres
2769 */
2770
2771 WARN_ON(crtc_state->has_pch_encoder);
2772
2773 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2774
2775 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2776 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
2777 else
2778 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
2779 }
2780
2781 static void intel_disable_ddi_buf(struct intel_encoder *encoder)
2782 {
2783 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2784 enum port port = encoder->port;
2785 bool wait = false;
2786 u32 val;
2787
2788 val = I915_READ(DDI_BUF_CTL(port));
2789 if (val & DDI_BUF_CTL_ENABLE) {
2790 val &= ~DDI_BUF_CTL_ENABLE;
2791 I915_WRITE(DDI_BUF_CTL(port), val);
2792 wait = true;
2793 }
2794
2795 val = I915_READ(DP_TP_CTL(port));
2796 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2797 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2798 I915_WRITE(DP_TP_CTL(port), val);
2799
2800 if (wait)
2801 intel_wait_ddi_buf_idle(dev_priv, port);
2802 }
2803
2804 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
2805 const struct intel_crtc_state *old_crtc_state,
2806 const struct drm_connector_state *old_conn_state)
2807 {
2808 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2809 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2810 struct intel_dp *intel_dp = &dig_port->dp;
2811 bool is_mst = intel_crtc_has_type(old_crtc_state,
2812 INTEL_OUTPUT_DP_MST);
2813
2814 if (!is_mst) {
2815 intel_ddi_disable_pipe_clock(old_crtc_state);
2816 /*
2817 * Power down sink before disabling the port, otherwise we end
2818 * up getting interrupts from the sink on detecting link loss.
2819 */
2820 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2821 }
2822
2823 intel_disable_ddi_buf(encoder);
2824
2825 intel_edp_panel_vdd_on(intel_dp);
2826 intel_edp_panel_off(intel_dp);
2827
2828 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2829
2830 intel_ddi_clk_disable(encoder);
2831
2832 intel_display_power_put(dev_priv,
2833 intel_ddi_main_link_aux_domain(intel_dp));
2834 }
2835
2836 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
2837 const struct intel_crtc_state *old_crtc_state,
2838 const struct drm_connector_state *old_conn_state)
2839 {
2840 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2841 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2842 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2843
2844 dig_port->set_infoframes(&encoder->base, false,
2845 old_crtc_state, old_conn_state);
2846
2847 intel_ddi_disable_pipe_clock(old_crtc_state);
2848
2849 intel_disable_ddi_buf(encoder);
2850
2851 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2852
2853 intel_ddi_clk_disable(encoder);
2854
2855 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2856 }
2857
2858 static void intel_ddi_post_disable(struct intel_encoder *encoder,
2859 const struct intel_crtc_state *old_crtc_state,
2860 const struct drm_connector_state *old_conn_state)
2861 {
2862 /*
2863 * When called from DP MST code:
2864 * - old_conn_state will be NULL
2865 * - encoder will be the main encoder (ie. mst->primary)
2866 * - the main connector associated with this port
2867 * won't be active or linked to a crtc
2868 * - old_crtc_state will be the state of the last stream to
2869 * be deactivated on this port, and it may not be the same
2870 * stream that was activated last, but each stream
2871 * should have a state that is identical when it comes to
2872 * the DP link parameteres
2873 */
2874
2875 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2876 intel_ddi_post_disable_hdmi(encoder,
2877 old_crtc_state, old_conn_state);
2878 else
2879 intel_ddi_post_disable_dp(encoder,
2880 old_crtc_state, old_conn_state);
2881 }
2882
2883 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
2884 const struct intel_crtc_state *old_crtc_state,
2885 const struct drm_connector_state *old_conn_state)
2886 {
2887 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2888 uint32_t val;
2889
2890 /*
2891 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2892 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2893 * step 13 is the correct place for it. Step 18 is where it was
2894 * originally before the BUN.
2895 */
2896 val = I915_READ(FDI_RX_CTL(PIPE_A));
2897 val &= ~FDI_RX_ENABLE;
2898 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2899
2900 intel_disable_ddi_buf(encoder);
2901 intel_ddi_clk_disable(encoder);
2902
2903 val = I915_READ(FDI_RX_MISC(PIPE_A));
2904 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2905 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2906 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
2907
2908 val = I915_READ(FDI_RX_CTL(PIPE_A));
2909 val &= ~FDI_PCDCLK;
2910 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2911
2912 val = I915_READ(FDI_RX_CTL(PIPE_A));
2913 val &= ~FDI_RX_PLL_ENABLE;
2914 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2915 }
2916
2917 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
2918 const struct intel_crtc_state *crtc_state,
2919 const struct drm_connector_state *conn_state)
2920 {
2921 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2922 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2923 enum port port = encoder->port;
2924
2925 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
2926 intel_dp_stop_link_train(intel_dp);
2927
2928 intel_edp_backlight_on(crtc_state, conn_state);
2929 intel_psr_enable(intel_dp, crtc_state);
2930 intel_edp_drrs_enable(intel_dp, crtc_state);
2931
2932 if (crtc_state->has_audio)
2933 intel_audio_codec_enable(encoder, crtc_state, conn_state);
2934 }
2935
2936 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
2937 const struct intel_crtc_state *crtc_state,
2938 const struct drm_connector_state *conn_state)
2939 {
2940 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2941 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2942 struct drm_connector *connector = conn_state->connector;
2943 enum port port = encoder->port;
2944
2945 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
2946 crtc_state->hdmi_high_tmds_clock_ratio,
2947 crtc_state->hdmi_scrambling))
2948 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
2949 connector->base.id, connector->name);
2950
2951 /* Display WA #1143: skl,kbl,cfl */
2952 if (IS_GEN9_BC(dev_priv)) {
2953 /*
2954 * For some reason these chicken bits have been
2955 * stuffed into a transcoder register, event though
2956 * the bits affect a specific DDI port rather than
2957 * a specific transcoder.
2958 */
2959 static const enum transcoder port_to_transcoder[] = {
2960 [PORT_A] = TRANSCODER_EDP,
2961 [PORT_B] = TRANSCODER_A,
2962 [PORT_C] = TRANSCODER_B,
2963 [PORT_D] = TRANSCODER_C,
2964 [PORT_E] = TRANSCODER_A,
2965 };
2966 enum transcoder transcoder = port_to_transcoder[port];
2967 u32 val;
2968
2969 val = I915_READ(CHICKEN_TRANS(transcoder));
2970
2971 if (port == PORT_E)
2972 val |= DDIE_TRAINING_OVERRIDE_ENABLE |
2973 DDIE_TRAINING_OVERRIDE_VALUE;
2974 else
2975 val |= DDI_TRAINING_OVERRIDE_ENABLE |
2976 DDI_TRAINING_OVERRIDE_VALUE;
2977
2978 I915_WRITE(CHICKEN_TRANS(transcoder), val);
2979 POSTING_READ(CHICKEN_TRANS(transcoder));
2980
2981 udelay(1);
2982
2983 if (port == PORT_E)
2984 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
2985 DDIE_TRAINING_OVERRIDE_VALUE);
2986 else
2987 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
2988 DDI_TRAINING_OVERRIDE_VALUE);
2989
2990 I915_WRITE(CHICKEN_TRANS(transcoder), val);
2991 }
2992
2993 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2994 * are ignored so nothing special needs to be done besides
2995 * enabling the port.
2996 */
2997 I915_WRITE(DDI_BUF_CTL(port),
2998 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
2999
3000 if (crtc_state->has_audio)
3001 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3002 }
3003
3004 static void intel_enable_ddi(struct intel_encoder *encoder,
3005 const struct intel_crtc_state *crtc_state,
3006 const struct drm_connector_state *conn_state)
3007 {
3008 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3009 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3010 else
3011 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
3012
3013 /* Enable hdcp if it's desired */
3014 if (conn_state->content_protection ==
3015 DRM_MODE_CONTENT_PROTECTION_DESIRED)
3016 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3017 }
3018
3019 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3020 const struct intel_crtc_state *old_crtc_state,
3021 const struct drm_connector_state *old_conn_state)
3022 {
3023 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3024
3025 intel_dp->link_trained = false;
3026
3027 if (old_crtc_state->has_audio)
3028 intel_audio_codec_disable(encoder,
3029 old_crtc_state, old_conn_state);
3030
3031 intel_edp_drrs_disable(intel_dp, old_crtc_state);
3032 intel_psr_disable(intel_dp, old_crtc_state);
3033 intel_edp_backlight_off(old_conn_state);
3034 }
3035
3036 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3037 const struct intel_crtc_state *old_crtc_state,
3038 const struct drm_connector_state *old_conn_state)
3039 {
3040 struct drm_connector *connector = old_conn_state->connector;
3041
3042 if (old_crtc_state->has_audio)
3043 intel_audio_codec_disable(encoder,
3044 old_crtc_state, old_conn_state);
3045
3046 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3047 false, false))
3048 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3049 connector->base.id, connector->name);
3050 }
3051
3052 static void intel_disable_ddi(struct intel_encoder *encoder,
3053 const struct intel_crtc_state *old_crtc_state,
3054 const struct drm_connector_state *old_conn_state)
3055 {
3056 intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3057
3058 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3059 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3060 else
3061 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
3062 }
3063
3064 static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
3065 const struct intel_crtc_state *pipe_config,
3066 const struct drm_connector_state *conn_state)
3067 {
3068 uint8_t mask = pipe_config->lane_lat_optim_mask;
3069
3070 bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
3071 }
3072
3073 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3074 {
3075 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3076 struct drm_i915_private *dev_priv =
3077 to_i915(intel_dig_port->base.base.dev);
3078 enum port port = intel_dig_port->base.port;
3079 uint32_t val;
3080 bool wait = false;
3081
3082 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3083 val = I915_READ(DDI_BUF_CTL(port));
3084 if (val & DDI_BUF_CTL_ENABLE) {
3085 val &= ~DDI_BUF_CTL_ENABLE;
3086 I915_WRITE(DDI_BUF_CTL(port), val);
3087 wait = true;
3088 }
3089
3090 val = I915_READ(DP_TP_CTL(port));
3091 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3092 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3093 I915_WRITE(DP_TP_CTL(port), val);
3094 POSTING_READ(DP_TP_CTL(port));
3095
3096 if (wait)
3097 intel_wait_ddi_buf_idle(dev_priv, port);
3098 }
3099
3100 val = DP_TP_CTL_ENABLE |
3101 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3102 if (intel_dp->link_mst)
3103 val |= DP_TP_CTL_MODE_MST;
3104 else {
3105 val |= DP_TP_CTL_MODE_SST;
3106 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3107 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3108 }
3109 I915_WRITE(DP_TP_CTL(port), val);
3110 POSTING_READ(DP_TP_CTL(port));
3111
3112 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3113 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3114 POSTING_READ(DDI_BUF_CTL(port));
3115
3116 udelay(600);
3117 }
3118
3119 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3120 enum transcoder cpu_transcoder)
3121 {
3122 if (cpu_transcoder == TRANSCODER_EDP)
3123 return false;
3124
3125 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3126 return false;
3127
3128 return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3129 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3130 }
3131
3132 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3133 struct intel_crtc_state *crtc_state)
3134 {
3135 if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3136 crtc_state->min_voltage_level = 2;
3137 else if (IS_ICELAKE(dev_priv) && crtc_state->port_clock > 594000)
3138 crtc_state->min_voltage_level = 1;
3139 }
3140
3141 void intel_ddi_get_config(struct intel_encoder *encoder,
3142 struct intel_crtc_state *pipe_config)
3143 {
3144 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3145 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
3146 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3147 struct intel_digital_port *intel_dig_port;
3148 u32 temp, flags = 0;
3149
3150 /* XXX: DSI transcoder paranoia */
3151 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3152 return;
3153
3154 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3155 if (temp & TRANS_DDI_PHSYNC)
3156 flags |= DRM_MODE_FLAG_PHSYNC;
3157 else
3158 flags |= DRM_MODE_FLAG_NHSYNC;
3159 if (temp & TRANS_DDI_PVSYNC)
3160 flags |= DRM_MODE_FLAG_PVSYNC;
3161 else
3162 flags |= DRM_MODE_FLAG_NVSYNC;
3163
3164 pipe_config->base.adjusted_mode.flags |= flags;
3165
3166 switch (temp & TRANS_DDI_BPC_MASK) {
3167 case TRANS_DDI_BPC_6:
3168 pipe_config->pipe_bpp = 18;
3169 break;
3170 case TRANS_DDI_BPC_8:
3171 pipe_config->pipe_bpp = 24;
3172 break;
3173 case TRANS_DDI_BPC_10:
3174 pipe_config->pipe_bpp = 30;
3175 break;
3176 case TRANS_DDI_BPC_12:
3177 pipe_config->pipe_bpp = 36;
3178 break;
3179 default:
3180 break;
3181 }
3182
3183 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3184 case TRANS_DDI_MODE_SELECT_HDMI:
3185 pipe_config->has_hdmi_sink = true;
3186 intel_dig_port = enc_to_dig_port(&encoder->base);
3187
3188 if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
3189 pipe_config->has_infoframe = true;
3190
3191 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
3192 TRANS_DDI_HDMI_SCRAMBLING_MASK)
3193 pipe_config->hdmi_scrambling = true;
3194 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3195 pipe_config->hdmi_high_tmds_clock_ratio = true;
3196 /* fall through */
3197 case TRANS_DDI_MODE_SELECT_DVI:
3198 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3199 pipe_config->lane_count = 4;
3200 break;
3201 case TRANS_DDI_MODE_SELECT_FDI:
3202 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3203 break;
3204 case TRANS_DDI_MODE_SELECT_DP_SST:
3205 if (encoder->type == INTEL_OUTPUT_EDP)
3206 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3207 else
3208 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3209 pipe_config->lane_count =
3210 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3211 intel_dp_get_m_n(intel_crtc, pipe_config);
3212 break;
3213 case TRANS_DDI_MODE_SELECT_DP_MST:
3214 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3215 pipe_config->lane_count =
3216 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3217 intel_dp_get_m_n(intel_crtc, pipe_config);
3218 break;
3219 default:
3220 break;
3221 }
3222
3223 pipe_config->has_audio =
3224 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3225
3226 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3227 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3228 /*
3229 * This is a big fat ugly hack.
3230 *
3231 * Some machines in UEFI boot mode provide us a VBT that has 18
3232 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3233 * unknown we fail to light up. Yet the same BIOS boots up with
3234 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3235 * max, not what it tells us to use.
3236 *
3237 * Note: This will still be broken if the eDP panel is not lit
3238 * up by the BIOS, and thus we can't get the mode at module
3239 * load.
3240 */
3241 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3242 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3243 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3244 }
3245
3246 intel_ddi_clock_get(encoder, pipe_config);
3247
3248 if (IS_GEN9_LP(dev_priv))
3249 pipe_config->lane_lat_optim_mask =
3250 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3251
3252 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3253 }
3254
3255 static enum intel_output_type
3256 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3257 struct intel_crtc_state *crtc_state,
3258 struct drm_connector_state *conn_state)
3259 {
3260 switch (conn_state->connector->connector_type) {
3261 case DRM_MODE_CONNECTOR_HDMIA:
3262 return INTEL_OUTPUT_HDMI;
3263 case DRM_MODE_CONNECTOR_eDP:
3264 return INTEL_OUTPUT_EDP;
3265 case DRM_MODE_CONNECTOR_DisplayPort:
3266 return INTEL_OUTPUT_DP;
3267 default:
3268 MISSING_CASE(conn_state->connector->connector_type);
3269 return INTEL_OUTPUT_UNUSED;
3270 }
3271 }
3272
3273 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
3274 struct intel_crtc_state *pipe_config,
3275 struct drm_connector_state *conn_state)
3276 {
3277 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3278 enum port port = encoder->port;
3279 int ret;
3280
3281 if (port == PORT_A)
3282 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3283
3284 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
3285 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3286 else
3287 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3288
3289 if (IS_GEN9_LP(dev_priv) && ret)
3290 pipe_config->lane_lat_optim_mask =
3291 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3292
3293 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3294
3295 return ret;
3296
3297 }
3298
3299 static const struct drm_encoder_funcs intel_ddi_funcs = {
3300 .reset = intel_dp_encoder_reset,
3301 .destroy = intel_dp_encoder_destroy,
3302 };
3303
3304 static struct intel_connector *
3305 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3306 {
3307 struct intel_connector *connector;
3308 enum port port = intel_dig_port->base.port;
3309
3310 connector = intel_connector_alloc();
3311 if (!connector)
3312 return NULL;
3313
3314 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3315 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3316 kfree(connector);
3317 return NULL;
3318 }
3319
3320 return connector;
3321 }
3322
3323 static int modeset_pipe(struct drm_crtc *crtc,
3324 struct drm_modeset_acquire_ctx *ctx)
3325 {
3326 struct drm_atomic_state *state;
3327 struct drm_crtc_state *crtc_state;
3328 int ret;
3329
3330 state = drm_atomic_state_alloc(crtc->dev);
3331 if (!state)
3332 return -ENOMEM;
3333
3334 state->acquire_ctx = ctx;
3335
3336 crtc_state = drm_atomic_get_crtc_state(state, crtc);
3337 if (IS_ERR(crtc_state)) {
3338 ret = PTR_ERR(crtc_state);
3339 goto out;
3340 }
3341
3342 crtc_state->mode_changed = true;
3343
3344 ret = drm_atomic_add_affected_connectors(state, crtc);
3345 if (ret)
3346 goto out;
3347
3348 ret = drm_atomic_add_affected_planes(state, crtc);
3349 if (ret)
3350 goto out;
3351
3352 ret = drm_atomic_commit(state);
3353 if (ret)
3354 goto out;
3355
3356 return 0;
3357
3358 out:
3359 drm_atomic_state_put(state);
3360
3361 return ret;
3362 }
3363
3364 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3365 struct drm_modeset_acquire_ctx *ctx)
3366 {
3367 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3368 struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
3369 struct intel_connector *connector = hdmi->attached_connector;
3370 struct i2c_adapter *adapter =
3371 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
3372 struct drm_connector_state *conn_state;
3373 struct intel_crtc_state *crtc_state;
3374 struct intel_crtc *crtc;
3375 u8 config;
3376 int ret;
3377
3378 if (!connector || connector->base.status != connector_status_connected)
3379 return 0;
3380
3381 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3382 ctx);
3383 if (ret)
3384 return ret;
3385
3386 conn_state = connector->base.state;
3387
3388 crtc = to_intel_crtc(conn_state->crtc);
3389 if (!crtc)
3390 return 0;
3391
3392 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3393 if (ret)
3394 return ret;
3395
3396 crtc_state = to_intel_crtc_state(crtc->base.state);
3397
3398 WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
3399
3400 if (!crtc_state->base.active)
3401 return 0;
3402
3403 if (!crtc_state->hdmi_high_tmds_clock_ratio &&
3404 !crtc_state->hdmi_scrambling)
3405 return 0;
3406
3407 if (conn_state->commit &&
3408 !try_wait_for_completion(&conn_state->commit->hw_done))
3409 return 0;
3410
3411 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
3412 if (ret < 0) {
3413 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
3414 return 0;
3415 }
3416
3417 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
3418 crtc_state->hdmi_high_tmds_clock_ratio &&
3419 !!(config & SCDC_SCRAMBLING_ENABLE) ==
3420 crtc_state->hdmi_scrambling)
3421 return 0;
3422
3423 /*
3424 * HDMI 2.0 says that one should not send scrambled data
3425 * prior to configuring the sink scrambling, and that
3426 * TMDS clock/data transmission should be suspended when
3427 * changing the TMDS clock rate in the sink. So let's
3428 * just do a full modeset here, even though some sinks
3429 * would be perfectly happy if were to just reconfigure
3430 * the SCDC settings on the fly.
3431 */
3432 return modeset_pipe(&crtc->base, ctx);
3433 }
3434
3435 static bool intel_ddi_hotplug(struct intel_encoder *encoder,
3436 struct intel_connector *connector)
3437 {
3438 struct drm_modeset_acquire_ctx ctx;
3439 bool changed;
3440 int ret;
3441
3442 changed = intel_encoder_hotplug(encoder, connector);
3443
3444 drm_modeset_acquire_init(&ctx, 0);
3445
3446 for (;;) {
3447 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
3448 ret = intel_hdmi_reset_link(encoder, &ctx);
3449 else
3450 ret = intel_dp_retrain_link(encoder, &ctx);
3451
3452 if (ret == -EDEADLK) {
3453 drm_modeset_backoff(&ctx);
3454 continue;
3455 }
3456
3457 break;
3458 }
3459
3460 drm_modeset_drop_locks(&ctx);
3461 drm_modeset_acquire_fini(&ctx);
3462 WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
3463
3464 return changed;
3465 }
3466
3467 static struct intel_connector *
3468 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3469 {
3470 struct intel_connector *connector;
3471 enum port port = intel_dig_port->base.port;
3472
3473 connector = intel_connector_alloc();
3474 if (!connector)
3475 return NULL;
3476
3477 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3478 intel_hdmi_init_connector(intel_dig_port, connector);
3479
3480 return connector;
3481 }
3482
3483 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
3484 {
3485 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
3486
3487 if (dport->base.port != PORT_A)
3488 return false;
3489
3490 if (dport->saved_port_bits & DDI_A_4_LANES)
3491 return false;
3492
3493 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
3494 * supported configuration
3495 */
3496 if (IS_GEN9_LP(dev_priv))
3497 return true;
3498
3499 /* Cannonlake: Most of SKUs don't support DDI_E, and the only
3500 * one who does also have a full A/E split called
3501 * DDI_F what makes DDI_E useless. However for this
3502 * case let's trust VBT info.
3503 */
3504 if (IS_CANNONLAKE(dev_priv) &&
3505 !intel_bios_is_port_present(dev_priv, PORT_E))
3506 return true;
3507
3508 return false;
3509 }
3510
3511 static int
3512 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
3513 {
3514 struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
3515 enum port port = intel_dport->base.port;
3516 int max_lanes = 4;
3517
3518 if (INTEL_GEN(dev_priv) >= 11)
3519 return max_lanes;
3520
3521 if (port == PORT_A || port == PORT_E) {
3522 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
3523 max_lanes = port == PORT_A ? 4 : 0;
3524 else
3525 /* Both A and E share 2 lanes */
3526 max_lanes = 2;
3527 }
3528
3529 /*
3530 * Some BIOS might fail to set this bit on port A if eDP
3531 * wasn't lit up at boot. Force this bit set when needed
3532 * so we use the proper lane count for our calculations.
3533 */
3534 if (intel_ddi_a_force_4_lanes(intel_dport)) {
3535 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
3536 intel_dport->saved_port_bits |= DDI_A_4_LANES;
3537 max_lanes = 4;
3538 }
3539
3540 return max_lanes;
3541 }
3542
3543 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
3544 {
3545 struct intel_digital_port *intel_dig_port;
3546 struct intel_encoder *intel_encoder;
3547 struct drm_encoder *encoder;
3548 bool init_hdmi, init_dp, init_lspcon = false;
3549
3550
3551 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3552 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3553 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3554
3555 if (intel_bios_is_lspcon_present(dev_priv, port)) {
3556 /*
3557 * Lspcon device needs to be driven with DP connector
3558 * with special detection sequence. So make sure DP
3559 * is initialized before lspcon.
3560 */
3561 init_dp = true;
3562 init_lspcon = true;
3563 init_hdmi = false;
3564 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
3565 }
3566
3567 if (!init_dp && !init_hdmi) {
3568 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
3569 port_name(port));
3570 return;
3571 }
3572
3573 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3574 if (!intel_dig_port)
3575 return;
3576
3577 intel_encoder = &intel_dig_port->base;
3578 encoder = &intel_encoder->base;
3579
3580 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
3581 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
3582
3583 intel_encoder->hotplug = intel_ddi_hotplug;
3584 intel_encoder->compute_output_type = intel_ddi_compute_output_type;
3585 intel_encoder->compute_config = intel_ddi_compute_config;
3586 intel_encoder->enable = intel_enable_ddi;
3587 if (IS_GEN9_LP(dev_priv))
3588 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
3589 intel_encoder->pre_enable = intel_ddi_pre_enable;
3590 intel_encoder->disable = intel_disable_ddi;
3591 intel_encoder->post_disable = intel_ddi_post_disable;
3592 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
3593 intel_encoder->get_config = intel_ddi_get_config;
3594 intel_encoder->suspend = intel_dp_encoder_suspend;
3595 intel_encoder->get_power_domains = intel_ddi_get_power_domains;
3596 intel_encoder->type = INTEL_OUTPUT_DDI;
3597 intel_encoder->power_domain = intel_port_to_power_domain(port);
3598 intel_encoder->port = port;
3599 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3600 intel_encoder->cloneable = 0;
3601
3602 if (INTEL_GEN(dev_priv) >= 11)
3603 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3604 DDI_BUF_PORT_REVERSAL;
3605 else
3606 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3607 (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
3608 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
3609 intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
3610
3611 switch (port) {
3612 case PORT_A:
3613 intel_dig_port->ddi_io_power_domain =
3614 POWER_DOMAIN_PORT_DDI_A_IO;
3615 break;
3616 case PORT_B:
3617 intel_dig_port->ddi_io_power_domain =
3618 POWER_DOMAIN_PORT_DDI_B_IO;
3619 break;
3620 case PORT_C:
3621 intel_dig_port->ddi_io_power_domain =
3622 POWER_DOMAIN_PORT_DDI_C_IO;
3623 break;
3624 case PORT_D:
3625 intel_dig_port->ddi_io_power_domain =
3626 POWER_DOMAIN_PORT_DDI_D_IO;
3627 break;
3628 case PORT_E:
3629 intel_dig_port->ddi_io_power_domain =
3630 POWER_DOMAIN_PORT_DDI_E_IO;
3631 break;
3632 case PORT_F:
3633 intel_dig_port->ddi_io_power_domain =
3634 POWER_DOMAIN_PORT_DDI_F_IO;
3635 break;
3636 default:
3637 MISSING_CASE(port);
3638 }
3639
3640 intel_infoframe_init(intel_dig_port);
3641
3642 if (init_dp) {
3643 if (!intel_ddi_init_dp_connector(intel_dig_port))
3644 goto err;
3645
3646 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
3647 }
3648
3649 /* In theory we don't need the encoder->type check, but leave it just in
3650 * case we have some really bad VBTs... */
3651 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3652 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3653 goto err;
3654 }
3655
3656 if (init_lspcon) {
3657 if (lspcon_init(intel_dig_port))
3658 /* TODO: handle hdmi info frame part */
3659 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
3660 port_name(port));
3661 else
3662 /*
3663 * LSPCON init faied, but DP init was success, so
3664 * lets try to drive as DP++ port.
3665 */
3666 DRM_ERROR("LSPCON init failed on port %c\n",
3667 port_name(port));
3668 }
3669
3670 return;
3671
3672 err:
3673 drm_encoder_cleanup(encoder);
3674 kfree(intel_dig_port);
3675 }
Linux with added FPC-III support