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vt: vt_ioctl: fix VT_DISALLOCATE freeing in-use virtual console
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / intel_display.c
blob6902fd2da19ca43eb8337774d79f732a24723716
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
51
52 /* Primary plane formats for gen <= 3 */
53 static const uint32_t i8xx_primary_formats[] = {
54 DRM_FORMAT_C8,
55 DRM_FORMAT_RGB565,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_XRGB8888,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t i965_primary_formats[] = {
62 DRM_FORMAT_C8,
63 DRM_FORMAT_RGB565,
64 DRM_FORMAT_XRGB8888,
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 };
69
70 static const uint64_t i9xx_format_modifiers[] = {
71 I915_FORMAT_MOD_X_TILED,
72 DRM_FORMAT_MOD_LINEAR,
73 DRM_FORMAT_MOD_INVALID
74 };
75
76 static const uint32_t skl_primary_formats[] = {
77 DRM_FORMAT_C8,
78 DRM_FORMAT_RGB565,
79 DRM_FORMAT_XRGB8888,
80 DRM_FORMAT_XBGR8888,
81 DRM_FORMAT_ARGB8888,
82 DRM_FORMAT_ABGR8888,
83 DRM_FORMAT_XRGB2101010,
84 DRM_FORMAT_XBGR2101010,
85 DRM_FORMAT_YUYV,
86 DRM_FORMAT_YVYU,
87 DRM_FORMAT_UYVY,
88 DRM_FORMAT_VYUY,
89 };
90
91 static const uint32_t skl_pri_planar_formats[] = {
92 DRM_FORMAT_C8,
93 DRM_FORMAT_RGB565,
94 DRM_FORMAT_XRGB8888,
95 DRM_FORMAT_XBGR8888,
96 DRM_FORMAT_ARGB8888,
97 DRM_FORMAT_ABGR8888,
98 DRM_FORMAT_XRGB2101010,
99 DRM_FORMAT_XBGR2101010,
100 DRM_FORMAT_YUYV,
101 DRM_FORMAT_YVYU,
102 DRM_FORMAT_UYVY,
103 DRM_FORMAT_VYUY,
104 DRM_FORMAT_NV12,
105 };
106
107 static const uint64_t skl_format_modifiers_noccs[] = {
108 I915_FORMAT_MOD_Yf_TILED,
109 I915_FORMAT_MOD_Y_TILED,
110 I915_FORMAT_MOD_X_TILED,
111 DRM_FORMAT_MOD_LINEAR,
112 DRM_FORMAT_MOD_INVALID
113 };
114
115 static const uint64_t skl_format_modifiers_ccs[] = {
116 I915_FORMAT_MOD_Yf_TILED_CCS,
117 I915_FORMAT_MOD_Y_TILED_CCS,
118 I915_FORMAT_MOD_Yf_TILED,
119 I915_FORMAT_MOD_Y_TILED,
120 I915_FORMAT_MOD_X_TILED,
121 DRM_FORMAT_MOD_LINEAR,
122 DRM_FORMAT_MOD_INVALID
123 };
124
125 /* Cursor formats */
126 static const uint32_t intel_cursor_formats[] = {
127 DRM_FORMAT_ARGB8888,
128 };
129
130 static const uint64_t cursor_format_modifiers[] = {
131 DRM_FORMAT_MOD_LINEAR,
132 DRM_FORMAT_MOD_INVALID
133 };
134
135 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
136 struct intel_crtc_state *pipe_config);
137 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
138 struct intel_crtc_state *pipe_config);
139
140 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
141 struct drm_i915_gem_object *obj,
142 struct drm_mode_fb_cmd2 *mode_cmd);
143 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
144 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
145 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
146 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
147 struct intel_link_m_n *m_n,
148 struct intel_link_m_n *m2_n2);
149 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
150 static void haswell_set_pipeconf(struct drm_crtc *crtc);
151 static void haswell_set_pipemisc(struct drm_crtc *crtc);
152 static void vlv_prepare_pll(struct intel_crtc *crtc,
153 const struct intel_crtc_state *pipe_config);
154 static void chv_prepare_pll(struct intel_crtc *crtc,
155 const struct intel_crtc_state *pipe_config);
156 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
157 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
158 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
159 struct intel_crtc_state *crtc_state);
160 static void skylake_pfit_enable(struct intel_crtc *crtc);
161 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
162 static void ironlake_pfit_enable(struct intel_crtc *crtc);
163 static void intel_modeset_setup_hw_state(struct drm_device *dev,
164 struct drm_modeset_acquire_ctx *ctx);
165 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
166
167 struct intel_limit {
168 struct {
169 int min, max;
170 } dot, vco, n, m, m1, m2, p, p1;
171
172 struct {
173 int dot_limit;
174 int p2_slow, p2_fast;
175 } p2;
176 };
177
178 /* returns HPLL frequency in kHz */
179 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
180 {
181 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
182
183 /* Obtain SKU information */
184 mutex_lock(&dev_priv->sb_lock);
185 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
186 CCK_FUSE_HPLL_FREQ_MASK;
187 mutex_unlock(&dev_priv->sb_lock);
188
189 return vco_freq[hpll_freq] * 1000;
190 }
191
192 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
193 const char *name, u32 reg, int ref_freq)
194 {
195 u32 val;
196 int divider;
197
198 mutex_lock(&dev_priv->sb_lock);
199 val = vlv_cck_read(dev_priv, reg);
200 mutex_unlock(&dev_priv->sb_lock);
201
202 divider = val & CCK_FREQUENCY_VALUES;
203
204 WARN((val & CCK_FREQUENCY_STATUS) !=
205 (divider << CCK_FREQUENCY_STATUS_SHIFT),
206 "%s change in progress\n", name);
207
208 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
209 }
210
211 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
212 const char *name, u32 reg)
213 {
214 if (dev_priv->hpll_freq == 0)
215 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
216
217 return vlv_get_cck_clock(dev_priv, name, reg,
218 dev_priv->hpll_freq);
219 }
220
221 static void intel_update_czclk(struct drm_i915_private *dev_priv)
222 {
223 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
224 return;
225
226 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
227 CCK_CZ_CLOCK_CONTROL);
228
229 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
230 }
231
232 static inline u32 /* units of 100MHz */
233 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
234 const struct intel_crtc_state *pipe_config)
235 {
236 if (HAS_DDI(dev_priv))
237 return pipe_config->port_clock; /* SPLL */
238 else
239 return dev_priv->fdi_pll_freq;
240 }
241
242 static const struct intel_limit intel_limits_i8xx_dac = {
243 .dot = { .min = 25000, .max = 350000 },
244 .vco = { .min = 908000, .max = 1512000 },
245 .n = { .min = 2, .max = 16 },
246 .m = { .min = 96, .max = 140 },
247 .m1 = { .min = 18, .max = 26 },
248 .m2 = { .min = 6, .max = 16 },
249 .p = { .min = 4, .max = 128 },
250 .p1 = { .min = 2, .max = 33 },
251 .p2 = { .dot_limit = 165000,
252 .p2_slow = 4, .p2_fast = 2 },
253 };
254
255 static const struct intel_limit intel_limits_i8xx_dvo = {
256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 908000, .max = 1512000 },
258 .n = { .min = 2, .max = 16 },
259 .m = { .min = 96, .max = 140 },
260 .m1 = { .min = 18, .max = 26 },
261 .m2 = { .min = 6, .max = 16 },
262 .p = { .min = 4, .max = 128 },
263 .p1 = { .min = 2, .max = 33 },
264 .p2 = { .dot_limit = 165000,
265 .p2_slow = 4, .p2_fast = 4 },
266 };
267
268 static const struct intel_limit intel_limits_i8xx_lvds = {
269 .dot = { .min = 25000, .max = 350000 },
270 .vco = { .min = 908000, .max = 1512000 },
271 .n = { .min = 2, .max = 16 },
272 .m = { .min = 96, .max = 140 },
273 .m1 = { .min = 18, .max = 26 },
274 .m2 = { .min = 6, .max = 16 },
275 .p = { .min = 4, .max = 128 },
276 .p1 = { .min = 1, .max = 6 },
277 .p2 = { .dot_limit = 165000,
278 .p2_slow = 14, .p2_fast = 7 },
279 };
280
281 static const struct intel_limit intel_limits_i9xx_sdvo = {
282 .dot = { .min = 20000, .max = 400000 },
283 .vco = { .min = 1400000, .max = 2800000 },
284 .n = { .min = 1, .max = 6 },
285 .m = { .min = 70, .max = 120 },
286 .m1 = { .min = 8, .max = 18 },
287 .m2 = { .min = 3, .max = 7 },
288 .p = { .min = 5, .max = 80 },
289 .p1 = { .min = 1, .max = 8 },
290 .p2 = { .dot_limit = 200000,
291 .p2_slow = 10, .p2_fast = 5 },
292 };
293
294 static const struct intel_limit intel_limits_i9xx_lvds = {
295 .dot = { .min = 20000, .max = 400000 },
296 .vco = { .min = 1400000, .max = 2800000 },
297 .n = { .min = 1, .max = 6 },
298 .m = { .min = 70, .max = 120 },
299 .m1 = { .min = 8, .max = 18 },
300 .m2 = { .min = 3, .max = 7 },
301 .p = { .min = 7, .max = 98 },
302 .p1 = { .min = 1, .max = 8 },
303 .p2 = { .dot_limit = 112000,
304 .p2_slow = 14, .p2_fast = 7 },
305 };
306
307
308 static const struct intel_limit intel_limits_g4x_sdvo = {
309 .dot = { .min = 25000, .max = 270000 },
310 .vco = { .min = 1750000, .max = 3500000},
311 .n = { .min = 1, .max = 4 },
312 .m = { .min = 104, .max = 138 },
313 .m1 = { .min = 17, .max = 23 },
314 .m2 = { .min = 5, .max = 11 },
315 .p = { .min = 10, .max = 30 },
316 .p1 = { .min = 1, .max = 3},
317 .p2 = { .dot_limit = 270000,
318 .p2_slow = 10,
319 .p2_fast = 10
320 },
321 };
322
323 static const struct intel_limit intel_limits_g4x_hdmi = {
324 .dot = { .min = 22000, .max = 400000 },
325 .vco = { .min = 1750000, .max = 3500000},
326 .n = { .min = 1, .max = 4 },
327 .m = { .min = 104, .max = 138 },
328 .m1 = { .min = 16, .max = 23 },
329 .m2 = { .min = 5, .max = 11 },
330 .p = { .min = 5, .max = 80 },
331 .p1 = { .min = 1, .max = 8},
332 .p2 = { .dot_limit = 165000,
333 .p2_slow = 10, .p2_fast = 5 },
334 };
335
336 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
337 .dot = { .min = 20000, .max = 115000 },
338 .vco = { .min = 1750000, .max = 3500000 },
339 .n = { .min = 1, .max = 3 },
340 .m = { .min = 104, .max = 138 },
341 .m1 = { .min = 17, .max = 23 },
342 .m2 = { .min = 5, .max = 11 },
343 .p = { .min = 28, .max = 112 },
344 .p1 = { .min = 2, .max = 8 },
345 .p2 = { .dot_limit = 0,
346 .p2_slow = 14, .p2_fast = 14
347 },
348 };
349
350 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
351 .dot = { .min = 80000, .max = 224000 },
352 .vco = { .min = 1750000, .max = 3500000 },
353 .n = { .min = 1, .max = 3 },
354 .m = { .min = 104, .max = 138 },
355 .m1 = { .min = 17, .max = 23 },
356 .m2 = { .min = 5, .max = 11 },
357 .p = { .min = 14, .max = 42 },
358 .p1 = { .min = 2, .max = 6 },
359 .p2 = { .dot_limit = 0,
360 .p2_slow = 7, .p2_fast = 7
361 },
362 };
363
364 static const struct intel_limit intel_limits_pineview_sdvo = {
365 .dot = { .min = 20000, .max = 400000},
366 .vco = { .min = 1700000, .max = 3500000 },
367 /* Pineview's Ncounter is a ring counter */
368 .n = { .min = 3, .max = 6 },
369 .m = { .min = 2, .max = 256 },
370 /* Pineview only has one combined m divider, which we treat as m2. */
371 .m1 = { .min = 0, .max = 0 },
372 .m2 = { .min = 0, .max = 254 },
373 .p = { .min = 5, .max = 80 },
374 .p1 = { .min = 1, .max = 8 },
375 .p2 = { .dot_limit = 200000,
376 .p2_slow = 10, .p2_fast = 5 },
377 };
378
379 static const struct intel_limit intel_limits_pineview_lvds = {
380 .dot = { .min = 20000, .max = 400000 },
381 .vco = { .min = 1700000, .max = 3500000 },
382 .n = { .min = 3, .max = 6 },
383 .m = { .min = 2, .max = 256 },
384 .m1 = { .min = 0, .max = 0 },
385 .m2 = { .min = 0, .max = 254 },
386 .p = { .min = 7, .max = 112 },
387 .p1 = { .min = 1, .max = 8 },
388 .p2 = { .dot_limit = 112000,
389 .p2_slow = 14, .p2_fast = 14 },
390 };
391
392 /* Ironlake / Sandybridge
393 *
394 * We calculate clock using (register_value + 2) for N/M1/M2, so here
395 * the range value for them is (actual_value - 2).
396 */
397 static const struct intel_limit intel_limits_ironlake_dac = {
398 .dot = { .min = 25000, .max = 350000 },
399 .vco = { .min = 1760000, .max = 3510000 },
400 .n = { .min = 1, .max = 5 },
401 .m = { .min = 79, .max = 127 },
402 .m1 = { .min = 12, .max = 22 },
403 .m2 = { .min = 5, .max = 9 },
404 .p = { .min = 5, .max = 80 },
405 .p1 = { .min = 1, .max = 8 },
406 .p2 = { .dot_limit = 225000,
407 .p2_slow = 10, .p2_fast = 5 },
408 };
409
410 static const struct intel_limit intel_limits_ironlake_single_lvds = {
411 .dot = { .min = 25000, .max = 350000 },
412 .vco = { .min = 1760000, .max = 3510000 },
413 .n = { .min = 1, .max = 3 },
414 .m = { .min = 79, .max = 118 },
415 .m1 = { .min = 12, .max = 22 },
416 .m2 = { .min = 5, .max = 9 },
417 .p = { .min = 28, .max = 112 },
418 .p1 = { .min = 2, .max = 8 },
419 .p2 = { .dot_limit = 225000,
420 .p2_slow = 14, .p2_fast = 14 },
421 };
422
423 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
424 .dot = { .min = 25000, .max = 350000 },
425 .vco = { .min = 1760000, .max = 3510000 },
426 .n = { .min = 1, .max = 3 },
427 .m = { .min = 79, .max = 127 },
428 .m1 = { .min = 12, .max = 22 },
429 .m2 = { .min = 5, .max = 9 },
430 .p = { .min = 14, .max = 56 },
431 .p1 = { .min = 2, .max = 8 },
432 .p2 = { .dot_limit = 225000,
433 .p2_slow = 7, .p2_fast = 7 },
434 };
435
436 /* LVDS 100mhz refclk limits. */
437 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
438 .dot = { .min = 25000, .max = 350000 },
439 .vco = { .min = 1760000, .max = 3510000 },
440 .n = { .min = 1, .max = 2 },
441 .m = { .min = 79, .max = 126 },
442 .m1 = { .min = 12, .max = 22 },
443 .m2 = { .min = 5, .max = 9 },
444 .p = { .min = 28, .max = 112 },
445 .p1 = { .min = 2, .max = 8 },
446 .p2 = { .dot_limit = 225000,
447 .p2_slow = 14, .p2_fast = 14 },
448 };
449
450 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
451 .dot = { .min = 25000, .max = 350000 },
452 .vco = { .min = 1760000, .max = 3510000 },
453 .n = { .min = 1, .max = 3 },
454 .m = { .min = 79, .max = 126 },
455 .m1 = { .min = 12, .max = 22 },
456 .m2 = { .min = 5, .max = 9 },
457 .p = { .min = 14, .max = 42 },
458 .p1 = { .min = 2, .max = 6 },
459 .p2 = { .dot_limit = 225000,
460 .p2_slow = 7, .p2_fast = 7 },
461 };
462
463 static const struct intel_limit intel_limits_vlv = {
464 /*
465 * These are the data rate limits (measured in fast clocks)
466 * since those are the strictest limits we have. The fast
467 * clock and actual rate limits are more relaxed, so checking
468 * them would make no difference.
469 */
470 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
471 .vco = { .min = 4000000, .max = 6000000 },
472 .n = { .min = 1, .max = 7 },
473 .m1 = { .min = 2, .max = 3 },
474 .m2 = { .min = 11, .max = 156 },
475 .p1 = { .min = 2, .max = 3 },
476 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
477 };
478
479 static const struct intel_limit intel_limits_chv = {
480 /*
481 * These are the data rate limits (measured in fast clocks)
482 * since those are the strictest limits we have. The fast
483 * clock and actual rate limits are more relaxed, so checking
484 * them would make no difference.
485 */
486 .dot = { .min = 25000 * 5, .max = 540000 * 5},
487 .vco = { .min = 4800000, .max = 6480000 },
488 .n = { .min = 1, .max = 1 },
489 .m1 = { .min = 2, .max = 2 },
490 .m2 = { .min = 24 << 22, .max = 175 << 22 },
491 .p1 = { .min = 2, .max = 4 },
492 .p2 = { .p2_slow = 1, .p2_fast = 14 },
493 };
494
495 static const struct intel_limit intel_limits_bxt = {
496 /* FIXME: find real dot limits */
497 .dot = { .min = 0, .max = INT_MAX },
498 .vco = { .min = 4800000, .max = 6700000 },
499 .n = { .min = 1, .max = 1 },
500 .m1 = { .min = 2, .max = 2 },
501 /* FIXME: find real m2 limits */
502 .m2 = { .min = 2 << 22, .max = 255 << 22 },
503 .p1 = { .min = 2, .max = 4 },
504 .p2 = { .p2_slow = 1, .p2_fast = 20 },
505 };
506
507 static void
508 skl_wa_528(struct drm_i915_private *dev_priv, int pipe, bool enable)
509 {
510 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
511 return;
512
513 if (enable)
514 I915_WRITE(CHICKEN_PIPESL_1(pipe), HSW_FBCQ_DIS);
515 else
516 I915_WRITE(CHICKEN_PIPESL_1(pipe), 0);
517 }
518
519 static void
520 skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)
521 {
522 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
523 return;
524
525 if (enable)
526 I915_WRITE(CLKGATE_DIS_PSL(pipe),
527 DUPS1_GATING_DIS | DUPS2_GATING_DIS);
528 else
529 I915_WRITE(CLKGATE_DIS_PSL(pipe),
530 I915_READ(CLKGATE_DIS_PSL(pipe)) &
531 ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
532 }
533
534 static bool
535 needs_modeset(const struct drm_crtc_state *state)
536 {
537 return drm_atomic_crtc_needs_modeset(state);
538 }
539
540 /*
541 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
542 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
543 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
544 * The helpers' return value is the rate of the clock that is fed to the
545 * display engine's pipe which can be the above fast dot clock rate or a
546 * divided-down version of it.
547 */
548 /* m1 is reserved as 0 in Pineview, n is a ring counter */
549 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
550 {
551 clock->m = clock->m2 + 2;
552 clock->p = clock->p1 * clock->p2;
553 if (WARN_ON(clock->n == 0 || clock->p == 0))
554 return 0;
555 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
556 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
557
558 return clock->dot;
559 }
560
561 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
562 {
563 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
564 }
565
566 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
567 {
568 clock->m = i9xx_dpll_compute_m(clock);
569 clock->p = clock->p1 * clock->p2;
570 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
571 return 0;
572 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
573 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
574
575 return clock->dot;
576 }
577
578 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
579 {
580 clock->m = clock->m1 * clock->m2;
581 clock->p = clock->p1 * clock->p2;
582 if (WARN_ON(clock->n == 0 || clock->p == 0))
583 return 0;
584 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
585 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
586
587 return clock->dot / 5;
588 }
589
590 int chv_calc_dpll_params(int refclk, struct dpll *clock)
591 {
592 clock->m = clock->m1 * clock->m2;
593 clock->p = clock->p1 * clock->p2;
594 if (WARN_ON(clock->n == 0 || clock->p == 0))
595 return 0;
596 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
597 clock->n << 22);
598 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
599
600 return clock->dot / 5;
601 }
602
603 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
604
605 /*
606 * Returns whether the given set of divisors are valid for a given refclk with
607 * the given connectors.
608 */
609 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
610 const struct intel_limit *limit,
611 const struct dpll *clock)
612 {
613 if (clock->n < limit->n.min || limit->n.max < clock->n)
614 INTELPllInvalid("n out of range\n");
615 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
616 INTELPllInvalid("p1 out of range\n");
617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
618 INTELPllInvalid("m2 out of range\n");
619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
620 INTELPllInvalid("m1 out of range\n");
621
622 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
623 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
624 if (clock->m1 <= clock->m2)
625 INTELPllInvalid("m1 <= m2\n");
626
627 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
628 !IS_GEN9_LP(dev_priv)) {
629 if (clock->p < limit->p.min || limit->p.max < clock->p)
630 INTELPllInvalid("p out of range\n");
631 if (clock->m < limit->m.min || limit->m.max < clock->m)
632 INTELPllInvalid("m out of range\n");
633 }
634
635 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
636 INTELPllInvalid("vco out of range\n");
637 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
638 * connector, etc., rather than just a single range.
639 */
640 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
641 INTELPllInvalid("dot out of range\n");
642
643 return true;
644 }
645
646 static int
647 i9xx_select_p2_div(const struct intel_limit *limit,
648 const struct intel_crtc_state *crtc_state,
649 int target)
650 {
651 struct drm_device *dev = crtc_state->base.crtc->dev;
652
653 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
654 /*
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
658 */
659 if (intel_is_dual_link_lvds(dev))
660 return limit->p2.p2_fast;
661 else
662 return limit->p2.p2_slow;
663 } else {
664 if (target < limit->p2.dot_limit)
665 return limit->p2.p2_slow;
666 else
667 return limit->p2.p2_fast;
668 }
669 }
670
671 /*
672 * Returns a set of divisors for the desired target clock with the given
673 * refclk, or FALSE. The returned values represent the clock equation:
674 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
675 *
676 * Target and reference clocks are specified in kHz.
677 *
678 * If match_clock is provided, then best_clock P divider must match the P
679 * divider from @match_clock used for LVDS downclocking.
680 */
681 static bool
682 i9xx_find_best_dpll(const struct intel_limit *limit,
683 struct intel_crtc_state *crtc_state,
684 int target, int refclk, struct dpll *match_clock,
685 struct dpll *best_clock)
686 {
687 struct drm_device *dev = crtc_state->base.crtc->dev;
688 struct dpll clock;
689 int err = target;
690
691 memset(best_clock, 0, sizeof(*best_clock));
692
693 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
694
695 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
696 clock.m1++) {
697 for (clock.m2 = limit->m2.min;
698 clock.m2 <= limit->m2.max; clock.m2++) {
699 if (clock.m2 >= clock.m1)
700 break;
701 for (clock.n = limit->n.min;
702 clock.n <= limit->n.max; clock.n++) {
703 for (clock.p1 = limit->p1.min;
704 clock.p1 <= limit->p1.max; clock.p1++) {
705 int this_err;
706
707 i9xx_calc_dpll_params(refclk, &clock);
708 if (!intel_PLL_is_valid(to_i915(dev),
709 limit,
710 &clock))
711 continue;
712 if (match_clock &&
713 clock.p != match_clock->p)
714 continue;
715
716 this_err = abs(clock.dot - target);
717 if (this_err < err) {
718 *best_clock = clock;
719 err = this_err;
720 }
721 }
722 }
723 }
724 }
725
726 return (err != target);
727 }
728
729 /*
730 * Returns a set of divisors for the desired target clock with the given
731 * refclk, or FALSE. The returned values represent the clock equation:
732 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
733 *
734 * Target and reference clocks are specified in kHz.
735 *
736 * If match_clock is provided, then best_clock P divider must match the P
737 * divider from @match_clock used for LVDS downclocking.
738 */
739 static bool
740 pnv_find_best_dpll(const struct intel_limit *limit,
741 struct intel_crtc_state *crtc_state,
742 int target, int refclk, struct dpll *match_clock,
743 struct dpll *best_clock)
744 {
745 struct drm_device *dev = crtc_state->base.crtc->dev;
746 struct dpll clock;
747 int err = target;
748
749 memset(best_clock, 0, sizeof(*best_clock));
750
751 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
752
753 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
754 clock.m1++) {
755 for (clock.m2 = limit->m2.min;
756 clock.m2 <= limit->m2.max; clock.m2++) {
757 for (clock.n = limit->n.min;
758 clock.n <= limit->n.max; clock.n++) {
759 for (clock.p1 = limit->p1.min;
760 clock.p1 <= limit->p1.max; clock.p1++) {
761 int this_err;
762
763 pnv_calc_dpll_params(refclk, &clock);
764 if (!intel_PLL_is_valid(to_i915(dev),
765 limit,
766 &clock))
767 continue;
768 if (match_clock &&
769 clock.p != match_clock->p)
770 continue;
771
772 this_err = abs(clock.dot - target);
773 if (this_err < err) {
774 *best_clock = clock;
775 err = this_err;
776 }
777 }
778 }
779 }
780 }
781
782 return (err != target);
783 }
784
785 /*
786 * Returns a set of divisors for the desired target clock with the given
787 * refclk, or FALSE. The returned values represent the clock equation:
788 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
789 *
790 * Target and reference clocks are specified in kHz.
791 *
792 * If match_clock is provided, then best_clock P divider must match the P
793 * divider from @match_clock used for LVDS downclocking.
794 */
795 static bool
796 g4x_find_best_dpll(const struct intel_limit *limit,
797 struct intel_crtc_state *crtc_state,
798 int target, int refclk, struct dpll *match_clock,
799 struct dpll *best_clock)
800 {
801 struct drm_device *dev = crtc_state->base.crtc->dev;
802 struct dpll clock;
803 int max_n;
804 bool found = false;
805 /* approximately equals target * 0.00585 */
806 int err_most = (target >> 8) + (target >> 9);
807
808 memset(best_clock, 0, sizeof(*best_clock));
809
810 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
811
812 max_n = limit->n.max;
813 /* based on hardware requirement, prefer smaller n to precision */
814 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
815 /* based on hardware requirement, prefere larger m1,m2 */
816 for (clock.m1 = limit->m1.max;
817 clock.m1 >= limit->m1.min; clock.m1--) {
818 for (clock.m2 = limit->m2.max;
819 clock.m2 >= limit->m2.min; clock.m2--) {
820 for (clock.p1 = limit->p1.max;
821 clock.p1 >= limit->p1.min; clock.p1--) {
822 int this_err;
823
824 i9xx_calc_dpll_params(refclk, &clock);
825 if (!intel_PLL_is_valid(to_i915(dev),
826 limit,
827 &clock))
828 continue;
829
830 this_err = abs(clock.dot - target);
831 if (this_err < err_most) {
832 *best_clock = clock;
833 err_most = this_err;
834 max_n = clock.n;
835 found = true;
836 }
837 }
838 }
839 }
840 }
841 return found;
842 }
843
844 /*
845 * Check if the calculated PLL configuration is more optimal compared to the
846 * best configuration and error found so far. Return the calculated error.
847 */
848 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
849 const struct dpll *calculated_clock,
850 const struct dpll *best_clock,
851 unsigned int best_error_ppm,
852 unsigned int *error_ppm)
853 {
854 /*
855 * For CHV ignore the error and consider only the P value.
856 * Prefer a bigger P value based on HW requirements.
857 */
858 if (IS_CHERRYVIEW(to_i915(dev))) {
859 *error_ppm = 0;
860
861 return calculated_clock->p > best_clock->p;
862 }
863
864 if (WARN_ON_ONCE(!target_freq))
865 return false;
866
867 *error_ppm = div_u64(1000000ULL *
868 abs(target_freq - calculated_clock->dot),
869 target_freq);
870 /*
871 * Prefer a better P value over a better (smaller) error if the error
872 * is small. Ensure this preference for future configurations too by
873 * setting the error to 0.
874 */
875 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
876 *error_ppm = 0;
877
878 return true;
879 }
880
881 return *error_ppm + 10 < best_error_ppm;
882 }
883
884 /*
885 * Returns a set of divisors for the desired target clock with the given
886 * refclk, or FALSE. The returned values represent the clock equation:
887 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
888 */
889 static bool
890 vlv_find_best_dpll(const struct intel_limit *limit,
891 struct intel_crtc_state *crtc_state,
892 int target, int refclk, struct dpll *match_clock,
893 struct dpll *best_clock)
894 {
895 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
896 struct drm_device *dev = crtc->base.dev;
897 struct dpll clock;
898 unsigned int bestppm = 1000000;
899 /* min update 19.2 MHz */
900 int max_n = min(limit->n.max, refclk / 19200);
901 bool found = false;
902
903 target *= 5; /* fast clock */
904
905 memset(best_clock, 0, sizeof(*best_clock));
906
907 /* based on hardware requirement, prefer smaller n to precision */
908 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
909 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
910 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
911 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
912 clock.p = clock.p1 * clock.p2;
913 /* based on hardware requirement, prefer bigger m1,m2 values */
914 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
915 unsigned int ppm;
916
917 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
918 refclk * clock.m1);
919
920 vlv_calc_dpll_params(refclk, &clock);
921
922 if (!intel_PLL_is_valid(to_i915(dev),
923 limit,
924 &clock))
925 continue;
926
927 if (!vlv_PLL_is_optimal(dev, target,
928 &clock,
929 best_clock,
930 bestppm, &ppm))
931 continue;
932
933 *best_clock = clock;
934 bestppm = ppm;
935 found = true;
936 }
937 }
938 }
939 }
940
941 return found;
942 }
943
944 /*
945 * Returns a set of divisors for the desired target clock with the given
946 * refclk, or FALSE. The returned values represent the clock equation:
947 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
948 */
949 static bool
950 chv_find_best_dpll(const struct intel_limit *limit,
951 struct intel_crtc_state *crtc_state,
952 int target, int refclk, struct dpll *match_clock,
953 struct dpll *best_clock)
954 {
955 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
956 struct drm_device *dev = crtc->base.dev;
957 unsigned int best_error_ppm;
958 struct dpll clock;
959 uint64_t m2;
960 int found = false;
961
962 memset(best_clock, 0, sizeof(*best_clock));
963 best_error_ppm = 1000000;
964
965 /*
966 * Based on hardware doc, the n always set to 1, and m1 always
967 * set to 2. If requires to support 200Mhz refclk, we need to
968 * revisit this because n may not 1 anymore.
969 */
970 clock.n = 1, clock.m1 = 2;
971 target *= 5; /* fast clock */
972
973 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
974 for (clock.p2 = limit->p2.p2_fast;
975 clock.p2 >= limit->p2.p2_slow;
976 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
977 unsigned int error_ppm;
978
979 clock.p = clock.p1 * clock.p2;
980
981 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
982 clock.n) << 22, refclk * clock.m1);
983
984 if (m2 > INT_MAX/clock.m1)
985 continue;
986
987 clock.m2 = m2;
988
989 chv_calc_dpll_params(refclk, &clock);
990
991 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
992 continue;
993
994 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
995 best_error_ppm, &error_ppm))
996 continue;
997
998 *best_clock = clock;
999 best_error_ppm = error_ppm;
1000 found = true;
1001 }
1002 }
1003
1004 return found;
1005 }
1006
1007 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1008 struct dpll *best_clock)
1009 {
1010 int refclk = 100000;
1011 const struct intel_limit *limit = &intel_limits_bxt;
1012
1013 return chv_find_best_dpll(limit, crtc_state,
1014 target_clock, refclk, NULL, best_clock);
1015 }
1016
1017 bool intel_crtc_active(struct intel_crtc *crtc)
1018 {
1019 /* Be paranoid as we can arrive here with only partial
1020 * state retrieved from the hardware during setup.
1021 *
1022 * We can ditch the adjusted_mode.crtc_clock check as soon
1023 * as Haswell has gained clock readout/fastboot support.
1024 *
1025 * We can ditch the crtc->primary->state->fb check as soon as we can
1026 * properly reconstruct framebuffers.
1027 *
1028 * FIXME: The intel_crtc->active here should be switched to
1029 * crtc->state->active once we have proper CRTC states wired up
1030 * for atomic.
1031 */
1032 return crtc->active && crtc->base.primary->state->fb &&
1033 crtc->config->base.adjusted_mode.crtc_clock;
1034 }
1035
1036 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1037 enum pipe pipe)
1038 {
1039 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1040
1041 return crtc->config->cpu_transcoder;
1042 }
1043
1044 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1045 enum pipe pipe)
1046 {
1047 i915_reg_t reg = PIPEDSL(pipe);
1048 u32 line1, line2;
1049 u32 line_mask;
1050
1051 if (IS_GEN2(dev_priv))
1052 line_mask = DSL_LINEMASK_GEN2;
1053 else
1054 line_mask = DSL_LINEMASK_GEN3;
1055
1056 line1 = I915_READ(reg) & line_mask;
1057 msleep(5);
1058 line2 = I915_READ(reg) & line_mask;
1059
1060 return line1 != line2;
1061 }
1062
1063 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1064 {
1065 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1066 enum pipe pipe = crtc->pipe;
1067
1068 /* Wait for the display line to settle/start moving */
1069 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1070 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1071 pipe_name(pipe), onoff(state));
1072 }
1073
1074 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1075 {
1076 wait_for_pipe_scanline_moving(crtc, false);
1077 }
1078
1079 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1080 {
1081 wait_for_pipe_scanline_moving(crtc, true);
1082 }
1083
1084 static void
1085 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1086 {
1087 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1088 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1089
1090 if (INTEL_GEN(dev_priv) >= 4) {
1091 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1092 i915_reg_t reg = PIPECONF(cpu_transcoder);
1093
1094 /* Wait for the Pipe State to go off */
1095 if (intel_wait_for_register(dev_priv,
1096 reg, I965_PIPECONF_ACTIVE, 0,
1097 100))
1098 WARN(1, "pipe_off wait timed out\n");
1099 } else {
1100 intel_wait_for_pipe_scanline_stopped(crtc);
1101 }
1102 }
1103
1104 /* Only for pre-ILK configs */
1105 void assert_pll(struct drm_i915_private *dev_priv,
1106 enum pipe pipe, bool state)
1107 {
1108 u32 val;
1109 bool cur_state;
1110
1111 val = I915_READ(DPLL(pipe));
1112 cur_state = !!(val & DPLL_VCO_ENABLE);
1113 I915_STATE_WARN(cur_state != state,
1114 "PLL state assertion failure (expected %s, current %s)\n",
1115 onoff(state), onoff(cur_state));
1116 }
1117
1118 /* XXX: the dsi pll is shared between MIPI DSI ports */
1119 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1120 {
1121 u32 val;
1122 bool cur_state;
1123
1124 mutex_lock(&dev_priv->sb_lock);
1125 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1126 mutex_unlock(&dev_priv->sb_lock);
1127
1128 cur_state = val & DSI_PLL_VCO_EN;
1129 I915_STATE_WARN(cur_state != state,
1130 "DSI PLL state assertion failure (expected %s, current %s)\n",
1131 onoff(state), onoff(cur_state));
1132 }
1133
1134 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1135 enum pipe pipe, bool state)
1136 {
1137 bool cur_state;
1138 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1139 pipe);
1140
1141 if (HAS_DDI(dev_priv)) {
1142 /* DDI does not have a specific FDI_TX register */
1143 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1144 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1145 } else {
1146 u32 val = I915_READ(FDI_TX_CTL(pipe));
1147 cur_state = !!(val & FDI_TX_ENABLE);
1148 }
1149 I915_STATE_WARN(cur_state != state,
1150 "FDI TX state assertion failure (expected %s, current %s)\n",
1151 onoff(state), onoff(cur_state));
1152 }
1153 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1154 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1155
1156 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1157 enum pipe pipe, bool state)
1158 {
1159 u32 val;
1160 bool cur_state;
1161
1162 val = I915_READ(FDI_RX_CTL(pipe));
1163 cur_state = !!(val & FDI_RX_ENABLE);
1164 I915_STATE_WARN(cur_state != state,
1165 "FDI RX state assertion failure (expected %s, current %s)\n",
1166 onoff(state), onoff(cur_state));
1167 }
1168 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1169 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1170
1171 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1172 enum pipe pipe)
1173 {
1174 u32 val;
1175
1176 /* ILK FDI PLL is always enabled */
1177 if (IS_GEN5(dev_priv))
1178 return;
1179
1180 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1181 if (HAS_DDI(dev_priv))
1182 return;
1183
1184 val = I915_READ(FDI_TX_CTL(pipe));
1185 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1189 enum pipe pipe, bool state)
1190 {
1191 u32 val;
1192 bool cur_state;
1193
1194 val = I915_READ(FDI_RX_CTL(pipe));
1195 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1196 I915_STATE_WARN(cur_state != state,
1197 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1198 onoff(state), onoff(cur_state));
1199 }
1200
1201 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1202 {
1203 i915_reg_t pp_reg;
1204 u32 val;
1205 enum pipe panel_pipe = INVALID_PIPE;
1206 bool locked = true;
1207
1208 if (WARN_ON(HAS_DDI(dev_priv)))
1209 return;
1210
1211 if (HAS_PCH_SPLIT(dev_priv)) {
1212 u32 port_sel;
1213
1214 pp_reg = PP_CONTROL(0);
1215 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1216
1217 switch (port_sel) {
1218 case PANEL_PORT_SELECT_LVDS:
1219 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1220 break;
1221 case PANEL_PORT_SELECT_DPA:
1222 intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1223 break;
1224 case PANEL_PORT_SELECT_DPC:
1225 intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1226 break;
1227 case PANEL_PORT_SELECT_DPD:
1228 intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1229 break;
1230 default:
1231 MISSING_CASE(port_sel);
1232 break;
1233 }
1234 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1235 /* presumably write lock depends on pipe, not port select */
1236 pp_reg = PP_CONTROL(pipe);
1237 panel_pipe = pipe;
1238 } else {
1239 u32 port_sel;
1240
1241 pp_reg = PP_CONTROL(0);
1242 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1243
1244 WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS);
1245 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1246 }
1247
1248 val = I915_READ(pp_reg);
1249 if (!(val & PANEL_POWER_ON) ||
1250 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1251 locked = false;
1252
1253 I915_STATE_WARN(panel_pipe == pipe && locked,
1254 "panel assertion failure, pipe %c regs locked\n",
1255 pipe_name(pipe));
1256 }
1257
1258 void assert_pipe(struct drm_i915_private *dev_priv,
1259 enum pipe pipe, bool state)
1260 {
1261 bool cur_state;
1262 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1263 pipe);
1264 enum intel_display_power_domain power_domain;
1265
1266 /* we keep both pipes enabled on 830 */
1267 if (IS_I830(dev_priv))
1268 state = true;
1269
1270 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1271 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1272 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1273 cur_state = !!(val & PIPECONF_ENABLE);
1274
1275 intel_display_power_put(dev_priv, power_domain);
1276 } else {
1277 cur_state = false;
1278 }
1279
1280 I915_STATE_WARN(cur_state != state,
1281 "pipe %c assertion failure (expected %s, current %s)\n",
1282 pipe_name(pipe), onoff(state), onoff(cur_state));
1283 }
1284
1285 static void assert_plane(struct intel_plane *plane, bool state)
1286 {
1287 enum pipe pipe;
1288 bool cur_state;
1289
1290 cur_state = plane->get_hw_state(plane, &pipe);
1291
1292 I915_STATE_WARN(cur_state != state,
1293 "%s assertion failure (expected %s, current %s)\n",
1294 plane->base.name, onoff(state), onoff(cur_state));
1295 }
1296
1297 #define assert_plane_enabled(p) assert_plane(p, true)
1298 #define assert_plane_disabled(p) assert_plane(p, false)
1299
1300 static void assert_planes_disabled(struct intel_crtc *crtc)
1301 {
1302 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1303 struct intel_plane *plane;
1304
1305 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1306 assert_plane_disabled(plane);
1307 }
1308
1309 static void assert_vblank_disabled(struct drm_crtc *crtc)
1310 {
1311 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1312 drm_crtc_vblank_put(crtc);
1313 }
1314
1315 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1316 enum pipe pipe)
1317 {
1318 u32 val;
1319 bool enabled;
1320
1321 val = I915_READ(PCH_TRANSCONF(pipe));
1322 enabled = !!(val & TRANS_ENABLE);
1323 I915_STATE_WARN(enabled,
1324 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1325 pipe_name(pipe));
1326 }
1327
1328 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1329 enum pipe pipe, enum port port,
1330 i915_reg_t dp_reg)
1331 {
1332 enum pipe port_pipe;
1333 bool state;
1334
1335 state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1336
1337 I915_STATE_WARN(state && port_pipe == pipe,
1338 "PCH DP %c enabled on transcoder %c, should be disabled\n",
1339 port_name(port), pipe_name(pipe));
1340
1341 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1342 "IBX PCH DP %c still using transcoder B\n",
1343 port_name(port));
1344 }
1345
1346 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1347 enum pipe pipe, enum port port,
1348 i915_reg_t hdmi_reg)
1349 {
1350 enum pipe port_pipe;
1351 bool state;
1352
1353 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1354
1355 I915_STATE_WARN(state && port_pipe == pipe,
1356 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1357 port_name(port), pipe_name(pipe));
1358
1359 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1360 "IBX PCH HDMI %c still using transcoder B\n",
1361 port_name(port));
1362 }
1363
1364 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1365 enum pipe pipe)
1366 {
1367 enum pipe port_pipe;
1368
1369 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1370 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1371 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1372
1373 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1374 port_pipe == pipe,
1375 "PCH VGA enabled on transcoder %c, should be disabled\n",
1376 pipe_name(pipe));
1377
1378 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1379 port_pipe == pipe,
1380 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1381 pipe_name(pipe));
1382
1383 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1384 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1385 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1386 }
1387
1388 static void _vlv_enable_pll(struct intel_crtc *crtc,
1389 const struct intel_crtc_state *pipe_config)
1390 {
1391 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1392 enum pipe pipe = crtc->pipe;
1393
1394 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1395 POSTING_READ(DPLL(pipe));
1396 udelay(150);
1397
1398 if (intel_wait_for_register(dev_priv,
1399 DPLL(pipe),
1400 DPLL_LOCK_VLV,
1401 DPLL_LOCK_VLV,
1402 1))
1403 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1404 }
1405
1406 static void vlv_enable_pll(struct intel_crtc *crtc,
1407 const struct intel_crtc_state *pipe_config)
1408 {
1409 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1410 enum pipe pipe = crtc->pipe;
1411
1412 assert_pipe_disabled(dev_priv, pipe);
1413
1414 /* PLL is protected by panel, make sure we can write it */
1415 assert_panel_unlocked(dev_priv, pipe);
1416
1417 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1418 _vlv_enable_pll(crtc, pipe_config);
1419
1420 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1421 POSTING_READ(DPLL_MD(pipe));
1422 }
1423
1424
1425 static void _chv_enable_pll(struct intel_crtc *crtc,
1426 const struct intel_crtc_state *pipe_config)
1427 {
1428 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1429 enum pipe pipe = crtc->pipe;
1430 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1431 u32 tmp;
1432
1433 mutex_lock(&dev_priv->sb_lock);
1434
1435 /* Enable back the 10bit clock to display controller */
1436 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1437 tmp |= DPIO_DCLKP_EN;
1438 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1439
1440 mutex_unlock(&dev_priv->sb_lock);
1441
1442 /*
1443 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1444 */
1445 udelay(1);
1446
1447 /* Enable PLL */
1448 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1449
1450 /* Check PLL is locked */
1451 if (intel_wait_for_register(dev_priv,
1452 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1453 1))
1454 DRM_ERROR("PLL %d failed to lock\n", pipe);
1455 }
1456
1457 static void chv_enable_pll(struct intel_crtc *crtc,
1458 const struct intel_crtc_state *pipe_config)
1459 {
1460 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1461 enum pipe pipe = crtc->pipe;
1462
1463 assert_pipe_disabled(dev_priv, pipe);
1464
1465 /* PLL is protected by panel, make sure we can write it */
1466 assert_panel_unlocked(dev_priv, pipe);
1467
1468 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1469 _chv_enable_pll(crtc, pipe_config);
1470
1471 if (pipe != PIPE_A) {
1472 /*
1473 * WaPixelRepeatModeFixForC0:chv
1474 *
1475 * DPLLCMD is AWOL. Use chicken bits to propagate
1476 * the value from DPLLBMD to either pipe B or C.
1477 */
1478 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1479 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1480 I915_WRITE(CBR4_VLV, 0);
1481 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1482
1483 /*
1484 * DPLLB VGA mode also seems to cause problems.
1485 * We should always have it disabled.
1486 */
1487 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1488 } else {
1489 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1490 POSTING_READ(DPLL_MD(pipe));
1491 }
1492 }
1493
1494 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1495 {
1496 struct intel_crtc *crtc;
1497 int count = 0;
1498
1499 for_each_intel_crtc(&dev_priv->drm, crtc) {
1500 count += crtc->base.state->active &&
1501 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1502 }
1503
1504 return count;
1505 }
1506
1507 static void i9xx_enable_pll(struct intel_crtc *crtc,
1508 const struct intel_crtc_state *crtc_state)
1509 {
1510 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1511 i915_reg_t reg = DPLL(crtc->pipe);
1512 u32 dpll = crtc_state->dpll_hw_state.dpll;
1513 int i;
1514
1515 assert_pipe_disabled(dev_priv, crtc->pipe);
1516
1517 /* PLL is protected by panel, make sure we can write it */
1518 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1519 assert_panel_unlocked(dev_priv, crtc->pipe);
1520
1521 /* Enable DVO 2x clock on both PLLs if necessary */
1522 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1523 /*
1524 * It appears to be important that we don't enable this
1525 * for the current pipe before otherwise configuring the
1526 * PLL. No idea how this should be handled if multiple
1527 * DVO outputs are enabled simultaneosly.
1528 */
1529 dpll |= DPLL_DVO_2X_MODE;
1530 I915_WRITE(DPLL(!crtc->pipe),
1531 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1532 }
1533
1534 /*
1535 * Apparently we need to have VGA mode enabled prior to changing
1536 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1537 * dividers, even though the register value does change.
1538 */
1539 I915_WRITE(reg, 0);
1540
1541 I915_WRITE(reg, dpll);
1542
1543 /* Wait for the clocks to stabilize. */
1544 POSTING_READ(reg);
1545 udelay(150);
1546
1547 if (INTEL_GEN(dev_priv) >= 4) {
1548 I915_WRITE(DPLL_MD(crtc->pipe),
1549 crtc_state->dpll_hw_state.dpll_md);
1550 } else {
1551 /* The pixel multiplier can only be updated once the
1552 * DPLL is enabled and the clocks are stable.
1553 *
1554 * So write it again.
1555 */
1556 I915_WRITE(reg, dpll);
1557 }
1558
1559 /* We do this three times for luck */
1560 for (i = 0; i < 3; i++) {
1561 I915_WRITE(reg, dpll);
1562 POSTING_READ(reg);
1563 udelay(150); /* wait for warmup */
1564 }
1565 }
1566
1567 static void i9xx_disable_pll(struct intel_crtc *crtc)
1568 {
1569 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1570 enum pipe pipe = crtc->pipe;
1571
1572 /* Disable DVO 2x clock on both PLLs if necessary */
1573 if (IS_I830(dev_priv) &&
1574 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1575 !intel_num_dvo_pipes(dev_priv)) {
1576 I915_WRITE(DPLL(PIPE_B),
1577 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1578 I915_WRITE(DPLL(PIPE_A),
1579 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1580 }
1581
1582 /* Don't disable pipe or pipe PLLs if needed */
1583 if (IS_I830(dev_priv))
1584 return;
1585
1586 /* Make sure the pipe isn't still relying on us */
1587 assert_pipe_disabled(dev_priv, pipe);
1588
1589 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1590 POSTING_READ(DPLL(pipe));
1591 }
1592
1593 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1594 {
1595 u32 val;
1596
1597 /* Make sure the pipe isn't still relying on us */
1598 assert_pipe_disabled(dev_priv, pipe);
1599
1600 val = DPLL_INTEGRATED_REF_CLK_VLV |
1601 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1602 if (pipe != PIPE_A)
1603 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1604
1605 I915_WRITE(DPLL(pipe), val);
1606 POSTING_READ(DPLL(pipe));
1607 }
1608
1609 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1610 {
1611 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1612 u32 val;
1613
1614 /* Make sure the pipe isn't still relying on us */
1615 assert_pipe_disabled(dev_priv, pipe);
1616
1617 val = DPLL_SSC_REF_CLK_CHV |
1618 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1619 if (pipe != PIPE_A)
1620 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1621
1622 I915_WRITE(DPLL(pipe), val);
1623 POSTING_READ(DPLL(pipe));
1624
1625 mutex_lock(&dev_priv->sb_lock);
1626
1627 /* Disable 10bit clock to display controller */
1628 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1629 val &= ~DPIO_DCLKP_EN;
1630 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1631
1632 mutex_unlock(&dev_priv->sb_lock);
1633 }
1634
1635 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1636 struct intel_digital_port *dport,
1637 unsigned int expected_mask)
1638 {
1639 u32 port_mask;
1640 i915_reg_t dpll_reg;
1641
1642 switch (dport->base.port) {
1643 case PORT_B:
1644 port_mask = DPLL_PORTB_READY_MASK;
1645 dpll_reg = DPLL(0);
1646 break;
1647 case PORT_C:
1648 port_mask = DPLL_PORTC_READY_MASK;
1649 dpll_reg = DPLL(0);
1650 expected_mask <<= 4;
1651 break;
1652 case PORT_D:
1653 port_mask = DPLL_PORTD_READY_MASK;
1654 dpll_reg = DPIO_PHY_STATUS;
1655 break;
1656 default:
1657 BUG();
1658 }
1659
1660 if (intel_wait_for_register(dev_priv,
1661 dpll_reg, port_mask, expected_mask,
1662 1000))
1663 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1664 port_name(dport->base.port),
1665 I915_READ(dpll_reg) & port_mask, expected_mask);
1666 }
1667
1668 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1669 enum pipe pipe)
1670 {
1671 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1672 pipe);
1673 i915_reg_t reg;
1674 uint32_t val, pipeconf_val;
1675
1676 /* Make sure PCH DPLL is enabled */
1677 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1678
1679 /* FDI must be feeding us bits for PCH ports */
1680 assert_fdi_tx_enabled(dev_priv, pipe);
1681 assert_fdi_rx_enabled(dev_priv, pipe);
1682
1683 if (HAS_PCH_CPT(dev_priv)) {
1684 /* Workaround: Set the timing override bit before enabling the
1685 * pch transcoder. */
1686 reg = TRANS_CHICKEN2(pipe);
1687 val = I915_READ(reg);
1688 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1689 I915_WRITE(reg, val);
1690 }
1691
1692 reg = PCH_TRANSCONF(pipe);
1693 val = I915_READ(reg);
1694 pipeconf_val = I915_READ(PIPECONF(pipe));
1695
1696 if (HAS_PCH_IBX(dev_priv)) {
1697 /*
1698 * Make the BPC in transcoder be consistent with
1699 * that in pipeconf reg. For HDMI we must use 8bpc
1700 * here for both 8bpc and 12bpc.
1701 */
1702 val &= ~PIPECONF_BPC_MASK;
1703 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1704 val |= PIPECONF_8BPC;
1705 else
1706 val |= pipeconf_val & PIPECONF_BPC_MASK;
1707 }
1708
1709 val &= ~TRANS_INTERLACE_MASK;
1710 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1711 if (HAS_PCH_IBX(dev_priv) &&
1712 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1713 val |= TRANS_LEGACY_INTERLACED_ILK;
1714 else
1715 val |= TRANS_INTERLACED;
1716 else
1717 val |= TRANS_PROGRESSIVE;
1718
1719 I915_WRITE(reg, val | TRANS_ENABLE);
1720 if (intel_wait_for_register(dev_priv,
1721 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1722 100))
1723 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1724 }
1725
1726 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1727 enum transcoder cpu_transcoder)
1728 {
1729 u32 val, pipeconf_val;
1730
1731 /* FDI must be feeding us bits for PCH ports */
1732 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1733 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1734
1735 /* Workaround: set timing override bit. */
1736 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1737 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1738 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1739
1740 val = TRANS_ENABLE;
1741 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1742
1743 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1744 PIPECONF_INTERLACED_ILK)
1745 val |= TRANS_INTERLACED;
1746 else
1747 val |= TRANS_PROGRESSIVE;
1748
1749 I915_WRITE(LPT_TRANSCONF, val);
1750 if (intel_wait_for_register(dev_priv,
1751 LPT_TRANSCONF,
1752 TRANS_STATE_ENABLE,
1753 TRANS_STATE_ENABLE,
1754 100))
1755 DRM_ERROR("Failed to enable PCH transcoder\n");
1756 }
1757
1758 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1759 enum pipe pipe)
1760 {
1761 i915_reg_t reg;
1762 uint32_t val;
1763
1764 /* FDI relies on the transcoder */
1765 assert_fdi_tx_disabled(dev_priv, pipe);
1766 assert_fdi_rx_disabled(dev_priv, pipe);
1767
1768 /* Ports must be off as well */
1769 assert_pch_ports_disabled(dev_priv, pipe);
1770
1771 reg = PCH_TRANSCONF(pipe);
1772 val = I915_READ(reg);
1773 val &= ~TRANS_ENABLE;
1774 I915_WRITE(reg, val);
1775 /* wait for PCH transcoder off, transcoder state */
1776 if (intel_wait_for_register(dev_priv,
1777 reg, TRANS_STATE_ENABLE, 0,
1778 50))
1779 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1780
1781 if (HAS_PCH_CPT(dev_priv)) {
1782 /* Workaround: Clear the timing override chicken bit again. */
1783 reg = TRANS_CHICKEN2(pipe);
1784 val = I915_READ(reg);
1785 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1786 I915_WRITE(reg, val);
1787 }
1788 }
1789
1790 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1791 {
1792 u32 val;
1793
1794 val = I915_READ(LPT_TRANSCONF);
1795 val &= ~TRANS_ENABLE;
1796 I915_WRITE(LPT_TRANSCONF, val);
1797 /* wait for PCH transcoder off, transcoder state */
1798 if (intel_wait_for_register(dev_priv,
1799 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1800 50))
1801 DRM_ERROR("Failed to disable PCH transcoder\n");
1802
1803 /* Workaround: clear timing override bit. */
1804 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1805 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1806 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1807 }
1808
1809 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1810 {
1811 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1812
1813 if (HAS_PCH_LPT(dev_priv))
1814 return PIPE_A;
1815 else
1816 return crtc->pipe;
1817 }
1818
1819 static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1820 {
1821 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
1822 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1823 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1824 enum pipe pipe = crtc->pipe;
1825 i915_reg_t reg;
1826 u32 val;
1827
1828 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1829
1830 assert_planes_disabled(crtc);
1831
1832 /*
1833 * A pipe without a PLL won't actually be able to drive bits from
1834 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1835 * need the check.
1836 */
1837 if (HAS_GMCH_DISPLAY(dev_priv)) {
1838 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1839 assert_dsi_pll_enabled(dev_priv);
1840 else
1841 assert_pll_enabled(dev_priv, pipe);
1842 } else {
1843 if (new_crtc_state->has_pch_encoder) {
1844 /* if driving the PCH, we need FDI enabled */
1845 assert_fdi_rx_pll_enabled(dev_priv,
1846 intel_crtc_pch_transcoder(crtc));
1847 assert_fdi_tx_pll_enabled(dev_priv,
1848 (enum pipe) cpu_transcoder);
1849 }
1850 /* FIXME: assert CPU port conditions for SNB+ */
1851 }
1852
1853 reg = PIPECONF(cpu_transcoder);
1854 val = I915_READ(reg);
1855 if (val & PIPECONF_ENABLE) {
1856 /* we keep both pipes enabled on 830 */
1857 WARN_ON(!IS_I830(dev_priv));
1858 return;
1859 }
1860
1861 I915_WRITE(reg, val | PIPECONF_ENABLE);
1862 POSTING_READ(reg);
1863
1864 /*
1865 * Until the pipe starts PIPEDSL reads will return a stale value,
1866 * which causes an apparent vblank timestamp jump when PIPEDSL
1867 * resets to its proper value. That also messes up the frame count
1868 * when it's derived from the timestamps. So let's wait for the
1869 * pipe to start properly before we call drm_crtc_vblank_on()
1870 */
1871 if (dev_priv->drm.max_vblank_count == 0)
1872 intel_wait_for_pipe_scanline_moving(crtc);
1873 }
1874
1875 static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1876 {
1877 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1878 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1879 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1880 enum pipe pipe = crtc->pipe;
1881 i915_reg_t reg;
1882 u32 val;
1883
1884 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1885
1886 /*
1887 * Make sure planes won't keep trying to pump pixels to us,
1888 * or we might hang the display.
1889 */
1890 assert_planes_disabled(crtc);
1891
1892 reg = PIPECONF(cpu_transcoder);
1893 val = I915_READ(reg);
1894 if ((val & PIPECONF_ENABLE) == 0)
1895 return;
1896
1897 /*
1898 * Double wide has implications for planes
1899 * so best keep it disabled when not needed.
1900 */
1901 if (old_crtc_state->double_wide)
1902 val &= ~PIPECONF_DOUBLE_WIDE;
1903
1904 /* Don't disable pipe or pipe PLLs if needed */
1905 if (!IS_I830(dev_priv))
1906 val &= ~PIPECONF_ENABLE;
1907
1908 I915_WRITE(reg, val);
1909 if ((val & PIPECONF_ENABLE) == 0)
1910 intel_wait_for_pipe_off(old_crtc_state);
1911 }
1912
1913 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1914 {
1915 return IS_GEN2(dev_priv) ? 2048 : 4096;
1916 }
1917
1918 static unsigned int
1919 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
1920 {
1921 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1922 unsigned int cpp = fb->format->cpp[plane];
1923
1924 switch (fb->modifier) {
1925 case DRM_FORMAT_MOD_LINEAR:
1926 return cpp;
1927 case I915_FORMAT_MOD_X_TILED:
1928 if (IS_GEN2(dev_priv))
1929 return 128;
1930 else
1931 return 512;
1932 case I915_FORMAT_MOD_Y_TILED_CCS:
1933 if (plane == 1)
1934 return 128;
1935 /* fall through */
1936 case I915_FORMAT_MOD_Y_TILED:
1937 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
1938 return 128;
1939 else
1940 return 512;
1941 case I915_FORMAT_MOD_Yf_TILED_CCS:
1942 if (plane == 1)
1943 return 128;
1944 /* fall through */
1945 case I915_FORMAT_MOD_Yf_TILED:
1946 switch (cpp) {
1947 case 1:
1948 return 64;
1949 case 2:
1950 case 4:
1951 return 128;
1952 case 8:
1953 case 16:
1954 return 256;
1955 default:
1956 MISSING_CASE(cpp);
1957 return cpp;
1958 }
1959 break;
1960 default:
1961 MISSING_CASE(fb->modifier);
1962 return cpp;
1963 }
1964 }
1965
1966 static unsigned int
1967 intel_tile_height(const struct drm_framebuffer *fb, int plane)
1968 {
1969 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
1970 return 1;
1971 else
1972 return intel_tile_size(to_i915(fb->dev)) /
1973 intel_tile_width_bytes(fb, plane);
1974 }
1975
1976 /* Return the tile dimensions in pixel units */
1977 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
1978 unsigned int *tile_width,
1979 unsigned int *tile_height)
1980 {
1981 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
1982 unsigned int cpp = fb->format->cpp[plane];
1983
1984 *tile_width = tile_width_bytes / cpp;
1985 *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
1986 }
1987
1988 unsigned int
1989 intel_fb_align_height(const struct drm_framebuffer *fb,
1990 int plane, unsigned int height)
1991 {
1992 unsigned int tile_height = intel_tile_height(fb, plane);
1993
1994 return ALIGN(height, tile_height);
1995 }
1996
1997 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
1998 {
1999 unsigned int size = 0;
2000 int i;
2001
2002 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2003 size += rot_info->plane[i].width * rot_info->plane[i].height;
2004
2005 return size;
2006 }
2007
2008 static void
2009 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2010 const struct drm_framebuffer *fb,
2011 unsigned int rotation)
2012 {
2013 view->type = I915_GGTT_VIEW_NORMAL;
2014 if (drm_rotation_90_or_270(rotation)) {
2015 view->type = I915_GGTT_VIEW_ROTATED;
2016 view->rotated = to_intel_framebuffer(fb)->rot_info;
2017 }
2018 }
2019
2020 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2021 {
2022 if (IS_I830(dev_priv))
2023 return 16 * 1024;
2024 else if (IS_I85X(dev_priv))
2025 return 256;
2026 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2027 return 32;
2028 else
2029 return 4 * 1024;
2030 }
2031
2032 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2033 {
2034 if (INTEL_GEN(dev_priv) >= 9)
2035 return 256 * 1024;
2036 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2037 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2038 return 128 * 1024;
2039 else if (INTEL_GEN(dev_priv) >= 4)
2040 return 4 * 1024;
2041 else
2042 return 0;
2043 }
2044
2045 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2046 int plane)
2047 {
2048 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2049
2050 /* AUX_DIST needs only 4K alignment */
2051 if (plane == 1)
2052 return 4096;
2053
2054 switch (fb->modifier) {
2055 case DRM_FORMAT_MOD_LINEAR:
2056 return intel_linear_alignment(dev_priv);
2057 case I915_FORMAT_MOD_X_TILED:
2058 if (INTEL_GEN(dev_priv) >= 9)
2059 return 256 * 1024;
2060 return 0;
2061 case I915_FORMAT_MOD_Y_TILED_CCS:
2062 case I915_FORMAT_MOD_Yf_TILED_CCS:
2063 case I915_FORMAT_MOD_Y_TILED:
2064 case I915_FORMAT_MOD_Yf_TILED:
2065 return 1 * 1024 * 1024;
2066 default:
2067 MISSING_CASE(fb->modifier);
2068 return 0;
2069 }
2070 }
2071
2072 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2073 {
2074 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2075 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2076
2077 return INTEL_GEN(dev_priv) < 4 || plane->has_fbc;
2078 }
2079
2080 struct i915_vma *
2081 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2082 unsigned int rotation,
2083 bool uses_fence,
2084 unsigned long *out_flags)
2085 {
2086 struct drm_device *dev = fb->dev;
2087 struct drm_i915_private *dev_priv = to_i915(dev);
2088 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2089 struct i915_ggtt_view view;
2090 struct i915_vma *vma;
2091 unsigned int pinctl;
2092 u32 alignment;
2093
2094 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2095
2096 alignment = intel_surf_alignment(fb, 0);
2097
2098 intel_fill_fb_ggtt_view(&view, fb, rotation);
2099
2100 /* Note that the w/a also requires 64 PTE of padding following the
2101 * bo. We currently fill all unused PTE with the shadow page and so
2102 * we should always have valid PTE following the scanout preventing
2103 * the VT-d warning.
2104 */
2105 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2106 alignment = 256 * 1024;
2107
2108 /*
2109 * Global gtt pte registers are special registers which actually forward
2110 * writes to a chunk of system memory. Which means that there is no risk
2111 * that the register values disappear as soon as we call
2112 * intel_runtime_pm_put(), so it is correct to wrap only the
2113 * pin/unpin/fence and not more.
2114 */
2115 intel_runtime_pm_get(dev_priv);
2116
2117 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2118
2119 pinctl = 0;
2120
2121 /* Valleyview is definitely limited to scanning out the first
2122 * 512MiB. Lets presume this behaviour was inherited from the
2123 * g4x display engine and that all earlier gen are similarly
2124 * limited. Testing suggests that it is a little more
2125 * complicated than this. For example, Cherryview appears quite
2126 * happy to scanout from anywhere within its global aperture.
2127 */
2128 if (HAS_GMCH_DISPLAY(dev_priv))
2129 pinctl |= PIN_MAPPABLE;
2130
2131 vma = i915_gem_object_pin_to_display_plane(obj,
2132 alignment, &view, pinctl);
2133 if (IS_ERR(vma))
2134 goto err;
2135
2136 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2137 int ret;
2138
2139 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2140 * fence, whereas 965+ only requires a fence if using
2141 * framebuffer compression. For simplicity, we always, when
2142 * possible, install a fence as the cost is not that onerous.
2143 *
2144 * If we fail to fence the tiled scanout, then either the
2145 * modeset will reject the change (which is highly unlikely as
2146 * the affected systems, all but one, do not have unmappable
2147 * space) or we will not be able to enable full powersaving
2148 * techniques (also likely not to apply due to various limits
2149 * FBC and the like impose on the size of the buffer, which
2150 * presumably we violated anyway with this unmappable buffer).
2151 * Anyway, it is presumably better to stumble onwards with
2152 * something and try to run the system in a "less than optimal"
2153 * mode that matches the user configuration.
2154 */
2155 ret = i915_vma_pin_fence(vma);
2156 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2157 i915_gem_object_unpin_from_display_plane(vma);
2158 vma = ERR_PTR(ret);
2159 goto err;
2160 }
2161
2162 if (ret == 0 && vma->fence)
2163 *out_flags |= PLANE_HAS_FENCE;
2164 }
2165
2166 i915_vma_get(vma);
2167 err:
2168 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2169
2170 intel_runtime_pm_put(dev_priv);
2171 return vma;
2172 }
2173
2174 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2175 {
2176 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2177
2178 if (flags & PLANE_HAS_FENCE)
2179 i915_vma_unpin_fence(vma);
2180 i915_gem_object_unpin_from_display_plane(vma);
2181 i915_vma_put(vma);
2182 }
2183
2184 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2185 unsigned int rotation)
2186 {
2187 if (drm_rotation_90_or_270(rotation))
2188 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2189 else
2190 return fb->pitches[plane];
2191 }
2192
2193 /*
2194 * Convert the x/y offsets into a linear offset.
2195 * Only valid with 0/180 degree rotation, which is fine since linear
2196 * offset is only used with linear buffers on pre-hsw and tiled buffers
2197 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2198 */
2199 u32 intel_fb_xy_to_linear(int x, int y,
2200 const struct intel_plane_state *state,
2201 int plane)
2202 {
2203 const struct drm_framebuffer *fb = state->base.fb;
2204 unsigned int cpp = fb->format->cpp[plane];
2205 unsigned int pitch = fb->pitches[plane];
2206
2207 return y * pitch + x * cpp;
2208 }
2209
2210 /*
2211 * Add the x/y offsets derived from fb->offsets[] to the user
2212 * specified plane src x/y offsets. The resulting x/y offsets
2213 * specify the start of scanout from the beginning of the gtt mapping.
2214 */
2215 void intel_add_fb_offsets(int *x, int *y,
2216 const struct intel_plane_state *state,
2217 int plane)
2218
2219 {
2220 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2221 unsigned int rotation = state->base.rotation;
2222
2223 if (drm_rotation_90_or_270(rotation)) {
2224 *x += intel_fb->rotated[plane].x;
2225 *y += intel_fb->rotated[plane].y;
2226 } else {
2227 *x += intel_fb->normal[plane].x;
2228 *y += intel_fb->normal[plane].y;
2229 }
2230 }
2231
2232 static u32 __intel_adjust_tile_offset(int *x, int *y,
2233 unsigned int tile_width,
2234 unsigned int tile_height,
2235 unsigned int tile_size,
2236 unsigned int pitch_tiles,
2237 u32 old_offset,
2238 u32 new_offset)
2239 {
2240 unsigned int pitch_pixels = pitch_tiles * tile_width;
2241 unsigned int tiles;
2242
2243 WARN_ON(old_offset & (tile_size - 1));
2244 WARN_ON(new_offset & (tile_size - 1));
2245 WARN_ON(new_offset > old_offset);
2246
2247 tiles = (old_offset - new_offset) / tile_size;
2248
2249 *y += tiles / pitch_tiles * tile_height;
2250 *x += tiles % pitch_tiles * tile_width;
2251
2252 /* minimize x in case it got needlessly big */
2253 *y += *x / pitch_pixels * tile_height;
2254 *x %= pitch_pixels;
2255
2256 return new_offset;
2257 }
2258
2259 static u32 _intel_adjust_tile_offset(int *x, int *y,
2260 const struct drm_framebuffer *fb, int plane,
2261 unsigned int rotation,
2262 u32 old_offset, u32 new_offset)
2263 {
2264 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2265 unsigned int cpp = fb->format->cpp[plane];
2266 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2267
2268 WARN_ON(new_offset > old_offset);
2269
2270 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2271 unsigned int tile_size, tile_width, tile_height;
2272 unsigned int pitch_tiles;
2273
2274 tile_size = intel_tile_size(dev_priv);
2275 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2276
2277 if (drm_rotation_90_or_270(rotation)) {
2278 pitch_tiles = pitch / tile_height;
2279 swap(tile_width, tile_height);
2280 } else {
2281 pitch_tiles = pitch / (tile_width * cpp);
2282 }
2283
2284 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2285 tile_size, pitch_tiles,
2286 old_offset, new_offset);
2287 } else {
2288 old_offset += *y * pitch + *x * cpp;
2289
2290 *y = (old_offset - new_offset) / pitch;
2291 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2292 }
2293
2294 return new_offset;
2295 }
2296
2297 /*
2298 * Adjust the tile offset by moving the difference into
2299 * the x/y offsets.
2300 */
2301 static u32 intel_adjust_tile_offset(int *x, int *y,
2302 const struct intel_plane_state *state, int plane,
2303 u32 old_offset, u32 new_offset)
2304 {
2305 return _intel_adjust_tile_offset(x, y, state->base.fb, plane,
2306 state->base.rotation,
2307 old_offset, new_offset);
2308 }
2309
2310 /*
2311 * Computes the linear offset to the base tile and adjusts
2312 * x, y. bytes per pixel is assumed to be a power-of-two.
2313 *
2314 * In the 90/270 rotated case, x and y are assumed
2315 * to be already rotated to match the rotated GTT view, and
2316 * pitch is the tile_height aligned framebuffer height.
2317 *
2318 * This function is used when computing the derived information
2319 * under intel_framebuffer, so using any of that information
2320 * here is not allowed. Anything under drm_framebuffer can be
2321 * used. This is why the user has to pass in the pitch since it
2322 * is specified in the rotated orientation.
2323 */
2324 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2325 int *x, int *y,
2326 const struct drm_framebuffer *fb, int plane,
2327 unsigned int pitch,
2328 unsigned int rotation,
2329 u32 alignment)
2330 {
2331 uint64_t fb_modifier = fb->modifier;
2332 unsigned int cpp = fb->format->cpp[plane];
2333 u32 offset, offset_aligned;
2334
2335 if (alignment)
2336 alignment--;
2337
2338 if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2339 unsigned int tile_size, tile_width, tile_height;
2340 unsigned int tile_rows, tiles, pitch_tiles;
2341
2342 tile_size = intel_tile_size(dev_priv);
2343 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2344
2345 if (drm_rotation_90_or_270(rotation)) {
2346 pitch_tiles = pitch / tile_height;
2347 swap(tile_width, tile_height);
2348 } else {
2349 pitch_tiles = pitch / (tile_width * cpp);
2350 }
2351
2352 tile_rows = *y / tile_height;
2353 *y %= tile_height;
2354
2355 tiles = *x / tile_width;
2356 *x %= tile_width;
2357
2358 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2359 offset_aligned = offset & ~alignment;
2360
2361 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2362 tile_size, pitch_tiles,
2363 offset, offset_aligned);
2364 } else {
2365 offset = *y * pitch + *x * cpp;
2366 offset_aligned = offset & ~alignment;
2367
2368 *y = (offset & alignment) / pitch;
2369 *x = ((offset & alignment) - *y * pitch) / cpp;
2370 }
2371
2372 return offset_aligned;
2373 }
2374
2375 u32 intel_compute_tile_offset(int *x, int *y,
2376 const struct intel_plane_state *state,
2377 int plane)
2378 {
2379 struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2380 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2381 const struct drm_framebuffer *fb = state->base.fb;
2382 unsigned int rotation = state->base.rotation;
2383 int pitch = intel_fb_pitch(fb, plane, rotation);
2384 u32 alignment;
2385
2386 if (intel_plane->id == PLANE_CURSOR)
2387 alignment = intel_cursor_alignment(dev_priv);
2388 else
2389 alignment = intel_surf_alignment(fb, plane);
2390
2391 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2392 rotation, alignment);
2393 }
2394
2395 /* Convert the fb->offset[] into x/y offsets */
2396 static int intel_fb_offset_to_xy(int *x, int *y,
2397 const struct drm_framebuffer *fb, int plane)
2398 {
2399 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2400
2401 if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2402 fb->offsets[plane] % intel_tile_size(dev_priv))
2403 return -EINVAL;
2404
2405 *x = 0;
2406 *y = 0;
2407
2408 _intel_adjust_tile_offset(x, y,
2409 fb, plane, DRM_MODE_ROTATE_0,
2410 fb->offsets[plane], 0);
2411
2412 return 0;
2413 }
2414
2415 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2416 {
2417 switch (fb_modifier) {
2418 case I915_FORMAT_MOD_X_TILED:
2419 return I915_TILING_X;
2420 case I915_FORMAT_MOD_Y_TILED:
2421 case I915_FORMAT_MOD_Y_TILED_CCS:
2422 return I915_TILING_Y;
2423 default:
2424 return I915_TILING_NONE;
2425 }
2426 }
2427
2428 /*
2429 * From the Sky Lake PRM:
2430 * "The Color Control Surface (CCS) contains the compression status of
2431 * the cache-line pairs. The compression state of the cache-line pair
2432 * is specified by 2 bits in the CCS. Each CCS cache-line represents
2433 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2434 * cache-line-pairs. CCS is always Y tiled."
2435 *
2436 * Since cache line pairs refers to horizontally adjacent cache lines,
2437 * each cache line in the CCS corresponds to an area of 32x16 cache
2438 * lines on the main surface. Since each pixel is 4 bytes, this gives
2439 * us a ratio of one byte in the CCS for each 8x16 pixels in the
2440 * main surface.
2441 */
2442 static const struct drm_format_info ccs_formats[] = {
2443 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2444 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2445 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2446 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2447 };
2448
2449 static const struct drm_format_info *
2450 lookup_format_info(const struct drm_format_info formats[],
2451 int num_formats, u32 format)
2452 {
2453 int i;
2454
2455 for (i = 0; i < num_formats; i++) {
2456 if (formats[i].format == format)
2457 return &formats[i];
2458 }
2459
2460 return NULL;
2461 }
2462
2463 static const struct drm_format_info *
2464 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2465 {
2466 switch (cmd->modifier[0]) {
2467 case I915_FORMAT_MOD_Y_TILED_CCS:
2468 case I915_FORMAT_MOD_Yf_TILED_CCS:
2469 return lookup_format_info(ccs_formats,
2470 ARRAY_SIZE(ccs_formats),
2471 cmd->pixel_format);
2472 default:
2473 return NULL;
2474 }
2475 }
2476
2477 static int
2478 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2479 struct drm_framebuffer *fb)
2480 {
2481 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2482 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2483 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2484 u32 gtt_offset_rotated = 0;
2485 unsigned int max_size = 0;
2486 int i, num_planes = fb->format->num_planes;
2487 unsigned int tile_size = intel_tile_size(dev_priv);
2488
2489 for (i = 0; i < num_planes; i++) {
2490 unsigned int width, height;
2491 unsigned int cpp, size;
2492 u32 offset;
2493 int x, y;
2494 int ret;
2495
2496 cpp = fb->format->cpp[i];
2497 width = drm_framebuffer_plane_width(fb->width, fb, i);
2498 height = drm_framebuffer_plane_height(fb->height, fb, i);
2499
2500 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2501 if (ret) {
2502 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2503 i, fb->offsets[i]);
2504 return ret;
2505 }
2506
2507 if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2508 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) {
2509 int hsub = fb->format->hsub;
2510 int vsub = fb->format->vsub;
2511 int tile_width, tile_height;
2512 int main_x, main_y;
2513 int ccs_x, ccs_y;
2514
2515 intel_tile_dims(fb, i, &tile_width, &tile_height);
2516 tile_width *= hsub;
2517 tile_height *= vsub;
2518
2519 ccs_x = (x * hsub) % tile_width;
2520 ccs_y = (y * vsub) % tile_height;
2521 main_x = intel_fb->normal[0].x % tile_width;
2522 main_y = intel_fb->normal[0].y % tile_height;
2523
2524 /*
2525 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2526 * x/y offsets must match between CCS and the main surface.
2527 */
2528 if (main_x != ccs_x || main_y != ccs_y) {
2529 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2530 main_x, main_y,
2531 ccs_x, ccs_y,
2532 intel_fb->normal[0].x,
2533 intel_fb->normal[0].y,
2534 x, y);
2535 return -EINVAL;
2536 }
2537 }
2538
2539 /*
2540 * The fence (if used) is aligned to the start of the object
2541 * so having the framebuffer wrap around across the edge of the
2542 * fenced region doesn't really work. We have no API to configure
2543 * the fence start offset within the object (nor could we probably
2544 * on gen2/3). So it's just easier if we just require that the
2545 * fb layout agrees with the fence layout. We already check that the
2546 * fb stride matches the fence stride elsewhere.
2547 */
2548 if (i == 0 && i915_gem_object_is_tiled(obj) &&
2549 (x + width) * cpp > fb->pitches[i]) {
2550 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2551 i, fb->offsets[i]);
2552 return -EINVAL;
2553 }
2554
2555 /*
2556 * First pixel of the framebuffer from
2557 * the start of the normal gtt mapping.
2558 */
2559 intel_fb->normal[i].x = x;
2560 intel_fb->normal[i].y = y;
2561
2562 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2563 fb, i, fb->pitches[i],
2564 DRM_MODE_ROTATE_0, tile_size);
2565 offset /= tile_size;
2566
2567 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2568 unsigned int tile_width, tile_height;
2569 unsigned int pitch_tiles;
2570 struct drm_rect r;
2571
2572 intel_tile_dims(fb, i, &tile_width, &tile_height);
2573
2574 rot_info->plane[i].offset = offset;
2575 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2576 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2577 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2578
2579 intel_fb->rotated[i].pitch =
2580 rot_info->plane[i].height * tile_height;
2581
2582 /* how many tiles does this plane need */
2583 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2584 /*
2585 * If the plane isn't horizontally tile aligned,
2586 * we need one more tile.
2587 */
2588 if (x != 0)
2589 size++;
2590
2591 /* rotate the x/y offsets to match the GTT view */
2592 r.x1 = x;
2593 r.y1 = y;
2594 r.x2 = x + width;
2595 r.y2 = y + height;
2596 drm_rect_rotate(&r,
2597 rot_info->plane[i].width * tile_width,
2598 rot_info->plane[i].height * tile_height,
2599 DRM_MODE_ROTATE_270);
2600 x = r.x1;
2601 y = r.y1;
2602
2603 /* rotate the tile dimensions to match the GTT view */
2604 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2605 swap(tile_width, tile_height);
2606
2607 /*
2608 * We only keep the x/y offsets, so push all of the
2609 * gtt offset into the x/y offsets.
2610 */
2611 __intel_adjust_tile_offset(&x, &y,
2612 tile_width, tile_height,
2613 tile_size, pitch_tiles,
2614 gtt_offset_rotated * tile_size, 0);
2615
2616 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2617
2618 /*
2619 * First pixel of the framebuffer from
2620 * the start of the rotated gtt mapping.
2621 */
2622 intel_fb->rotated[i].x = x;
2623 intel_fb->rotated[i].y = y;
2624 } else {
2625 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2626 x * cpp, tile_size);
2627 }
2628
2629 /* how many tiles in total needed in the bo */
2630 max_size = max(max_size, offset + size);
2631 }
2632
2633 if (max_size * tile_size > obj->base.size) {
2634 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2635 max_size * tile_size, obj->base.size);
2636 return -EINVAL;
2637 }
2638
2639 return 0;
2640 }
2641
2642 static int i9xx_format_to_fourcc(int format)
2643 {
2644 switch (format) {
2645 case DISPPLANE_8BPP:
2646 return DRM_FORMAT_C8;
2647 case DISPPLANE_BGRX555:
2648 return DRM_FORMAT_XRGB1555;
2649 case DISPPLANE_BGRX565:
2650 return DRM_FORMAT_RGB565;
2651 default:
2652 case DISPPLANE_BGRX888:
2653 return DRM_FORMAT_XRGB8888;
2654 case DISPPLANE_RGBX888:
2655 return DRM_FORMAT_XBGR8888;
2656 case DISPPLANE_BGRX101010:
2657 return DRM_FORMAT_XRGB2101010;
2658 case DISPPLANE_RGBX101010:
2659 return DRM_FORMAT_XBGR2101010;
2660 }
2661 }
2662
2663 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2664 {
2665 switch (format) {
2666 case PLANE_CTL_FORMAT_RGB_565:
2667 return DRM_FORMAT_RGB565;
2668 case PLANE_CTL_FORMAT_NV12:
2669 return DRM_FORMAT_NV12;
2670 default:
2671 case PLANE_CTL_FORMAT_XRGB_8888:
2672 if (rgb_order) {
2673 if (alpha)
2674 return DRM_FORMAT_ABGR8888;
2675 else
2676 return DRM_FORMAT_XBGR8888;
2677 } else {
2678 if (alpha)
2679 return DRM_FORMAT_ARGB8888;
2680 else
2681 return DRM_FORMAT_XRGB8888;
2682 }
2683 case PLANE_CTL_FORMAT_XRGB_2101010:
2684 if (rgb_order)
2685 return DRM_FORMAT_XBGR2101010;
2686 else
2687 return DRM_FORMAT_XRGB2101010;
2688 }
2689 }
2690
2691 static bool
2692 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2693 struct intel_initial_plane_config *plane_config)
2694 {
2695 struct drm_device *dev = crtc->base.dev;
2696 struct drm_i915_private *dev_priv = to_i915(dev);
2697 struct drm_i915_gem_object *obj = NULL;
2698 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2699 struct drm_framebuffer *fb = &plane_config->fb->base;
2700 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2701 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2702 PAGE_SIZE);
2703
2704 size_aligned -= base_aligned;
2705
2706 if (plane_config->size == 0)
2707 return false;
2708
2709 /* If the FB is too big, just don't use it since fbdev is not very
2710 * important and we should probably use that space with FBC or other
2711 * features. */
2712 if (size_aligned * 2 > dev_priv->stolen_usable_size)
2713 return false;
2714
2715 switch (fb->modifier) {
2716 case DRM_FORMAT_MOD_LINEAR:
2717 case I915_FORMAT_MOD_X_TILED:
2718 case I915_FORMAT_MOD_Y_TILED:
2719 break;
2720 default:
2721 DRM_DEBUG_DRIVER("Unsupported modifier for initial FB: 0x%llx\n",
2722 fb->modifier);
2723 return false;
2724 }
2725
2726 mutex_lock(&dev->struct_mutex);
2727 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2728 base_aligned,
2729 base_aligned,
2730 size_aligned);
2731 mutex_unlock(&dev->struct_mutex);
2732 if (!obj)
2733 return false;
2734
2735 switch (plane_config->tiling) {
2736 case I915_TILING_NONE:
2737 break;
2738 case I915_TILING_X:
2739 case I915_TILING_Y:
2740 obj->tiling_and_stride = fb->pitches[0] | plane_config->tiling;
2741 break;
2742 default:
2743 MISSING_CASE(plane_config->tiling);
2744 return false;
2745 }
2746
2747 mode_cmd.pixel_format = fb->format->format;
2748 mode_cmd.width = fb->width;
2749 mode_cmd.height = fb->height;
2750 mode_cmd.pitches[0] = fb->pitches[0];
2751 mode_cmd.modifier[0] = fb->modifier;
2752 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2753
2754 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2755 DRM_DEBUG_KMS("intel fb init failed\n");
2756 goto out_unref_obj;
2757 }
2758
2759
2760 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2761 return true;
2762
2763 out_unref_obj:
2764 i915_gem_object_put(obj);
2765 return false;
2766 }
2767
2768 static void
2769 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2770 struct intel_plane_state *plane_state,
2771 bool visible)
2772 {
2773 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2774
2775 plane_state->base.visible = visible;
2776
2777 if (visible)
2778 crtc_state->base.plane_mask |= drm_plane_mask(&plane->base);
2779 else
2780 crtc_state->base.plane_mask &= ~drm_plane_mask(&plane->base);
2781
2782 DRM_DEBUG_KMS("%s active planes 0x%x\n",
2783 crtc_state->base.crtc->name,
2784 crtc_state->active_planes);
2785 }
2786
2787 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
2788 {
2789 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2790 struct drm_plane *plane;
2791
2792 /*
2793 * Active_planes aliases if multiple "primary" or cursor planes
2794 * have been used on the same (or wrong) pipe. plane_mask uses
2795 * unique ids, hence we can use that to reconstruct active_planes.
2796 */
2797 crtc_state->active_planes = 0;
2798
2799 drm_for_each_plane_mask(plane, &dev_priv->drm,
2800 crtc_state->base.plane_mask)
2801 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
2802 }
2803
2804 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
2805 struct intel_plane *plane)
2806 {
2807 struct intel_crtc_state *crtc_state =
2808 to_intel_crtc_state(crtc->base.state);
2809 struct intel_plane_state *plane_state =
2810 to_intel_plane_state(plane->base.state);
2811
2812 intel_set_plane_visible(crtc_state, plane_state, false);
2813 fixup_active_planes(crtc_state);
2814
2815 if (plane->id == PLANE_PRIMARY)
2816 intel_pre_disable_primary_noatomic(&crtc->base);
2817
2818 trace_intel_disable_plane(&plane->base, crtc);
2819 plane->disable_plane(plane, crtc);
2820 }
2821
2822 static void
2823 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2824 struct intel_initial_plane_config *plane_config)
2825 {
2826 struct drm_device *dev = intel_crtc->base.dev;
2827 struct drm_i915_private *dev_priv = to_i915(dev);
2828 struct drm_crtc *c;
2829 struct drm_i915_gem_object *obj;
2830 struct drm_plane *primary = intel_crtc->base.primary;
2831 struct drm_plane_state *plane_state = primary->state;
2832 struct intel_plane *intel_plane = to_intel_plane(primary);
2833 struct intel_plane_state *intel_state =
2834 to_intel_plane_state(plane_state);
2835 struct drm_framebuffer *fb;
2836
2837 if (!plane_config->fb)
2838 return;
2839
2840 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2841 fb = &plane_config->fb->base;
2842 goto valid_fb;
2843 }
2844
2845 kfree(plane_config->fb);
2846
2847 /*
2848 * Failed to alloc the obj, check to see if we should share
2849 * an fb with another CRTC instead
2850 */
2851 for_each_crtc(dev, c) {
2852 struct intel_plane_state *state;
2853
2854 if (c == &intel_crtc->base)
2855 continue;
2856
2857 if (!to_intel_crtc(c)->active)
2858 continue;
2859
2860 state = to_intel_plane_state(c->primary->state);
2861 if (!state->vma)
2862 continue;
2863
2864 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2865 fb = state->base.fb;
2866 drm_framebuffer_get(fb);
2867 goto valid_fb;
2868 }
2869 }
2870
2871 /*
2872 * We've failed to reconstruct the BIOS FB. Current display state
2873 * indicates that the primary plane is visible, but has a NULL FB,
2874 * which will lead to problems later if we don't fix it up. The
2875 * simplest solution is to just disable the primary plane now and
2876 * pretend the BIOS never had it enabled.
2877 */
2878 intel_plane_disable_noatomic(intel_crtc, intel_plane);
2879
2880 return;
2881
2882 valid_fb:
2883 mutex_lock(&dev->struct_mutex);
2884 intel_state->vma =
2885 intel_pin_and_fence_fb_obj(fb,
2886 primary->state->rotation,
2887 intel_plane_uses_fence(intel_state),
2888 &intel_state->flags);
2889 mutex_unlock(&dev->struct_mutex);
2890 if (IS_ERR(intel_state->vma)) {
2891 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2892 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2893
2894 intel_state->vma = NULL;
2895 drm_framebuffer_put(fb);
2896 return;
2897 }
2898
2899 obj = intel_fb_obj(fb);
2900 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
2901
2902 plane_state->src_x = 0;
2903 plane_state->src_y = 0;
2904 plane_state->src_w = fb->width << 16;
2905 plane_state->src_h = fb->height << 16;
2906
2907 plane_state->crtc_x = 0;
2908 plane_state->crtc_y = 0;
2909 plane_state->crtc_w = fb->width;
2910 plane_state->crtc_h = fb->height;
2911
2912 intel_state->base.src = drm_plane_state_src(plane_state);
2913 intel_state->base.dst = drm_plane_state_dest(plane_state);
2914
2915 if (i915_gem_object_is_tiled(obj))
2916 dev_priv->preserve_bios_swizzle = true;
2917
2918 plane_state->fb = fb;
2919 plane_state->crtc = &intel_crtc->base;
2920
2921 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2922 &obj->frontbuffer_bits);
2923 }
2924
2925 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2926 unsigned int rotation)
2927 {
2928 int cpp = fb->format->cpp[plane];
2929
2930 switch (fb->modifier) {
2931 case DRM_FORMAT_MOD_LINEAR:
2932 case I915_FORMAT_MOD_X_TILED:
2933 switch (cpp) {
2934 case 8:
2935 return 4096;
2936 case 4:
2937 case 2:
2938 case 1:
2939 return 8192;
2940 default:
2941 MISSING_CASE(cpp);
2942 break;
2943 }
2944 break;
2945 case I915_FORMAT_MOD_Y_TILED_CCS:
2946 case I915_FORMAT_MOD_Yf_TILED_CCS:
2947 /* FIXME AUX plane? */
2948 case I915_FORMAT_MOD_Y_TILED:
2949 case I915_FORMAT_MOD_Yf_TILED:
2950 switch (cpp) {
2951 case 8:
2952 return 2048;
2953 case 4:
2954 return 4096;
2955 case 2:
2956 case 1:
2957 return 8192;
2958 default:
2959 MISSING_CASE(cpp);
2960 break;
2961 }
2962 break;
2963 default:
2964 MISSING_CASE(fb->modifier);
2965 }
2966
2967 return 2048;
2968 }
2969
2970 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
2971 int main_x, int main_y, u32 main_offset)
2972 {
2973 const struct drm_framebuffer *fb = plane_state->base.fb;
2974 int hsub = fb->format->hsub;
2975 int vsub = fb->format->vsub;
2976 int aux_x = plane_state->aux.x;
2977 int aux_y = plane_state->aux.y;
2978 u32 aux_offset = plane_state->aux.offset;
2979 u32 alignment = intel_surf_alignment(fb, 1);
2980
2981 while (aux_offset >= main_offset && aux_y <= main_y) {
2982 int x, y;
2983
2984 if (aux_x == main_x && aux_y == main_y)
2985 break;
2986
2987 if (aux_offset == 0)
2988 break;
2989
2990 x = aux_x / hsub;
2991 y = aux_y / vsub;
2992 aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1,
2993 aux_offset, aux_offset - alignment);
2994 aux_x = x * hsub + aux_x % hsub;
2995 aux_y = y * vsub + aux_y % vsub;
2996 }
2997
2998 if (aux_x != main_x || aux_y != main_y)
2999 return false;
3000
3001 plane_state->aux.offset = aux_offset;
3002 plane_state->aux.x = aux_x;
3003 plane_state->aux.y = aux_y;
3004
3005 return true;
3006 }
3007
3008 static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
3009 struct intel_plane_state *plane_state)
3010 {
3011 struct drm_i915_private *dev_priv =
3012 to_i915(plane_state->base.plane->dev);
3013 const struct drm_framebuffer *fb = plane_state->base.fb;
3014 unsigned int rotation = plane_state->base.rotation;
3015 int x = plane_state->base.src.x1 >> 16;
3016 int y = plane_state->base.src.y1 >> 16;
3017 int w = drm_rect_width(&plane_state->base.src) >> 16;
3018 int h = drm_rect_height(&plane_state->base.src) >> 16;
3019 int dst_x = plane_state->base.dst.x1;
3020 int dst_w = drm_rect_width(&plane_state->base.dst);
3021 int pipe_src_w = crtc_state->pipe_src_w;
3022 int max_width = skl_max_plane_width(fb, 0, rotation);
3023 int max_height = 4096;
3024 u32 alignment, offset, aux_offset = plane_state->aux.offset;
3025
3026 if (w > max_width || h > max_height) {
3027 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3028 w, h, max_width, max_height);
3029 return -EINVAL;
3030 }
3031
3032 /*
3033 * Display WA #1175: cnl,glk
3034 * Planes other than the cursor may cause FIFO underflow and display
3035 * corruption if starting less than 4 pixels from the right edge of
3036 * the screen.
3037 * Besides the above WA fix the similar problem, where planes other
3038 * than the cursor ending less than 4 pixels from the left edge of the
3039 * screen may cause FIFO underflow and display corruption.
3040 */
3041 if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
3042 (dst_x + dst_w < 4 || dst_x > pipe_src_w - 4)) {
3043 DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n",
3044 dst_x + dst_w < 4 ? "end" : "start",
3045 dst_x + dst_w < 4 ? dst_x + dst_w : dst_x,
3046 4, pipe_src_w - 4);
3047 return -ERANGE;
3048 }
3049
3050 intel_add_fb_offsets(&x, &y, plane_state, 0);
3051 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
3052 alignment = intel_surf_alignment(fb, 0);
3053
3054 /*
3055 * AUX surface offset is specified as the distance from the
3056 * main surface offset, and it must be non-negative. Make
3057 * sure that is what we will get.
3058 */
3059 if (offset > aux_offset)
3060 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3061 offset, aux_offset & ~(alignment - 1));
3062
3063 /*
3064 * When using an X-tiled surface, the plane blows up
3065 * if the x offset + width exceed the stride.
3066 *
3067 * TODO: linear and Y-tiled seem fine, Yf untested,
3068 */
3069 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3070 int cpp = fb->format->cpp[0];
3071
3072 while ((x + w) * cpp > fb->pitches[0]) {
3073 if (offset == 0) {
3074 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3075 return -EINVAL;
3076 }
3077
3078 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3079 offset, offset - alignment);
3080 }
3081 }
3082
3083 /*
3084 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3085 * they match with the main surface x/y offsets.
3086 */
3087 if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3088 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3089 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3090 if (offset == 0)
3091 break;
3092
3093 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3094 offset, offset - alignment);
3095 }
3096
3097 if (x != plane_state->aux.x || y != plane_state->aux.y) {
3098 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3099 return -EINVAL;
3100 }
3101 }
3102
3103 plane_state->main.offset = offset;
3104 plane_state->main.x = x;
3105 plane_state->main.y = y;
3106
3107 return 0;
3108 }
3109
3110 static int
3111 skl_check_nv12_surface(const struct intel_crtc_state *crtc_state,
3112 struct intel_plane_state *plane_state)
3113 {
3114 /* Display WA #1106 */
3115 if (plane_state->base.rotation !=
3116 (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90) &&
3117 plane_state->base.rotation != DRM_MODE_ROTATE_270)
3118 return 0;
3119
3120 /*
3121 * src coordinates are rotated here.
3122 * We check height but report it as width
3123 */
3124 if (((drm_rect_height(&plane_state->base.src) >> 16) % 4) != 0) {
3125 DRM_DEBUG_KMS("src width must be multiple "
3126 "of 4 for rotated NV12\n");
3127 return -EINVAL;
3128 }
3129
3130 return 0;
3131 }
3132
3133 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3134 {
3135 const struct drm_framebuffer *fb = plane_state->base.fb;
3136 unsigned int rotation = plane_state->base.rotation;
3137 int max_width = skl_max_plane_width(fb, 1, rotation);
3138 int max_height = 4096;
3139 int x = plane_state->base.src.x1 >> 17;
3140 int y = plane_state->base.src.y1 >> 17;
3141 int w = drm_rect_width(&plane_state->base.src) >> 17;
3142 int h = drm_rect_height(&plane_state->base.src) >> 17;
3143 u32 offset;
3144
3145 intel_add_fb_offsets(&x, &y, plane_state, 1);
3146 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3147
3148 /* FIXME not quite sure how/if these apply to the chroma plane */
3149 if (w > max_width || h > max_height) {
3150 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3151 w, h, max_width, max_height);
3152 return -EINVAL;
3153 }
3154
3155 plane_state->aux.offset = offset;
3156 plane_state->aux.x = x;
3157 plane_state->aux.y = y;
3158
3159 return 0;
3160 }
3161
3162 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3163 {
3164 const struct drm_framebuffer *fb = plane_state->base.fb;
3165 int src_x = plane_state->base.src.x1 >> 16;
3166 int src_y = plane_state->base.src.y1 >> 16;
3167 int hsub = fb->format->hsub;
3168 int vsub = fb->format->vsub;
3169 int x = src_x / hsub;
3170 int y = src_y / vsub;
3171 u32 offset;
3172
3173 if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) {
3174 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n",
3175 plane_state->base.rotation);
3176 return -EINVAL;
3177 }
3178
3179 intel_add_fb_offsets(&x, &y, plane_state, 1);
3180 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3181
3182 plane_state->aux.offset = offset;
3183 plane_state->aux.x = x * hsub + src_x % hsub;
3184 plane_state->aux.y = y * vsub + src_y % vsub;
3185
3186 return 0;
3187 }
3188
3189 int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
3190 struct intel_plane_state *plane_state)
3191 {
3192 const struct drm_framebuffer *fb = plane_state->base.fb;
3193 unsigned int rotation = plane_state->base.rotation;
3194 int ret;
3195
3196 if (rotation & DRM_MODE_REFLECT_X &&
3197 fb->modifier == DRM_FORMAT_MOD_LINEAR) {
3198 DRM_DEBUG_KMS("horizontal flip is not supported with linear surface formats\n");
3199 return -EINVAL;
3200 }
3201
3202 if (!plane_state->base.visible)
3203 return 0;
3204
3205 /* Rotate src coordinates to match rotated GTT view */
3206 if (drm_rotation_90_or_270(rotation))
3207 drm_rect_rotate(&plane_state->base.src,
3208 fb->width << 16, fb->height << 16,
3209 DRM_MODE_ROTATE_270);
3210
3211 /*
3212 * Handle the AUX surface first since
3213 * the main surface setup depends on it.
3214 */
3215 if (fb->format->format == DRM_FORMAT_NV12) {
3216 ret = skl_check_nv12_surface(crtc_state, plane_state);
3217 if (ret)
3218 return ret;
3219 ret = skl_check_nv12_aux_surface(plane_state);
3220 if (ret)
3221 return ret;
3222 } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3223 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3224 ret = skl_check_ccs_aux_surface(plane_state);
3225 if (ret)
3226 return ret;
3227 } else {
3228 plane_state->aux.offset = ~0xfff;
3229 plane_state->aux.x = 0;
3230 plane_state->aux.y = 0;
3231 }
3232
3233 ret = skl_check_main_surface(crtc_state, plane_state);
3234 if (ret)
3235 return ret;
3236
3237 return 0;
3238 }
3239
3240 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3241 const struct intel_plane_state *plane_state)
3242 {
3243 struct drm_i915_private *dev_priv =
3244 to_i915(plane_state->base.plane->dev);
3245 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3246 const struct drm_framebuffer *fb = plane_state->base.fb;
3247 unsigned int rotation = plane_state->base.rotation;
3248 u32 dspcntr;
3249
3250 dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
3251
3252 if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
3253 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
3254 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3255
3256 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3257 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3258
3259 if (INTEL_GEN(dev_priv) < 5)
3260 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3261
3262 switch (fb->format->format) {
3263 case DRM_FORMAT_C8:
3264 dspcntr |= DISPPLANE_8BPP;
3265 break;
3266 case DRM_FORMAT_XRGB1555:
3267 dspcntr |= DISPPLANE_BGRX555;
3268 break;
3269 case DRM_FORMAT_RGB565:
3270 dspcntr |= DISPPLANE_BGRX565;
3271 break;
3272 case DRM_FORMAT_XRGB8888:
3273 dspcntr |= DISPPLANE_BGRX888;
3274 break;
3275 case DRM_FORMAT_XBGR8888:
3276 dspcntr |= DISPPLANE_RGBX888;
3277 break;
3278 case DRM_FORMAT_XRGB2101010:
3279 dspcntr |= DISPPLANE_BGRX101010;
3280 break;
3281 case DRM_FORMAT_XBGR2101010:
3282 dspcntr |= DISPPLANE_RGBX101010;
3283 break;
3284 default:
3285 MISSING_CASE(fb->format->format);
3286 return 0;
3287 }
3288
3289 if (INTEL_GEN(dev_priv) >= 4 &&
3290 fb->modifier == I915_FORMAT_MOD_X_TILED)
3291 dspcntr |= DISPPLANE_TILED;
3292
3293 if (rotation & DRM_MODE_ROTATE_180)
3294 dspcntr |= DISPPLANE_ROTATE_180;
3295
3296 if (rotation & DRM_MODE_REFLECT_X)
3297 dspcntr |= DISPPLANE_MIRROR;
3298
3299 return dspcntr;
3300 }
3301
3302 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3303 {
3304 struct drm_i915_private *dev_priv =
3305 to_i915(plane_state->base.plane->dev);
3306 int src_x = plane_state->base.src.x1 >> 16;
3307 int src_y = plane_state->base.src.y1 >> 16;
3308 u32 offset;
3309
3310 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3311
3312 if (INTEL_GEN(dev_priv) >= 4)
3313 offset = intel_compute_tile_offset(&src_x, &src_y,
3314 plane_state, 0);
3315 else
3316 offset = 0;
3317
3318 /* HSW/BDW do this automagically in hardware */
3319 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3320 unsigned int rotation = plane_state->base.rotation;
3321 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3322 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3323
3324 if (rotation & DRM_MODE_ROTATE_180) {
3325 src_x += src_w - 1;
3326 src_y += src_h - 1;
3327 } else if (rotation & DRM_MODE_REFLECT_X) {
3328 src_x += src_w - 1;
3329 }
3330 }
3331
3332 plane_state->main.offset = offset;
3333 plane_state->main.x = src_x;
3334 plane_state->main.y = src_y;
3335
3336 return 0;
3337 }
3338
3339 static void i9xx_update_plane(struct intel_plane *plane,
3340 const struct intel_crtc_state *crtc_state,
3341 const struct intel_plane_state *plane_state)
3342 {
3343 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3344 const struct drm_framebuffer *fb = plane_state->base.fb;
3345 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3346 u32 linear_offset;
3347 u32 dspcntr = plane_state->ctl;
3348 i915_reg_t reg = DSPCNTR(i9xx_plane);
3349 int x = plane_state->main.x;
3350 int y = plane_state->main.y;
3351 unsigned long irqflags;
3352 u32 dspaddr_offset;
3353
3354 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3355
3356 if (INTEL_GEN(dev_priv) >= 4)
3357 dspaddr_offset = plane_state->main.offset;
3358 else
3359 dspaddr_offset = linear_offset;
3360
3361 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3362
3363 if (INTEL_GEN(dev_priv) < 4) {
3364 /* pipesrc and dspsize control the size that is scaled from,
3365 * which should always be the user's requested size.
3366 */
3367 I915_WRITE_FW(DSPSIZE(i9xx_plane),
3368 ((crtc_state->pipe_src_h - 1) << 16) |
3369 (crtc_state->pipe_src_w - 1));
3370 I915_WRITE_FW(DSPPOS(i9xx_plane), 0);
3371 } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
3372 I915_WRITE_FW(PRIMSIZE(i9xx_plane),
3373 ((crtc_state->pipe_src_h - 1) << 16) |
3374 (crtc_state->pipe_src_w - 1));
3375 I915_WRITE_FW(PRIMPOS(i9xx_plane), 0);
3376 I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
3377 }
3378
3379 I915_WRITE_FW(reg, dspcntr);
3380
3381 I915_WRITE_FW(DSPSTRIDE(i9xx_plane), fb->pitches[0]);
3382 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3383 I915_WRITE_FW(DSPSURF(i9xx_plane),
3384 intel_plane_ggtt_offset(plane_state) +
3385 dspaddr_offset);
3386 I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
3387 } else if (INTEL_GEN(dev_priv) >= 4) {
3388 I915_WRITE_FW(DSPSURF(i9xx_plane),
3389 intel_plane_ggtt_offset(plane_state) +
3390 dspaddr_offset);
3391 I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x);
3392 I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset);
3393 } else {
3394 I915_WRITE_FW(DSPADDR(i9xx_plane),
3395 intel_plane_ggtt_offset(plane_state) +
3396 dspaddr_offset);
3397 }
3398 POSTING_READ_FW(reg);
3399
3400 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3401 }
3402
3403 static void i9xx_disable_plane(struct intel_plane *plane,
3404 struct intel_crtc *crtc)
3405 {
3406 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3407 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3408 unsigned long irqflags;
3409
3410 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3411
3412 I915_WRITE_FW(DSPCNTR(i9xx_plane), 0);
3413 if (INTEL_GEN(dev_priv) >= 4)
3414 I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
3415 else
3416 I915_WRITE_FW(DSPADDR(i9xx_plane), 0);
3417 POSTING_READ_FW(DSPCNTR(i9xx_plane));
3418
3419 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3420 }
3421
3422 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
3423 enum pipe *pipe)
3424 {
3425 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3426 enum intel_display_power_domain power_domain;
3427 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3428 bool ret;
3429 u32 val;
3430
3431 /*
3432 * Not 100% correct for planes that can move between pipes,
3433 * but that's only the case for gen2-4 which don't have any
3434 * display power wells.
3435 */
3436 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
3437 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3438 return false;
3439
3440 val = I915_READ(DSPCNTR(i9xx_plane));
3441
3442 ret = val & DISPLAY_PLANE_ENABLE;
3443
3444 if (INTEL_GEN(dev_priv) >= 5)
3445 *pipe = plane->pipe;
3446 else
3447 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
3448 DISPPLANE_SEL_PIPE_SHIFT;
3449
3450 intel_display_power_put(dev_priv, power_domain);
3451
3452 return ret;
3453 }
3454
3455 static u32
3456 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3457 {
3458 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3459 return 64;
3460 else
3461 return intel_tile_width_bytes(fb, plane);
3462 }
3463
3464 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3465 {
3466 struct drm_device *dev = intel_crtc->base.dev;
3467 struct drm_i915_private *dev_priv = to_i915(dev);
3468
3469 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3470 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3471 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3472 }
3473
3474 /*
3475 * This function detaches (aka. unbinds) unused scalers in hardware
3476 */
3477 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3478 {
3479 struct intel_crtc_scaler_state *scaler_state;
3480 int i;
3481
3482 scaler_state = &intel_crtc->config->scaler_state;
3483
3484 /* loop through and disable scalers that aren't in use */
3485 for (i = 0; i < intel_crtc->num_scalers; i++) {
3486 if (!scaler_state->scalers[i].in_use)
3487 skl_detach_scaler(intel_crtc, i);
3488 }
3489 }
3490
3491 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3492 unsigned int rotation)
3493 {
3494 u32 stride;
3495
3496 if (plane >= fb->format->num_planes)
3497 return 0;
3498
3499 stride = intel_fb_pitch(fb, plane, rotation);
3500
3501 /*
3502 * The stride is either expressed as a multiple of 64 bytes chunks for
3503 * linear buffers or in number of tiles for tiled buffers.
3504 */
3505 if (drm_rotation_90_or_270(rotation))
3506 stride /= intel_tile_height(fb, plane);
3507 else
3508 stride /= intel_fb_stride_alignment(fb, plane);
3509
3510 return stride;
3511 }
3512
3513 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3514 {
3515 switch (pixel_format) {
3516 case DRM_FORMAT_C8:
3517 return PLANE_CTL_FORMAT_INDEXED;
3518 case DRM_FORMAT_RGB565:
3519 return PLANE_CTL_FORMAT_RGB_565;
3520 case DRM_FORMAT_XBGR8888:
3521 case DRM_FORMAT_ABGR8888:
3522 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3523 case DRM_FORMAT_XRGB8888:
3524 case DRM_FORMAT_ARGB8888:
3525 return PLANE_CTL_FORMAT_XRGB_8888;
3526 case DRM_FORMAT_XRGB2101010:
3527 return PLANE_CTL_FORMAT_XRGB_2101010;
3528 case DRM_FORMAT_XBGR2101010:
3529 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3530 case DRM_FORMAT_YUYV:
3531 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3532 case DRM_FORMAT_YVYU:
3533 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3534 case DRM_FORMAT_UYVY:
3535 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3536 case DRM_FORMAT_VYUY:
3537 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3538 case DRM_FORMAT_NV12:
3539 return PLANE_CTL_FORMAT_NV12;
3540 default:
3541 MISSING_CASE(pixel_format);
3542 }
3543
3544 return 0;
3545 }
3546
3547 /*
3548 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3549 * to be already pre-multiplied. We need to add a knob (or a different
3550 * DRM_FORMAT) for user-space to configure that.
3551 */
3552 static u32 skl_plane_ctl_alpha(uint32_t pixel_format)
3553 {
3554 switch (pixel_format) {
3555 case DRM_FORMAT_ABGR8888:
3556 case DRM_FORMAT_ARGB8888:
3557 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3558 default:
3559 return PLANE_CTL_ALPHA_DISABLE;
3560 }
3561 }
3562
3563 static u32 glk_plane_color_ctl_alpha(uint32_t pixel_format)
3564 {
3565 switch (pixel_format) {
3566 case DRM_FORMAT_ABGR8888:
3567 case DRM_FORMAT_ARGB8888:
3568 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
3569 default:
3570 return PLANE_COLOR_ALPHA_DISABLE;
3571 }
3572 }
3573
3574 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3575 {
3576 switch (fb_modifier) {
3577 case DRM_FORMAT_MOD_LINEAR:
3578 break;
3579 case I915_FORMAT_MOD_X_TILED:
3580 return PLANE_CTL_TILED_X;
3581 case I915_FORMAT_MOD_Y_TILED:
3582 return PLANE_CTL_TILED_Y;
3583 case I915_FORMAT_MOD_Y_TILED_CCS:
3584 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
3585 case I915_FORMAT_MOD_Yf_TILED:
3586 return PLANE_CTL_TILED_YF;
3587 case I915_FORMAT_MOD_Yf_TILED_CCS:
3588 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
3589 default:
3590 MISSING_CASE(fb_modifier);
3591 }
3592
3593 return 0;
3594 }
3595
3596 static u32 skl_plane_ctl_rotate(unsigned int rotate)
3597 {
3598 switch (rotate) {
3599 case DRM_MODE_ROTATE_0:
3600 break;
3601 /*
3602 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3603 * while i915 HW rotation is clockwise, thats why this swapping.
3604 */
3605 case DRM_MODE_ROTATE_90:
3606 return PLANE_CTL_ROTATE_270;
3607 case DRM_MODE_ROTATE_180:
3608 return PLANE_CTL_ROTATE_180;
3609 case DRM_MODE_ROTATE_270:
3610 return PLANE_CTL_ROTATE_90;
3611 default:
3612 MISSING_CASE(rotate);
3613 }
3614
3615 return 0;
3616 }
3617
3618 static u32 cnl_plane_ctl_flip(unsigned int reflect)
3619 {
3620 switch (reflect) {
3621 case 0:
3622 break;
3623 case DRM_MODE_REFLECT_X:
3624 return PLANE_CTL_FLIP_HORIZONTAL;
3625 case DRM_MODE_REFLECT_Y:
3626 default:
3627 MISSING_CASE(reflect);
3628 }
3629
3630 return 0;
3631 }
3632
3633 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3634 const struct intel_plane_state *plane_state)
3635 {
3636 struct drm_i915_private *dev_priv =
3637 to_i915(plane_state->base.plane->dev);
3638 const struct drm_framebuffer *fb = plane_state->base.fb;
3639 unsigned int rotation = plane_state->base.rotation;
3640 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3641 u32 plane_ctl;
3642
3643 plane_ctl = PLANE_CTL_ENABLE;
3644
3645 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
3646 plane_ctl |= skl_plane_ctl_alpha(fb->format->format);
3647 plane_ctl |=
3648 PLANE_CTL_PIPE_GAMMA_ENABLE |
3649 PLANE_CTL_PIPE_CSC_ENABLE |
3650 PLANE_CTL_PLANE_GAMMA_DISABLE;
3651
3652 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
3653 plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
3654
3655 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3656 plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
3657 }
3658
3659 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3660 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3661 plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
3662
3663 if (INTEL_GEN(dev_priv) >= 10)
3664 plane_ctl |= cnl_plane_ctl_flip(rotation &
3665 DRM_MODE_REFLECT_MASK);
3666
3667 if (key->flags & I915_SET_COLORKEY_DESTINATION)
3668 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3669 else if (key->flags & I915_SET_COLORKEY_SOURCE)
3670 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3671
3672 return plane_ctl;
3673 }
3674
3675 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
3676 const struct intel_plane_state *plane_state)
3677 {
3678 struct drm_i915_private *dev_priv =
3679 to_i915(plane_state->base.plane->dev);
3680 const struct drm_framebuffer *fb = plane_state->base.fb;
3681 u32 plane_color_ctl = 0;
3682
3683 if (INTEL_GEN(dev_priv) < 11) {
3684 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
3685 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
3686 }
3687 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
3688 plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
3689
3690 if (fb->format->is_yuv) {
3691 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
3692 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
3693 else
3694 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
3695
3696 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3697 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
3698 }
3699
3700 return plane_color_ctl;
3701 }
3702
3703 static int
3704 __intel_display_resume(struct drm_device *dev,
3705 struct drm_atomic_state *state,
3706 struct drm_modeset_acquire_ctx *ctx)
3707 {
3708 struct drm_crtc_state *crtc_state;
3709 struct drm_crtc *crtc;
3710 int i, ret;
3711
3712 intel_modeset_setup_hw_state(dev, ctx);
3713 i915_redisable_vga(to_i915(dev));
3714
3715 if (!state)
3716 return 0;
3717
3718 /*
3719 * We've duplicated the state, pointers to the old state are invalid.
3720 *
3721 * Don't attempt to use the old state until we commit the duplicated state.
3722 */
3723 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3724 /*
3725 * Force recalculation even if we restore
3726 * current state. With fast modeset this may not result
3727 * in a modeset when the state is compatible.
3728 */
3729 crtc_state->mode_changed = true;
3730 }
3731
3732 /* ignore any reset values/BIOS leftovers in the WM registers */
3733 if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3734 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3735
3736 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3737
3738 WARN_ON(ret == -EDEADLK);
3739 return ret;
3740 }
3741
3742 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3743 {
3744 return intel_has_gpu_reset(dev_priv) &&
3745 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3746 }
3747
3748 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3749 {
3750 struct drm_device *dev = &dev_priv->drm;
3751 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3752 struct drm_atomic_state *state;
3753 int ret;
3754
3755 /* reset doesn't touch the display */
3756 if (!i915_modparams.force_reset_modeset_test &&
3757 !gpu_reset_clobbers_display(dev_priv))
3758 return;
3759
3760 /* We have a modeset vs reset deadlock, defensively unbreak it. */
3761 set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3762 wake_up_all(&dev_priv->gpu_error.wait_queue);
3763
3764 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
3765 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3766 i915_gem_set_wedged(dev_priv);
3767 }
3768
3769 /*
3770 * Need mode_config.mutex so that we don't
3771 * trample ongoing ->detect() and whatnot.
3772 */
3773 mutex_lock(&dev->mode_config.mutex);
3774 drm_modeset_acquire_init(ctx, 0);
3775 while (1) {
3776 ret = drm_modeset_lock_all_ctx(dev, ctx);
3777 if (ret != -EDEADLK)
3778 break;
3779
3780 drm_modeset_backoff(ctx);
3781 }
3782 /*
3783 * Disabling the crtcs gracefully seems nicer. Also the
3784 * g33 docs say we should at least disable all the planes.
3785 */
3786 state = drm_atomic_helper_duplicate_state(dev, ctx);
3787 if (IS_ERR(state)) {
3788 ret = PTR_ERR(state);
3789 DRM_ERROR("Duplicating state failed with %i\n", ret);
3790 return;
3791 }
3792
3793 ret = drm_atomic_helper_disable_all(dev, ctx);
3794 if (ret) {
3795 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3796 drm_atomic_state_put(state);
3797 return;
3798 }
3799
3800 dev_priv->modeset_restore_state = state;
3801 state->acquire_ctx = ctx;
3802 }
3803
3804 void intel_finish_reset(struct drm_i915_private *dev_priv)
3805 {
3806 struct drm_device *dev = &dev_priv->drm;
3807 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3808 struct drm_atomic_state *state;
3809 int ret;
3810
3811 /* reset doesn't touch the display */
3812 if (!test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
3813 return;
3814
3815 state = fetch_and_zero(&dev_priv->modeset_restore_state);
3816 if (!state)
3817 goto unlock;
3818
3819 /* reset doesn't touch the display */
3820 if (!gpu_reset_clobbers_display(dev_priv)) {
3821 /* for testing only restore the display */
3822 ret = __intel_display_resume(dev, state, ctx);
3823 if (ret)
3824 DRM_ERROR("Restoring old state failed with %i\n", ret);
3825 } else {
3826 /*
3827 * The display has been reset as well,
3828 * so need a full re-initialization.
3829 */
3830 intel_runtime_pm_disable_interrupts(dev_priv);
3831 intel_runtime_pm_enable_interrupts(dev_priv);
3832
3833 intel_pps_unlock_regs_wa(dev_priv);
3834 intel_modeset_init_hw(dev);
3835 intel_init_clock_gating(dev_priv);
3836
3837 spin_lock_irq(&dev_priv->irq_lock);
3838 if (dev_priv->display.hpd_irq_setup)
3839 dev_priv->display.hpd_irq_setup(dev_priv);
3840 spin_unlock_irq(&dev_priv->irq_lock);
3841
3842 ret = __intel_display_resume(dev, state, ctx);
3843 if (ret)
3844 DRM_ERROR("Restoring old state failed with %i\n", ret);
3845
3846 intel_hpd_init(dev_priv);
3847 }
3848
3849 drm_atomic_state_put(state);
3850 unlock:
3851 drm_modeset_drop_locks(ctx);
3852 drm_modeset_acquire_fini(ctx);
3853 mutex_unlock(&dev->mode_config.mutex);
3854
3855 clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3856 }
3857
3858 static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
3859 const struct intel_crtc_state *new_crtc_state)
3860 {
3861 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
3862 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3863
3864 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3865 crtc->base.mode = new_crtc_state->base.mode;
3866
3867 /*
3868 * Update pipe size and adjust fitter if needed: the reason for this is
3869 * that in compute_mode_changes we check the native mode (not the pfit
3870 * mode) to see if we can flip rather than do a full mode set. In the
3871 * fastboot case, we'll flip, but if we don't update the pipesrc and
3872 * pfit state, we'll end up with a big fb scanned out into the wrong
3873 * sized surface.
3874 */
3875
3876 I915_WRITE(PIPESRC(crtc->pipe),
3877 ((new_crtc_state->pipe_src_w - 1) << 16) |
3878 (new_crtc_state->pipe_src_h - 1));
3879
3880 /* on skylake this is done by detaching scalers */
3881 if (INTEL_GEN(dev_priv) >= 9) {
3882 skl_detach_scalers(crtc);
3883
3884 if (new_crtc_state->pch_pfit.enabled)
3885 skylake_pfit_enable(crtc);
3886 } else if (HAS_PCH_SPLIT(dev_priv)) {
3887 if (new_crtc_state->pch_pfit.enabled)
3888 ironlake_pfit_enable(crtc);
3889 else if (old_crtc_state->pch_pfit.enabled)
3890 ironlake_pfit_disable(crtc, true);
3891 }
3892 }
3893
3894 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3895 {
3896 struct drm_device *dev = crtc->base.dev;
3897 struct drm_i915_private *dev_priv = to_i915(dev);
3898 int pipe = crtc->pipe;
3899 i915_reg_t reg;
3900 u32 temp;
3901
3902 /* enable normal train */
3903 reg = FDI_TX_CTL(pipe);
3904 temp = I915_READ(reg);
3905 if (IS_IVYBRIDGE(dev_priv)) {
3906 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3907 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3908 } else {
3909 temp &= ~FDI_LINK_TRAIN_NONE;
3910 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3911 }
3912 I915_WRITE(reg, temp);
3913
3914 reg = FDI_RX_CTL(pipe);
3915 temp = I915_READ(reg);
3916 if (HAS_PCH_CPT(dev_priv)) {
3917 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3918 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3919 } else {
3920 temp &= ~FDI_LINK_TRAIN_NONE;
3921 temp |= FDI_LINK_TRAIN_NONE;
3922 }
3923 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3924
3925 /* wait one idle pattern time */
3926 POSTING_READ(reg);
3927 udelay(1000);
3928
3929 /* IVB wants error correction enabled */
3930 if (IS_IVYBRIDGE(dev_priv))
3931 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3932 FDI_FE_ERRC_ENABLE);
3933 }
3934
3935 /* The FDI link training functions for ILK/Ibexpeak. */
3936 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3937 const struct intel_crtc_state *crtc_state)
3938 {
3939 struct drm_device *dev = crtc->base.dev;
3940 struct drm_i915_private *dev_priv = to_i915(dev);
3941 int pipe = crtc->pipe;
3942 i915_reg_t reg;
3943 u32 temp, tries;
3944
3945 /* FDI needs bits from pipe first */
3946 assert_pipe_enabled(dev_priv, pipe);
3947
3948 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3949 for train result */
3950 reg = FDI_RX_IMR(pipe);
3951 temp = I915_READ(reg);
3952 temp &= ~FDI_RX_SYMBOL_LOCK;
3953 temp &= ~FDI_RX_BIT_LOCK;
3954 I915_WRITE(reg, temp);
3955 I915_READ(reg);
3956 udelay(150);
3957
3958 /* enable CPU FDI TX and PCH FDI RX */
3959 reg = FDI_TX_CTL(pipe);
3960 temp = I915_READ(reg);
3961 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3962 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3963 temp &= ~FDI_LINK_TRAIN_NONE;
3964 temp |= FDI_LINK_TRAIN_PATTERN_1;
3965 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3966
3967 reg = FDI_RX_CTL(pipe);
3968 temp = I915_READ(reg);
3969 temp &= ~FDI_LINK_TRAIN_NONE;
3970 temp |= FDI_LINK_TRAIN_PATTERN_1;
3971 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3972
3973 POSTING_READ(reg);
3974 udelay(150);
3975
3976 /* Ironlake workaround, enable clock pointer after FDI enable*/
3977 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3978 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3979 FDI_RX_PHASE_SYNC_POINTER_EN);
3980
3981 reg = FDI_RX_IIR(pipe);
3982 for (tries = 0; tries < 5; tries++) {
3983 temp = I915_READ(reg);
3984 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3985
3986 if ((temp & FDI_RX_BIT_LOCK)) {
3987 DRM_DEBUG_KMS("FDI train 1 done.\n");
3988 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3989 break;
3990 }
3991 }
3992 if (tries == 5)
3993 DRM_ERROR("FDI train 1 fail!\n");
3994
3995 /* Train 2 */
3996 reg = FDI_TX_CTL(pipe);
3997 temp = I915_READ(reg);
3998 temp &= ~FDI_LINK_TRAIN_NONE;
3999 temp |= FDI_LINK_TRAIN_PATTERN_2;
4000 I915_WRITE(reg, temp);
4001
4002 reg = FDI_RX_CTL(pipe);
4003 temp = I915_READ(reg);
4004 temp &= ~FDI_LINK_TRAIN_NONE;
4005 temp |= FDI_LINK_TRAIN_PATTERN_2;
4006 I915_WRITE(reg, temp);
4007
4008 POSTING_READ(reg);
4009 udelay(150);
4010
4011 reg = FDI_RX_IIR(pipe);
4012 for (tries = 0; tries < 5; tries++) {
4013 temp = I915_READ(reg);
4014 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4015
4016 if (temp & FDI_RX_SYMBOL_LOCK) {
4017 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4018 DRM_DEBUG_KMS("FDI train 2 done.\n");
4019 break;
4020 }
4021 }
4022 if (tries == 5)
4023 DRM_ERROR("FDI train 2 fail!\n");
4024
4025 DRM_DEBUG_KMS("FDI train done\n");
4026
4027 }
4028
4029 static const int snb_b_fdi_train_param[] = {
4030 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
4031 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
4032 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
4033 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
4034 };
4035
4036 /* The FDI link training functions for SNB/Cougarpoint. */
4037 static void gen6_fdi_link_train(struct intel_crtc *crtc,
4038 const struct intel_crtc_state *crtc_state)
4039 {
4040 struct drm_device *dev = crtc->base.dev;
4041 struct drm_i915_private *dev_priv = to_i915(dev);
4042 int pipe = crtc->pipe;
4043 i915_reg_t reg;
4044 u32 temp, i, retry;
4045
4046 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4047 for train result */
4048 reg = FDI_RX_IMR(pipe);
4049 temp = I915_READ(reg);
4050 temp &= ~FDI_RX_SYMBOL_LOCK;
4051 temp &= ~FDI_RX_BIT_LOCK;
4052 I915_WRITE(reg, temp);
4053
4054 POSTING_READ(reg);
4055 udelay(150);
4056
4057 /* enable CPU FDI TX and PCH FDI RX */
4058 reg = FDI_TX_CTL(pipe);
4059 temp = I915_READ(reg);
4060 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4061 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4062 temp &= ~FDI_LINK_TRAIN_NONE;
4063 temp |= FDI_LINK_TRAIN_PATTERN_1;
4064 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4065 /* SNB-B */
4066 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4067 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4068
4069 I915_WRITE(FDI_RX_MISC(pipe),
4070 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4071
4072 reg = FDI_RX_CTL(pipe);
4073 temp = I915_READ(reg);
4074 if (HAS_PCH_CPT(dev_priv)) {
4075 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4076 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4077 } else {
4078 temp &= ~FDI_LINK_TRAIN_NONE;
4079 temp |= FDI_LINK_TRAIN_PATTERN_1;
4080 }
4081 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4082
4083 POSTING_READ(reg);
4084 udelay(150);
4085
4086 for (i = 0; i < 4; i++) {
4087 reg = FDI_TX_CTL(pipe);
4088 temp = I915_READ(reg);
4089 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4090 temp |= snb_b_fdi_train_param[i];
4091 I915_WRITE(reg, temp);
4092
4093 POSTING_READ(reg);
4094 udelay(500);
4095
4096 for (retry = 0; retry < 5; retry++) {
4097 reg = FDI_RX_IIR(pipe);
4098 temp = I915_READ(reg);
4099 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4100 if (temp & FDI_RX_BIT_LOCK) {
4101 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4102 DRM_DEBUG_KMS("FDI train 1 done.\n");
4103 break;
4104 }
4105 udelay(50);
4106 }
4107 if (retry < 5)
4108 break;
4109 }
4110 if (i == 4)
4111 DRM_ERROR("FDI train 1 fail!\n");
4112
4113 /* Train 2 */
4114 reg = FDI_TX_CTL(pipe);
4115 temp = I915_READ(reg);
4116 temp &= ~FDI_LINK_TRAIN_NONE;
4117 temp |= FDI_LINK_TRAIN_PATTERN_2;
4118 if (IS_GEN6(dev_priv)) {
4119 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4120 /* SNB-B */
4121 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4122 }
4123 I915_WRITE(reg, temp);
4124
4125 reg = FDI_RX_CTL(pipe);
4126 temp = I915_READ(reg);
4127 if (HAS_PCH_CPT(dev_priv)) {
4128 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4129 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4130 } else {
4131 temp &= ~FDI_LINK_TRAIN_NONE;
4132 temp |= FDI_LINK_TRAIN_PATTERN_2;
4133 }
4134 I915_WRITE(reg, temp);
4135
4136 POSTING_READ(reg);
4137 udelay(150);
4138
4139 for (i = 0; i < 4; i++) {
4140 reg = FDI_TX_CTL(pipe);
4141 temp = I915_READ(reg);
4142 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4143 temp |= snb_b_fdi_train_param[i];
4144 I915_WRITE(reg, temp);
4145
4146 POSTING_READ(reg);
4147 udelay(500);
4148
4149 for (retry = 0; retry < 5; retry++) {
4150 reg = FDI_RX_IIR(pipe);
4151 temp = I915_READ(reg);
4152 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4153 if (temp & FDI_RX_SYMBOL_LOCK) {
4154 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4155 DRM_DEBUG_KMS("FDI train 2 done.\n");
4156 break;
4157 }
4158 udelay(50);
4159 }
4160 if (retry < 5)
4161 break;
4162 }
4163 if (i == 4)
4164 DRM_ERROR("FDI train 2 fail!\n");
4165
4166 DRM_DEBUG_KMS("FDI train done.\n");
4167 }
4168
4169 /* Manual link training for Ivy Bridge A0 parts */
4170 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4171 const struct intel_crtc_state *crtc_state)
4172 {
4173 struct drm_device *dev = crtc->base.dev;
4174 struct drm_i915_private *dev_priv = to_i915(dev);
4175 int pipe = crtc->pipe;
4176 i915_reg_t reg;
4177 u32 temp, i, j;
4178
4179 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4180 for train result */
4181 reg = FDI_RX_IMR(pipe);
4182 temp = I915_READ(reg);
4183 temp &= ~FDI_RX_SYMBOL_LOCK;
4184 temp &= ~FDI_RX_BIT_LOCK;
4185 I915_WRITE(reg, temp);
4186
4187 POSTING_READ(reg);
4188 udelay(150);
4189
4190 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4191 I915_READ(FDI_RX_IIR(pipe)));
4192
4193 /* Try each vswing and preemphasis setting twice before moving on */
4194 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4195 /* disable first in case we need to retry */
4196 reg = FDI_TX_CTL(pipe);
4197 temp = I915_READ(reg);
4198 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4199 temp &= ~FDI_TX_ENABLE;
4200 I915_WRITE(reg, temp);
4201
4202 reg = FDI_RX_CTL(pipe);
4203 temp = I915_READ(reg);
4204 temp &= ~FDI_LINK_TRAIN_AUTO;
4205 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4206 temp &= ~FDI_RX_ENABLE;
4207 I915_WRITE(reg, temp);
4208
4209 /* enable CPU FDI TX and PCH FDI RX */
4210 reg = FDI_TX_CTL(pipe);
4211 temp = I915_READ(reg);
4212 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4213 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4214 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4215 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4216 temp |= snb_b_fdi_train_param[j/2];
4217 temp |= FDI_COMPOSITE_SYNC;
4218 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4219
4220 I915_WRITE(FDI_RX_MISC(pipe),
4221 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4222
4223 reg = FDI_RX_CTL(pipe);
4224 temp = I915_READ(reg);
4225 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4226 temp |= FDI_COMPOSITE_SYNC;
4227 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4228
4229 POSTING_READ(reg);
4230 udelay(1); /* should be 0.5us */
4231
4232 for (i = 0; i < 4; i++) {
4233 reg = FDI_RX_IIR(pipe);
4234 temp = I915_READ(reg);
4235 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4236
4237 if (temp & FDI_RX_BIT_LOCK ||
4238 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4239 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4240 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4241 i);
4242 break;
4243 }
4244 udelay(1); /* should be 0.5us */
4245 }
4246 if (i == 4) {
4247 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4248 continue;
4249 }
4250
4251 /* Train 2 */
4252 reg = FDI_TX_CTL(pipe);
4253 temp = I915_READ(reg);
4254 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4255 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4256 I915_WRITE(reg, temp);
4257
4258 reg = FDI_RX_CTL(pipe);
4259 temp = I915_READ(reg);
4260 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4261 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4262 I915_WRITE(reg, temp);
4263
4264 POSTING_READ(reg);
4265 udelay(2); /* should be 1.5us */
4266
4267 for (i = 0; i < 4; i++) {
4268 reg = FDI_RX_IIR(pipe);
4269 temp = I915_READ(reg);
4270 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4271
4272 if (temp & FDI_RX_SYMBOL_LOCK ||
4273 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4274 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4275 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4276 i);
4277 goto train_done;
4278 }
4279 udelay(2); /* should be 1.5us */
4280 }
4281 if (i == 4)
4282 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4283 }
4284
4285 train_done:
4286 DRM_DEBUG_KMS("FDI train done.\n");
4287 }
4288
4289 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4290 {
4291 struct drm_device *dev = intel_crtc->base.dev;
4292 struct drm_i915_private *dev_priv = to_i915(dev);
4293 int pipe = intel_crtc->pipe;
4294 i915_reg_t reg;
4295 u32 temp;
4296
4297 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4298 reg = FDI_RX_CTL(pipe);
4299 temp = I915_READ(reg);
4300 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4301 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4302 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4303 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4304
4305 POSTING_READ(reg);
4306 udelay(200);
4307
4308 /* Switch from Rawclk to PCDclk */
4309 temp = I915_READ(reg);
4310 I915_WRITE(reg, temp | FDI_PCDCLK);
4311
4312 POSTING_READ(reg);
4313 udelay(200);
4314
4315 /* Enable CPU FDI TX PLL, always on for Ironlake */
4316 reg = FDI_TX_CTL(pipe);
4317 temp = I915_READ(reg);
4318 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4319 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4320
4321 POSTING_READ(reg);
4322 udelay(100);
4323 }
4324 }
4325
4326 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4327 {
4328 struct drm_device *dev = intel_crtc->base.dev;
4329 struct drm_i915_private *dev_priv = to_i915(dev);
4330 int pipe = intel_crtc->pipe;
4331 i915_reg_t reg;
4332 u32 temp;
4333
4334 /* Switch from PCDclk to Rawclk */
4335 reg = FDI_RX_CTL(pipe);
4336 temp = I915_READ(reg);
4337 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4338
4339 /* Disable CPU FDI TX PLL */
4340 reg = FDI_TX_CTL(pipe);
4341 temp = I915_READ(reg);
4342 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4343
4344 POSTING_READ(reg);
4345 udelay(100);
4346
4347 reg = FDI_RX_CTL(pipe);
4348 temp = I915_READ(reg);
4349 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4350
4351 /* Wait for the clocks to turn off. */
4352 POSTING_READ(reg);
4353 udelay(100);
4354 }
4355
4356 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4357 {
4358 struct drm_device *dev = crtc->dev;
4359 struct drm_i915_private *dev_priv = to_i915(dev);
4360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4361 int pipe = intel_crtc->pipe;
4362 i915_reg_t reg;
4363 u32 temp;
4364
4365 /* disable CPU FDI tx and PCH FDI rx */
4366 reg = FDI_TX_CTL(pipe);
4367 temp = I915_READ(reg);
4368 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4369 POSTING_READ(reg);
4370
4371 reg = FDI_RX_CTL(pipe);
4372 temp = I915_READ(reg);
4373 temp &= ~(0x7 << 16);
4374 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4375 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4376
4377 POSTING_READ(reg);
4378 udelay(100);
4379
4380 /* Ironlake workaround, disable clock pointer after downing FDI */
4381 if (HAS_PCH_IBX(dev_priv))
4382 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4383
4384 /* still set train pattern 1 */
4385 reg = FDI_TX_CTL(pipe);
4386 temp = I915_READ(reg);
4387 temp &= ~FDI_LINK_TRAIN_NONE;
4388 temp |= FDI_LINK_TRAIN_PATTERN_1;
4389 I915_WRITE(reg, temp);
4390
4391 reg = FDI_RX_CTL(pipe);
4392 temp = I915_READ(reg);
4393 if (HAS_PCH_CPT(dev_priv)) {
4394 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4395 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4396 } else {
4397 temp &= ~FDI_LINK_TRAIN_NONE;
4398 temp |= FDI_LINK_TRAIN_PATTERN_1;
4399 }
4400 /* BPC in FDI rx is consistent with that in PIPECONF */
4401 temp &= ~(0x07 << 16);
4402 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4403 I915_WRITE(reg, temp);
4404
4405 POSTING_READ(reg);
4406 udelay(100);
4407 }
4408
4409 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4410 {
4411 struct drm_crtc *crtc;
4412 bool cleanup_done;
4413
4414 drm_for_each_crtc(crtc, &dev_priv->drm) {
4415 struct drm_crtc_commit *commit;
4416 spin_lock(&crtc->commit_lock);
4417 commit = list_first_entry_or_null(&crtc->commit_list,
4418 struct drm_crtc_commit, commit_entry);
4419 cleanup_done = commit ?
4420 try_wait_for_completion(&commit->cleanup_done) : true;
4421 spin_unlock(&crtc->commit_lock);
4422
4423 if (cleanup_done)
4424 continue;
4425
4426 drm_crtc_wait_one_vblank(crtc);
4427
4428 return true;
4429 }
4430
4431 return false;
4432 }
4433
4434 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4435 {
4436 u32 temp;
4437
4438 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4439
4440 mutex_lock(&dev_priv->sb_lock);
4441
4442 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4443 temp |= SBI_SSCCTL_DISABLE;
4444 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4445
4446 mutex_unlock(&dev_priv->sb_lock);
4447 }
4448
4449 /* Program iCLKIP clock to the desired frequency */
4450 static void lpt_program_iclkip(struct intel_crtc *crtc)
4451 {
4452 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4453 int clock = crtc->config->base.adjusted_mode.crtc_clock;
4454 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4455 u32 temp;
4456
4457 lpt_disable_iclkip(dev_priv);
4458
4459 /* The iCLK virtual clock root frequency is in MHz,
4460 * but the adjusted_mode->crtc_clock in in KHz. To get the
4461 * divisors, it is necessary to divide one by another, so we
4462 * convert the virtual clock precision to KHz here for higher
4463 * precision.
4464 */
4465 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4466 u32 iclk_virtual_root_freq = 172800 * 1000;
4467 u32 iclk_pi_range = 64;
4468 u32 desired_divisor;
4469
4470 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4471 clock << auxdiv);
4472 divsel = (desired_divisor / iclk_pi_range) - 2;
4473 phaseinc = desired_divisor % iclk_pi_range;
4474
4475 /*
4476 * Near 20MHz is a corner case which is
4477 * out of range for the 7-bit divisor
4478 */
4479 if (divsel <= 0x7f)
4480 break;
4481 }
4482
4483 /* This should not happen with any sane values */
4484 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4485 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4486 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4487 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4488
4489 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4490 clock,
4491 auxdiv,
4492 divsel,
4493 phasedir,
4494 phaseinc);
4495
4496 mutex_lock(&dev_priv->sb_lock);
4497
4498 /* Program SSCDIVINTPHASE6 */
4499 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4500 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4501 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4502 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4503 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4504 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4505 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4506 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4507
4508 /* Program SSCAUXDIV */
4509 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4510 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4511 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4512 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4513
4514 /* Enable modulator and associated divider */
4515 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4516 temp &= ~SBI_SSCCTL_DISABLE;
4517 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4518
4519 mutex_unlock(&dev_priv->sb_lock);
4520
4521 /* Wait for initialization time */
4522 udelay(24);
4523
4524 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4525 }
4526
4527 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4528 {
4529 u32 divsel, phaseinc, auxdiv;
4530 u32 iclk_virtual_root_freq = 172800 * 1000;
4531 u32 iclk_pi_range = 64;
4532 u32 desired_divisor;
4533 u32 temp;
4534
4535 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4536 return 0;
4537
4538 mutex_lock(&dev_priv->sb_lock);
4539
4540 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4541 if (temp & SBI_SSCCTL_DISABLE) {
4542 mutex_unlock(&dev_priv->sb_lock);
4543 return 0;
4544 }
4545
4546 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4547 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4548 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4549 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4550 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4551
4552 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4553 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4554 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4555
4556 mutex_unlock(&dev_priv->sb_lock);
4557
4558 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4559
4560 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4561 desired_divisor << auxdiv);
4562 }
4563
4564 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4565 enum pipe pch_transcoder)
4566 {
4567 struct drm_device *dev = crtc->base.dev;
4568 struct drm_i915_private *dev_priv = to_i915(dev);
4569 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4570
4571 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4572 I915_READ(HTOTAL(cpu_transcoder)));
4573 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4574 I915_READ(HBLANK(cpu_transcoder)));
4575 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4576 I915_READ(HSYNC(cpu_transcoder)));
4577
4578 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4579 I915_READ(VTOTAL(cpu_transcoder)));
4580 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4581 I915_READ(VBLANK(cpu_transcoder)));
4582 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4583 I915_READ(VSYNC(cpu_transcoder)));
4584 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4585 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4586 }
4587
4588 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4589 {
4590 struct drm_i915_private *dev_priv = to_i915(dev);
4591 uint32_t temp;
4592
4593 temp = I915_READ(SOUTH_CHICKEN1);
4594 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4595 return;
4596
4597 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4598 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4599
4600 temp &= ~FDI_BC_BIFURCATION_SELECT;
4601 if (enable)
4602 temp |= FDI_BC_BIFURCATION_SELECT;
4603
4604 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4605 I915_WRITE(SOUTH_CHICKEN1, temp);
4606 POSTING_READ(SOUTH_CHICKEN1);
4607 }
4608
4609 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4610 {
4611 struct drm_device *dev = intel_crtc->base.dev;
4612
4613 switch (intel_crtc->pipe) {
4614 case PIPE_A:
4615 break;
4616 case PIPE_B:
4617 if (intel_crtc->config->fdi_lanes > 2)
4618 cpt_set_fdi_bc_bifurcation(dev, false);
4619 else
4620 cpt_set_fdi_bc_bifurcation(dev, true);
4621
4622 break;
4623 case PIPE_C:
4624 cpt_set_fdi_bc_bifurcation(dev, true);
4625
4626 break;
4627 default:
4628 BUG();
4629 }
4630 }
4631
4632 /*
4633 * Finds the encoder associated with the given CRTC. This can only be
4634 * used when we know that the CRTC isn't feeding multiple encoders!
4635 */
4636 static struct intel_encoder *
4637 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
4638 const struct intel_crtc_state *crtc_state)
4639 {
4640 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4641 const struct drm_connector_state *connector_state;
4642 const struct drm_connector *connector;
4643 struct intel_encoder *encoder = NULL;
4644 int num_encoders = 0;
4645 int i;
4646
4647 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4648 if (connector_state->crtc != &crtc->base)
4649 continue;
4650
4651 encoder = to_intel_encoder(connector_state->best_encoder);
4652 num_encoders++;
4653 }
4654
4655 WARN(num_encoders != 1, "%d encoders for pipe %c\n",
4656 num_encoders, pipe_name(crtc->pipe));
4657
4658 return encoder;
4659 }
4660
4661 /*
4662 * Enable PCH resources required for PCH ports:
4663 * - PCH PLLs
4664 * - FDI training & RX/TX
4665 * - update transcoder timings
4666 * - DP transcoding bits
4667 * - transcoder
4668 */
4669 static void ironlake_pch_enable(const struct intel_atomic_state *state,
4670 const struct intel_crtc_state *crtc_state)
4671 {
4672 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4673 struct drm_device *dev = crtc->base.dev;
4674 struct drm_i915_private *dev_priv = to_i915(dev);
4675 int pipe = crtc->pipe;
4676 u32 temp;
4677
4678 assert_pch_transcoder_disabled(dev_priv, pipe);
4679
4680 if (IS_IVYBRIDGE(dev_priv))
4681 ivybridge_update_fdi_bc_bifurcation(crtc);
4682
4683 /* Write the TU size bits before fdi link training, so that error
4684 * detection works. */
4685 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4686 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4687
4688 /* For PCH output, training FDI link */
4689 dev_priv->display.fdi_link_train(crtc, crtc_state);
4690
4691 /* We need to program the right clock selection before writing the pixel
4692 * mutliplier into the DPLL. */
4693 if (HAS_PCH_CPT(dev_priv)) {
4694 u32 sel;
4695
4696 temp = I915_READ(PCH_DPLL_SEL);
4697 temp |= TRANS_DPLL_ENABLE(pipe);
4698 sel = TRANS_DPLLB_SEL(pipe);
4699 if (crtc_state->shared_dpll ==
4700 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4701 temp |= sel;
4702 else
4703 temp &= ~sel;
4704 I915_WRITE(PCH_DPLL_SEL, temp);
4705 }
4706
4707 /* XXX: pch pll's can be enabled any time before we enable the PCH
4708 * transcoder, and we actually should do this to not upset any PCH
4709 * transcoder that already use the clock when we share it.
4710 *
4711 * Note that enable_shared_dpll tries to do the right thing, but
4712 * get_shared_dpll unconditionally resets the pll - we need that to have
4713 * the right LVDS enable sequence. */
4714 intel_enable_shared_dpll(crtc);
4715
4716 /* set transcoder timing, panel must allow it */
4717 assert_panel_unlocked(dev_priv, pipe);
4718 ironlake_pch_transcoder_set_timings(crtc, pipe);
4719
4720 intel_fdi_normal_train(crtc);
4721
4722 /* For PCH DP, enable TRANS_DP_CTL */
4723 if (HAS_PCH_CPT(dev_priv) &&
4724 intel_crtc_has_dp_encoder(crtc_state)) {
4725 const struct drm_display_mode *adjusted_mode =
4726 &crtc_state->base.adjusted_mode;
4727 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4728 i915_reg_t reg = TRANS_DP_CTL(pipe);
4729 enum port port;
4730
4731 temp = I915_READ(reg);
4732 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4733 TRANS_DP_SYNC_MASK |
4734 TRANS_DP_BPC_MASK);
4735 temp |= TRANS_DP_OUTPUT_ENABLE;
4736 temp |= bpc << 9; /* same format but at 11:9 */
4737
4738 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4739 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4740 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4741 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4742
4743 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
4744 WARN_ON(port < PORT_B || port > PORT_D);
4745 temp |= TRANS_DP_PORT_SEL(port);
4746
4747 I915_WRITE(reg, temp);
4748 }
4749
4750 ironlake_enable_pch_transcoder(dev_priv, pipe);
4751 }
4752
4753 static void lpt_pch_enable(const struct intel_atomic_state *state,
4754 const struct intel_crtc_state *crtc_state)
4755 {
4756 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4757 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4758 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4759
4760 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4761
4762 lpt_program_iclkip(crtc);
4763
4764 /* Set transcoder timing. */
4765 ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4766
4767 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4768 }
4769
4770 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4771 {
4772 struct drm_i915_private *dev_priv = to_i915(dev);
4773 i915_reg_t dslreg = PIPEDSL(pipe);
4774 u32 temp;
4775
4776 temp = I915_READ(dslreg);
4777 udelay(500);
4778 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4779 if (wait_for(I915_READ(dslreg) != temp, 5))
4780 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4781 }
4782 }
4783
4784 /*
4785 * The hardware phase 0.0 refers to the center of the pixel.
4786 * We want to start from the top/left edge which is phase
4787 * -0.5. That matches how the hardware calculates the scaling
4788 * factors (from top-left of the first pixel to bottom-right
4789 * of the last pixel, as opposed to the pixel centers).
4790 *
4791 * For 4:2:0 subsampled chroma planes we obviously have to
4792 * adjust that so that the chroma sample position lands in
4793 * the right spot.
4794 *
4795 * Note that for packed YCbCr 4:2:2 formats there is no way to
4796 * control chroma siting. The hardware simply replicates the
4797 * chroma samples for both of the luma samples, and thus we don't
4798 * actually get the expected MPEG2 chroma siting convention :(
4799 * The same behaviour is observed on pre-SKL platforms as well.
4800 */
4801 u16 skl_scaler_calc_phase(int sub, bool chroma_cosited)
4802 {
4803 int phase = -0x8000;
4804 u16 trip = 0;
4805
4806 if (chroma_cosited)
4807 phase += (sub - 1) * 0x8000 / sub;
4808
4809 if (phase < 0)
4810 phase = 0x10000 + phase;
4811 else
4812 trip = PS_PHASE_TRIP;
4813
4814 return ((phase >> 2) & PS_PHASE_MASK) | trip;
4815 }
4816
4817 static int
4818 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4819 unsigned int scaler_user, int *scaler_id,
4820 int src_w, int src_h, int dst_w, int dst_h,
4821 bool plane_scaler_check,
4822 uint32_t pixel_format)
4823 {
4824 struct intel_crtc_scaler_state *scaler_state =
4825 &crtc_state->scaler_state;
4826 struct intel_crtc *intel_crtc =
4827 to_intel_crtc(crtc_state->base.crtc);
4828 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4829 const struct drm_display_mode *adjusted_mode =
4830 &crtc_state->base.adjusted_mode;
4831 int need_scaling;
4832
4833 /*
4834 * Src coordinates are already rotated by 270 degrees for
4835 * the 90/270 degree plane rotation cases (to match the
4836 * GTT mapping), hence no need to account for rotation here.
4837 */
4838 need_scaling = src_w != dst_w || src_h != dst_h;
4839
4840 if (plane_scaler_check)
4841 if (pixel_format == DRM_FORMAT_NV12)
4842 need_scaling = true;
4843
4844 if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
4845 need_scaling = true;
4846
4847 /*
4848 * Scaling/fitting not supported in IF-ID mode in GEN9+
4849 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4850 * Once NV12 is enabled, handle it here while allocating scaler
4851 * for NV12.
4852 */
4853 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4854 need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4855 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4856 return -EINVAL;
4857 }
4858
4859 /*
4860 * if plane is being disabled or scaler is no more required or force detach
4861 * - free scaler binded to this plane/crtc
4862 * - in order to do this, update crtc->scaler_usage
4863 *
4864 * Here scaler state in crtc_state is set free so that
4865 * scaler can be assigned to other user. Actual register
4866 * update to free the scaler is done in plane/panel-fit programming.
4867 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4868 */
4869 if (force_detach || !need_scaling) {
4870 if (*scaler_id >= 0) {
4871 scaler_state->scaler_users &= ~(1 << scaler_user);
4872 scaler_state->scalers[*scaler_id].in_use = 0;
4873
4874 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4875 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4876 intel_crtc->pipe, scaler_user, *scaler_id,
4877 scaler_state->scaler_users);
4878 *scaler_id = -1;
4879 }
4880 return 0;
4881 }
4882
4883 if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
4884 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
4885 DRM_DEBUG_KMS("NV12: src dimensions not met\n");
4886 return -EINVAL;
4887 }
4888
4889 /* range checks */
4890 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4891 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4892 (IS_GEN11(dev_priv) &&
4893 (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
4894 dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
4895 (!IS_GEN11(dev_priv) &&
4896 (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4897 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
4898 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4899 "size is out of scaler range\n",
4900 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4901 return -EINVAL;
4902 }
4903
4904 /* mark this plane as a scaler user in crtc_state */
4905 scaler_state->scaler_users |= (1 << scaler_user);
4906 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4907 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4908 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4909 scaler_state->scaler_users);
4910
4911 return 0;
4912 }
4913
4914 /**
4915 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4916 *
4917 * @state: crtc's scaler state
4918 *
4919 * Return
4920 * 0 - scaler_usage updated successfully
4921 * error - requested scaling cannot be supported or other error condition
4922 */
4923 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4924 {
4925 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4926
4927 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4928 &state->scaler_state.scaler_id,
4929 state->pipe_src_w, state->pipe_src_h,
4930 adjusted_mode->crtc_hdisplay,
4931 adjusted_mode->crtc_vdisplay, false, 0);
4932 }
4933
4934 /**
4935 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4936 * @crtc_state: crtc's scaler state
4937 * @plane_state: atomic plane state to update
4938 *
4939 * Return
4940 * 0 - scaler_usage updated successfully
4941 * error - requested scaling cannot be supported or other error condition
4942 */
4943 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4944 struct intel_plane_state *plane_state)
4945 {
4946
4947 struct intel_plane *intel_plane =
4948 to_intel_plane(plane_state->base.plane);
4949 struct drm_framebuffer *fb = plane_state->base.fb;
4950 int ret;
4951
4952 bool force_detach = !fb || !plane_state->base.visible;
4953
4954 ret = skl_update_scaler(crtc_state, force_detach,
4955 drm_plane_index(&intel_plane->base),
4956 &plane_state->scaler_id,
4957 drm_rect_width(&plane_state->base.src) >> 16,
4958 drm_rect_height(&plane_state->base.src) >> 16,
4959 drm_rect_width(&plane_state->base.dst),
4960 drm_rect_height(&plane_state->base.dst),
4961 fb ? true : false, fb ? fb->format->format : 0);
4962
4963 if (ret || plane_state->scaler_id < 0)
4964 return ret;
4965
4966 /* check colorkey */
4967 if (plane_state->ckey.flags) {
4968 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4969 intel_plane->base.base.id,
4970 intel_plane->base.name);
4971 return -EINVAL;
4972 }
4973
4974 /* Check src format */
4975 switch (fb->format->format) {
4976 case DRM_FORMAT_RGB565:
4977 case DRM_FORMAT_XBGR8888:
4978 case DRM_FORMAT_XRGB8888:
4979 case DRM_FORMAT_ABGR8888:
4980 case DRM_FORMAT_ARGB8888:
4981 case DRM_FORMAT_XRGB2101010:
4982 case DRM_FORMAT_XBGR2101010:
4983 case DRM_FORMAT_YUYV:
4984 case DRM_FORMAT_YVYU:
4985 case DRM_FORMAT_UYVY:
4986 case DRM_FORMAT_VYUY:
4987 case DRM_FORMAT_NV12:
4988 break;
4989 default:
4990 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4991 intel_plane->base.base.id, intel_plane->base.name,
4992 fb->base.id, fb->format->format);
4993 return -EINVAL;
4994 }
4995
4996 return 0;
4997 }
4998
4999 static void skylake_scaler_disable(struct intel_crtc *crtc)
5000 {
5001 int i;
5002
5003 for (i = 0; i < crtc->num_scalers; i++)
5004 skl_detach_scaler(crtc, i);
5005 }
5006
5007 static void skylake_pfit_enable(struct intel_crtc *crtc)
5008 {
5009 struct drm_device *dev = crtc->base.dev;
5010 struct drm_i915_private *dev_priv = to_i915(dev);
5011 int pipe = crtc->pipe;
5012 struct intel_crtc_scaler_state *scaler_state =
5013 &crtc->config->scaler_state;
5014
5015 if (crtc->config->pch_pfit.enabled) {
5016 u16 uv_rgb_hphase, uv_rgb_vphase;
5017 int id;
5018
5019 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
5020 return;
5021
5022 uv_rgb_hphase = skl_scaler_calc_phase(1, false);
5023 uv_rgb_vphase = skl_scaler_calc_phase(1, false);
5024
5025 id = scaler_state->scaler_id;
5026 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
5027 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
5028 I915_WRITE_FW(SKL_PS_VPHASE(pipe, id),
5029 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
5030 I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
5031 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
5032 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
5033 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
5034 }
5035 }
5036
5037 static void ironlake_pfit_enable(struct intel_crtc *crtc)
5038 {
5039 struct drm_device *dev = crtc->base.dev;
5040 struct drm_i915_private *dev_priv = to_i915(dev);
5041 int pipe = crtc->pipe;
5042
5043 if (crtc->config->pch_pfit.enabled) {
5044 /* Force use of hard-coded filter coefficients
5045 * as some pre-programmed values are broken,
5046 * e.g. x201.
5047 */
5048 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
5049 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
5050 PF_PIPE_SEL_IVB(pipe));
5051 else
5052 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
5053 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
5054 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
5055 }
5056 }
5057
5058 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
5059 {
5060 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5061 struct drm_device *dev = crtc->base.dev;
5062 struct drm_i915_private *dev_priv = to_i915(dev);
5063
5064 if (!crtc_state->ips_enabled)
5065 return;
5066
5067 /*
5068 * We can only enable IPS after we enable a plane and wait for a vblank
5069 * This function is called from post_plane_update, which is run after
5070 * a vblank wait.
5071 */
5072 WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
5073
5074 if (IS_BROADWELL(dev_priv)) {
5075 mutex_lock(&dev_priv->pcu_lock);
5076 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
5077 IPS_ENABLE | IPS_PCODE_CONTROL));
5078 mutex_unlock(&dev_priv->pcu_lock);
5079 /* Quoting Art Runyan: "its not safe to expect any particular
5080 * value in IPS_CTL bit 31 after enabling IPS through the
5081 * mailbox." Moreover, the mailbox may return a bogus state,
5082 * so we need to just enable it and continue on.
5083 */
5084 } else {
5085 I915_WRITE(IPS_CTL, IPS_ENABLE);
5086 /* The bit only becomes 1 in the next vblank, so this wait here
5087 * is essentially intel_wait_for_vblank. If we don't have this
5088 * and don't wait for vblanks until the end of crtc_enable, then
5089 * the HW state readout code will complain that the expected
5090 * IPS_CTL value is not the one we read. */
5091 if (intel_wait_for_register(dev_priv,
5092 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
5093 50))
5094 DRM_ERROR("Timed out waiting for IPS enable\n");
5095 }
5096 }
5097
5098 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
5099 {
5100 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5101 struct drm_device *dev = crtc->base.dev;
5102 struct drm_i915_private *dev_priv = to_i915(dev);
5103
5104 if (!crtc_state->ips_enabled)
5105 return;
5106
5107 if (IS_BROADWELL(dev_priv)) {
5108 mutex_lock(&dev_priv->pcu_lock);
5109 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
5110 mutex_unlock(&dev_priv->pcu_lock);
5111 /*
5112 * Wait for PCODE to finish disabling IPS. The BSpec specified
5113 * 42ms timeout value leads to occasional timeouts so use 100ms
5114 * instead.
5115 */
5116 if (intel_wait_for_register(dev_priv,
5117 IPS_CTL, IPS_ENABLE, 0,
5118 100))
5119 DRM_ERROR("Timed out waiting for IPS disable\n");
5120 } else {
5121 I915_WRITE(IPS_CTL, 0);
5122 POSTING_READ(IPS_CTL);
5123 }
5124
5125 /* We need to wait for a vblank before we can disable the plane. */
5126 intel_wait_for_vblank(dev_priv, crtc->pipe);
5127 }
5128
5129 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
5130 {
5131 if (intel_crtc->overlay) {
5132 struct drm_device *dev = intel_crtc->base.dev;
5133
5134 mutex_lock(&dev->struct_mutex);
5135 (void) intel_overlay_switch_off(intel_crtc->overlay);
5136 mutex_unlock(&dev->struct_mutex);
5137 }
5138
5139 /* Let userspace switch the overlay on again. In most cases userspace
5140 * has to recompute where to put it anyway.
5141 */
5142 }
5143
5144 /**
5145 * intel_post_enable_primary - Perform operations after enabling primary plane
5146 * @crtc: the CRTC whose primary plane was just enabled
5147 * @new_crtc_state: the enabling state
5148 *
5149 * Performs potentially sleeping operations that must be done after the primary
5150 * plane is enabled, such as updating FBC and IPS. Note that this may be
5151 * called due to an explicit primary plane update, or due to an implicit
5152 * re-enable that is caused when a sprite plane is updated to no longer
5153 * completely hide the primary plane.
5154 */
5155 static void
5156 intel_post_enable_primary(struct drm_crtc *crtc,
5157 const struct intel_crtc_state *new_crtc_state)
5158 {
5159 struct drm_device *dev = crtc->dev;
5160 struct drm_i915_private *dev_priv = to_i915(dev);
5161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5162 int pipe = intel_crtc->pipe;
5163
5164 /*
5165 * Gen2 reports pipe underruns whenever all planes are disabled.
5166 * So don't enable underrun reporting before at least some planes
5167 * are enabled.
5168 * FIXME: Need to fix the logic to work when we turn off all planes
5169 * but leave the pipe running.
5170 */
5171 if (IS_GEN2(dev_priv))
5172 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5173
5174 /* Underruns don't always raise interrupts, so check manually. */
5175 intel_check_cpu_fifo_underruns(dev_priv);
5176 intel_check_pch_fifo_underruns(dev_priv);
5177 }
5178
5179 /* FIXME get rid of this and use pre_plane_update */
5180 static void
5181 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5182 {
5183 struct drm_device *dev = crtc->dev;
5184 struct drm_i915_private *dev_priv = to_i915(dev);
5185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5186 int pipe = intel_crtc->pipe;
5187
5188 /*
5189 * Gen2 reports pipe underruns whenever all planes are disabled.
5190 * So disable underrun reporting before all the planes get disabled.
5191 */
5192 if (IS_GEN2(dev_priv))
5193 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5194
5195 hsw_disable_ips(to_intel_crtc_state(crtc->state));
5196
5197 /*
5198 * Vblank time updates from the shadow to live plane control register
5199 * are blocked if the memory self-refresh mode is active at that
5200 * moment. So to make sure the plane gets truly disabled, disable
5201 * first the self-refresh mode. The self-refresh enable bit in turn
5202 * will be checked/applied by the HW only at the next frame start
5203 * event which is after the vblank start event, so we need to have a
5204 * wait-for-vblank between disabling the plane and the pipe.
5205 */
5206 if (HAS_GMCH_DISPLAY(dev_priv) &&
5207 intel_set_memory_cxsr(dev_priv, false))
5208 intel_wait_for_vblank(dev_priv, pipe);
5209 }
5210
5211 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
5212 const struct intel_crtc_state *new_crtc_state)
5213 {
5214 if (!old_crtc_state->ips_enabled)
5215 return false;
5216
5217 if (needs_modeset(&new_crtc_state->base))
5218 return true;
5219
5220 return !new_crtc_state->ips_enabled;
5221 }
5222
5223 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
5224 const struct intel_crtc_state *new_crtc_state)
5225 {
5226 if (!new_crtc_state->ips_enabled)
5227 return false;
5228
5229 if (needs_modeset(&new_crtc_state->base))
5230 return true;
5231
5232 /*
5233 * We can't read out IPS on broadwell, assume the worst and
5234 * forcibly enable IPS on the first fastset.
5235 */
5236 if (new_crtc_state->update_pipe &&
5237 old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
5238 return true;
5239
5240 return !old_crtc_state->ips_enabled;
5241 }
5242
5243 static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
5244 const struct intel_crtc_state *crtc_state)
5245 {
5246 if (!crtc_state->nv12_planes)
5247 return false;
5248
5249 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
5250 return false;
5251
5252 if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
5253 IS_CANNONLAKE(dev_priv))
5254 return true;
5255
5256 return false;
5257 }
5258
5259 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5260 {
5261 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5262 struct drm_device *dev = crtc->base.dev;
5263 struct drm_i915_private *dev_priv = to_i915(dev);
5264 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5265 struct intel_crtc_state *pipe_config =
5266 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
5267 crtc);
5268 struct drm_plane *primary = crtc->base.primary;
5269 struct drm_plane_state *old_primary_state =
5270 drm_atomic_get_old_plane_state(old_state, primary);
5271
5272 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5273
5274 if (pipe_config->update_wm_post && pipe_config->base.active)
5275 intel_update_watermarks(crtc);
5276
5277 if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
5278 hsw_enable_ips(pipe_config);
5279
5280 if (old_primary_state) {
5281 struct drm_plane_state *new_primary_state =
5282 drm_atomic_get_new_plane_state(old_state, primary);
5283
5284 intel_fbc_post_update(crtc);
5285
5286 if (new_primary_state->visible &&
5287 (needs_modeset(&pipe_config->base) ||
5288 !old_primary_state->visible))
5289 intel_post_enable_primary(&crtc->base, pipe_config);
5290 }
5291
5292 /* Display WA 827 */
5293 if (needs_nv12_wa(dev_priv, old_crtc_state) &&
5294 !needs_nv12_wa(dev_priv, pipe_config)) {
5295 skl_wa_clkgate(dev_priv, crtc->pipe, false);
5296 skl_wa_528(dev_priv, crtc->pipe, false);
5297 }
5298 }
5299
5300 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5301 struct intel_crtc_state *pipe_config)
5302 {
5303 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5304 struct drm_device *dev = crtc->base.dev;
5305 struct drm_i915_private *dev_priv = to_i915(dev);
5306 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5307 struct drm_plane *primary = crtc->base.primary;
5308 struct drm_plane_state *old_primary_state =
5309 drm_atomic_get_old_plane_state(old_state, primary);
5310 bool modeset = needs_modeset(&pipe_config->base);
5311 struct intel_atomic_state *old_intel_state =
5312 to_intel_atomic_state(old_state);
5313
5314 if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
5315 hsw_disable_ips(old_crtc_state);
5316
5317 if (old_primary_state) {
5318 struct intel_plane_state *new_primary_state =
5319 intel_atomic_get_new_plane_state(old_intel_state,
5320 to_intel_plane(primary));
5321
5322 intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
5323 /*
5324 * Gen2 reports pipe underruns whenever all planes are disabled.
5325 * So disable underrun reporting before all the planes get disabled.
5326 */
5327 if (IS_GEN2(dev_priv) && old_primary_state->visible &&
5328 (modeset || !new_primary_state->base.visible))
5329 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5330 }
5331
5332 /* Display WA 827 */
5333 if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
5334 needs_nv12_wa(dev_priv, pipe_config)) {
5335 skl_wa_clkgate(dev_priv, crtc->pipe, true);
5336 skl_wa_528(dev_priv, crtc->pipe, true);
5337 }
5338
5339 /*
5340 * Vblank time updates from the shadow to live plane control register
5341 * are blocked if the memory self-refresh mode is active at that
5342 * moment. So to make sure the plane gets truly disabled, disable
5343 * first the self-refresh mode. The self-refresh enable bit in turn
5344 * will be checked/applied by the HW only at the next frame start
5345 * event which is after the vblank start event, so we need to have a
5346 * wait-for-vblank between disabling the plane and the pipe.
5347 */
5348 if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5349 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5350 intel_wait_for_vblank(dev_priv, crtc->pipe);
5351
5352 /*
5353 * IVB workaround: must disable low power watermarks for at least
5354 * one frame before enabling scaling. LP watermarks can be re-enabled
5355 * when scaling is disabled.
5356 *
5357 * WaCxSRDisabledForSpriteScaling:ivb
5358 */
5359 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5360 intel_wait_for_vblank(dev_priv, crtc->pipe);
5361
5362 /*
5363 * If we're doing a modeset, we're done. No need to do any pre-vblank
5364 * watermark programming here.
5365 */
5366 if (needs_modeset(&pipe_config->base))
5367 return;
5368
5369 /*
5370 * For platforms that support atomic watermarks, program the
5371 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5372 * will be the intermediate values that are safe for both pre- and
5373 * post- vblank; when vblank happens, the 'active' values will be set
5374 * to the final 'target' values and we'll do this again to get the
5375 * optimal watermarks. For gen9+ platforms, the values we program here
5376 * will be the final target values which will get automatically latched
5377 * at vblank time; no further programming will be necessary.
5378 *
5379 * If a platform hasn't been transitioned to atomic watermarks yet,
5380 * we'll continue to update watermarks the old way, if flags tell
5381 * us to.
5382 */
5383 if (dev_priv->display.initial_watermarks != NULL)
5384 dev_priv->display.initial_watermarks(old_intel_state,
5385 pipe_config);
5386 else if (pipe_config->update_wm_pre)
5387 intel_update_watermarks(crtc);
5388 }
5389
5390 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5391 {
5392 struct drm_device *dev = crtc->dev;
5393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5394 struct drm_plane *p;
5395 int pipe = intel_crtc->pipe;
5396
5397 intel_crtc_dpms_overlay_disable(intel_crtc);
5398
5399 drm_for_each_plane_mask(p, dev, plane_mask)
5400 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5401
5402 /*
5403 * FIXME: Once we grow proper nuclear flip support out of this we need
5404 * to compute the mask of flip planes precisely. For the time being
5405 * consider this a flip to a NULL plane.
5406 */
5407 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5408 }
5409
5410 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5411 struct intel_crtc_state *crtc_state,
5412 struct drm_atomic_state *old_state)
5413 {
5414 struct drm_connector_state *conn_state;
5415 struct drm_connector *conn;
5416 int i;
5417
5418 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5419 struct intel_encoder *encoder =
5420 to_intel_encoder(conn_state->best_encoder);
5421
5422 if (conn_state->crtc != crtc)
5423 continue;
5424
5425 if (encoder->pre_pll_enable)
5426 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5427 }
5428 }
5429
5430 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5431 struct intel_crtc_state *crtc_state,
5432 struct drm_atomic_state *old_state)
5433 {
5434 struct drm_connector_state *conn_state;
5435 struct drm_connector *conn;
5436 int i;
5437
5438 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5439 struct intel_encoder *encoder =
5440 to_intel_encoder(conn_state->best_encoder);
5441
5442 if (conn_state->crtc != crtc)
5443 continue;
5444
5445 if (encoder->pre_enable)
5446 encoder->pre_enable(encoder, crtc_state, conn_state);
5447 }
5448 }
5449
5450 static void intel_encoders_enable(struct drm_crtc *crtc,
5451 struct intel_crtc_state *crtc_state,
5452 struct drm_atomic_state *old_state)
5453 {
5454 struct drm_connector_state *conn_state;
5455 struct drm_connector *conn;
5456 int i;
5457
5458 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5459 struct intel_encoder *encoder =
5460 to_intel_encoder(conn_state->best_encoder);
5461
5462 if (conn_state->crtc != crtc)
5463 continue;
5464
5465 encoder->enable(encoder, crtc_state, conn_state);
5466 intel_opregion_notify_encoder(encoder, true);
5467 }
5468 }
5469
5470 static void intel_encoders_disable(struct drm_crtc *crtc,
5471 struct intel_crtc_state *old_crtc_state,
5472 struct drm_atomic_state *old_state)
5473 {
5474 struct drm_connector_state *old_conn_state;
5475 struct drm_connector *conn;
5476 int i;
5477
5478 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5479 struct intel_encoder *encoder =
5480 to_intel_encoder(old_conn_state->best_encoder);
5481
5482 if (old_conn_state->crtc != crtc)
5483 continue;
5484
5485 intel_opregion_notify_encoder(encoder, false);
5486 encoder->disable(encoder, old_crtc_state, old_conn_state);
5487 }
5488 }
5489
5490 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5491 struct intel_crtc_state *old_crtc_state,
5492 struct drm_atomic_state *old_state)
5493 {
5494 struct drm_connector_state *old_conn_state;
5495 struct drm_connector *conn;
5496 int i;
5497
5498 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5499 struct intel_encoder *encoder =
5500 to_intel_encoder(old_conn_state->best_encoder);
5501
5502 if (old_conn_state->crtc != crtc)
5503 continue;
5504
5505 if (encoder->post_disable)
5506 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5507 }
5508 }
5509
5510 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5511 struct intel_crtc_state *old_crtc_state,
5512 struct drm_atomic_state *old_state)
5513 {
5514 struct drm_connector_state *old_conn_state;
5515 struct drm_connector *conn;
5516 int i;
5517
5518 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5519 struct intel_encoder *encoder =
5520 to_intel_encoder(old_conn_state->best_encoder);
5521
5522 if (old_conn_state->crtc != crtc)
5523 continue;
5524
5525 if (encoder->post_pll_disable)
5526 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5527 }
5528 }
5529
5530 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5531 struct drm_atomic_state *old_state)
5532 {
5533 struct drm_crtc *crtc = pipe_config->base.crtc;
5534 struct drm_device *dev = crtc->dev;
5535 struct drm_i915_private *dev_priv = to_i915(dev);
5536 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5537 int pipe = intel_crtc->pipe;
5538 struct intel_atomic_state *old_intel_state =
5539 to_intel_atomic_state(old_state);
5540
5541 if (WARN_ON(intel_crtc->active))
5542 return;
5543
5544 /*
5545 * Sometimes spurious CPU pipe underruns happen during FDI
5546 * training, at least with VGA+HDMI cloning. Suppress them.
5547 *
5548 * On ILK we get an occasional spurious CPU pipe underruns
5549 * between eDP port A enable and vdd enable. Also PCH port
5550 * enable seems to result in the occasional CPU pipe underrun.
5551 *
5552 * Spurious PCH underruns also occur during PCH enabling.
5553 */
5554 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5555 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5556
5557 if (intel_crtc->config->has_pch_encoder)
5558 intel_prepare_shared_dpll(intel_crtc);
5559
5560 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5561 intel_dp_set_m_n(intel_crtc, M1_N1);
5562
5563 intel_set_pipe_timings(intel_crtc);
5564 intel_set_pipe_src_size(intel_crtc);
5565
5566 if (intel_crtc->config->has_pch_encoder) {
5567 intel_cpu_transcoder_set_m_n(intel_crtc,
5568 &intel_crtc->config->fdi_m_n, NULL);
5569 }
5570
5571 ironlake_set_pipeconf(crtc);
5572
5573 intel_crtc->active = true;
5574
5575 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5576
5577 if (intel_crtc->config->has_pch_encoder) {
5578 /* Note: FDI PLL enabling _must_ be done before we enable the
5579 * cpu pipes, hence this is separate from all the other fdi/pch
5580 * enabling. */
5581 ironlake_fdi_pll_enable(intel_crtc);
5582 } else {
5583 assert_fdi_tx_disabled(dev_priv, pipe);
5584 assert_fdi_rx_disabled(dev_priv, pipe);
5585 }
5586
5587 ironlake_pfit_enable(intel_crtc);
5588
5589 /*
5590 * On ILK+ LUT must be loaded before the pipe is running but with
5591 * clocks enabled
5592 */
5593 intel_color_load_luts(&pipe_config->base);
5594
5595 if (dev_priv->display.initial_watermarks != NULL)
5596 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5597 intel_enable_pipe(pipe_config);
5598
5599 if (intel_crtc->config->has_pch_encoder)
5600 ironlake_pch_enable(old_intel_state, pipe_config);
5601
5602 assert_vblank_disabled(crtc);
5603 drm_crtc_vblank_on(crtc);
5604
5605 intel_encoders_enable(crtc, pipe_config, old_state);
5606
5607 if (HAS_PCH_CPT(dev_priv))
5608 cpt_verify_modeset(dev, intel_crtc->pipe);
5609
5610 /*
5611 * Must wait for vblank to avoid spurious PCH FIFO underruns.
5612 * And a second vblank wait is needed at least on ILK with
5613 * some interlaced HDMI modes. Let's do the double wait always
5614 * in case there are more corner cases we don't know about.
5615 */
5616 if (intel_crtc->config->has_pch_encoder) {
5617 intel_wait_for_vblank(dev_priv, pipe);
5618 intel_wait_for_vblank(dev_priv, pipe);
5619 }
5620 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5621 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5622 }
5623
5624 /* IPS only exists on ULT machines and is tied to pipe A. */
5625 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5626 {
5627 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5628 }
5629
5630 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
5631 enum pipe pipe, bool apply)
5632 {
5633 u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
5634 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
5635
5636 if (apply)
5637 val |= mask;
5638 else
5639 val &= ~mask;
5640
5641 I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
5642 }
5643
5644 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
5645 {
5646 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5647 enum pipe pipe = crtc->pipe;
5648 uint32_t val;
5649
5650 val = MBUS_DBOX_BW_CREDIT(1) | MBUS_DBOX_A_CREDIT(2);
5651
5652 /* Program B credit equally to all pipes */
5653 val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes);
5654
5655 I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
5656 }
5657
5658 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5659 struct drm_atomic_state *old_state)
5660 {
5661 struct drm_crtc *crtc = pipe_config->base.crtc;
5662 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5664 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5665 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5666 struct intel_atomic_state *old_intel_state =
5667 to_intel_atomic_state(old_state);
5668 bool psl_clkgate_wa;
5669 u32 pipe_chicken;
5670
5671 if (WARN_ON(intel_crtc->active))
5672 return;
5673
5674 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5675
5676 if (intel_crtc->config->shared_dpll)
5677 intel_enable_shared_dpll(intel_crtc);
5678
5679 if (INTEL_GEN(dev_priv) >= 11)
5680 icl_map_plls_to_ports(crtc, pipe_config, old_state);
5681
5682 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5683
5684 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5685 intel_dp_set_m_n(intel_crtc, M1_N1);
5686
5687 if (!transcoder_is_dsi(cpu_transcoder))
5688 intel_set_pipe_timings(intel_crtc);
5689
5690 intel_set_pipe_src_size(intel_crtc);
5691
5692 if (cpu_transcoder != TRANSCODER_EDP &&
5693 !transcoder_is_dsi(cpu_transcoder)) {
5694 I915_WRITE(PIPE_MULT(cpu_transcoder),
5695 intel_crtc->config->pixel_multiplier - 1);
5696 }
5697
5698 if (intel_crtc->config->has_pch_encoder) {
5699 intel_cpu_transcoder_set_m_n(intel_crtc,
5700 &intel_crtc->config->fdi_m_n, NULL);
5701 }
5702
5703 if (!transcoder_is_dsi(cpu_transcoder))
5704 haswell_set_pipeconf(crtc);
5705
5706 haswell_set_pipemisc(crtc);
5707
5708 intel_color_set_csc(&pipe_config->base);
5709
5710 intel_crtc->active = true;
5711
5712 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
5713 psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
5714 intel_crtc->config->pch_pfit.enabled;
5715 if (psl_clkgate_wa)
5716 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
5717
5718 if (INTEL_GEN(dev_priv) >= 9)
5719 skylake_pfit_enable(intel_crtc);
5720 else
5721 ironlake_pfit_enable(intel_crtc);
5722
5723 /*
5724 * On ILK+ LUT must be loaded before the pipe is running but with
5725 * clocks enabled
5726 */
5727 intel_color_load_luts(&pipe_config->base);
5728
5729 /*
5730 * Display WA #1153: enable hardware to bypass the alpha math
5731 * and rounding for per-pixel values 00 and 0xff
5732 */
5733 if (INTEL_GEN(dev_priv) >= 11) {
5734 pipe_chicken = I915_READ(PIPE_CHICKEN(pipe));
5735 if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN))
5736 I915_WRITE_FW(PIPE_CHICKEN(pipe),
5737 pipe_chicken | PER_PIXEL_ALPHA_BYPASS_EN);
5738 }
5739
5740 intel_ddi_set_pipe_settings(pipe_config);
5741 if (!transcoder_is_dsi(cpu_transcoder))
5742 intel_ddi_enable_transcoder_func(pipe_config);
5743
5744 if (dev_priv->display.initial_watermarks != NULL)
5745 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5746
5747 if (INTEL_GEN(dev_priv) >= 11)
5748 icl_pipe_mbus_enable(intel_crtc);
5749
5750 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5751 if (!transcoder_is_dsi(cpu_transcoder))
5752 intel_enable_pipe(pipe_config);
5753
5754 if (intel_crtc->config->has_pch_encoder)
5755 lpt_pch_enable(old_intel_state, pipe_config);
5756
5757 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5758 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5759
5760 assert_vblank_disabled(crtc);
5761 drm_crtc_vblank_on(crtc);
5762
5763 intel_encoders_enable(crtc, pipe_config, old_state);
5764
5765 if (psl_clkgate_wa) {
5766 intel_wait_for_vblank(dev_priv, pipe);
5767 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
5768 }
5769
5770 /* If we change the relative order between pipe/planes enabling, we need
5771 * to change the workaround. */
5772 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5773 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5774 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5775 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5776 }
5777 }
5778
5779 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5780 {
5781 struct drm_device *dev = crtc->base.dev;
5782 struct drm_i915_private *dev_priv = to_i915(dev);
5783 int pipe = crtc->pipe;
5784
5785 /* To avoid upsetting the power well on haswell only disable the pfit if
5786 * it's in use. The hw state code will make sure we get this right. */
5787 if (force || crtc->config->pch_pfit.enabled) {
5788 I915_WRITE(PF_CTL(pipe), 0);
5789 I915_WRITE(PF_WIN_POS(pipe), 0);
5790 I915_WRITE(PF_WIN_SZ(pipe), 0);
5791 }
5792 }
5793
5794 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5795 struct drm_atomic_state *old_state)
5796 {
5797 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5798 struct drm_device *dev = crtc->dev;
5799 struct drm_i915_private *dev_priv = to_i915(dev);
5800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5801 int pipe = intel_crtc->pipe;
5802
5803 /*
5804 * Sometimes spurious CPU pipe underruns happen when the
5805 * pipe is already disabled, but FDI RX/TX is still enabled.
5806 * Happens at least with VGA+HDMI cloning. Suppress them.
5807 */
5808 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5809 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5810
5811 intel_encoders_disable(crtc, old_crtc_state, old_state);
5812
5813 drm_crtc_vblank_off(crtc);
5814 assert_vblank_disabled(crtc);
5815
5816 intel_disable_pipe(old_crtc_state);
5817
5818 ironlake_pfit_disable(intel_crtc, false);
5819
5820 if (intel_crtc->config->has_pch_encoder)
5821 ironlake_fdi_disable(crtc);
5822
5823 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5824
5825 if (intel_crtc->config->has_pch_encoder) {
5826 ironlake_disable_pch_transcoder(dev_priv, pipe);
5827
5828 if (HAS_PCH_CPT(dev_priv)) {
5829 i915_reg_t reg;
5830 u32 temp;
5831
5832 /* disable TRANS_DP_CTL */
5833 reg = TRANS_DP_CTL(pipe);
5834 temp = I915_READ(reg);
5835 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5836 TRANS_DP_PORT_SEL_MASK);
5837 temp |= TRANS_DP_PORT_SEL_NONE;
5838 I915_WRITE(reg, temp);
5839
5840 /* disable DPLL_SEL */
5841 temp = I915_READ(PCH_DPLL_SEL);
5842 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5843 I915_WRITE(PCH_DPLL_SEL, temp);
5844 }
5845
5846 ironlake_fdi_pll_disable(intel_crtc);
5847 }
5848
5849 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5850 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5851 }
5852
5853 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5854 struct drm_atomic_state *old_state)
5855 {
5856 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5857 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5859 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
5860
5861 intel_encoders_disable(crtc, old_crtc_state, old_state);
5862
5863 drm_crtc_vblank_off(crtc);
5864 assert_vblank_disabled(crtc);
5865
5866 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5867 if (!transcoder_is_dsi(cpu_transcoder))
5868 intel_disable_pipe(old_crtc_state);
5869
5870 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
5871 intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
5872
5873 if (!transcoder_is_dsi(cpu_transcoder))
5874 intel_ddi_disable_transcoder_func(old_crtc_state);
5875
5876 if (INTEL_GEN(dev_priv) >= 9)
5877 skylake_scaler_disable(intel_crtc);
5878 else
5879 ironlake_pfit_disable(intel_crtc, false);
5880
5881 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5882
5883 if (INTEL_GEN(dev_priv) >= 11)
5884 icl_unmap_plls_to_ports(crtc, old_crtc_state, old_state);
5885 }
5886
5887 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5888 {
5889 struct drm_device *dev = crtc->base.dev;
5890 struct drm_i915_private *dev_priv = to_i915(dev);
5891 struct intel_crtc_state *pipe_config = crtc->config;
5892
5893 if (!pipe_config->gmch_pfit.control)
5894 return;
5895
5896 /*
5897 * The panel fitter should only be adjusted whilst the pipe is disabled,
5898 * according to register description and PRM.
5899 */
5900 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5901 assert_pipe_disabled(dev_priv, crtc->pipe);
5902
5903 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5904 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5905
5906 /* Border color in case we don't scale up to the full screen. Black by
5907 * default, change to something else for debugging. */
5908 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5909 }
5910
5911 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
5912 {
5913 if (IS_ICELAKE(dev_priv))
5914 return port >= PORT_C && port <= PORT_F;
5915
5916 return false;
5917 }
5918
5919 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
5920 {
5921 if (!intel_port_is_tc(dev_priv, port))
5922 return PORT_TC_NONE;
5923
5924 return port - PORT_C;
5925 }
5926
5927 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5928 {
5929 switch (port) {
5930 case PORT_A:
5931 return POWER_DOMAIN_PORT_DDI_A_LANES;
5932 case PORT_B:
5933 return POWER_DOMAIN_PORT_DDI_B_LANES;
5934 case PORT_C:
5935 return POWER_DOMAIN_PORT_DDI_C_LANES;
5936 case PORT_D:
5937 return POWER_DOMAIN_PORT_DDI_D_LANES;
5938 case PORT_E:
5939 return POWER_DOMAIN_PORT_DDI_E_LANES;
5940 case PORT_F:
5941 return POWER_DOMAIN_PORT_DDI_F_LANES;
5942 default:
5943 MISSING_CASE(port);
5944 return POWER_DOMAIN_PORT_OTHER;
5945 }
5946 }
5947
5948 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5949 struct intel_crtc_state *crtc_state)
5950 {
5951 struct drm_device *dev = crtc->dev;
5952 struct drm_i915_private *dev_priv = to_i915(dev);
5953 struct drm_encoder *encoder;
5954 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5955 enum pipe pipe = intel_crtc->pipe;
5956 u64 mask;
5957 enum transcoder transcoder = crtc_state->cpu_transcoder;
5958
5959 if (!crtc_state->base.active)
5960 return 0;
5961
5962 mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
5963 mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
5964 if (crtc_state->pch_pfit.enabled ||
5965 crtc_state->pch_pfit.force_thru)
5966 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5967
5968 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5969 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5970
5971 mask |= BIT_ULL(intel_encoder->power_domain);
5972 }
5973
5974 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5975 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
5976
5977 if (crtc_state->shared_dpll)
5978 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5979
5980 return mask;
5981 }
5982
5983 static u64
5984 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5985 struct intel_crtc_state *crtc_state)
5986 {
5987 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5989 enum intel_display_power_domain domain;
5990 u64 domains, new_domains, old_domains;
5991
5992 old_domains = intel_crtc->enabled_power_domains;
5993 intel_crtc->enabled_power_domains = new_domains =
5994 get_crtc_power_domains(crtc, crtc_state);
5995
5996 domains = new_domains & ~old_domains;
5997
5998 for_each_power_domain(domain, domains)
5999 intel_display_power_get(dev_priv, domain);
6000
6001 return old_domains & ~new_domains;
6002 }
6003
6004 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
6005 u64 domains)
6006 {
6007 enum intel_display_power_domain domain;
6008
6009 for_each_power_domain(domain, domains)
6010 intel_display_power_put(dev_priv, domain);
6011 }
6012
6013 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6014 struct drm_atomic_state *old_state)
6015 {
6016 struct intel_atomic_state *old_intel_state =
6017 to_intel_atomic_state(old_state);
6018 struct drm_crtc *crtc = pipe_config->base.crtc;
6019 struct drm_device *dev = crtc->dev;
6020 struct drm_i915_private *dev_priv = to_i915(dev);
6021 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6022 int pipe = intel_crtc->pipe;
6023
6024 if (WARN_ON(intel_crtc->active))
6025 return;
6026
6027 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6028 intel_dp_set_m_n(intel_crtc, M1_N1);
6029
6030 intel_set_pipe_timings(intel_crtc);
6031 intel_set_pipe_src_size(intel_crtc);
6032
6033 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
6034 struct drm_i915_private *dev_priv = to_i915(dev);
6035
6036 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6037 I915_WRITE(CHV_CANVAS(pipe), 0);
6038 }
6039
6040 i9xx_set_pipeconf(intel_crtc);
6041
6042 intel_crtc->active = true;
6043
6044 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6045
6046 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6047
6048 if (IS_CHERRYVIEW(dev_priv)) {
6049 chv_prepare_pll(intel_crtc, intel_crtc->config);
6050 chv_enable_pll(intel_crtc, intel_crtc->config);
6051 } else {
6052 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6053 vlv_enable_pll(intel_crtc, intel_crtc->config);
6054 }
6055
6056 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6057
6058 i9xx_pfit_enable(intel_crtc);
6059
6060 intel_color_load_luts(&pipe_config->base);
6061
6062 dev_priv->display.initial_watermarks(old_intel_state,
6063 pipe_config);
6064 intel_enable_pipe(pipe_config);
6065
6066 assert_vblank_disabled(crtc);
6067 drm_crtc_vblank_on(crtc);
6068
6069 intel_encoders_enable(crtc, pipe_config, old_state);
6070 }
6071
6072 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6073 {
6074 struct drm_device *dev = crtc->base.dev;
6075 struct drm_i915_private *dev_priv = to_i915(dev);
6076
6077 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6078 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6079 }
6080
6081 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6082 struct drm_atomic_state *old_state)
6083 {
6084 struct intel_atomic_state *old_intel_state =
6085 to_intel_atomic_state(old_state);
6086 struct drm_crtc *crtc = pipe_config->base.crtc;
6087 struct drm_device *dev = crtc->dev;
6088 struct drm_i915_private *dev_priv = to_i915(dev);
6089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6090 enum pipe pipe = intel_crtc->pipe;
6091
6092 if (WARN_ON(intel_crtc->active))
6093 return;
6094
6095 i9xx_set_pll_dividers(intel_crtc);
6096
6097 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6098 intel_dp_set_m_n(intel_crtc, M1_N1);
6099
6100 intel_set_pipe_timings(intel_crtc);
6101 intel_set_pipe_src_size(intel_crtc);
6102
6103 i9xx_set_pipeconf(intel_crtc);
6104
6105 intel_crtc->active = true;
6106
6107 if (!IS_GEN2(dev_priv))
6108 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6109
6110 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6111
6112 i9xx_enable_pll(intel_crtc, pipe_config);
6113
6114 i9xx_pfit_enable(intel_crtc);
6115
6116 intel_color_load_luts(&pipe_config->base);
6117
6118 if (dev_priv->display.initial_watermarks != NULL)
6119 dev_priv->display.initial_watermarks(old_intel_state,
6120 intel_crtc->config);
6121 else
6122 intel_update_watermarks(intel_crtc);
6123 intel_enable_pipe(pipe_config);
6124
6125 assert_vblank_disabled(crtc);
6126 drm_crtc_vblank_on(crtc);
6127
6128 intel_encoders_enable(crtc, pipe_config, old_state);
6129 }
6130
6131 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6132 {
6133 struct drm_device *dev = crtc->base.dev;
6134 struct drm_i915_private *dev_priv = to_i915(dev);
6135
6136 if (!crtc->config->gmch_pfit.control)
6137 return;
6138
6139 assert_pipe_disabled(dev_priv, crtc->pipe);
6140
6141 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6142 I915_READ(PFIT_CONTROL));
6143 I915_WRITE(PFIT_CONTROL, 0);
6144 }
6145
6146 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6147 struct drm_atomic_state *old_state)
6148 {
6149 struct drm_crtc *crtc = old_crtc_state->base.crtc;
6150 struct drm_device *dev = crtc->dev;
6151 struct drm_i915_private *dev_priv = to_i915(dev);
6152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6153 int pipe = intel_crtc->pipe;
6154
6155 /*
6156 * On gen2 planes are double buffered but the pipe isn't, so we must
6157 * wait for planes to fully turn off before disabling the pipe.
6158 */
6159 if (IS_GEN2(dev_priv))
6160 intel_wait_for_vblank(dev_priv, pipe);
6161
6162 intel_encoders_disable(crtc, old_crtc_state, old_state);
6163
6164 drm_crtc_vblank_off(crtc);
6165 assert_vblank_disabled(crtc);
6166
6167 intel_disable_pipe(old_crtc_state);
6168
6169 i9xx_pfit_disable(intel_crtc);
6170
6171 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6172
6173 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6174 if (IS_CHERRYVIEW(dev_priv))
6175 chv_disable_pll(dev_priv, pipe);
6176 else if (IS_VALLEYVIEW(dev_priv))
6177 vlv_disable_pll(dev_priv, pipe);
6178 else
6179 i9xx_disable_pll(intel_crtc);
6180 }
6181
6182 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6183
6184 if (!IS_GEN2(dev_priv))
6185 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6186
6187 if (!dev_priv->display.initial_watermarks)
6188 intel_update_watermarks(intel_crtc);
6189
6190 /* clock the pipe down to 640x480@60 to potentially save power */
6191 if (IS_I830(dev_priv))
6192 i830_enable_pipe(dev_priv, pipe);
6193 }
6194
6195 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
6196 struct drm_modeset_acquire_ctx *ctx)
6197 {
6198 struct intel_encoder *encoder;
6199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6200 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6201 enum intel_display_power_domain domain;
6202 struct intel_plane *plane;
6203 u64 domains;
6204 struct drm_atomic_state *state;
6205 struct intel_crtc_state *crtc_state;
6206 int ret;
6207
6208 if (!intel_crtc->active)
6209 return;
6210
6211 for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
6212 const struct intel_plane_state *plane_state =
6213 to_intel_plane_state(plane->base.state);
6214
6215 if (plane_state->base.visible)
6216 intel_plane_disable_noatomic(intel_crtc, plane);
6217 }
6218
6219 state = drm_atomic_state_alloc(crtc->dev);
6220 if (!state) {
6221 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
6222 crtc->base.id, crtc->name);
6223 return;
6224 }
6225
6226 state->acquire_ctx = ctx;
6227
6228 /* Everything's already locked, -EDEADLK can't happen. */
6229 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6230 ret = drm_atomic_add_affected_connectors(state, crtc);
6231
6232 WARN_ON(IS_ERR(crtc_state) || ret);
6233
6234 dev_priv->display.crtc_disable(crtc_state, state);
6235
6236 drm_atomic_state_put(state);
6237
6238 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6239 crtc->base.id, crtc->name);
6240
6241 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6242 crtc->state->active = false;
6243 intel_crtc->active = false;
6244 crtc->enabled = false;
6245 crtc->state->connector_mask = 0;
6246 crtc->state->encoder_mask = 0;
6247
6248 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6249 encoder->base.crtc = NULL;
6250
6251 intel_fbc_disable(intel_crtc);
6252 intel_update_watermarks(intel_crtc);
6253 intel_disable_shared_dpll(intel_crtc);
6254
6255 domains = intel_crtc->enabled_power_domains;
6256 for_each_power_domain(domain, domains)
6257 intel_display_power_put(dev_priv, domain);
6258 intel_crtc->enabled_power_domains = 0;
6259
6260 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6261 dev_priv->min_cdclk[intel_crtc->pipe] = 0;
6262 dev_priv->min_voltage_level[intel_crtc->pipe] = 0;
6263 }
6264
6265 /*
6266 * turn all crtc's off, but do not adjust state
6267 * This has to be paired with a call to intel_modeset_setup_hw_state.
6268 */
6269 int intel_display_suspend(struct drm_device *dev)
6270 {
6271 struct drm_i915_private *dev_priv = to_i915(dev);
6272 struct drm_atomic_state *state;
6273 int ret;
6274
6275 state = drm_atomic_helper_suspend(dev);
6276 ret = PTR_ERR_OR_ZERO(state);
6277 if (ret)
6278 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6279 else
6280 dev_priv->modeset_restore_state = state;
6281 return ret;
6282 }
6283
6284 void intel_encoder_destroy(struct drm_encoder *encoder)
6285 {
6286 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6287
6288 drm_encoder_cleanup(encoder);
6289 kfree(intel_encoder);
6290 }
6291
6292 /* Cross check the actual hw state with our own modeset state tracking (and it's
6293 * internal consistency). */
6294 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
6295 struct drm_connector_state *conn_state)
6296 {
6297 struct intel_connector *connector = to_intel_connector(conn_state->connector);
6298
6299 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6300 connector->base.base.id,
6301 connector->base.name);
6302
6303 if (connector->get_hw_state(connector)) {
6304 struct intel_encoder *encoder = connector->encoder;
6305
6306 I915_STATE_WARN(!crtc_state,
6307 "connector enabled without attached crtc\n");
6308
6309 if (!crtc_state)
6310 return;
6311
6312 I915_STATE_WARN(!crtc_state->active,
6313 "connector is active, but attached crtc isn't\n");
6314
6315 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6316 return;
6317
6318 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6319 "atomic encoder doesn't match attached encoder\n");
6320
6321 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6322 "attached encoder crtc differs from connector crtc\n");
6323 } else {
6324 I915_STATE_WARN(crtc_state && crtc_state->active,
6325 "attached crtc is active, but connector isn't\n");
6326 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
6327 "best encoder set without crtc!\n");
6328 }
6329 }
6330
6331 int intel_connector_init(struct intel_connector *connector)
6332 {
6333 struct intel_digital_connector_state *conn_state;
6334
6335 /*
6336 * Allocate enough memory to hold intel_digital_connector_state,
6337 * This might be a few bytes too many, but for connectors that don't
6338 * need it we'll free the state and allocate a smaller one on the first
6339 * succesful commit anyway.
6340 */
6341 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
6342 if (!conn_state)
6343 return -ENOMEM;
6344
6345 __drm_atomic_helper_connector_reset(&connector->base,
6346 &conn_state->base);
6347
6348 return 0;
6349 }
6350
6351 struct intel_connector *intel_connector_alloc(void)
6352 {
6353 struct intel_connector *connector;
6354
6355 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6356 if (!connector)
6357 return NULL;
6358
6359 if (intel_connector_init(connector) < 0) {
6360 kfree(connector);
6361 return NULL;
6362 }
6363
6364 return connector;
6365 }
6366
6367 /*
6368 * Free the bits allocated by intel_connector_alloc.
6369 * This should only be used after intel_connector_alloc has returned
6370 * successfully, and before drm_connector_init returns successfully.
6371 * Otherwise the destroy callbacks for the connector and the state should
6372 * take care of proper cleanup/free
6373 */
6374 void intel_connector_free(struct intel_connector *connector)
6375 {
6376 kfree(to_intel_digital_connector_state(connector->base.state));
6377 kfree(connector);
6378 }
6379
6380 /* Simple connector->get_hw_state implementation for encoders that support only
6381 * one connector and no cloning and hence the encoder state determines the state
6382 * of the connector. */
6383 bool intel_connector_get_hw_state(struct intel_connector *connector)
6384 {
6385 enum pipe pipe = 0;
6386 struct intel_encoder *encoder = connector->encoder;
6387
6388 return encoder->get_hw_state(encoder, &pipe);
6389 }
6390
6391 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6392 {
6393 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6394 return crtc_state->fdi_lanes;
6395
6396 return 0;
6397 }
6398
6399 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6400 struct intel_crtc_state *pipe_config)
6401 {
6402 struct drm_i915_private *dev_priv = to_i915(dev);
6403 struct drm_atomic_state *state = pipe_config->base.state;
6404 struct intel_crtc *other_crtc;
6405 struct intel_crtc_state *other_crtc_state;
6406
6407 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6408 pipe_name(pipe), pipe_config->fdi_lanes);
6409 if (pipe_config->fdi_lanes > 4) {
6410 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6411 pipe_name(pipe), pipe_config->fdi_lanes);
6412 return -EINVAL;
6413 }
6414
6415 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6416 if (pipe_config->fdi_lanes > 2) {
6417 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6418 pipe_config->fdi_lanes);
6419 return -EINVAL;
6420 } else {
6421 return 0;
6422 }
6423 }
6424
6425 if (INTEL_INFO(dev_priv)->num_pipes == 2)
6426 return 0;
6427
6428 /* Ivybridge 3 pipe is really complicated */
6429 switch (pipe) {
6430 case PIPE_A:
6431 return 0;
6432 case PIPE_B:
6433 if (pipe_config->fdi_lanes <= 2)
6434 return 0;
6435
6436 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6437 other_crtc_state =
6438 intel_atomic_get_crtc_state(state, other_crtc);
6439 if (IS_ERR(other_crtc_state))
6440 return PTR_ERR(other_crtc_state);
6441
6442 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6443 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6444 pipe_name(pipe), pipe_config->fdi_lanes);
6445 return -EINVAL;
6446 }
6447 return 0;
6448 case PIPE_C:
6449 if (pipe_config->fdi_lanes > 2) {
6450 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6451 pipe_name(pipe), pipe_config->fdi_lanes);
6452 return -EINVAL;
6453 }
6454
6455 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6456 other_crtc_state =
6457 intel_atomic_get_crtc_state(state, other_crtc);
6458 if (IS_ERR(other_crtc_state))
6459 return PTR_ERR(other_crtc_state);
6460
6461 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6462 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6463 return -EINVAL;
6464 }
6465 return 0;
6466 default:
6467 BUG();
6468 }
6469 }
6470
6471 #define RETRY 1
6472 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6473 struct intel_crtc_state *pipe_config)
6474 {
6475 struct drm_device *dev = intel_crtc->base.dev;
6476 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6477 int lane, link_bw, fdi_dotclock, ret;
6478 bool needs_recompute = false;
6479
6480 retry:
6481 /* FDI is a binary signal running at ~2.7GHz, encoding
6482 * each output octet as 10 bits. The actual frequency
6483 * is stored as a divider into a 100MHz clock, and the
6484 * mode pixel clock is stored in units of 1KHz.
6485 * Hence the bw of each lane in terms of the mode signal
6486 * is:
6487 */
6488 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6489
6490 fdi_dotclock = adjusted_mode->crtc_clock;
6491
6492 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6493 pipe_config->pipe_bpp);
6494
6495 pipe_config->fdi_lanes = lane;
6496
6497 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6498 link_bw, &pipe_config->fdi_m_n, false);
6499
6500 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6501 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6502 pipe_config->pipe_bpp -= 2*3;
6503 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6504 pipe_config->pipe_bpp);
6505 needs_recompute = true;
6506 pipe_config->bw_constrained = true;
6507
6508 goto retry;
6509 }
6510
6511 if (needs_recompute)
6512 return RETRY;
6513
6514 return ret;
6515 }
6516
6517 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
6518 {
6519 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6520 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6521
6522 /* IPS only exists on ULT machines and is tied to pipe A. */
6523 if (!hsw_crtc_supports_ips(crtc))
6524 return false;
6525
6526 if (!i915_modparams.enable_ips)
6527 return false;
6528
6529 if (crtc_state->pipe_bpp > 24)
6530 return false;
6531
6532 /*
6533 * We compare against max which means we must take
6534 * the increased cdclk requirement into account when
6535 * calculating the new cdclk.
6536 *
6537 * Should measure whether using a lower cdclk w/o IPS
6538 */
6539 if (IS_BROADWELL(dev_priv) &&
6540 crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
6541 return false;
6542
6543 return true;
6544 }
6545
6546 static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
6547 {
6548 struct drm_i915_private *dev_priv =
6549 to_i915(crtc_state->base.crtc->dev);
6550 struct intel_atomic_state *intel_state =
6551 to_intel_atomic_state(crtc_state->base.state);
6552
6553 if (!hsw_crtc_state_ips_capable(crtc_state))
6554 return false;
6555
6556 if (crtc_state->ips_force_disable)
6557 return false;
6558
6559 /* IPS should be fine as long as at least one plane is enabled. */
6560 if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
6561 return false;
6562
6563 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
6564 if (IS_BROADWELL(dev_priv) &&
6565 crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100)
6566 return false;
6567
6568 return true;
6569 }
6570
6571 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6572 {
6573 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6574
6575 /* GDG double wide on either pipe, otherwise pipe A only */
6576 return INTEL_GEN(dev_priv) < 4 &&
6577 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6578 }
6579
6580 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6581 {
6582 uint32_t pixel_rate;
6583
6584 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6585
6586 /*
6587 * We only use IF-ID interlacing. If we ever use
6588 * PF-ID we'll need to adjust the pixel_rate here.
6589 */
6590
6591 if (pipe_config->pch_pfit.enabled) {
6592 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6593 uint32_t pfit_size = pipe_config->pch_pfit.size;
6594
6595 pipe_w = pipe_config->pipe_src_w;
6596 pipe_h = pipe_config->pipe_src_h;
6597
6598 pfit_w = (pfit_size >> 16) & 0xFFFF;
6599 pfit_h = pfit_size & 0xFFFF;
6600 if (pipe_w < pfit_w)
6601 pipe_w = pfit_w;
6602 if (pipe_h < pfit_h)
6603 pipe_h = pfit_h;
6604
6605 if (WARN_ON(!pfit_w || !pfit_h))
6606 return pixel_rate;
6607
6608 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6609 pfit_w * pfit_h);
6610 }
6611
6612 return pixel_rate;
6613 }
6614
6615 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6616 {
6617 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6618
6619 if (HAS_GMCH_DISPLAY(dev_priv))
6620 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6621 crtc_state->pixel_rate =
6622 crtc_state->base.adjusted_mode.crtc_clock;
6623 else
6624 crtc_state->pixel_rate =
6625 ilk_pipe_pixel_rate(crtc_state);
6626 }
6627
6628 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6629 struct intel_crtc_state *pipe_config)
6630 {
6631 struct drm_device *dev = crtc->base.dev;
6632 struct drm_i915_private *dev_priv = to_i915(dev);
6633 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6634 int clock_limit = dev_priv->max_dotclk_freq;
6635
6636 if (INTEL_GEN(dev_priv) < 4) {
6637 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6638
6639 /*
6640 * Enable double wide mode when the dot clock
6641 * is > 90% of the (display) core speed.
6642 */
6643 if (intel_crtc_supports_double_wide(crtc) &&
6644 adjusted_mode->crtc_clock > clock_limit) {
6645 clock_limit = dev_priv->max_dotclk_freq;
6646 pipe_config->double_wide = true;
6647 }
6648 }
6649
6650 if (adjusted_mode->crtc_clock > clock_limit) {
6651 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6652 adjusted_mode->crtc_clock, clock_limit,
6653 yesno(pipe_config->double_wide));
6654 return -EINVAL;
6655 }
6656
6657 if (pipe_config->ycbcr420 && pipe_config->base.ctm) {
6658 /*
6659 * There is only one pipe CSC unit per pipe, and we need that
6660 * for output conversion from RGB->YCBCR. So if CTM is already
6661 * applied we can't support YCBCR420 output.
6662 */
6663 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6664 return -EINVAL;
6665 }
6666
6667 /*
6668 * Pipe horizontal size must be even in:
6669 * - DVO ganged mode
6670 * - LVDS dual channel mode
6671 * - Double wide pipe
6672 */
6673 if (pipe_config->pipe_src_w & 1) {
6674 if (pipe_config->double_wide) {
6675 DRM_DEBUG_KMS("Odd pipe source width not supported with double wide pipe\n");
6676 return -EINVAL;
6677 }
6678
6679 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6680 intel_is_dual_link_lvds(dev)) {
6681 DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n");
6682 return -EINVAL;
6683 }
6684 }
6685
6686 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6687 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6688 */
6689 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6690 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6691 return -EINVAL;
6692
6693 intel_crtc_compute_pixel_rate(pipe_config);
6694
6695 if (pipe_config->has_pch_encoder)
6696 return ironlake_fdi_compute_config(crtc, pipe_config);
6697
6698 return 0;
6699 }
6700
6701 static void
6702 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6703 {
6704 while (*num > DATA_LINK_M_N_MASK ||
6705 *den > DATA_LINK_M_N_MASK) {
6706 *num >>= 1;
6707 *den >>= 1;
6708 }
6709 }
6710
6711 static void compute_m_n(unsigned int m, unsigned int n,
6712 uint32_t *ret_m, uint32_t *ret_n,
6713 bool reduce_m_n)
6714 {
6715 /*
6716 * Reduce M/N as much as possible without loss in precision. Several DP
6717 * dongles in particular seem to be fussy about too large *link* M/N
6718 * values. The passed in values are more likely to have the least
6719 * significant bits zero than M after rounding below, so do this first.
6720 */
6721 if (reduce_m_n) {
6722 while ((m & 1) == 0 && (n & 1) == 0) {
6723 m >>= 1;
6724 n >>= 1;
6725 }
6726 }
6727
6728 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6729 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6730 intel_reduce_m_n_ratio(ret_m, ret_n);
6731 }
6732
6733 void
6734 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6735 int pixel_clock, int link_clock,
6736 struct intel_link_m_n *m_n,
6737 bool reduce_m_n)
6738 {
6739 m_n->tu = 64;
6740
6741 compute_m_n(bits_per_pixel * pixel_clock,
6742 link_clock * nlanes * 8,
6743 &m_n->gmch_m, &m_n->gmch_n,
6744 reduce_m_n);
6745
6746 compute_m_n(pixel_clock, link_clock,
6747 &m_n->link_m, &m_n->link_n,
6748 reduce_m_n);
6749 }
6750
6751 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6752 {
6753 if (i915_modparams.panel_use_ssc >= 0)
6754 return i915_modparams.panel_use_ssc != 0;
6755 return dev_priv->vbt.lvds_use_ssc
6756 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6757 }
6758
6759 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6760 {
6761 return (1 << dpll->n) << 16 | dpll->m2;
6762 }
6763
6764 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6765 {
6766 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6767 }
6768
6769 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6770 struct intel_crtc_state *crtc_state,
6771 struct dpll *reduced_clock)
6772 {
6773 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6774 u32 fp, fp2 = 0;
6775
6776 if (IS_PINEVIEW(dev_priv)) {
6777 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6778 if (reduced_clock)
6779 fp2 = pnv_dpll_compute_fp(reduced_clock);
6780 } else {
6781 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6782 if (reduced_clock)
6783 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6784 }
6785
6786 crtc_state->dpll_hw_state.fp0 = fp;
6787
6788 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6789 reduced_clock) {
6790 crtc_state->dpll_hw_state.fp1 = fp2;
6791 } else {
6792 crtc_state->dpll_hw_state.fp1 = fp;
6793 }
6794 }
6795
6796 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6797 pipe)
6798 {
6799 u32 reg_val;
6800
6801 /*
6802 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6803 * and set it to a reasonable value instead.
6804 */
6805 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6806 reg_val &= 0xffffff00;
6807 reg_val |= 0x00000030;
6808 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6809
6810 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6811 reg_val &= 0x00ffffff;
6812 reg_val |= 0x8c000000;
6813 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6814
6815 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6816 reg_val &= 0xffffff00;
6817 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6818
6819 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6820 reg_val &= 0x00ffffff;
6821 reg_val |= 0xb0000000;
6822 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6823 }
6824
6825 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6826 struct intel_link_m_n *m_n)
6827 {
6828 struct drm_device *dev = crtc->base.dev;
6829 struct drm_i915_private *dev_priv = to_i915(dev);
6830 int pipe = crtc->pipe;
6831
6832 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6833 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6834 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6835 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6836 }
6837
6838 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6839 struct intel_link_m_n *m_n,
6840 struct intel_link_m_n *m2_n2)
6841 {
6842 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6843 int pipe = crtc->pipe;
6844 enum transcoder transcoder = crtc->config->cpu_transcoder;
6845
6846 if (INTEL_GEN(dev_priv) >= 5) {
6847 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6848 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6849 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6850 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6851 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6852 * for gen < 8) and if DRRS is supported (to make sure the
6853 * registers are not unnecessarily accessed).
6854 */
6855 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6856 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6857 I915_WRITE(PIPE_DATA_M2(transcoder),
6858 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6859 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6860 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6861 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6862 }
6863 } else {
6864 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6865 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6866 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6867 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6868 }
6869 }
6870
6871 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6872 {
6873 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6874
6875 if (m_n == M1_N1) {
6876 dp_m_n = &crtc->config->dp_m_n;
6877 dp_m2_n2 = &crtc->config->dp_m2_n2;
6878 } else if (m_n == M2_N2) {
6879
6880 /*
6881 * M2_N2 registers are not supported. Hence m2_n2 divider value
6882 * needs to be programmed into M1_N1.
6883 */
6884 dp_m_n = &crtc->config->dp_m2_n2;
6885 } else {
6886 DRM_ERROR("Unsupported divider value\n");
6887 return;
6888 }
6889
6890 if (crtc->config->has_pch_encoder)
6891 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6892 else
6893 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6894 }
6895
6896 static void vlv_compute_dpll(struct intel_crtc *crtc,
6897 struct intel_crtc_state *pipe_config)
6898 {
6899 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6900 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6901 if (crtc->pipe != PIPE_A)
6902 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6903
6904 /* DPLL not used with DSI, but still need the rest set up */
6905 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6906 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6907 DPLL_EXT_BUFFER_ENABLE_VLV;
6908
6909 pipe_config->dpll_hw_state.dpll_md =
6910 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6911 }
6912
6913 static void chv_compute_dpll(struct intel_crtc *crtc,
6914 struct intel_crtc_state *pipe_config)
6915 {
6916 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6917 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6918 if (crtc->pipe != PIPE_A)
6919 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6920
6921 /* DPLL not used with DSI, but still need the rest set up */
6922 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6923 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6924
6925 pipe_config->dpll_hw_state.dpll_md =
6926 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6927 }
6928
6929 static void vlv_prepare_pll(struct intel_crtc *crtc,
6930 const struct intel_crtc_state *pipe_config)
6931 {
6932 struct drm_device *dev = crtc->base.dev;
6933 struct drm_i915_private *dev_priv = to_i915(dev);
6934 enum pipe pipe = crtc->pipe;
6935 u32 mdiv;
6936 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6937 u32 coreclk, reg_val;
6938
6939 /* Enable Refclk */
6940 I915_WRITE(DPLL(pipe),
6941 pipe_config->dpll_hw_state.dpll &
6942 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6943
6944 /* No need to actually set up the DPLL with DSI */
6945 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6946 return;
6947
6948 mutex_lock(&dev_priv->sb_lock);
6949
6950 bestn = pipe_config->dpll.n;
6951 bestm1 = pipe_config->dpll.m1;
6952 bestm2 = pipe_config->dpll.m2;
6953 bestp1 = pipe_config->dpll.p1;
6954 bestp2 = pipe_config->dpll.p2;
6955
6956 /* See eDP HDMI DPIO driver vbios notes doc */
6957
6958 /* PLL B needs special handling */
6959 if (pipe == PIPE_B)
6960 vlv_pllb_recal_opamp(dev_priv, pipe);
6961
6962 /* Set up Tx target for periodic Rcomp update */
6963 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6964
6965 /* Disable target IRef on PLL */
6966 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6967 reg_val &= 0x00ffffff;
6968 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6969
6970 /* Disable fast lock */
6971 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6972
6973 /* Set idtafcrecal before PLL is enabled */
6974 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6975 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6976 mdiv |= ((bestn << DPIO_N_SHIFT));
6977 mdiv |= (1 << DPIO_K_SHIFT);
6978
6979 /*
6980 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6981 * but we don't support that).
6982 * Note: don't use the DAC post divider as it seems unstable.
6983 */
6984 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6985 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6986
6987 mdiv |= DPIO_ENABLE_CALIBRATION;
6988 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6989
6990 /* Set HBR and RBR LPF coefficients */
6991 if (pipe_config->port_clock == 162000 ||
6992 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6993 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6994 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6995 0x009f0003);
6996 else
6997 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6998 0x00d0000f);
6999
7000 if (intel_crtc_has_dp_encoder(pipe_config)) {
7001 /* Use SSC source */
7002 if (pipe == PIPE_A)
7003 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7004 0x0df40000);
7005 else
7006 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7007 0x0df70000);
7008 } else { /* HDMI or VGA */
7009 /* Use bend source */
7010 if (pipe == PIPE_A)
7011 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7012 0x0df70000);
7013 else
7014 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7015 0x0df40000);
7016 }
7017
7018 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7019 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7020 if (intel_crtc_has_dp_encoder(crtc->config))
7021 coreclk |= 0x01000000;
7022 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7023
7024 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7025 mutex_unlock(&dev_priv->sb_lock);
7026 }
7027
7028 static void chv_prepare_pll(struct intel_crtc *crtc,
7029 const struct intel_crtc_state *pipe_config)
7030 {
7031 struct drm_device *dev = crtc->base.dev;
7032 struct drm_i915_private *dev_priv = to_i915(dev);
7033 enum pipe pipe = crtc->pipe;
7034 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7035 u32 loopfilter, tribuf_calcntr;
7036 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7037 u32 dpio_val;
7038 int vco;
7039
7040 /* Enable Refclk and SSC */
7041 I915_WRITE(DPLL(pipe),
7042 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7043
7044 /* No need to actually set up the DPLL with DSI */
7045 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7046 return;
7047
7048 bestn = pipe_config->dpll.n;
7049 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7050 bestm1 = pipe_config->dpll.m1;
7051 bestm2 = pipe_config->dpll.m2 >> 22;
7052 bestp1 = pipe_config->dpll.p1;
7053 bestp2 = pipe_config->dpll.p2;
7054 vco = pipe_config->dpll.vco;
7055 dpio_val = 0;
7056 loopfilter = 0;
7057
7058 mutex_lock(&dev_priv->sb_lock);
7059
7060 /* p1 and p2 divider */
7061 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7062 5 << DPIO_CHV_S1_DIV_SHIFT |
7063 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7064 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7065 1 << DPIO_CHV_K_DIV_SHIFT);
7066
7067 /* Feedback post-divider - m2 */
7068 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7069
7070 /* Feedback refclk divider - n and m1 */
7071 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7072 DPIO_CHV_M1_DIV_BY_2 |
7073 1 << DPIO_CHV_N_DIV_SHIFT);
7074
7075 /* M2 fraction division */
7076 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7077
7078 /* M2 fraction division enable */
7079 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7080 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7081 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7082 if (bestm2_frac)
7083 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7084 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7085
7086 /* Program digital lock detect threshold */
7087 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7088 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7089 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7090 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7091 if (!bestm2_frac)
7092 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7093 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7094
7095 /* Loop filter */
7096 if (vco == 5400000) {
7097 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7098 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7099 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7100 tribuf_calcntr = 0x9;
7101 } else if (vco <= 6200000) {
7102 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7103 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7104 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7105 tribuf_calcntr = 0x9;
7106 } else if (vco <= 6480000) {
7107 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7108 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7109 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7110 tribuf_calcntr = 0x8;
7111 } else {
7112 /* Not supported. Apply the same limits as in the max case */
7113 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7114 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7115 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7116 tribuf_calcntr = 0;
7117 }
7118 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7119
7120 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7121 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7122 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7123 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7124
7125 /* AFC Recal */
7126 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7127 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7128 DPIO_AFC_RECAL);
7129
7130 mutex_unlock(&dev_priv->sb_lock);
7131 }
7132
7133 /**
7134 * vlv_force_pll_on - forcibly enable just the PLL
7135 * @dev_priv: i915 private structure
7136 * @pipe: pipe PLL to enable
7137 * @dpll: PLL configuration
7138 *
7139 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7140 * in cases where we need the PLL enabled even when @pipe is not going to
7141 * be enabled.
7142 */
7143 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
7144 const struct dpll *dpll)
7145 {
7146 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
7147 struct intel_crtc_state *pipe_config;
7148
7149 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7150 if (!pipe_config)
7151 return -ENOMEM;
7152
7153 pipe_config->base.crtc = &crtc->base;
7154 pipe_config->pixel_multiplier = 1;
7155 pipe_config->dpll = *dpll;
7156
7157 if (IS_CHERRYVIEW(dev_priv)) {
7158 chv_compute_dpll(crtc, pipe_config);
7159 chv_prepare_pll(crtc, pipe_config);
7160 chv_enable_pll(crtc, pipe_config);
7161 } else {
7162 vlv_compute_dpll(crtc, pipe_config);
7163 vlv_prepare_pll(crtc, pipe_config);
7164 vlv_enable_pll(crtc, pipe_config);
7165 }
7166
7167 kfree(pipe_config);
7168
7169 return 0;
7170 }
7171
7172 /**
7173 * vlv_force_pll_off - forcibly disable just the PLL
7174 * @dev_priv: i915 private structure
7175 * @pipe: pipe PLL to disable
7176 *
7177 * Disable the PLL for @pipe. To be used in cases where we need
7178 * the PLL enabled even when @pipe is not going to be enabled.
7179 */
7180 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
7181 {
7182 if (IS_CHERRYVIEW(dev_priv))
7183 chv_disable_pll(dev_priv, pipe);
7184 else
7185 vlv_disable_pll(dev_priv, pipe);
7186 }
7187
7188 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7189 struct intel_crtc_state *crtc_state,
7190 struct dpll *reduced_clock)
7191 {
7192 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7193 u32 dpll;
7194 struct dpll *clock = &crtc_state->dpll;
7195
7196 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7197
7198 dpll = DPLL_VGA_MODE_DIS;
7199
7200 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
7201 dpll |= DPLLB_MODE_LVDS;
7202 else
7203 dpll |= DPLLB_MODE_DAC_SERIAL;
7204
7205 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7206 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7207 dpll |= (crtc_state->pixel_multiplier - 1)
7208 << SDVO_MULTIPLIER_SHIFT_HIRES;
7209 }
7210
7211 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7212 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
7213 dpll |= DPLL_SDVO_HIGH_SPEED;
7214
7215 if (intel_crtc_has_dp_encoder(crtc_state))
7216 dpll |= DPLL_SDVO_HIGH_SPEED;
7217
7218 /* compute bitmask from p1 value */
7219 if (IS_PINEVIEW(dev_priv))
7220 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7221 else {
7222 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7223 if (IS_G4X(dev_priv) && reduced_clock)
7224 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7225 }
7226 switch (clock->p2) {
7227 case 5:
7228 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7229 break;
7230 case 7:
7231 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7232 break;
7233 case 10:
7234 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7235 break;
7236 case 14:
7237 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7238 break;
7239 }
7240 if (INTEL_GEN(dev_priv) >= 4)
7241 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7242
7243 if (crtc_state->sdvo_tv_clock)
7244 dpll |= PLL_REF_INPUT_TVCLKINBC;
7245 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7246 intel_panel_use_ssc(dev_priv))
7247 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7248 else
7249 dpll |= PLL_REF_INPUT_DREFCLK;
7250
7251 dpll |= DPLL_VCO_ENABLE;
7252 crtc_state->dpll_hw_state.dpll = dpll;
7253
7254 if (INTEL_GEN(dev_priv) >= 4) {
7255 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7256 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7257 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7258 }
7259 }
7260
7261 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7262 struct intel_crtc_state *crtc_state,
7263 struct dpll *reduced_clock)
7264 {
7265 struct drm_device *dev = crtc->base.dev;
7266 struct drm_i915_private *dev_priv = to_i915(dev);
7267 u32 dpll;
7268 struct dpll *clock = &crtc_state->dpll;
7269
7270 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7271
7272 dpll = DPLL_VGA_MODE_DIS;
7273
7274 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7275 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7276 } else {
7277 if (clock->p1 == 2)
7278 dpll |= PLL_P1_DIVIDE_BY_TWO;
7279 else
7280 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7281 if (clock->p2 == 4)
7282 dpll |= PLL_P2_DIVIDE_BY_4;
7283 }
7284
7285 if (!IS_I830(dev_priv) &&
7286 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
7287 dpll |= DPLL_DVO_2X_MODE;
7288
7289 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7290 intel_panel_use_ssc(dev_priv))
7291 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7292 else
7293 dpll |= PLL_REF_INPUT_DREFCLK;
7294
7295 dpll |= DPLL_VCO_ENABLE;
7296 crtc_state->dpll_hw_state.dpll = dpll;
7297 }
7298
7299 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7300 {
7301 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7302 enum pipe pipe = intel_crtc->pipe;
7303 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7304 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7305 uint32_t crtc_vtotal, crtc_vblank_end;
7306 int vsyncshift = 0;
7307
7308 /* We need to be careful not to changed the adjusted mode, for otherwise
7309 * the hw state checker will get angry at the mismatch. */
7310 crtc_vtotal = adjusted_mode->crtc_vtotal;
7311 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7312
7313 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7314 /* the chip adds 2 halflines automatically */
7315 crtc_vtotal -= 1;
7316 crtc_vblank_end -= 1;
7317
7318 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7319 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7320 else
7321 vsyncshift = adjusted_mode->crtc_hsync_start -
7322 adjusted_mode->crtc_htotal / 2;
7323 if (vsyncshift < 0)
7324 vsyncshift += adjusted_mode->crtc_htotal;
7325 }
7326
7327 if (INTEL_GEN(dev_priv) > 3)
7328 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7329
7330 I915_WRITE(HTOTAL(cpu_transcoder),
7331 (adjusted_mode->crtc_hdisplay - 1) |
7332 ((adjusted_mode->crtc_htotal - 1) << 16));
7333 I915_WRITE(HBLANK(cpu_transcoder),
7334 (adjusted_mode->crtc_hblank_start - 1) |
7335 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7336 I915_WRITE(HSYNC(cpu_transcoder),
7337 (adjusted_mode->crtc_hsync_start - 1) |
7338 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7339
7340 I915_WRITE(VTOTAL(cpu_transcoder),
7341 (adjusted_mode->crtc_vdisplay - 1) |
7342 ((crtc_vtotal - 1) << 16));
7343 I915_WRITE(VBLANK(cpu_transcoder),
7344 (adjusted_mode->crtc_vblank_start - 1) |
7345 ((crtc_vblank_end - 1) << 16));
7346 I915_WRITE(VSYNC(cpu_transcoder),
7347 (adjusted_mode->crtc_vsync_start - 1) |
7348 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7349
7350 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7351 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7352 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7353 * bits. */
7354 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
7355 (pipe == PIPE_B || pipe == PIPE_C))
7356 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7357
7358 }
7359
7360 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7361 {
7362 struct drm_device *dev = intel_crtc->base.dev;
7363 struct drm_i915_private *dev_priv = to_i915(dev);
7364 enum pipe pipe = intel_crtc->pipe;
7365
7366 /* pipesrc controls the size that is scaled from, which should
7367 * always be the user's requested size.
7368 */
7369 I915_WRITE(PIPESRC(pipe),
7370 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7371 (intel_crtc->config->pipe_src_h - 1));
7372 }
7373
7374 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7375 struct intel_crtc_state *pipe_config)
7376 {
7377 struct drm_device *dev = crtc->base.dev;
7378 struct drm_i915_private *dev_priv = to_i915(dev);
7379 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7380 uint32_t tmp;
7381
7382 tmp = I915_READ(HTOTAL(cpu_transcoder));
7383 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7384 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7385 tmp = I915_READ(HBLANK(cpu_transcoder));
7386 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7387 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7388 tmp = I915_READ(HSYNC(cpu_transcoder));
7389 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7390 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7391
7392 tmp = I915_READ(VTOTAL(cpu_transcoder));
7393 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7394 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7395 tmp = I915_READ(VBLANK(cpu_transcoder));
7396 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7397 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7398 tmp = I915_READ(VSYNC(cpu_transcoder));
7399 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7400 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7401
7402 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7403 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7404 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7405 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7406 }
7407 }
7408
7409 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7410 struct intel_crtc_state *pipe_config)
7411 {
7412 struct drm_device *dev = crtc->base.dev;
7413 struct drm_i915_private *dev_priv = to_i915(dev);
7414 u32 tmp;
7415
7416 tmp = I915_READ(PIPESRC(crtc->pipe));
7417 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7418 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7419
7420 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7421 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7422 }
7423
7424 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7425 struct intel_crtc_state *pipe_config)
7426 {
7427 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7428 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7429 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7430 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7431
7432 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7433 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7434 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7435 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7436
7437 mode->flags = pipe_config->base.adjusted_mode.flags;
7438 mode->type = DRM_MODE_TYPE_DRIVER;
7439
7440 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7441
7442 mode->hsync = drm_mode_hsync(mode);
7443 mode->vrefresh = drm_mode_vrefresh(mode);
7444 drm_mode_set_name(mode);
7445 }
7446
7447 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7448 {
7449 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7450 uint32_t pipeconf;
7451
7452 pipeconf = 0;
7453
7454 /* we keep both pipes enabled on 830 */
7455 if (IS_I830(dev_priv))
7456 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7457
7458 if (intel_crtc->config->double_wide)
7459 pipeconf |= PIPECONF_DOUBLE_WIDE;
7460
7461 /* only g4x and later have fancy bpc/dither controls */
7462 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7463 IS_CHERRYVIEW(dev_priv)) {
7464 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7465 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7466 pipeconf |= PIPECONF_DITHER_EN |
7467 PIPECONF_DITHER_TYPE_SP;
7468
7469 switch (intel_crtc->config->pipe_bpp) {
7470 case 18:
7471 pipeconf |= PIPECONF_6BPC;
7472 break;
7473 case 24:
7474 pipeconf |= PIPECONF_8BPC;
7475 break;
7476 case 30:
7477 pipeconf |= PIPECONF_10BPC;
7478 break;
7479 default:
7480 /* Case prevented by intel_choose_pipe_bpp_dither. */
7481 BUG();
7482 }
7483 }
7484
7485 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7486 if (INTEL_GEN(dev_priv) < 4 ||
7487 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7488 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7489 else
7490 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7491 } else
7492 pipeconf |= PIPECONF_PROGRESSIVE;
7493
7494 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7495 intel_crtc->config->limited_color_range)
7496 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7497
7498 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7499 POSTING_READ(PIPECONF(intel_crtc->pipe));
7500 }
7501
7502 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7503 struct intel_crtc_state *crtc_state)
7504 {
7505 struct drm_device *dev = crtc->base.dev;
7506 struct drm_i915_private *dev_priv = to_i915(dev);
7507 const struct intel_limit *limit;
7508 int refclk = 48000;
7509
7510 memset(&crtc_state->dpll_hw_state, 0,
7511 sizeof(crtc_state->dpll_hw_state));
7512
7513 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7514 if (intel_panel_use_ssc(dev_priv)) {
7515 refclk = dev_priv->vbt.lvds_ssc_freq;
7516 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7517 }
7518
7519 limit = &intel_limits_i8xx_lvds;
7520 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7521 limit = &intel_limits_i8xx_dvo;
7522 } else {
7523 limit = &intel_limits_i8xx_dac;
7524 }
7525
7526 if (!crtc_state->clock_set &&
7527 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7528 refclk, NULL, &crtc_state->dpll)) {
7529 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7530 return -EINVAL;
7531 }
7532
7533 i8xx_compute_dpll(crtc, crtc_state, NULL);
7534
7535 return 0;
7536 }
7537
7538 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7539 struct intel_crtc_state *crtc_state)
7540 {
7541 struct drm_device *dev = crtc->base.dev;
7542 struct drm_i915_private *dev_priv = to_i915(dev);
7543 const struct intel_limit *limit;
7544 int refclk = 96000;
7545
7546 memset(&crtc_state->dpll_hw_state, 0,
7547 sizeof(crtc_state->dpll_hw_state));
7548
7549 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7550 if (intel_panel_use_ssc(dev_priv)) {
7551 refclk = dev_priv->vbt.lvds_ssc_freq;
7552 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7553 }
7554
7555 if (intel_is_dual_link_lvds(dev))
7556 limit = &intel_limits_g4x_dual_channel_lvds;
7557 else
7558 limit = &intel_limits_g4x_single_channel_lvds;
7559 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7560 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7561 limit = &intel_limits_g4x_hdmi;
7562 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7563 limit = &intel_limits_g4x_sdvo;
7564 } else {
7565 /* The option is for other outputs */
7566 limit = &intel_limits_i9xx_sdvo;
7567 }
7568
7569 if (!crtc_state->clock_set &&
7570 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7571 refclk, NULL, &crtc_state->dpll)) {
7572 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7573 return -EINVAL;
7574 }
7575
7576 i9xx_compute_dpll(crtc, crtc_state, NULL);
7577
7578 return 0;
7579 }
7580
7581 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7582 struct intel_crtc_state *crtc_state)
7583 {
7584 struct drm_device *dev = crtc->base.dev;
7585 struct drm_i915_private *dev_priv = to_i915(dev);
7586 const struct intel_limit *limit;
7587 int refclk = 96000;
7588
7589 memset(&crtc_state->dpll_hw_state, 0,
7590 sizeof(crtc_state->dpll_hw_state));
7591
7592 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7593 if (intel_panel_use_ssc(dev_priv)) {
7594 refclk = dev_priv->vbt.lvds_ssc_freq;
7595 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7596 }
7597
7598 limit = &intel_limits_pineview_lvds;
7599 } else {
7600 limit = &intel_limits_pineview_sdvo;
7601 }
7602
7603 if (!crtc_state->clock_set &&
7604 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7605 refclk, NULL, &crtc_state->dpll)) {
7606 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7607 return -EINVAL;
7608 }
7609
7610 i9xx_compute_dpll(crtc, crtc_state, NULL);
7611
7612 return 0;
7613 }
7614
7615 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7616 struct intel_crtc_state *crtc_state)
7617 {
7618 struct drm_device *dev = crtc->base.dev;
7619 struct drm_i915_private *dev_priv = to_i915(dev);
7620 const struct intel_limit *limit;
7621 int refclk = 96000;
7622
7623 memset(&crtc_state->dpll_hw_state, 0,
7624 sizeof(crtc_state->dpll_hw_state));
7625
7626 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7627 if (intel_panel_use_ssc(dev_priv)) {
7628 refclk = dev_priv->vbt.lvds_ssc_freq;
7629 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7630 }
7631
7632 limit = &intel_limits_i9xx_lvds;
7633 } else {
7634 limit = &intel_limits_i9xx_sdvo;
7635 }
7636
7637 if (!crtc_state->clock_set &&
7638 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7639 refclk, NULL, &crtc_state->dpll)) {
7640 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7641 return -EINVAL;
7642 }
7643
7644 i9xx_compute_dpll(crtc, crtc_state, NULL);
7645
7646 return 0;
7647 }
7648
7649 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7650 struct intel_crtc_state *crtc_state)
7651 {
7652 int refclk = 100000;
7653 const struct intel_limit *limit = &intel_limits_chv;
7654
7655 memset(&crtc_state->dpll_hw_state, 0,
7656 sizeof(crtc_state->dpll_hw_state));
7657
7658 if (!crtc_state->clock_set &&
7659 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7660 refclk, NULL, &crtc_state->dpll)) {
7661 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7662 return -EINVAL;
7663 }
7664
7665 chv_compute_dpll(crtc, crtc_state);
7666
7667 return 0;
7668 }
7669
7670 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7671 struct intel_crtc_state *crtc_state)
7672 {
7673 int refclk = 100000;
7674 const struct intel_limit *limit = &intel_limits_vlv;
7675
7676 memset(&crtc_state->dpll_hw_state, 0,
7677 sizeof(crtc_state->dpll_hw_state));
7678
7679 if (!crtc_state->clock_set &&
7680 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7681 refclk, NULL, &crtc_state->dpll)) {
7682 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7683 return -EINVAL;
7684 }
7685
7686 vlv_compute_dpll(crtc, crtc_state);
7687
7688 return 0;
7689 }
7690
7691 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7692 struct intel_crtc_state *pipe_config)
7693 {
7694 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7695 uint32_t tmp;
7696
7697 if (INTEL_GEN(dev_priv) <= 3 &&
7698 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7699 return;
7700
7701 tmp = I915_READ(PFIT_CONTROL);
7702 if (!(tmp & PFIT_ENABLE))
7703 return;
7704
7705 /* Check whether the pfit is attached to our pipe. */
7706 if (INTEL_GEN(dev_priv) < 4) {
7707 if (crtc->pipe != PIPE_B)
7708 return;
7709 } else {
7710 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7711 return;
7712 }
7713
7714 pipe_config->gmch_pfit.control = tmp;
7715 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7716 }
7717
7718 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7719 struct intel_crtc_state *pipe_config)
7720 {
7721 struct drm_device *dev = crtc->base.dev;
7722 struct drm_i915_private *dev_priv = to_i915(dev);
7723 int pipe = pipe_config->cpu_transcoder;
7724 struct dpll clock;
7725 u32 mdiv;
7726 int refclk = 100000;
7727
7728 /* In case of DSI, DPLL will not be used */
7729 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7730 return;
7731
7732 mutex_lock(&dev_priv->sb_lock);
7733 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7734 mutex_unlock(&dev_priv->sb_lock);
7735
7736 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7737 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7738 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7739 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7740 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7741
7742 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7743 }
7744
7745 static void
7746 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7747 struct intel_initial_plane_config *plane_config)
7748 {
7749 struct drm_device *dev = crtc->base.dev;
7750 struct drm_i915_private *dev_priv = to_i915(dev);
7751 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
7752 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
7753 enum pipe pipe;
7754 u32 val, base, offset;
7755 int fourcc, pixel_format;
7756 unsigned int aligned_height;
7757 struct drm_framebuffer *fb;
7758 struct intel_framebuffer *intel_fb;
7759
7760 if (!plane->get_hw_state(plane, &pipe))
7761 return;
7762
7763 WARN_ON(pipe != crtc->pipe);
7764
7765 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7766 if (!intel_fb) {
7767 DRM_DEBUG_KMS("failed to alloc fb\n");
7768 return;
7769 }
7770
7771 fb = &intel_fb->base;
7772
7773 fb->dev = dev;
7774
7775 val = I915_READ(DSPCNTR(i9xx_plane));
7776
7777 if (INTEL_GEN(dev_priv) >= 4) {
7778 if (val & DISPPLANE_TILED) {
7779 plane_config->tiling = I915_TILING_X;
7780 fb->modifier = I915_FORMAT_MOD_X_TILED;
7781 }
7782 }
7783
7784 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7785 fourcc = i9xx_format_to_fourcc(pixel_format);
7786 fb->format = drm_format_info(fourcc);
7787
7788 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7789 offset = I915_READ(DSPOFFSET(i9xx_plane));
7790 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
7791 } else if (INTEL_GEN(dev_priv) >= 4) {
7792 if (plane_config->tiling)
7793 offset = I915_READ(DSPTILEOFF(i9xx_plane));
7794 else
7795 offset = I915_READ(DSPLINOFF(i9xx_plane));
7796 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
7797 } else {
7798 base = I915_READ(DSPADDR(i9xx_plane));
7799 }
7800 plane_config->base = base;
7801
7802 val = I915_READ(PIPESRC(pipe));
7803 fb->width = ((val >> 16) & 0xfff) + 1;
7804 fb->height = ((val >> 0) & 0xfff) + 1;
7805
7806 val = I915_READ(DSPSTRIDE(i9xx_plane));
7807 fb->pitches[0] = val & 0xffffffc0;
7808
7809 aligned_height = intel_fb_align_height(fb, 0, fb->height);
7810
7811 plane_config->size = fb->pitches[0] * aligned_height;
7812
7813 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7814 crtc->base.name, plane->base.name, fb->width, fb->height,
7815 fb->format->cpp[0] * 8, base, fb->pitches[0],
7816 plane_config->size);
7817
7818 plane_config->fb = intel_fb;
7819 }
7820
7821 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7822 struct intel_crtc_state *pipe_config)
7823 {
7824 struct drm_device *dev = crtc->base.dev;
7825 struct drm_i915_private *dev_priv = to_i915(dev);
7826 int pipe = pipe_config->cpu_transcoder;
7827 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7828 struct dpll clock;
7829 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7830 int refclk = 100000;
7831
7832 /* In case of DSI, DPLL will not be used */
7833 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7834 return;
7835
7836 mutex_lock(&dev_priv->sb_lock);
7837 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7838 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7839 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7840 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7841 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7842 mutex_unlock(&dev_priv->sb_lock);
7843
7844 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7845 clock.m2 = (pll_dw0 & 0xff) << 22;
7846 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7847 clock.m2 |= pll_dw2 & 0x3fffff;
7848 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7849 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7850 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7851
7852 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7853 }
7854
7855 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7856 struct intel_crtc_state *pipe_config)
7857 {
7858 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7859 enum intel_display_power_domain power_domain;
7860 uint32_t tmp;
7861 bool ret;
7862
7863 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7864 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7865 return false;
7866
7867 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7868 pipe_config->shared_dpll = NULL;
7869
7870 ret = false;
7871
7872 tmp = I915_READ(PIPECONF(crtc->pipe));
7873 if (!(tmp & PIPECONF_ENABLE))
7874 goto out;
7875
7876 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7877 IS_CHERRYVIEW(dev_priv)) {
7878 switch (tmp & PIPECONF_BPC_MASK) {
7879 case PIPECONF_6BPC:
7880 pipe_config->pipe_bpp = 18;
7881 break;
7882 case PIPECONF_8BPC:
7883 pipe_config->pipe_bpp = 24;
7884 break;
7885 case PIPECONF_10BPC:
7886 pipe_config->pipe_bpp = 30;
7887 break;
7888 default:
7889 break;
7890 }
7891 }
7892
7893 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7894 (tmp & PIPECONF_COLOR_RANGE_SELECT))
7895 pipe_config->limited_color_range = true;
7896
7897 if (INTEL_GEN(dev_priv) < 4)
7898 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7899
7900 intel_get_pipe_timings(crtc, pipe_config);
7901 intel_get_pipe_src_size(crtc, pipe_config);
7902
7903 i9xx_get_pfit_config(crtc, pipe_config);
7904
7905 if (INTEL_GEN(dev_priv) >= 4) {
7906 /* No way to read it out on pipes B and C */
7907 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7908 tmp = dev_priv->chv_dpll_md[crtc->pipe];
7909 else
7910 tmp = I915_READ(DPLL_MD(crtc->pipe));
7911 pipe_config->pixel_multiplier =
7912 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7913 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7914 pipe_config->dpll_hw_state.dpll_md = tmp;
7915 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7916 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7917 tmp = I915_READ(DPLL(crtc->pipe));
7918 pipe_config->pixel_multiplier =
7919 ((tmp & SDVO_MULTIPLIER_MASK)
7920 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7921 } else {
7922 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7923 * port and will be fixed up in the encoder->get_config
7924 * function. */
7925 pipe_config->pixel_multiplier = 1;
7926 }
7927 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7928 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7929 /*
7930 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7931 * on 830. Filter it out here so that we don't
7932 * report errors due to that.
7933 */
7934 if (IS_I830(dev_priv))
7935 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7936
7937 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7938 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7939 } else {
7940 /* Mask out read-only status bits. */
7941 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7942 DPLL_PORTC_READY_MASK |
7943 DPLL_PORTB_READY_MASK);
7944 }
7945
7946 if (IS_CHERRYVIEW(dev_priv))
7947 chv_crtc_clock_get(crtc, pipe_config);
7948 else if (IS_VALLEYVIEW(dev_priv))
7949 vlv_crtc_clock_get(crtc, pipe_config);
7950 else
7951 i9xx_crtc_clock_get(crtc, pipe_config);
7952
7953 /*
7954 * Normally the dotclock is filled in by the encoder .get_config()
7955 * but in case the pipe is enabled w/o any ports we need a sane
7956 * default.
7957 */
7958 pipe_config->base.adjusted_mode.crtc_clock =
7959 pipe_config->port_clock / pipe_config->pixel_multiplier;
7960
7961 ret = true;
7962
7963 out:
7964 intel_display_power_put(dev_priv, power_domain);
7965
7966 return ret;
7967 }
7968
7969 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7970 {
7971 struct intel_encoder *encoder;
7972 int i;
7973 u32 val, final;
7974 bool has_lvds = false;
7975 bool has_cpu_edp = false;
7976 bool has_panel = false;
7977 bool has_ck505 = false;
7978 bool can_ssc = false;
7979 bool using_ssc_source = false;
7980
7981 /* We need to take the global config into account */
7982 for_each_intel_encoder(&dev_priv->drm, encoder) {
7983 switch (encoder->type) {
7984 case INTEL_OUTPUT_LVDS:
7985 has_panel = true;
7986 has_lvds = true;
7987 break;
7988 case INTEL_OUTPUT_EDP:
7989 has_panel = true;
7990 if (encoder->port == PORT_A)
7991 has_cpu_edp = true;
7992 break;
7993 default:
7994 break;
7995 }
7996 }
7997
7998 if (HAS_PCH_IBX(dev_priv)) {
7999 has_ck505 = dev_priv->vbt.display_clock_mode;
8000 can_ssc = has_ck505;
8001 } else {
8002 has_ck505 = false;
8003 can_ssc = true;
8004 }
8005
8006 /* Check if any DPLLs are using the SSC source */
8007 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8008 u32 temp = I915_READ(PCH_DPLL(i));
8009
8010 if (!(temp & DPLL_VCO_ENABLE))
8011 continue;
8012
8013 if ((temp & PLL_REF_INPUT_MASK) ==
8014 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8015 using_ssc_source = true;
8016 break;
8017 }
8018 }
8019
8020 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8021 has_panel, has_lvds, has_ck505, using_ssc_source);
8022
8023 /* Ironlake: try to setup display ref clock before DPLL
8024 * enabling. This is only under driver's control after
8025 * PCH B stepping, previous chipset stepping should be
8026 * ignoring this setting.
8027 */
8028 val = I915_READ(PCH_DREF_CONTROL);
8029
8030 /* As we must carefully and slowly disable/enable each source in turn,
8031 * compute the final state we want first and check if we need to
8032 * make any changes at all.
8033 */
8034 final = val;
8035 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8036 if (has_ck505)
8037 final |= DREF_NONSPREAD_CK505_ENABLE;
8038 else
8039 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8040
8041 final &= ~DREF_SSC_SOURCE_MASK;
8042 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8043 final &= ~DREF_SSC1_ENABLE;
8044
8045 if (has_panel) {
8046 final |= DREF_SSC_SOURCE_ENABLE;
8047
8048 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8049 final |= DREF_SSC1_ENABLE;
8050
8051 if (has_cpu_edp) {
8052 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8053 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8054 else
8055 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8056 } else
8057 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8058 } else if (using_ssc_source) {
8059 final |= DREF_SSC_SOURCE_ENABLE;
8060 final |= DREF_SSC1_ENABLE;
8061 }
8062
8063 if (final == val)
8064 return;
8065
8066 /* Always enable nonspread source */
8067 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8068
8069 if (has_ck505)
8070 val |= DREF_NONSPREAD_CK505_ENABLE;
8071 else
8072 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8073
8074 if (has_panel) {
8075 val &= ~DREF_SSC_SOURCE_MASK;
8076 val |= DREF_SSC_SOURCE_ENABLE;
8077
8078 /* SSC must be turned on before enabling the CPU output */
8079 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8080 DRM_DEBUG_KMS("Using SSC on panel\n");
8081 val |= DREF_SSC1_ENABLE;
8082 } else
8083 val &= ~DREF_SSC1_ENABLE;
8084
8085 /* Get SSC going before enabling the outputs */
8086 I915_WRITE(PCH_DREF_CONTROL, val);
8087 POSTING_READ(PCH_DREF_CONTROL);
8088 udelay(200);
8089
8090 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8091
8092 /* Enable CPU source on CPU attached eDP */
8093 if (has_cpu_edp) {
8094 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8095 DRM_DEBUG_KMS("Using SSC on eDP\n");
8096 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8097 } else
8098 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8099 } else
8100 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8101
8102 I915_WRITE(PCH_DREF_CONTROL, val);
8103 POSTING_READ(PCH_DREF_CONTROL);
8104 udelay(200);
8105 } else {
8106 DRM_DEBUG_KMS("Disabling CPU source output\n");
8107
8108 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8109
8110 /* Turn off CPU output */
8111 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8112
8113 I915_WRITE(PCH_DREF_CONTROL, val);
8114 POSTING_READ(PCH_DREF_CONTROL);
8115 udelay(200);
8116
8117 if (!using_ssc_source) {
8118 DRM_DEBUG_KMS("Disabling SSC source\n");
8119
8120 /* Turn off the SSC source */
8121 val &= ~DREF_SSC_SOURCE_MASK;
8122 val |= DREF_SSC_SOURCE_DISABLE;
8123
8124 /* Turn off SSC1 */
8125 val &= ~DREF_SSC1_ENABLE;
8126
8127 I915_WRITE(PCH_DREF_CONTROL, val);
8128 POSTING_READ(PCH_DREF_CONTROL);
8129 udelay(200);
8130 }
8131 }
8132
8133 BUG_ON(val != final);
8134 }
8135
8136 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8137 {
8138 uint32_t tmp;
8139
8140 tmp = I915_READ(SOUTH_CHICKEN2);
8141 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8142 I915_WRITE(SOUTH_CHICKEN2, tmp);
8143
8144 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8145 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8146 DRM_ERROR("FDI mPHY reset assert timeout\n");
8147
8148 tmp = I915_READ(SOUTH_CHICKEN2);
8149 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8150 I915_WRITE(SOUTH_CHICKEN2, tmp);
8151
8152 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8153 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8154 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8155 }
8156
8157 /* WaMPhyProgramming:hsw */
8158 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8159 {
8160 uint32_t tmp;
8161
8162 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8163 tmp &= ~(0xFF << 24);
8164 tmp |= (0x12 << 24);
8165 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8166
8167 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8168 tmp |= (1 << 11);
8169 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8170
8171 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8172 tmp |= (1 << 11);
8173 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8174
8175 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8176 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8177 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8178
8179 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8180 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8181 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8182
8183 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8184 tmp &= ~(7 << 13);
8185 tmp |= (5 << 13);
8186 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8187
8188 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8189 tmp &= ~(7 << 13);
8190 tmp |= (5 << 13);
8191 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8192
8193 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8194 tmp &= ~0xFF;
8195 tmp |= 0x1C;
8196 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8197
8198 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8199 tmp &= ~0xFF;
8200 tmp |= 0x1C;
8201 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8202
8203 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8204 tmp &= ~(0xFF << 16);
8205 tmp |= (0x1C << 16);
8206 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8207
8208 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8209 tmp &= ~(0xFF << 16);
8210 tmp |= (0x1C << 16);
8211 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8212
8213 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8214 tmp |= (1 << 27);
8215 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8216
8217 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8218 tmp |= (1 << 27);
8219 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8220
8221 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8222 tmp &= ~(0xF << 28);
8223 tmp |= (4 << 28);
8224 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8225
8226 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8227 tmp &= ~(0xF << 28);
8228 tmp |= (4 << 28);
8229 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8230 }
8231
8232 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8233 * Programming" based on the parameters passed:
8234 * - Sequence to enable CLKOUT_DP
8235 * - Sequence to enable CLKOUT_DP without spread
8236 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8237 */
8238 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
8239 bool with_spread, bool with_fdi)
8240 {
8241 uint32_t reg, tmp;
8242
8243 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8244 with_spread = true;
8245 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
8246 with_fdi, "LP PCH doesn't have FDI\n"))
8247 with_fdi = false;
8248
8249 mutex_lock(&dev_priv->sb_lock);
8250
8251 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8252 tmp &= ~SBI_SSCCTL_DISABLE;
8253 tmp |= SBI_SSCCTL_PATHALT;
8254 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8255
8256 udelay(24);
8257
8258 if (with_spread) {
8259 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8260 tmp &= ~SBI_SSCCTL_PATHALT;
8261 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8262
8263 if (with_fdi) {
8264 lpt_reset_fdi_mphy(dev_priv);
8265 lpt_program_fdi_mphy(dev_priv);
8266 }
8267 }
8268
8269 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8270 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8271 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8272 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8273
8274 mutex_unlock(&dev_priv->sb_lock);
8275 }
8276
8277 /* Sequence to disable CLKOUT_DP */
8278 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
8279 {
8280 uint32_t reg, tmp;
8281
8282 mutex_lock(&dev_priv->sb_lock);
8283
8284 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8285 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8286 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8287 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8288
8289 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8290 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8291 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8292 tmp |= SBI_SSCCTL_PATHALT;
8293 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8294 udelay(32);
8295 }
8296 tmp |= SBI_SSCCTL_DISABLE;
8297 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8298 }
8299
8300 mutex_unlock(&dev_priv->sb_lock);
8301 }
8302
8303 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8304
8305 static const uint16_t sscdivintphase[] = {
8306 [BEND_IDX( 50)] = 0x3B23,
8307 [BEND_IDX( 45)] = 0x3B23,
8308 [BEND_IDX( 40)] = 0x3C23,
8309 [BEND_IDX( 35)] = 0x3C23,
8310 [BEND_IDX( 30)] = 0x3D23,
8311 [BEND_IDX( 25)] = 0x3D23,
8312 [BEND_IDX( 20)] = 0x3E23,
8313 [BEND_IDX( 15)] = 0x3E23,
8314 [BEND_IDX( 10)] = 0x3F23,
8315 [BEND_IDX( 5)] = 0x3F23,
8316 [BEND_IDX( 0)] = 0x0025,
8317 [BEND_IDX( -5)] = 0x0025,
8318 [BEND_IDX(-10)] = 0x0125,
8319 [BEND_IDX(-15)] = 0x0125,
8320 [BEND_IDX(-20)] = 0x0225,
8321 [BEND_IDX(-25)] = 0x0225,
8322 [BEND_IDX(-30)] = 0x0325,
8323 [BEND_IDX(-35)] = 0x0325,
8324 [BEND_IDX(-40)] = 0x0425,
8325 [BEND_IDX(-45)] = 0x0425,
8326 [BEND_IDX(-50)] = 0x0525,
8327 };
8328
8329 /*
8330 * Bend CLKOUT_DP
8331 * steps -50 to 50 inclusive, in steps of 5
8332 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8333 * change in clock period = -(steps / 10) * 5.787 ps
8334 */
8335 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8336 {
8337 uint32_t tmp;
8338 int idx = BEND_IDX(steps);
8339
8340 if (WARN_ON(steps % 5 != 0))
8341 return;
8342
8343 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8344 return;
8345
8346 mutex_lock(&dev_priv->sb_lock);
8347
8348 if (steps % 10 != 0)
8349 tmp = 0xAAAAAAAB;
8350 else
8351 tmp = 0x00000000;
8352 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8353
8354 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8355 tmp &= 0xffff0000;
8356 tmp |= sscdivintphase[idx];
8357 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8358
8359 mutex_unlock(&dev_priv->sb_lock);
8360 }
8361
8362 #undef BEND_IDX
8363
8364 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
8365 {
8366 struct intel_encoder *encoder;
8367 bool has_vga = false;
8368
8369 for_each_intel_encoder(&dev_priv->drm, encoder) {
8370 switch (encoder->type) {
8371 case INTEL_OUTPUT_ANALOG:
8372 has_vga = true;
8373 break;
8374 default:
8375 break;
8376 }
8377 }
8378
8379 if (has_vga) {
8380 lpt_bend_clkout_dp(dev_priv, 0);
8381 lpt_enable_clkout_dp(dev_priv, true, true);
8382 } else {
8383 lpt_disable_clkout_dp(dev_priv);
8384 }
8385 }
8386
8387 /*
8388 * Initialize reference clocks when the driver loads
8389 */
8390 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8391 {
8392 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8393 ironlake_init_pch_refclk(dev_priv);
8394 else if (HAS_PCH_LPT(dev_priv))
8395 lpt_init_pch_refclk(dev_priv);
8396 }
8397
8398 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8399 {
8400 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8401 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8402 int pipe = intel_crtc->pipe;
8403 uint32_t val;
8404
8405 val = 0;
8406
8407 switch (intel_crtc->config->pipe_bpp) {
8408 case 18:
8409 val |= PIPECONF_6BPC;
8410 break;
8411 case 24:
8412 val |= PIPECONF_8BPC;
8413 break;
8414 case 30:
8415 val |= PIPECONF_10BPC;
8416 break;
8417 case 36:
8418 val |= PIPECONF_12BPC;
8419 break;
8420 default:
8421 /* Case prevented by intel_choose_pipe_bpp_dither. */
8422 BUG();
8423 }
8424
8425 if (intel_crtc->config->dither)
8426 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8427
8428 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8429 val |= PIPECONF_INTERLACED_ILK;
8430 else
8431 val |= PIPECONF_PROGRESSIVE;
8432
8433 if (intel_crtc->config->limited_color_range)
8434 val |= PIPECONF_COLOR_RANGE_SELECT;
8435
8436 I915_WRITE(PIPECONF(pipe), val);
8437 POSTING_READ(PIPECONF(pipe));
8438 }
8439
8440 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8441 {
8442 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8443 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8444 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8445 u32 val = 0;
8446
8447 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8448 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8449
8450 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8451 val |= PIPECONF_INTERLACED_ILK;
8452 else
8453 val |= PIPECONF_PROGRESSIVE;
8454
8455 I915_WRITE(PIPECONF(cpu_transcoder), val);
8456 POSTING_READ(PIPECONF(cpu_transcoder));
8457 }
8458
8459 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8460 {
8461 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8462 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8463 struct intel_crtc_state *config = intel_crtc->config;
8464
8465 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
8466 u32 val = 0;
8467
8468 switch (intel_crtc->config->pipe_bpp) {
8469 case 18:
8470 val |= PIPEMISC_DITHER_6_BPC;
8471 break;
8472 case 24:
8473 val |= PIPEMISC_DITHER_8_BPC;
8474 break;
8475 case 30:
8476 val |= PIPEMISC_DITHER_10_BPC;
8477 break;
8478 case 36:
8479 val |= PIPEMISC_DITHER_12_BPC;
8480 break;
8481 default:
8482 /* Case prevented by pipe_config_set_bpp. */
8483 BUG();
8484 }
8485
8486 if (intel_crtc->config->dither)
8487 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8488
8489 if (config->ycbcr420) {
8490 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV |
8491 PIPEMISC_YUV420_ENABLE |
8492 PIPEMISC_YUV420_MODE_FULL_BLEND;
8493 }
8494
8495 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8496 }
8497 }
8498
8499 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8500 {
8501 /*
8502 * Account for spread spectrum to avoid
8503 * oversubscribing the link. Max center spread
8504 * is 2.5%; use 5% for safety's sake.
8505 */
8506 u32 bps = target_clock * bpp * 21 / 20;
8507 return DIV_ROUND_UP(bps, link_bw * 8);
8508 }
8509
8510 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8511 {
8512 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8513 }
8514
8515 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8516 struct intel_crtc_state *crtc_state,
8517 struct dpll *reduced_clock)
8518 {
8519 struct drm_crtc *crtc = &intel_crtc->base;
8520 struct drm_device *dev = crtc->dev;
8521 struct drm_i915_private *dev_priv = to_i915(dev);
8522 u32 dpll, fp, fp2;
8523 int factor;
8524
8525 /* Enable autotuning of the PLL clock (if permissible) */
8526 factor = 21;
8527 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8528 if ((intel_panel_use_ssc(dev_priv) &&
8529 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8530 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8531 factor = 25;
8532 } else if (crtc_state->sdvo_tv_clock)
8533 factor = 20;
8534
8535 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8536
8537 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8538 fp |= FP_CB_TUNE;
8539
8540 if (reduced_clock) {
8541 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8542
8543 if (reduced_clock->m < factor * reduced_clock->n)
8544 fp2 |= FP_CB_TUNE;
8545 } else {
8546 fp2 = fp;
8547 }
8548
8549 dpll = 0;
8550
8551 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8552 dpll |= DPLLB_MODE_LVDS;
8553 else
8554 dpll |= DPLLB_MODE_DAC_SERIAL;
8555
8556 dpll |= (crtc_state->pixel_multiplier - 1)
8557 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8558
8559 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8560 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8561 dpll |= DPLL_SDVO_HIGH_SPEED;
8562
8563 if (intel_crtc_has_dp_encoder(crtc_state))
8564 dpll |= DPLL_SDVO_HIGH_SPEED;
8565
8566 /*
8567 * The high speed IO clock is only really required for
8568 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8569 * possible to share the DPLL between CRT and HDMI. Enabling
8570 * the clock needlessly does no real harm, except use up a
8571 * bit of power potentially.
8572 *
8573 * We'll limit this to IVB with 3 pipes, since it has only two
8574 * DPLLs and so DPLL sharing is the only way to get three pipes
8575 * driving PCH ports at the same time. On SNB we could do this,
8576 * and potentially avoid enabling the second DPLL, but it's not
8577 * clear if it''s a win or loss power wise. No point in doing
8578 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8579 */
8580 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8581 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8582 dpll |= DPLL_SDVO_HIGH_SPEED;
8583
8584 /* compute bitmask from p1 value */
8585 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8586 /* also FPA1 */
8587 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8588
8589 switch (crtc_state->dpll.p2) {
8590 case 5:
8591 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8592 break;
8593 case 7:
8594 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8595 break;
8596 case 10:
8597 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8598 break;
8599 case 14:
8600 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8601 break;
8602 }
8603
8604 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8605 intel_panel_use_ssc(dev_priv))
8606 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8607 else
8608 dpll |= PLL_REF_INPUT_DREFCLK;
8609
8610 dpll |= DPLL_VCO_ENABLE;
8611
8612 crtc_state->dpll_hw_state.dpll = dpll;
8613 crtc_state->dpll_hw_state.fp0 = fp;
8614 crtc_state->dpll_hw_state.fp1 = fp2;
8615 }
8616
8617 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8618 struct intel_crtc_state *crtc_state)
8619 {
8620 struct drm_device *dev = crtc->base.dev;
8621 struct drm_i915_private *dev_priv = to_i915(dev);
8622 const struct intel_limit *limit;
8623 int refclk = 120000;
8624
8625 memset(&crtc_state->dpll_hw_state, 0,
8626 sizeof(crtc_state->dpll_hw_state));
8627
8628 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8629 if (!crtc_state->has_pch_encoder)
8630 return 0;
8631
8632 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8633 if (intel_panel_use_ssc(dev_priv)) {
8634 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8635 dev_priv->vbt.lvds_ssc_freq);
8636 refclk = dev_priv->vbt.lvds_ssc_freq;
8637 }
8638
8639 if (intel_is_dual_link_lvds(dev)) {
8640 if (refclk == 100000)
8641 limit = &intel_limits_ironlake_dual_lvds_100m;
8642 else
8643 limit = &intel_limits_ironlake_dual_lvds;
8644 } else {
8645 if (refclk == 100000)
8646 limit = &intel_limits_ironlake_single_lvds_100m;
8647 else
8648 limit = &intel_limits_ironlake_single_lvds;
8649 }
8650 } else {
8651 limit = &intel_limits_ironlake_dac;
8652 }
8653
8654 if (!crtc_state->clock_set &&
8655 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8656 refclk, NULL, &crtc_state->dpll)) {
8657 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8658 return -EINVAL;
8659 }
8660
8661 ironlake_compute_dpll(crtc, crtc_state, NULL);
8662
8663 if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8664 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8665 pipe_name(crtc->pipe));
8666 return -EINVAL;
8667 }
8668
8669 return 0;
8670 }
8671
8672 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8673 struct intel_link_m_n *m_n)
8674 {
8675 struct drm_device *dev = crtc->base.dev;
8676 struct drm_i915_private *dev_priv = to_i915(dev);
8677 enum pipe pipe = crtc->pipe;
8678
8679 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8680 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8681 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8682 & ~TU_SIZE_MASK;
8683 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8684 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8685 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8686 }
8687
8688 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8689 enum transcoder transcoder,
8690 struct intel_link_m_n *m_n,
8691 struct intel_link_m_n *m2_n2)
8692 {
8693 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8694 enum pipe pipe = crtc->pipe;
8695
8696 if (INTEL_GEN(dev_priv) >= 5) {
8697 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8698 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8699 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8700 & ~TU_SIZE_MASK;
8701 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8702 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8703 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8704 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8705 * gen < 8) and if DRRS is supported (to make sure the
8706 * registers are not unnecessarily read).
8707 */
8708 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8709 crtc->config->has_drrs) {
8710 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8711 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8712 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8713 & ~TU_SIZE_MASK;
8714 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8715 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8716 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8717 }
8718 } else {
8719 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8720 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8721 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8722 & ~TU_SIZE_MASK;
8723 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8724 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8725 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8726 }
8727 }
8728
8729 void intel_dp_get_m_n(struct intel_crtc *crtc,
8730 struct intel_crtc_state *pipe_config)
8731 {
8732 if (pipe_config->has_pch_encoder)
8733 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8734 else
8735 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8736 &pipe_config->dp_m_n,
8737 &pipe_config->dp_m2_n2);
8738 }
8739
8740 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8741 struct intel_crtc_state *pipe_config)
8742 {
8743 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8744 &pipe_config->fdi_m_n, NULL);
8745 }
8746
8747 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8748 struct intel_crtc_state *pipe_config)
8749 {
8750 struct drm_device *dev = crtc->base.dev;
8751 struct drm_i915_private *dev_priv = to_i915(dev);
8752 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8753 uint32_t ps_ctrl = 0;
8754 int id = -1;
8755 int i;
8756
8757 /* find scaler attached to this pipe */
8758 for (i = 0; i < crtc->num_scalers; i++) {
8759 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8760 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8761 id = i;
8762 pipe_config->pch_pfit.enabled = true;
8763 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8764 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8765 break;
8766 }
8767 }
8768
8769 scaler_state->scaler_id = id;
8770 if (id >= 0) {
8771 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8772 } else {
8773 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8774 }
8775 }
8776
8777 static void
8778 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8779 struct intel_initial_plane_config *plane_config)
8780 {
8781 struct drm_device *dev = crtc->base.dev;
8782 struct drm_i915_private *dev_priv = to_i915(dev);
8783 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8784 enum plane_id plane_id = plane->id;
8785 enum pipe pipe;
8786 u32 val, base, offset, stride_mult, tiling, alpha;
8787 int fourcc, pixel_format;
8788 unsigned int aligned_height;
8789 struct drm_framebuffer *fb;
8790 struct intel_framebuffer *intel_fb;
8791
8792 if (!plane->get_hw_state(plane, &pipe))
8793 return;
8794
8795 WARN_ON(pipe != crtc->pipe);
8796
8797 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8798 if (!intel_fb) {
8799 DRM_DEBUG_KMS("failed to alloc fb\n");
8800 return;
8801 }
8802
8803 fb = &intel_fb->base;
8804
8805 fb->dev = dev;
8806
8807 val = I915_READ(PLANE_CTL(pipe, plane_id));
8808
8809 if (INTEL_GEN(dev_priv) >= 11)
8810 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
8811 else
8812 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8813
8814 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
8815 alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
8816 alpha &= PLANE_COLOR_ALPHA_MASK;
8817 } else {
8818 alpha = val & PLANE_CTL_ALPHA_MASK;
8819 }
8820
8821 fourcc = skl_format_to_fourcc(pixel_format,
8822 val & PLANE_CTL_ORDER_RGBX, alpha);
8823 fb->format = drm_format_info(fourcc);
8824
8825 tiling = val & PLANE_CTL_TILED_MASK;
8826 switch (tiling) {
8827 case PLANE_CTL_TILED_LINEAR:
8828 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8829 break;
8830 case PLANE_CTL_TILED_X:
8831 plane_config->tiling = I915_TILING_X;
8832 fb->modifier = I915_FORMAT_MOD_X_TILED;
8833 break;
8834 case PLANE_CTL_TILED_Y:
8835 plane_config->tiling = I915_TILING_Y;
8836 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
8837 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
8838 else
8839 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8840 break;
8841 case PLANE_CTL_TILED_YF:
8842 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
8843 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
8844 else
8845 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8846 break;
8847 default:
8848 MISSING_CASE(tiling);
8849 goto error;
8850 }
8851
8852 base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
8853 plane_config->base = base;
8854
8855 offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
8856
8857 val = I915_READ(PLANE_SIZE(pipe, plane_id));
8858 fb->height = ((val >> 16) & 0xfff) + 1;
8859 fb->width = ((val >> 0) & 0x1fff) + 1;
8860
8861 val = I915_READ(PLANE_STRIDE(pipe, plane_id));
8862 stride_mult = intel_fb_stride_alignment(fb, 0);
8863 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8864
8865 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8866
8867 plane_config->size = fb->pitches[0] * aligned_height;
8868
8869 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8870 crtc->base.name, plane->base.name, fb->width, fb->height,
8871 fb->format->cpp[0] * 8, base, fb->pitches[0],
8872 plane_config->size);
8873
8874 plane_config->fb = intel_fb;
8875 return;
8876
8877 error:
8878 kfree(intel_fb);
8879 }
8880
8881 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8882 struct intel_crtc_state *pipe_config)
8883 {
8884 struct drm_device *dev = crtc->base.dev;
8885 struct drm_i915_private *dev_priv = to_i915(dev);
8886 uint32_t tmp;
8887
8888 tmp = I915_READ(PF_CTL(crtc->pipe));
8889
8890 if (tmp & PF_ENABLE) {
8891 pipe_config->pch_pfit.enabled = true;
8892 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8893 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8894
8895 /* We currently do not free assignements of panel fitters on
8896 * ivb/hsw (since we don't use the higher upscaling modes which
8897 * differentiates them) so just WARN about this case for now. */
8898 if (IS_GEN7(dev_priv)) {
8899 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8900 PF_PIPE_SEL_IVB(crtc->pipe));
8901 }
8902 }
8903 }
8904
8905 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8906 struct intel_crtc_state *pipe_config)
8907 {
8908 struct drm_device *dev = crtc->base.dev;
8909 struct drm_i915_private *dev_priv = to_i915(dev);
8910 enum intel_display_power_domain power_domain;
8911 uint32_t tmp;
8912 bool ret;
8913
8914 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8915 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8916 return false;
8917
8918 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8919 pipe_config->shared_dpll = NULL;
8920
8921 ret = false;
8922 tmp = I915_READ(PIPECONF(crtc->pipe));
8923 if (!(tmp & PIPECONF_ENABLE))
8924 goto out;
8925
8926 switch (tmp & PIPECONF_BPC_MASK) {
8927 case PIPECONF_6BPC:
8928 pipe_config->pipe_bpp = 18;
8929 break;
8930 case PIPECONF_8BPC:
8931 pipe_config->pipe_bpp = 24;
8932 break;
8933 case PIPECONF_10BPC:
8934 pipe_config->pipe_bpp = 30;
8935 break;
8936 case PIPECONF_12BPC:
8937 pipe_config->pipe_bpp = 36;
8938 break;
8939 default:
8940 break;
8941 }
8942
8943 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8944 pipe_config->limited_color_range = true;
8945
8946 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8947 struct intel_shared_dpll *pll;
8948 enum intel_dpll_id pll_id;
8949
8950 pipe_config->has_pch_encoder = true;
8951
8952 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8953 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8954 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8955
8956 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8957
8958 if (HAS_PCH_IBX(dev_priv)) {
8959 /*
8960 * The pipe->pch transcoder and pch transcoder->pll
8961 * mapping is fixed.
8962 */
8963 pll_id = (enum intel_dpll_id) crtc->pipe;
8964 } else {
8965 tmp = I915_READ(PCH_DPLL_SEL);
8966 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8967 pll_id = DPLL_ID_PCH_PLL_B;
8968 else
8969 pll_id= DPLL_ID_PCH_PLL_A;
8970 }
8971
8972 pipe_config->shared_dpll =
8973 intel_get_shared_dpll_by_id(dev_priv, pll_id);
8974 pll = pipe_config->shared_dpll;
8975
8976 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
8977 &pipe_config->dpll_hw_state));
8978
8979 tmp = pipe_config->dpll_hw_state.dpll;
8980 pipe_config->pixel_multiplier =
8981 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8982 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8983
8984 ironlake_pch_clock_get(crtc, pipe_config);
8985 } else {
8986 pipe_config->pixel_multiplier = 1;
8987 }
8988
8989 intel_get_pipe_timings(crtc, pipe_config);
8990 intel_get_pipe_src_size(crtc, pipe_config);
8991
8992 ironlake_get_pfit_config(crtc, pipe_config);
8993
8994 ret = true;
8995
8996 out:
8997 intel_display_power_put(dev_priv, power_domain);
8998
8999 return ret;
9000 }
9001
9002 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9003 {
9004 struct drm_device *dev = &dev_priv->drm;
9005 struct intel_crtc *crtc;
9006
9007 for_each_intel_crtc(dev, crtc)
9008 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9009 pipe_name(crtc->pipe));
9010
9011 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)),
9012 "Display power well on\n");
9013 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9014 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9015 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9016 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
9017 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9018 "CPU PWM1 enabled\n");
9019 if (IS_HASWELL(dev_priv))
9020 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9021 "CPU PWM2 enabled\n");
9022 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9023 "PCH PWM1 enabled\n");
9024 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9025 "Utility pin enabled\n");
9026 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9027
9028 /*
9029 * In theory we can still leave IRQs enabled, as long as only the HPD
9030 * interrupts remain enabled. We used to check for that, but since it's
9031 * gen-specific and since we only disable LCPLL after we fully disable
9032 * the interrupts, the check below should be enough.
9033 */
9034 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9035 }
9036
9037 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9038 {
9039 if (IS_HASWELL(dev_priv))
9040 return I915_READ(D_COMP_HSW);
9041 else
9042 return I915_READ(D_COMP_BDW);
9043 }
9044
9045 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9046 {
9047 if (IS_HASWELL(dev_priv)) {
9048 mutex_lock(&dev_priv->pcu_lock);
9049 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9050 val))
9051 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
9052 mutex_unlock(&dev_priv->pcu_lock);
9053 } else {
9054 I915_WRITE(D_COMP_BDW, val);
9055 POSTING_READ(D_COMP_BDW);
9056 }
9057 }
9058
9059 /*
9060 * This function implements pieces of two sequences from BSpec:
9061 * - Sequence for display software to disable LCPLL
9062 * - Sequence for display software to allow package C8+
9063 * The steps implemented here are just the steps that actually touch the LCPLL
9064 * register. Callers should take care of disabling all the display engine
9065 * functions, doing the mode unset, fixing interrupts, etc.
9066 */
9067 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9068 bool switch_to_fclk, bool allow_power_down)
9069 {
9070 uint32_t val;
9071
9072 assert_can_disable_lcpll(dev_priv);
9073
9074 val = I915_READ(LCPLL_CTL);
9075
9076 if (switch_to_fclk) {
9077 val |= LCPLL_CD_SOURCE_FCLK;
9078 I915_WRITE(LCPLL_CTL, val);
9079
9080 if (wait_for_us(I915_READ(LCPLL_CTL) &
9081 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9082 DRM_ERROR("Switching to FCLK failed\n");
9083
9084 val = I915_READ(LCPLL_CTL);
9085 }
9086
9087 val |= LCPLL_PLL_DISABLE;
9088 I915_WRITE(LCPLL_CTL, val);
9089 POSTING_READ(LCPLL_CTL);
9090
9091 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
9092 DRM_ERROR("LCPLL still locked\n");
9093
9094 val = hsw_read_dcomp(dev_priv);
9095 val |= D_COMP_COMP_DISABLE;
9096 hsw_write_dcomp(dev_priv, val);
9097 ndelay(100);
9098
9099 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9100 1))
9101 DRM_ERROR("D_COMP RCOMP still in progress\n");
9102
9103 if (allow_power_down) {
9104 val = I915_READ(LCPLL_CTL);
9105 val |= LCPLL_POWER_DOWN_ALLOW;
9106 I915_WRITE(LCPLL_CTL, val);
9107 POSTING_READ(LCPLL_CTL);
9108 }
9109 }
9110
9111 /*
9112 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9113 * source.
9114 */
9115 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9116 {
9117 uint32_t val;
9118
9119 val = I915_READ(LCPLL_CTL);
9120
9121 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9122 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9123 return;
9124
9125 /*
9126 * Make sure we're not on PC8 state before disabling PC8, otherwise
9127 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9128 */
9129 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9130
9131 if (val & LCPLL_POWER_DOWN_ALLOW) {
9132 val &= ~LCPLL_POWER_DOWN_ALLOW;
9133 I915_WRITE(LCPLL_CTL, val);
9134 POSTING_READ(LCPLL_CTL);
9135 }
9136
9137 val = hsw_read_dcomp(dev_priv);
9138 val |= D_COMP_COMP_FORCE;
9139 val &= ~D_COMP_COMP_DISABLE;
9140 hsw_write_dcomp(dev_priv, val);
9141
9142 val = I915_READ(LCPLL_CTL);
9143 val &= ~LCPLL_PLL_DISABLE;
9144 I915_WRITE(LCPLL_CTL, val);
9145
9146 if (intel_wait_for_register(dev_priv,
9147 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
9148 5))
9149 DRM_ERROR("LCPLL not locked yet\n");
9150
9151 if (val & LCPLL_CD_SOURCE_FCLK) {
9152 val = I915_READ(LCPLL_CTL);
9153 val &= ~LCPLL_CD_SOURCE_FCLK;
9154 I915_WRITE(LCPLL_CTL, val);
9155
9156 if (wait_for_us((I915_READ(LCPLL_CTL) &
9157 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9158 DRM_ERROR("Switching back to LCPLL failed\n");
9159 }
9160
9161 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9162
9163 intel_update_cdclk(dev_priv);
9164 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
9165 }
9166
9167 /*
9168 * Package states C8 and deeper are really deep PC states that can only be
9169 * reached when all the devices on the system allow it, so even if the graphics
9170 * device allows PC8+, it doesn't mean the system will actually get to these
9171 * states. Our driver only allows PC8+ when going into runtime PM.
9172 *
9173 * The requirements for PC8+ are that all the outputs are disabled, the power
9174 * well is disabled and most interrupts are disabled, and these are also
9175 * requirements for runtime PM. When these conditions are met, we manually do
9176 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9177 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9178 * hang the machine.
9179 *
9180 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9181 * the state of some registers, so when we come back from PC8+ we need to
9182 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9183 * need to take care of the registers kept by RC6. Notice that this happens even
9184 * if we don't put the device in PCI D3 state (which is what currently happens
9185 * because of the runtime PM support).
9186 *
9187 * For more, read "Display Sequences for Package C8" on the hardware
9188 * documentation.
9189 */
9190 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9191 {
9192 uint32_t val;
9193
9194 DRM_DEBUG_KMS("Enabling package C8+\n");
9195
9196 if (HAS_PCH_LPT_LP(dev_priv)) {
9197 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9198 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9199 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9200 }
9201
9202 lpt_disable_clkout_dp(dev_priv);
9203 hsw_disable_lcpll(dev_priv, true, true);
9204 }
9205
9206 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9207 {
9208 uint32_t val;
9209
9210 DRM_DEBUG_KMS("Disabling package C8+\n");
9211
9212 hsw_restore_lcpll(dev_priv);
9213 lpt_init_pch_refclk(dev_priv);
9214
9215 if (HAS_PCH_LPT_LP(dev_priv)) {
9216 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9217 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9218 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9219 }
9220 }
9221
9222 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9223 struct intel_crtc_state *crtc_state)
9224 {
9225 struct intel_atomic_state *state =
9226 to_intel_atomic_state(crtc_state->base.state);
9227
9228 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
9229 struct intel_encoder *encoder =
9230 intel_get_crtc_new_encoder(state, crtc_state);
9231
9232 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
9233 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9234 pipe_name(crtc->pipe));
9235 return -EINVAL;
9236 }
9237 }
9238
9239 return 0;
9240 }
9241
9242 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
9243 enum port port,
9244 struct intel_crtc_state *pipe_config)
9245 {
9246 enum intel_dpll_id id;
9247 u32 temp;
9248
9249 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9250 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
9251
9252 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
9253 return;
9254
9255 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9256 }
9257
9258 static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
9259 enum port port,
9260 struct intel_crtc_state *pipe_config)
9261 {
9262 enum intel_dpll_id id;
9263 u32 temp;
9264
9265 /* TODO: TBT pll not implemented. */
9266 switch (port) {
9267 case PORT_A:
9268 case PORT_B:
9269 temp = I915_READ(DPCLKA_CFGCR0_ICL) &
9270 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9271 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
9272
9273 if (WARN_ON(id != DPLL_ID_ICL_DPLL0 && id != DPLL_ID_ICL_DPLL1))
9274 return;
9275 break;
9276 case PORT_C:
9277 id = DPLL_ID_ICL_MGPLL1;
9278 break;
9279 case PORT_D:
9280 id = DPLL_ID_ICL_MGPLL2;
9281 break;
9282 case PORT_E:
9283 id = DPLL_ID_ICL_MGPLL3;
9284 break;
9285 case PORT_F:
9286 id = DPLL_ID_ICL_MGPLL4;
9287 break;
9288 default:
9289 MISSING_CASE(port);
9290 return;
9291 }
9292
9293 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9294 }
9295
9296 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9297 enum port port,
9298 struct intel_crtc_state *pipe_config)
9299 {
9300 enum intel_dpll_id id;
9301
9302 switch (port) {
9303 case PORT_A:
9304 id = DPLL_ID_SKL_DPLL0;
9305 break;
9306 case PORT_B:
9307 id = DPLL_ID_SKL_DPLL1;
9308 break;
9309 case PORT_C:
9310 id = DPLL_ID_SKL_DPLL2;
9311 break;
9312 default:
9313 DRM_ERROR("Incorrect port type\n");
9314 return;
9315 }
9316
9317 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9318 }
9319
9320 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9321 enum port port,
9322 struct intel_crtc_state *pipe_config)
9323 {
9324 enum intel_dpll_id id;
9325 u32 temp;
9326
9327 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9328 id = temp >> (port * 3 + 1);
9329
9330 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
9331 return;
9332
9333 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9334 }
9335
9336 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9337 enum port port,
9338 struct intel_crtc_state *pipe_config)
9339 {
9340 enum intel_dpll_id id;
9341 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9342
9343 switch (ddi_pll_sel) {
9344 case PORT_CLK_SEL_WRPLL1:
9345 id = DPLL_ID_WRPLL1;
9346 break;
9347 case PORT_CLK_SEL_WRPLL2:
9348 id = DPLL_ID_WRPLL2;
9349 break;
9350 case PORT_CLK_SEL_SPLL:
9351 id = DPLL_ID_SPLL;
9352 break;
9353 case PORT_CLK_SEL_LCPLL_810:
9354 id = DPLL_ID_LCPLL_810;
9355 break;
9356 case PORT_CLK_SEL_LCPLL_1350:
9357 id = DPLL_ID_LCPLL_1350;
9358 break;
9359 case PORT_CLK_SEL_LCPLL_2700:
9360 id = DPLL_ID_LCPLL_2700;
9361 break;
9362 default:
9363 MISSING_CASE(ddi_pll_sel);
9364 /* fall through */
9365 case PORT_CLK_SEL_NONE:
9366 return;
9367 }
9368
9369 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9370 }
9371
9372 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9373 struct intel_crtc_state *pipe_config,
9374 u64 *power_domain_mask)
9375 {
9376 struct drm_device *dev = crtc->base.dev;
9377 struct drm_i915_private *dev_priv = to_i915(dev);
9378 enum intel_display_power_domain power_domain;
9379 u32 tmp;
9380
9381 /*
9382 * The pipe->transcoder mapping is fixed with the exception of the eDP
9383 * transcoder handled below.
9384 */
9385 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9386
9387 /*
9388 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9389 * consistency and less surprising code; it's in always on power).
9390 */
9391 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9392 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9393 enum pipe trans_edp_pipe;
9394 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9395 default:
9396 WARN(1, "unknown pipe linked to edp transcoder\n");
9397 /* fall through */
9398 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9399 case TRANS_DDI_EDP_INPUT_A_ON:
9400 trans_edp_pipe = PIPE_A;
9401 break;
9402 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9403 trans_edp_pipe = PIPE_B;
9404 break;
9405 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9406 trans_edp_pipe = PIPE_C;
9407 break;
9408 }
9409
9410 if (trans_edp_pipe == crtc->pipe)
9411 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9412 }
9413
9414 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9415 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9416 return false;
9417 *power_domain_mask |= BIT_ULL(power_domain);
9418
9419 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9420
9421 return tmp & PIPECONF_ENABLE;
9422 }
9423
9424 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9425 struct intel_crtc_state *pipe_config,
9426 u64 *power_domain_mask)
9427 {
9428 struct drm_device *dev = crtc->base.dev;
9429 struct drm_i915_private *dev_priv = to_i915(dev);
9430 enum intel_display_power_domain power_domain;
9431 enum port port;
9432 enum transcoder cpu_transcoder;
9433 u32 tmp;
9434
9435 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9436 if (port == PORT_A)
9437 cpu_transcoder = TRANSCODER_DSI_A;
9438 else
9439 cpu_transcoder = TRANSCODER_DSI_C;
9440
9441 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9442 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9443 continue;
9444 *power_domain_mask |= BIT_ULL(power_domain);
9445
9446 /*
9447 * The PLL needs to be enabled with a valid divider
9448 * configuration, otherwise accessing DSI registers will hang
9449 * the machine. See BSpec North Display Engine
9450 * registers/MIPI[BXT]. We can break out here early, since we
9451 * need the same DSI PLL to be enabled for both DSI ports.
9452 */
9453 if (!bxt_dsi_pll_is_enabled(dev_priv))
9454 break;
9455
9456 /* XXX: this works for video mode only */
9457 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9458 if (!(tmp & DPI_ENABLE))
9459 continue;
9460
9461 tmp = I915_READ(MIPI_CTRL(port));
9462 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9463 continue;
9464
9465 pipe_config->cpu_transcoder = cpu_transcoder;
9466 break;
9467 }
9468
9469 return transcoder_is_dsi(pipe_config->cpu_transcoder);
9470 }
9471
9472 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9473 struct intel_crtc_state *pipe_config)
9474 {
9475 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9476 struct intel_shared_dpll *pll;
9477 enum port port;
9478 uint32_t tmp;
9479
9480 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9481
9482 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9483
9484 if (IS_ICELAKE(dev_priv))
9485 icelake_get_ddi_pll(dev_priv, port, pipe_config);
9486 else if (IS_CANNONLAKE(dev_priv))
9487 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9488 else if (IS_GEN9_BC(dev_priv))
9489 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9490 else if (IS_GEN9_LP(dev_priv))
9491 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9492 else
9493 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9494
9495 pll = pipe_config->shared_dpll;
9496 if (pll) {
9497 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
9498 &pipe_config->dpll_hw_state));
9499 }
9500
9501 /*
9502 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9503 * DDI E. So just check whether this pipe is wired to DDI E and whether
9504 * the PCH transcoder is on.
9505 */
9506 if (INTEL_GEN(dev_priv) < 9 &&
9507 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9508 pipe_config->has_pch_encoder = true;
9509
9510 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9511 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9512 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9513
9514 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9515 }
9516 }
9517
9518 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9519 struct intel_crtc_state *pipe_config)
9520 {
9521 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9522 enum intel_display_power_domain power_domain;
9523 u64 power_domain_mask;
9524 bool active;
9525
9526 intel_crtc_init_scalers(crtc, pipe_config);
9527
9528 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9529 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9530 return false;
9531 power_domain_mask = BIT_ULL(power_domain);
9532
9533 pipe_config->shared_dpll = NULL;
9534
9535 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9536
9537 if (IS_GEN9_LP(dev_priv) &&
9538 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9539 WARN_ON(active);
9540 active = true;
9541 }
9542
9543 if (!active)
9544 goto out;
9545
9546 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9547 haswell_get_ddi_port_state(crtc, pipe_config);
9548 intel_get_pipe_timings(crtc, pipe_config);
9549 }
9550
9551 intel_get_pipe_src_size(crtc, pipe_config);
9552
9553 pipe_config->gamma_mode =
9554 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9555
9556 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
9557 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
9558 bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
9559
9560 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
9561 bool blend_mode_420 = tmp &
9562 PIPEMISC_YUV420_MODE_FULL_BLEND;
9563
9564 pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE;
9565 if (pipe_config->ycbcr420 != clrspace_yuv ||
9566 pipe_config->ycbcr420 != blend_mode_420)
9567 DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp);
9568 } else if (clrspace_yuv) {
9569 DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n");
9570 }
9571 }
9572
9573 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9574 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9575 power_domain_mask |= BIT_ULL(power_domain);
9576 if (INTEL_GEN(dev_priv) >= 9)
9577 skylake_get_pfit_config(crtc, pipe_config);
9578 else
9579 ironlake_get_pfit_config(crtc, pipe_config);
9580 }
9581
9582 if (hsw_crtc_supports_ips(crtc)) {
9583 if (IS_HASWELL(dev_priv))
9584 pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE;
9585 else {
9586 /*
9587 * We cannot readout IPS state on broadwell, set to
9588 * true so we can set it to a defined state on first
9589 * commit.
9590 */
9591 pipe_config->ips_enabled = true;
9592 }
9593 }
9594
9595 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9596 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9597 pipe_config->pixel_multiplier =
9598 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9599 } else {
9600 pipe_config->pixel_multiplier = 1;
9601 }
9602
9603 out:
9604 for_each_power_domain(power_domain, power_domain_mask)
9605 intel_display_power_put(dev_priv, power_domain);
9606
9607 return active;
9608 }
9609
9610 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9611 {
9612 struct drm_i915_private *dev_priv =
9613 to_i915(plane_state->base.plane->dev);
9614 const struct drm_framebuffer *fb = plane_state->base.fb;
9615 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9616 u32 base;
9617
9618 if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9619 base = obj->phys_handle->busaddr;
9620 else
9621 base = intel_plane_ggtt_offset(plane_state);
9622
9623 base += plane_state->main.offset;
9624
9625 /* ILK+ do this automagically */
9626 if (HAS_GMCH_DISPLAY(dev_priv) &&
9627 plane_state->base.rotation & DRM_MODE_ROTATE_180)
9628 base += (plane_state->base.crtc_h *
9629 plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9630
9631 return base;
9632 }
9633
9634 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9635 {
9636 int x = plane_state->base.crtc_x;
9637 int y = plane_state->base.crtc_y;
9638 u32 pos = 0;
9639
9640 if (x < 0) {
9641 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9642 x = -x;
9643 }
9644 pos |= x << CURSOR_X_SHIFT;
9645
9646 if (y < 0) {
9647 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9648 y = -y;
9649 }
9650 pos |= y << CURSOR_Y_SHIFT;
9651
9652 return pos;
9653 }
9654
9655 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9656 {
9657 const struct drm_mode_config *config =
9658 &plane_state->base.plane->dev->mode_config;
9659 int width = plane_state->base.crtc_w;
9660 int height = plane_state->base.crtc_h;
9661
9662 return width > 0 && width <= config->cursor_width &&
9663 height > 0 && height <= config->cursor_height;
9664 }
9665
9666 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9667 struct intel_plane_state *plane_state)
9668 {
9669 const struct drm_framebuffer *fb = plane_state->base.fb;
9670 int src_x, src_y;
9671 u32 offset;
9672 int ret;
9673
9674 ret = drm_atomic_helper_check_plane_state(&plane_state->base,
9675 &crtc_state->base,
9676 DRM_PLANE_HELPER_NO_SCALING,
9677 DRM_PLANE_HELPER_NO_SCALING,
9678 true, true);
9679 if (ret)
9680 return ret;
9681
9682 if (!fb)
9683 return 0;
9684
9685 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9686 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9687 return -EINVAL;
9688 }
9689
9690 src_x = plane_state->base.src_x >> 16;
9691 src_y = plane_state->base.src_y >> 16;
9692
9693 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9694 offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9695
9696 if (src_x != 0 || src_y != 0) {
9697 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9698 return -EINVAL;
9699 }
9700
9701 plane_state->main.offset = offset;
9702
9703 return 0;
9704 }
9705
9706 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9707 const struct intel_plane_state *plane_state)
9708 {
9709 const struct drm_framebuffer *fb = plane_state->base.fb;
9710
9711 return CURSOR_ENABLE |
9712 CURSOR_GAMMA_ENABLE |
9713 CURSOR_FORMAT_ARGB |
9714 CURSOR_STRIDE(fb->pitches[0]);
9715 }
9716
9717 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9718 {
9719 int width = plane_state->base.crtc_w;
9720
9721 /*
9722 * 845g/865g are only limited by the width of their cursors,
9723 * the height is arbitrary up to the precision of the register.
9724 */
9725 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9726 }
9727
9728 static int i845_check_cursor(struct intel_plane *plane,
9729 struct intel_crtc_state *crtc_state,
9730 struct intel_plane_state *plane_state)
9731 {
9732 const struct drm_framebuffer *fb = plane_state->base.fb;
9733 int ret;
9734
9735 ret = intel_check_cursor(crtc_state, plane_state);
9736 if (ret)
9737 return ret;
9738
9739 /* if we want to turn off the cursor ignore width and height */
9740 if (!fb)
9741 return 0;
9742
9743 /* Check for which cursor types we support */
9744 if (!i845_cursor_size_ok(plane_state)) {
9745 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9746 plane_state->base.crtc_w,
9747 plane_state->base.crtc_h);
9748 return -EINVAL;
9749 }
9750
9751 switch (fb->pitches[0]) {
9752 case 256:
9753 case 512:
9754 case 1024:
9755 case 2048:
9756 break;
9757 default:
9758 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9759 fb->pitches[0]);
9760 return -EINVAL;
9761 }
9762
9763 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9764
9765 return 0;
9766 }
9767
9768 static void i845_update_cursor(struct intel_plane *plane,
9769 const struct intel_crtc_state *crtc_state,
9770 const struct intel_plane_state *plane_state)
9771 {
9772 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9773 u32 cntl = 0, base = 0, pos = 0, size = 0;
9774 unsigned long irqflags;
9775
9776 if (plane_state && plane_state->base.visible) {
9777 unsigned int width = plane_state->base.crtc_w;
9778 unsigned int height = plane_state->base.crtc_h;
9779
9780 cntl = plane_state->ctl;
9781 size = (height << 12) | width;
9782
9783 base = intel_cursor_base(plane_state);
9784 pos = intel_cursor_position(plane_state);
9785 }
9786
9787 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9788
9789 /* On these chipsets we can only modify the base/size/stride
9790 * whilst the cursor is disabled.
9791 */
9792 if (plane->cursor.base != base ||
9793 plane->cursor.size != size ||
9794 plane->cursor.cntl != cntl) {
9795 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9796 I915_WRITE_FW(CURBASE(PIPE_A), base);
9797 I915_WRITE_FW(CURSIZE, size);
9798 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9799 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9800
9801 plane->cursor.base = base;
9802 plane->cursor.size = size;
9803 plane->cursor.cntl = cntl;
9804 } else {
9805 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9806 }
9807
9808 POSTING_READ_FW(CURCNTR(PIPE_A));
9809
9810 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9811 }
9812
9813 static void i845_disable_cursor(struct intel_plane *plane,
9814 struct intel_crtc *crtc)
9815 {
9816 i845_update_cursor(plane, NULL, NULL);
9817 }
9818
9819 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
9820 enum pipe *pipe)
9821 {
9822 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9823 enum intel_display_power_domain power_domain;
9824 bool ret;
9825
9826 power_domain = POWER_DOMAIN_PIPE(PIPE_A);
9827 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9828 return false;
9829
9830 ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
9831
9832 *pipe = PIPE_A;
9833
9834 intel_display_power_put(dev_priv, power_domain);
9835
9836 return ret;
9837 }
9838
9839 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9840 const struct intel_plane_state *plane_state)
9841 {
9842 struct drm_i915_private *dev_priv =
9843 to_i915(plane_state->base.plane->dev);
9844 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9845 u32 cntl = 0;
9846
9847 if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
9848 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
9849
9850 if (INTEL_GEN(dev_priv) <= 10) {
9851 cntl |= MCURSOR_GAMMA_ENABLE;
9852
9853 if (HAS_DDI(dev_priv))
9854 cntl |= MCURSOR_PIPE_CSC_ENABLE;
9855 }
9856
9857 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
9858 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9859
9860 switch (plane_state->base.crtc_w) {
9861 case 64:
9862 cntl |= MCURSOR_MODE_64_ARGB_AX;
9863 break;
9864 case 128:
9865 cntl |= MCURSOR_MODE_128_ARGB_AX;
9866 break;
9867 case 256:
9868 cntl |= MCURSOR_MODE_256_ARGB_AX;
9869 break;
9870 default:
9871 MISSING_CASE(plane_state->base.crtc_w);
9872 return 0;
9873 }
9874
9875 if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9876 cntl |= MCURSOR_ROTATE_180;
9877
9878 return cntl;
9879 }
9880
9881 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9882 {
9883 struct drm_i915_private *dev_priv =
9884 to_i915(plane_state->base.plane->dev);
9885 int width = plane_state->base.crtc_w;
9886 int height = plane_state->base.crtc_h;
9887
9888 if (!intel_cursor_size_ok(plane_state))
9889 return false;
9890
9891 /* Cursor width is limited to a few power-of-two sizes */
9892 switch (width) {
9893 case 256:
9894 case 128:
9895 case 64:
9896 break;
9897 default:
9898 return false;
9899 }
9900
9901 /*
9902 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9903 * height from 8 lines up to the cursor width, when the
9904 * cursor is not rotated. Everything else requires square
9905 * cursors.
9906 */
9907 if (HAS_CUR_FBC(dev_priv) &&
9908 plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9909 if (height < 8 || height > width)
9910 return false;
9911 } else {
9912 if (height != width)
9913 return false;
9914 }
9915
9916 return true;
9917 }
9918
9919 static int i9xx_check_cursor(struct intel_plane *plane,
9920 struct intel_crtc_state *crtc_state,
9921 struct intel_plane_state *plane_state)
9922 {
9923 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9924 const struct drm_framebuffer *fb = plane_state->base.fb;
9925 enum pipe pipe = plane->pipe;
9926 int ret;
9927
9928 ret = intel_check_cursor(crtc_state, plane_state);
9929 if (ret)
9930 return ret;
9931
9932 /* if we want to turn off the cursor ignore width and height */
9933 if (!fb)
9934 return 0;
9935
9936 /* Check for which cursor types we support */
9937 if (!i9xx_cursor_size_ok(plane_state)) {
9938 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9939 plane_state->base.crtc_w,
9940 plane_state->base.crtc_h);
9941 return -EINVAL;
9942 }
9943
9944 if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9945 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9946 fb->pitches[0], plane_state->base.crtc_w);
9947 return -EINVAL;
9948 }
9949
9950 /*
9951 * There's something wrong with the cursor on CHV pipe C.
9952 * If it straddles the left edge of the screen then
9953 * moving it away from the edge or disabling it often
9954 * results in a pipe underrun, and often that can lead to
9955 * dead pipe (constant underrun reported, and it scans
9956 * out just a solid color). To recover from that, the
9957 * display power well must be turned off and on again.
9958 * Refuse the put the cursor into that compromised position.
9959 */
9960 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9961 plane_state->base.visible && plane_state->base.crtc_x < 0) {
9962 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9963 return -EINVAL;
9964 }
9965
9966 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9967
9968 return 0;
9969 }
9970
9971 static void i9xx_update_cursor(struct intel_plane *plane,
9972 const struct intel_crtc_state *crtc_state,
9973 const struct intel_plane_state *plane_state)
9974 {
9975 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9976 enum pipe pipe = plane->pipe;
9977 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9978 unsigned long irqflags;
9979
9980 if (plane_state && plane_state->base.visible) {
9981 cntl = plane_state->ctl;
9982
9983 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9984 fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9985
9986 base = intel_cursor_base(plane_state);
9987 pos = intel_cursor_position(plane_state);
9988 }
9989
9990 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9991
9992 /*
9993 * On some platforms writing CURCNTR first will also
9994 * cause CURPOS to be armed by the CURBASE write.
9995 * Without the CURCNTR write the CURPOS write would
9996 * arm itself. Thus we always start the full update
9997 * with a CURCNTR write.
9998 *
9999 * On other platforms CURPOS always requires the
10000 * CURBASE write to arm the update. Additonally
10001 * a write to any of the cursor register will cancel
10002 * an already armed cursor update. Thus leaving out
10003 * the CURBASE write after CURPOS could lead to a
10004 * cursor that doesn't appear to move, or even change
10005 * shape. Thus we always write CURBASE.
10006 *
10007 * CURCNTR and CUR_FBC_CTL are always
10008 * armed by the CURBASE write only.
10009 */
10010 if (plane->cursor.base != base ||
10011 plane->cursor.size != fbc_ctl ||
10012 plane->cursor.cntl != cntl) {
10013 I915_WRITE_FW(CURCNTR(pipe), cntl);
10014 if (HAS_CUR_FBC(dev_priv))
10015 I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
10016 I915_WRITE_FW(CURPOS(pipe), pos);
10017 I915_WRITE_FW(CURBASE(pipe), base);
10018
10019 plane->cursor.base = base;
10020 plane->cursor.size = fbc_ctl;
10021 plane->cursor.cntl = cntl;
10022 } else {
10023 I915_WRITE_FW(CURPOS(pipe), pos);
10024 I915_WRITE_FW(CURBASE(pipe), base);
10025 }
10026
10027 POSTING_READ_FW(CURBASE(pipe));
10028
10029 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
10030 }
10031
10032 static void i9xx_disable_cursor(struct intel_plane *plane,
10033 struct intel_crtc *crtc)
10034 {
10035 i9xx_update_cursor(plane, NULL, NULL);
10036 }
10037
10038 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
10039 enum pipe *pipe)
10040 {
10041 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10042 enum intel_display_power_domain power_domain;
10043 bool ret;
10044 u32 val;
10045
10046 /*
10047 * Not 100% correct for planes that can move between pipes,
10048 * but that's only the case for gen2-3 which don't have any
10049 * display power wells.
10050 */
10051 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
10052 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10053 return false;
10054
10055 val = I915_READ(CURCNTR(plane->pipe));
10056
10057 ret = val & MCURSOR_MODE;
10058
10059 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
10060 *pipe = plane->pipe;
10061 else
10062 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
10063 MCURSOR_PIPE_SELECT_SHIFT;
10064
10065 intel_display_power_put(dev_priv, power_domain);
10066
10067 return ret;
10068 }
10069
10070 /* VESA 640x480x72Hz mode to set on the pipe */
10071 static const struct drm_display_mode load_detect_mode = {
10072 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10073 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10074 };
10075
10076 struct drm_framebuffer *
10077 intel_framebuffer_create(struct drm_i915_gem_object *obj,
10078 struct drm_mode_fb_cmd2 *mode_cmd)
10079 {
10080 struct intel_framebuffer *intel_fb;
10081 int ret;
10082
10083 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10084 if (!intel_fb)
10085 return ERR_PTR(-ENOMEM);
10086
10087 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
10088 if (ret)
10089 goto err;
10090
10091 return &intel_fb->base;
10092
10093 err:
10094 kfree(intel_fb);
10095 return ERR_PTR(ret);
10096 }
10097
10098 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
10099 struct drm_crtc *crtc)
10100 {
10101 struct drm_plane *plane;
10102 struct drm_plane_state *plane_state;
10103 int ret, i;
10104
10105 ret = drm_atomic_add_affected_planes(state, crtc);
10106 if (ret)
10107 return ret;
10108
10109 for_each_new_plane_in_state(state, plane, plane_state, i) {
10110 if (plane_state->crtc != crtc)
10111 continue;
10112
10113 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
10114 if (ret)
10115 return ret;
10116
10117 drm_atomic_set_fb_for_plane(plane_state, NULL);
10118 }
10119
10120 return 0;
10121 }
10122
10123 int intel_get_load_detect_pipe(struct drm_connector *connector,
10124 const struct drm_display_mode *mode,
10125 struct intel_load_detect_pipe *old,
10126 struct drm_modeset_acquire_ctx *ctx)
10127 {
10128 struct intel_crtc *intel_crtc;
10129 struct intel_encoder *intel_encoder =
10130 intel_attached_encoder(connector);
10131 struct drm_crtc *possible_crtc;
10132 struct drm_encoder *encoder = &intel_encoder->base;
10133 struct drm_crtc *crtc = NULL;
10134 struct drm_device *dev = encoder->dev;
10135 struct drm_i915_private *dev_priv = to_i915(dev);
10136 struct drm_mode_config *config = &dev->mode_config;
10137 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10138 struct drm_connector_state *connector_state;
10139 struct intel_crtc_state *crtc_state;
10140 int ret, i = -1;
10141
10142 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10143 connector->base.id, connector->name,
10144 encoder->base.id, encoder->name);
10145
10146 old->restore_state = NULL;
10147
10148 WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
10149
10150 /*
10151 * Algorithm gets a little messy:
10152 *
10153 * - if the connector already has an assigned crtc, use it (but make
10154 * sure it's on first)
10155 *
10156 * - try to find the first unused crtc that can drive this connector,
10157 * and use that if we find one
10158 */
10159
10160 /* See if we already have a CRTC for this connector */
10161 if (connector->state->crtc) {
10162 crtc = connector->state->crtc;
10163
10164 ret = drm_modeset_lock(&crtc->mutex, ctx);
10165 if (ret)
10166 goto fail;
10167
10168 /* Make sure the crtc and connector are running */
10169 goto found;
10170 }
10171
10172 /* Find an unused one (if possible) */
10173 for_each_crtc(dev, possible_crtc) {
10174 i++;
10175 if (!(encoder->possible_crtcs & (1 << i)))
10176 continue;
10177
10178 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10179 if (ret)
10180 goto fail;
10181
10182 if (possible_crtc->state->enable) {
10183 drm_modeset_unlock(&possible_crtc->mutex);
10184 continue;
10185 }
10186
10187 crtc = possible_crtc;
10188 break;
10189 }
10190
10191 /*
10192 * If we didn't find an unused CRTC, don't use any.
10193 */
10194 if (!crtc) {
10195 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10196 ret = -ENODEV;
10197 goto fail;
10198 }
10199
10200 found:
10201 intel_crtc = to_intel_crtc(crtc);
10202
10203 state = drm_atomic_state_alloc(dev);
10204 restore_state = drm_atomic_state_alloc(dev);
10205 if (!state || !restore_state) {
10206 ret = -ENOMEM;
10207 goto fail;
10208 }
10209
10210 state->acquire_ctx = ctx;
10211 restore_state->acquire_ctx = ctx;
10212
10213 connector_state = drm_atomic_get_connector_state(state, connector);
10214 if (IS_ERR(connector_state)) {
10215 ret = PTR_ERR(connector_state);
10216 goto fail;
10217 }
10218
10219 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10220 if (ret)
10221 goto fail;
10222
10223 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10224 if (IS_ERR(crtc_state)) {
10225 ret = PTR_ERR(crtc_state);
10226 goto fail;
10227 }
10228
10229 crtc_state->base.active = crtc_state->base.enable = true;
10230
10231 if (!mode)
10232 mode = &load_detect_mode;
10233
10234 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10235 if (ret)
10236 goto fail;
10237
10238 ret = intel_modeset_disable_planes(state, crtc);
10239 if (ret)
10240 goto fail;
10241
10242 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10243 if (!ret)
10244 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10245 if (!ret)
10246 ret = drm_atomic_add_affected_planes(restore_state, crtc);
10247 if (ret) {
10248 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10249 goto fail;
10250 }
10251
10252 ret = drm_atomic_commit(state);
10253 if (ret) {
10254 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10255 goto fail;
10256 }
10257
10258 old->restore_state = restore_state;
10259 drm_atomic_state_put(state);
10260
10261 /* let the connector get through one full cycle before testing */
10262 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
10263 return true;
10264
10265 fail:
10266 if (state) {
10267 drm_atomic_state_put(state);
10268 state = NULL;
10269 }
10270 if (restore_state) {
10271 drm_atomic_state_put(restore_state);
10272 restore_state = NULL;
10273 }
10274
10275 if (ret == -EDEADLK)
10276 return ret;
10277
10278 return false;
10279 }
10280
10281 void intel_release_load_detect_pipe(struct drm_connector *connector,
10282 struct intel_load_detect_pipe *old,
10283 struct drm_modeset_acquire_ctx *ctx)
10284 {
10285 struct intel_encoder *intel_encoder =
10286 intel_attached_encoder(connector);
10287 struct drm_encoder *encoder = &intel_encoder->base;
10288 struct drm_atomic_state *state = old->restore_state;
10289 int ret;
10290
10291 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10292 connector->base.id, connector->name,
10293 encoder->base.id, encoder->name);
10294
10295 if (!state)
10296 return;
10297
10298 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
10299 if (ret)
10300 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10301 drm_atomic_state_put(state);
10302 }
10303
10304 static int i9xx_pll_refclk(struct drm_device *dev,
10305 const struct intel_crtc_state *pipe_config)
10306 {
10307 struct drm_i915_private *dev_priv = to_i915(dev);
10308 u32 dpll = pipe_config->dpll_hw_state.dpll;
10309
10310 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10311 return dev_priv->vbt.lvds_ssc_freq;
10312 else if (HAS_PCH_SPLIT(dev_priv))
10313 return 120000;
10314 else if (!IS_GEN2(dev_priv))
10315 return 96000;
10316 else
10317 return 48000;
10318 }
10319
10320 /* Returns the clock of the currently programmed mode of the given pipe. */
10321 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10322 struct intel_crtc_state *pipe_config)
10323 {
10324 struct drm_device *dev = crtc->base.dev;
10325 struct drm_i915_private *dev_priv = to_i915(dev);
10326 int pipe = pipe_config->cpu_transcoder;
10327 u32 dpll = pipe_config->dpll_hw_state.dpll;
10328 u32 fp;
10329 struct dpll clock;
10330 int port_clock;
10331 int refclk = i9xx_pll_refclk(dev, pipe_config);
10332
10333 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10334 fp = pipe_config->dpll_hw_state.fp0;
10335 else
10336 fp = pipe_config->dpll_hw_state.fp1;
10337
10338 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10339 if (IS_PINEVIEW(dev_priv)) {
10340 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10341 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10342 } else {
10343 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10344 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10345 }
10346
10347 if (!IS_GEN2(dev_priv)) {
10348 if (IS_PINEVIEW(dev_priv))
10349 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10350 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10351 else
10352 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10353 DPLL_FPA01_P1_POST_DIV_SHIFT);
10354
10355 switch (dpll & DPLL_MODE_MASK) {
10356 case DPLLB_MODE_DAC_SERIAL:
10357 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10358 5 : 10;
10359 break;
10360 case DPLLB_MODE_LVDS:
10361 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10362 7 : 14;
10363 break;
10364 default:
10365 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10366 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10367 return;
10368 }
10369
10370 if (IS_PINEVIEW(dev_priv))
10371 port_clock = pnv_calc_dpll_params(refclk, &clock);
10372 else
10373 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10374 } else {
10375 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
10376 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10377
10378 if (is_lvds) {
10379 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10380 DPLL_FPA01_P1_POST_DIV_SHIFT);
10381
10382 if (lvds & LVDS_CLKB_POWER_UP)
10383 clock.p2 = 7;
10384 else
10385 clock.p2 = 14;
10386 } else {
10387 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10388 clock.p1 = 2;
10389 else {
10390 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10391 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10392 }
10393 if (dpll & PLL_P2_DIVIDE_BY_4)
10394 clock.p2 = 4;
10395 else
10396 clock.p2 = 2;
10397 }
10398
10399 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10400 }
10401
10402 /*
10403 * This value includes pixel_multiplier. We will use
10404 * port_clock to compute adjusted_mode.crtc_clock in the
10405 * encoder's get_config() function.
10406 */
10407 pipe_config->port_clock = port_clock;
10408 }
10409
10410 int intel_dotclock_calculate(int link_freq,
10411 const struct intel_link_m_n *m_n)
10412 {
10413 /*
10414 * The calculation for the data clock is:
10415 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10416 * But we want to avoid losing precison if possible, so:
10417 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10418 *
10419 * and the link clock is simpler:
10420 * link_clock = (m * link_clock) / n
10421 */
10422
10423 if (!m_n->link_n)
10424 return 0;
10425
10426 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
10427 }
10428
10429 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10430 struct intel_crtc_state *pipe_config)
10431 {
10432 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10433
10434 /* read out port_clock from the DPLL */
10435 i9xx_crtc_clock_get(crtc, pipe_config);
10436
10437 /*
10438 * In case there is an active pipe without active ports,
10439 * we may need some idea for the dotclock anyway.
10440 * Calculate one based on the FDI configuration.
10441 */
10442 pipe_config->base.adjusted_mode.crtc_clock =
10443 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10444 &pipe_config->fdi_m_n);
10445 }
10446
10447 /* Returns the currently programmed mode of the given encoder. */
10448 struct drm_display_mode *
10449 intel_encoder_current_mode(struct intel_encoder *encoder)
10450 {
10451 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
10452 struct intel_crtc_state *crtc_state;
10453 struct drm_display_mode *mode;
10454 struct intel_crtc *crtc;
10455 enum pipe pipe;
10456
10457 if (!encoder->get_hw_state(encoder, &pipe))
10458 return NULL;
10459
10460 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10461
10462 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10463 if (!mode)
10464 return NULL;
10465
10466 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
10467 if (!crtc_state) {
10468 kfree(mode);
10469 return NULL;
10470 }
10471
10472 crtc_state->base.crtc = &crtc->base;
10473
10474 if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
10475 kfree(crtc_state);
10476 kfree(mode);
10477 return NULL;
10478 }
10479
10480 encoder->get_config(encoder, crtc_state);
10481
10482 intel_mode_from_pipe_config(mode, crtc_state);
10483
10484 kfree(crtc_state);
10485
10486 return mode;
10487 }
10488
10489 static void intel_crtc_destroy(struct drm_crtc *crtc)
10490 {
10491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10492
10493 drm_crtc_cleanup(crtc);
10494 kfree(intel_crtc);
10495 }
10496
10497 /**
10498 * intel_wm_need_update - Check whether watermarks need updating
10499 * @plane: drm plane
10500 * @state: new plane state
10501 *
10502 * Check current plane state versus the new one to determine whether
10503 * watermarks need to be recalculated.
10504 *
10505 * Returns true or false.
10506 */
10507 static bool intel_wm_need_update(struct drm_plane *plane,
10508 struct drm_plane_state *state)
10509 {
10510 struct intel_plane_state *new = to_intel_plane_state(state);
10511 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10512
10513 /* Update watermarks on tiling or size changes. */
10514 if (new->base.visible != cur->base.visible)
10515 return true;
10516
10517 if (!cur->base.fb || !new->base.fb)
10518 return false;
10519
10520 if (cur->base.fb->modifier != new->base.fb->modifier ||
10521 cur->base.rotation != new->base.rotation ||
10522 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10523 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10524 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10525 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10526 return true;
10527
10528 return false;
10529 }
10530
10531 static bool needs_scaling(const struct intel_plane_state *state)
10532 {
10533 int src_w = drm_rect_width(&state->base.src) >> 16;
10534 int src_h = drm_rect_height(&state->base.src) >> 16;
10535 int dst_w = drm_rect_width(&state->base.dst);
10536 int dst_h = drm_rect_height(&state->base.dst);
10537
10538 return (src_w != dst_w || src_h != dst_h);
10539 }
10540
10541 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
10542 struct drm_crtc_state *crtc_state,
10543 const struct intel_plane_state *old_plane_state,
10544 struct drm_plane_state *plane_state)
10545 {
10546 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10547 struct drm_crtc *crtc = crtc_state->crtc;
10548 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10549 struct intel_plane *plane = to_intel_plane(plane_state->plane);
10550 struct drm_device *dev = crtc->dev;
10551 struct drm_i915_private *dev_priv = to_i915(dev);
10552 bool mode_changed = needs_modeset(crtc_state);
10553 bool was_crtc_enabled = old_crtc_state->base.active;
10554 bool is_crtc_enabled = crtc_state->active;
10555 bool turn_off, turn_on, visible, was_visible;
10556 struct drm_framebuffer *fb = plane_state->fb;
10557 int ret;
10558
10559 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10560 ret = skl_update_scaler_plane(
10561 to_intel_crtc_state(crtc_state),
10562 to_intel_plane_state(plane_state));
10563 if (ret)
10564 return ret;
10565 }
10566
10567 was_visible = old_plane_state->base.visible;
10568 visible = plane_state->visible;
10569
10570 if (!was_crtc_enabled && WARN_ON(was_visible))
10571 was_visible = false;
10572
10573 /*
10574 * Visibility is calculated as if the crtc was on, but
10575 * after scaler setup everything depends on it being off
10576 * when the crtc isn't active.
10577 *
10578 * FIXME this is wrong for watermarks. Watermarks should also
10579 * be computed as if the pipe would be active. Perhaps move
10580 * per-plane wm computation to the .check_plane() hook, and
10581 * only combine the results from all planes in the current place?
10582 */
10583 if (!is_crtc_enabled) {
10584 plane_state->visible = visible = false;
10585 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10586 }
10587
10588 if (!was_visible && !visible)
10589 return 0;
10590
10591 if (fb != old_plane_state->base.fb)
10592 pipe_config->fb_changed = true;
10593
10594 turn_off = was_visible && (!visible || mode_changed);
10595 turn_on = visible && (!was_visible || mode_changed);
10596
10597 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10598 intel_crtc->base.base.id, intel_crtc->base.name,
10599 plane->base.base.id, plane->base.name,
10600 fb ? fb->base.id : -1);
10601
10602 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10603 plane->base.base.id, plane->base.name,
10604 was_visible, visible,
10605 turn_off, turn_on, mode_changed);
10606
10607 if (turn_on) {
10608 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10609 pipe_config->update_wm_pre = true;
10610
10611 /* must disable cxsr around plane enable/disable */
10612 if (plane->id != PLANE_CURSOR)
10613 pipe_config->disable_cxsr = true;
10614 } else if (turn_off) {
10615 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10616 pipe_config->update_wm_post = true;
10617
10618 /* must disable cxsr around plane enable/disable */
10619 if (plane->id != PLANE_CURSOR)
10620 pipe_config->disable_cxsr = true;
10621 } else if (intel_wm_need_update(&plane->base, plane_state)) {
10622 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
10623 /* FIXME bollocks */
10624 pipe_config->update_wm_pre = true;
10625 pipe_config->update_wm_post = true;
10626 }
10627 }
10628
10629 if (visible || was_visible)
10630 pipe_config->fb_bits |= plane->frontbuffer_bit;
10631
10632 /*
10633 * WaCxSRDisabledForSpriteScaling:ivb
10634 *
10635 * cstate->update_wm was already set above, so this flag will
10636 * take effect when we commit and program watermarks.
10637 */
10638 if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10639 needs_scaling(to_intel_plane_state(plane_state)) &&
10640 !needs_scaling(old_plane_state))
10641 pipe_config->disable_lp_wm = true;
10642
10643 return 0;
10644 }
10645
10646 static bool encoders_cloneable(const struct intel_encoder *a,
10647 const struct intel_encoder *b)
10648 {
10649 /* masks could be asymmetric, so check both ways */
10650 return a == b || (a->cloneable & (1 << b->type) &&
10651 b->cloneable & (1 << a->type));
10652 }
10653
10654 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10655 struct intel_crtc *crtc,
10656 struct intel_encoder *encoder)
10657 {
10658 struct intel_encoder *source_encoder;
10659 struct drm_connector *connector;
10660 struct drm_connector_state *connector_state;
10661 int i;
10662
10663 for_each_new_connector_in_state(state, connector, connector_state, i) {
10664 if (connector_state->crtc != &crtc->base)
10665 continue;
10666
10667 source_encoder =
10668 to_intel_encoder(connector_state->best_encoder);
10669 if (!encoders_cloneable(encoder, source_encoder))
10670 return false;
10671 }
10672
10673 return true;
10674 }
10675
10676 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10677 struct drm_crtc_state *crtc_state)
10678 {
10679 struct drm_device *dev = crtc->dev;
10680 struct drm_i915_private *dev_priv = to_i915(dev);
10681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10682 struct intel_crtc_state *pipe_config =
10683 to_intel_crtc_state(crtc_state);
10684 struct drm_atomic_state *state = crtc_state->state;
10685 int ret;
10686 bool mode_changed = needs_modeset(crtc_state);
10687
10688 if (mode_changed && !crtc_state->active)
10689 pipe_config->update_wm_post = true;
10690
10691 if (mode_changed && crtc_state->enable &&
10692 dev_priv->display.crtc_compute_clock &&
10693 !WARN_ON(pipe_config->shared_dpll)) {
10694 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10695 pipe_config);
10696 if (ret)
10697 return ret;
10698 }
10699
10700 if (crtc_state->color_mgmt_changed) {
10701 ret = intel_color_check(crtc, crtc_state);
10702 if (ret)
10703 return ret;
10704
10705 /*
10706 * Changing color management on Intel hardware is
10707 * handled as part of planes update.
10708 */
10709 crtc_state->planes_changed = true;
10710 }
10711
10712 ret = 0;
10713 if (dev_priv->display.compute_pipe_wm) {
10714 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10715 if (ret) {
10716 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10717 return ret;
10718 }
10719 }
10720
10721 if (dev_priv->display.compute_intermediate_wm &&
10722 !to_intel_atomic_state(state)->skip_intermediate_wm) {
10723 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10724 return 0;
10725
10726 /*
10727 * Calculate 'intermediate' watermarks that satisfy both the
10728 * old state and the new state. We can program these
10729 * immediately.
10730 */
10731 ret = dev_priv->display.compute_intermediate_wm(dev,
10732 intel_crtc,
10733 pipe_config);
10734 if (ret) {
10735 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10736 return ret;
10737 }
10738 } else if (dev_priv->display.compute_intermediate_wm) {
10739 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10740 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10741 }
10742
10743 if (INTEL_GEN(dev_priv) >= 9) {
10744 if (mode_changed)
10745 ret = skl_update_scaler_crtc(pipe_config);
10746
10747 if (!ret)
10748 ret = skl_check_pipe_max_pixel_rate(intel_crtc,
10749 pipe_config);
10750 if (!ret)
10751 ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
10752 pipe_config);
10753 }
10754
10755 if (HAS_IPS(dev_priv))
10756 pipe_config->ips_enabled = hsw_compute_ips_config(pipe_config);
10757
10758 return ret;
10759 }
10760
10761 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
10762 .atomic_begin = intel_begin_crtc_commit,
10763 .atomic_flush = intel_finish_crtc_commit,
10764 .atomic_check = intel_crtc_atomic_check,
10765 };
10766
10767 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10768 {
10769 struct intel_connector *connector;
10770 struct drm_connector_list_iter conn_iter;
10771
10772 drm_connector_list_iter_begin(dev, &conn_iter);
10773 for_each_intel_connector_iter(connector, &conn_iter) {
10774 if (connector->base.state->crtc)
10775 drm_connector_put(&connector->base);
10776
10777 if (connector->base.encoder) {
10778 connector->base.state->best_encoder =
10779 connector->base.encoder;
10780 connector->base.state->crtc =
10781 connector->base.encoder->crtc;
10782
10783 drm_connector_get(&connector->base);
10784 } else {
10785 connector->base.state->best_encoder = NULL;
10786 connector->base.state->crtc = NULL;
10787 }
10788 }
10789 drm_connector_list_iter_end(&conn_iter);
10790 }
10791
10792 static void
10793 connected_sink_compute_bpp(struct intel_connector *connector,
10794 struct intel_crtc_state *pipe_config)
10795 {
10796 const struct drm_display_info *info = &connector->base.display_info;
10797 int bpp = pipe_config->pipe_bpp;
10798
10799 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10800 connector->base.base.id,
10801 connector->base.name);
10802
10803 /* Don't use an invalid EDID bpc value */
10804 if (info->bpc != 0 && info->bpc * 3 < bpp) {
10805 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10806 bpp, info->bpc * 3);
10807 pipe_config->pipe_bpp = info->bpc * 3;
10808 }
10809
10810 /* Clamp bpp to 8 on screens without EDID 1.4 */
10811 if (info->bpc == 0 && bpp > 24) {
10812 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10813 bpp);
10814 pipe_config->pipe_bpp = 24;
10815 }
10816 }
10817
10818 static int
10819 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10820 struct intel_crtc_state *pipe_config)
10821 {
10822 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10823 struct drm_atomic_state *state;
10824 struct drm_connector *connector;
10825 struct drm_connector_state *connector_state;
10826 int bpp, i;
10827
10828 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
10829 IS_CHERRYVIEW(dev_priv)))
10830 bpp = 10*3;
10831 else if (INTEL_GEN(dev_priv) >= 5)
10832 bpp = 12*3;
10833 else
10834 bpp = 8*3;
10835
10836
10837 pipe_config->pipe_bpp = bpp;
10838
10839 state = pipe_config->base.state;
10840
10841 /* Clamp display bpp to EDID value */
10842 for_each_new_connector_in_state(state, connector, connector_state, i) {
10843 if (connector_state->crtc != &crtc->base)
10844 continue;
10845
10846 connected_sink_compute_bpp(to_intel_connector(connector),
10847 pipe_config);
10848 }
10849
10850 return bpp;
10851 }
10852
10853 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10854 {
10855 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10856 "type: 0x%x flags: 0x%x\n",
10857 mode->crtc_clock,
10858 mode->crtc_hdisplay, mode->crtc_hsync_start,
10859 mode->crtc_hsync_end, mode->crtc_htotal,
10860 mode->crtc_vdisplay, mode->crtc_vsync_start,
10861 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10862 }
10863
10864 static inline void
10865 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
10866 unsigned int lane_count, struct intel_link_m_n *m_n)
10867 {
10868 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10869 id, lane_count,
10870 m_n->gmch_m, m_n->gmch_n,
10871 m_n->link_m, m_n->link_n, m_n->tu);
10872 }
10873
10874 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
10875
10876 static const char * const output_type_str[] = {
10877 OUTPUT_TYPE(UNUSED),
10878 OUTPUT_TYPE(ANALOG),
10879 OUTPUT_TYPE(DVO),
10880 OUTPUT_TYPE(SDVO),
10881 OUTPUT_TYPE(LVDS),
10882 OUTPUT_TYPE(TVOUT),
10883 OUTPUT_TYPE(HDMI),
10884 OUTPUT_TYPE(DP),
10885 OUTPUT_TYPE(EDP),
10886 OUTPUT_TYPE(DSI),
10887 OUTPUT_TYPE(DDI),
10888 OUTPUT_TYPE(DP_MST),
10889 };
10890
10891 #undef OUTPUT_TYPE
10892
10893 static void snprintf_output_types(char *buf, size_t len,
10894 unsigned int output_types)
10895 {
10896 char *str = buf;
10897 int i;
10898
10899 str[0] = '\0';
10900
10901 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
10902 int r;
10903
10904 if ((output_types & BIT(i)) == 0)
10905 continue;
10906
10907 r = snprintf(str, len, "%s%s",
10908 str != buf ? "," : "", output_type_str[i]);
10909 if (r >= len)
10910 break;
10911 str += r;
10912 len -= r;
10913
10914 output_types &= ~BIT(i);
10915 }
10916
10917 WARN_ON_ONCE(output_types != 0);
10918 }
10919
10920 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10921 struct intel_crtc_state *pipe_config,
10922 const char *context)
10923 {
10924 struct drm_device *dev = crtc->base.dev;
10925 struct drm_i915_private *dev_priv = to_i915(dev);
10926 struct drm_plane *plane;
10927 struct intel_plane *intel_plane;
10928 struct intel_plane_state *state;
10929 struct drm_framebuffer *fb;
10930 char buf[64];
10931
10932 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
10933 crtc->base.base.id, crtc->base.name, context);
10934
10935 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
10936 DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
10937 buf, pipe_config->output_types);
10938
10939 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
10940 transcoder_name(pipe_config->cpu_transcoder),
10941 pipe_config->pipe_bpp, pipe_config->dither);
10942
10943 if (pipe_config->has_pch_encoder)
10944 intel_dump_m_n_config(pipe_config, "fdi",
10945 pipe_config->fdi_lanes,
10946 &pipe_config->fdi_m_n);
10947
10948 if (pipe_config->ycbcr420)
10949 DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n");
10950
10951 if (intel_crtc_has_dp_encoder(pipe_config)) {
10952 intel_dump_m_n_config(pipe_config, "dp m_n",
10953 pipe_config->lane_count, &pipe_config->dp_m_n);
10954 if (pipe_config->has_drrs)
10955 intel_dump_m_n_config(pipe_config, "dp m2_n2",
10956 pipe_config->lane_count,
10957 &pipe_config->dp_m2_n2);
10958 }
10959
10960 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10961 pipe_config->has_audio, pipe_config->has_infoframe);
10962
10963 DRM_DEBUG_KMS("requested mode:\n");
10964 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10965 DRM_DEBUG_KMS("adjusted mode:\n");
10966 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10967 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10968 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
10969 pipe_config->port_clock,
10970 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
10971 pipe_config->pixel_rate);
10972
10973 if (INTEL_GEN(dev_priv) >= 9)
10974 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
10975 crtc->num_scalers,
10976 pipe_config->scaler_state.scaler_users,
10977 pipe_config->scaler_state.scaler_id);
10978
10979 if (HAS_GMCH_DISPLAY(dev_priv))
10980 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10981 pipe_config->gmch_pfit.control,
10982 pipe_config->gmch_pfit.pgm_ratios,
10983 pipe_config->gmch_pfit.lvds_border_bits);
10984 else
10985 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10986 pipe_config->pch_pfit.pos,
10987 pipe_config->pch_pfit.size,
10988 enableddisabled(pipe_config->pch_pfit.enabled));
10989
10990 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
10991 pipe_config->ips_enabled, pipe_config->double_wide);
10992
10993 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
10994
10995 DRM_DEBUG_KMS("planes on this crtc\n");
10996 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
10997 struct drm_format_name_buf format_name;
10998 intel_plane = to_intel_plane(plane);
10999 if (intel_plane->pipe != crtc->pipe)
11000 continue;
11001
11002 state = to_intel_plane_state(plane->state);
11003 fb = state->base.fb;
11004 if (!fb) {
11005 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11006 plane->base.id, plane->name, state->scaler_id);
11007 continue;
11008 }
11009
11010 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11011 plane->base.id, plane->name,
11012 fb->base.id, fb->width, fb->height,
11013 drm_get_format_name(fb->format->format, &format_name));
11014 if (INTEL_GEN(dev_priv) >= 9)
11015 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11016 state->scaler_id,
11017 state->base.src.x1 >> 16,
11018 state->base.src.y1 >> 16,
11019 drm_rect_width(&state->base.src) >> 16,
11020 drm_rect_height(&state->base.src) >> 16,
11021 state->base.dst.x1, state->base.dst.y1,
11022 drm_rect_width(&state->base.dst),
11023 drm_rect_height(&state->base.dst));
11024 }
11025 }
11026
11027 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11028 {
11029 struct drm_device *dev = state->dev;
11030 struct drm_connector *connector;
11031 struct drm_connector_list_iter conn_iter;
11032 unsigned int used_ports = 0;
11033 unsigned int used_mst_ports = 0;
11034 bool ret = true;
11035
11036 /*
11037 * Walk the connector list instead of the encoder
11038 * list to detect the problem on ddi platforms
11039 * where there's just one encoder per digital port.
11040 */
11041 drm_connector_list_iter_begin(dev, &conn_iter);
11042 drm_for_each_connector_iter(connector, &conn_iter) {
11043 struct drm_connector_state *connector_state;
11044 struct intel_encoder *encoder;
11045
11046 connector_state = drm_atomic_get_new_connector_state(state, connector);
11047 if (!connector_state)
11048 connector_state = connector->state;
11049
11050 if (!connector_state->best_encoder)
11051 continue;
11052
11053 encoder = to_intel_encoder(connector_state->best_encoder);
11054
11055 WARN_ON(!connector_state->crtc);
11056
11057 switch (encoder->type) {
11058 unsigned int port_mask;
11059 case INTEL_OUTPUT_DDI:
11060 if (WARN_ON(!HAS_DDI(to_i915(dev))))
11061 break;
11062 /* else: fall through */
11063 case INTEL_OUTPUT_DP:
11064 case INTEL_OUTPUT_HDMI:
11065 case INTEL_OUTPUT_EDP:
11066 port_mask = 1 << encoder->port;
11067
11068 /* the same port mustn't appear more than once */
11069 if (used_ports & port_mask)
11070 ret = false;
11071
11072 used_ports |= port_mask;
11073 break;
11074 case INTEL_OUTPUT_DP_MST:
11075 used_mst_ports |=
11076 1 << encoder->port;
11077 break;
11078 default:
11079 break;
11080 }
11081 }
11082 drm_connector_list_iter_end(&conn_iter);
11083
11084 /* can't mix MST and SST/HDMI on the same port */
11085 if (used_ports & used_mst_ports)
11086 return false;
11087
11088 return ret;
11089 }
11090
11091 static void
11092 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11093 {
11094 struct drm_i915_private *dev_priv =
11095 to_i915(crtc_state->base.crtc->dev);
11096 struct intel_crtc_scaler_state scaler_state;
11097 struct intel_dpll_hw_state dpll_hw_state;
11098 struct intel_shared_dpll *shared_dpll;
11099 struct intel_crtc_wm_state wm_state;
11100 bool force_thru, ips_force_disable;
11101
11102 /* FIXME: before the switch to atomic started, a new pipe_config was
11103 * kzalloc'd. Code that depends on any field being zero should be
11104 * fixed, so that the crtc_state can be safely duplicated. For now,
11105 * only fields that are know to not cause problems are preserved. */
11106
11107 scaler_state = crtc_state->scaler_state;
11108 shared_dpll = crtc_state->shared_dpll;
11109 dpll_hw_state = crtc_state->dpll_hw_state;
11110 force_thru = crtc_state->pch_pfit.force_thru;
11111 ips_force_disable = crtc_state->ips_force_disable;
11112 if (IS_G4X(dev_priv) ||
11113 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11114 wm_state = crtc_state->wm;
11115
11116 /* Keep base drm_crtc_state intact, only clear our extended struct */
11117 BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
11118 memset(&crtc_state->base + 1, 0,
11119 sizeof(*crtc_state) - sizeof(crtc_state->base));
11120
11121 crtc_state->scaler_state = scaler_state;
11122 crtc_state->shared_dpll = shared_dpll;
11123 crtc_state->dpll_hw_state = dpll_hw_state;
11124 crtc_state->pch_pfit.force_thru = force_thru;
11125 crtc_state->ips_force_disable = ips_force_disable;
11126 if (IS_G4X(dev_priv) ||
11127 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11128 crtc_state->wm = wm_state;
11129 }
11130
11131 static int
11132 intel_modeset_pipe_config(struct drm_crtc *crtc,
11133 struct intel_crtc_state *pipe_config)
11134 {
11135 struct drm_atomic_state *state = pipe_config->base.state;
11136 struct intel_encoder *encoder;
11137 struct drm_connector *connector;
11138 struct drm_connector_state *connector_state;
11139 int base_bpp, ret = -EINVAL;
11140 int i;
11141 bool retry = true;
11142
11143 clear_intel_crtc_state(pipe_config);
11144
11145 pipe_config->cpu_transcoder =
11146 (enum transcoder) to_intel_crtc(crtc)->pipe;
11147
11148 /*
11149 * Sanitize sync polarity flags based on requested ones. If neither
11150 * positive or negative polarity is requested, treat this as meaning
11151 * negative polarity.
11152 */
11153 if (!(pipe_config->base.adjusted_mode.flags &
11154 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11155 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11156
11157 if (!(pipe_config->base.adjusted_mode.flags &
11158 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11159 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11160
11161 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11162 pipe_config);
11163 if (base_bpp < 0)
11164 goto fail;
11165
11166 /*
11167 * Determine the real pipe dimensions. Note that stereo modes can
11168 * increase the actual pipe size due to the frame doubling and
11169 * insertion of additional space for blanks between the frame. This
11170 * is stored in the crtc timings. We use the requested mode to do this
11171 * computation to clearly distinguish it from the adjusted mode, which
11172 * can be changed by the connectors in the below retry loop.
11173 */
11174 drm_mode_get_hv_timing(&pipe_config->base.mode,
11175 &pipe_config->pipe_src_w,
11176 &pipe_config->pipe_src_h);
11177
11178 for_each_new_connector_in_state(state, connector, connector_state, i) {
11179 if (connector_state->crtc != crtc)
11180 continue;
11181
11182 encoder = to_intel_encoder(connector_state->best_encoder);
11183
11184 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11185 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11186 goto fail;
11187 }
11188
11189 /*
11190 * Determine output_types before calling the .compute_config()
11191 * hooks so that the hooks can use this information safely.
11192 */
11193 if (encoder->compute_output_type)
11194 pipe_config->output_types |=
11195 BIT(encoder->compute_output_type(encoder, pipe_config,
11196 connector_state));
11197 else
11198 pipe_config->output_types |= BIT(encoder->type);
11199 }
11200
11201 encoder_retry:
11202 /* Ensure the port clock defaults are reset when retrying. */
11203 pipe_config->port_clock = 0;
11204 pipe_config->pixel_multiplier = 1;
11205
11206 /* Fill in default crtc timings, allow encoders to overwrite them. */
11207 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11208 CRTC_STEREO_DOUBLE);
11209
11210 /* Pass our mode to the connectors and the CRTC to give them a chance to
11211 * adjust it according to limitations or connector properties, and also
11212 * a chance to reject the mode entirely.
11213 */
11214 for_each_new_connector_in_state(state, connector, connector_state, i) {
11215 if (connector_state->crtc != crtc)
11216 continue;
11217
11218 encoder = to_intel_encoder(connector_state->best_encoder);
11219
11220 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
11221 DRM_DEBUG_KMS("Encoder config failure\n");
11222 goto fail;
11223 }
11224 }
11225
11226 /* Set default port clock if not overwritten by the encoder. Needs to be
11227 * done afterwards in case the encoder adjusts the mode. */
11228 if (!pipe_config->port_clock)
11229 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11230 * pipe_config->pixel_multiplier;
11231
11232 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11233 if (ret < 0) {
11234 DRM_DEBUG_KMS("CRTC fixup failed\n");
11235 goto fail;
11236 }
11237
11238 if (ret == RETRY) {
11239 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11240 ret = -EINVAL;
11241 goto fail;
11242 }
11243
11244 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11245 retry = false;
11246 goto encoder_retry;
11247 }
11248
11249 /* Dithering seems to not pass-through bits correctly when it should, so
11250 * only enable it on 6bpc panels and when its not a compliance
11251 * test requesting 6bpc video pattern.
11252 */
11253 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11254 !pipe_config->dither_force_disable;
11255 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11256 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11257
11258 fail:
11259 return ret;
11260 }
11261
11262 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11263 {
11264 int diff;
11265
11266 if (clock1 == clock2)
11267 return true;
11268
11269 if (!clock1 || !clock2)
11270 return false;
11271
11272 diff = abs(clock1 - clock2);
11273
11274 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11275 return true;
11276
11277 return false;
11278 }
11279
11280 static bool
11281 intel_compare_m_n(unsigned int m, unsigned int n,
11282 unsigned int m2, unsigned int n2,
11283 bool exact)
11284 {
11285 if (m == m2 && n == n2)
11286 return true;
11287
11288 if (exact || !m || !n || !m2 || !n2)
11289 return false;
11290
11291 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11292
11293 if (n > n2) {
11294 while (n > n2) {
11295 m2 <<= 1;
11296 n2 <<= 1;
11297 }
11298 } else if (n < n2) {
11299 while (n < n2) {
11300 m <<= 1;
11301 n <<= 1;
11302 }
11303 }
11304
11305 if (n != n2)
11306 return false;
11307
11308 return intel_fuzzy_clock_check(m, m2);
11309 }
11310
11311 static bool
11312 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11313 struct intel_link_m_n *m2_n2,
11314 bool adjust)
11315 {
11316 if (m_n->tu == m2_n2->tu &&
11317 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11318 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11319 intel_compare_m_n(m_n->link_m, m_n->link_n,
11320 m2_n2->link_m, m2_n2->link_n, !adjust)) {
11321 if (adjust)
11322 *m2_n2 = *m_n;
11323
11324 return true;
11325 }
11326
11327 return false;
11328 }
11329
11330 static void __printf(3, 4)
11331 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11332 {
11333 struct va_format vaf;
11334 va_list args;
11335
11336 va_start(args, format);
11337 vaf.fmt = format;
11338 vaf.va = &args;
11339
11340 if (adjust)
11341 drm_dbg(DRM_UT_KMS, "mismatch in %s %pV", name, &vaf);
11342 else
11343 drm_err("mismatch in %s %pV", name, &vaf);
11344
11345 va_end(args);
11346 }
11347
11348 static bool
11349 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11350 struct intel_crtc_state *current_config,
11351 struct intel_crtc_state *pipe_config,
11352 bool adjust)
11353 {
11354 bool ret = true;
11355 bool fixup_inherited = adjust &&
11356 (current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
11357 !(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
11358
11359 #define PIPE_CONF_CHECK_X(name) do { \
11360 if (current_config->name != pipe_config->name) { \
11361 pipe_config_err(adjust, __stringify(name), \
11362 "(expected 0x%08x, found 0x%08x)\n", \
11363 current_config->name, \
11364 pipe_config->name); \
11365 ret = false; \
11366 } \
11367 } while (0)
11368
11369 #define PIPE_CONF_CHECK_I(name) do { \
11370 if (current_config->name != pipe_config->name) { \
11371 pipe_config_err(adjust, __stringify(name), \
11372 "(expected %i, found %i)\n", \
11373 current_config->name, \
11374 pipe_config->name); \
11375 ret = false; \
11376 } \
11377 } while (0)
11378
11379 #define PIPE_CONF_CHECK_BOOL(name) do { \
11380 if (current_config->name != pipe_config->name) { \
11381 pipe_config_err(adjust, __stringify(name), \
11382 "(expected %s, found %s)\n", \
11383 yesno(current_config->name), \
11384 yesno(pipe_config->name)); \
11385 ret = false; \
11386 } \
11387 } while (0)
11388
11389 /*
11390 * Checks state where we only read out the enabling, but not the entire
11391 * state itself (like full infoframes or ELD for audio). These states
11392 * require a full modeset on bootup to fix up.
11393 */
11394 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
11395 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
11396 PIPE_CONF_CHECK_BOOL(name); \
11397 } else { \
11398 pipe_config_err(adjust, __stringify(name), \
11399 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)\n", \
11400 yesno(current_config->name), \
11401 yesno(pipe_config->name)); \
11402 ret = false; \
11403 } \
11404 } while (0)
11405
11406 #define PIPE_CONF_CHECK_P(name) do { \
11407 if (current_config->name != pipe_config->name) { \
11408 pipe_config_err(adjust, __stringify(name), \
11409 "(expected %p, found %p)\n", \
11410 current_config->name, \
11411 pipe_config->name); \
11412 ret = false; \
11413 } \
11414 } while (0)
11415
11416 #define PIPE_CONF_CHECK_M_N(name) do { \
11417 if (!intel_compare_link_m_n(&current_config->name, \
11418 &pipe_config->name,\
11419 adjust)) { \
11420 pipe_config_err(adjust, __stringify(name), \
11421 "(expected tu %i gmch %i/%i link %i/%i, " \
11422 "found tu %i, gmch %i/%i link %i/%i)\n", \
11423 current_config->name.tu, \
11424 current_config->name.gmch_m, \
11425 current_config->name.gmch_n, \
11426 current_config->name.link_m, \
11427 current_config->name.link_n, \
11428 pipe_config->name.tu, \
11429 pipe_config->name.gmch_m, \
11430 pipe_config->name.gmch_n, \
11431 pipe_config->name.link_m, \
11432 pipe_config->name.link_n); \
11433 ret = false; \
11434 } \
11435 } while (0)
11436
11437 /* This is required for BDW+ where there is only one set of registers for
11438 * switching between high and low RR.
11439 * This macro can be used whenever a comparison has to be made between one
11440 * hw state and multiple sw state variables.
11441 */
11442 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
11443 if (!intel_compare_link_m_n(&current_config->name, \
11444 &pipe_config->name, adjust) && \
11445 !intel_compare_link_m_n(&current_config->alt_name, \
11446 &pipe_config->name, adjust)) { \
11447 pipe_config_err(adjust, __stringify(name), \
11448 "(expected tu %i gmch %i/%i link %i/%i, " \
11449 "or tu %i gmch %i/%i link %i/%i, " \
11450 "found tu %i, gmch %i/%i link %i/%i)\n", \
11451 current_config->name.tu, \
11452 current_config->name.gmch_m, \
11453 current_config->name.gmch_n, \
11454 current_config->name.link_m, \
11455 current_config->name.link_n, \
11456 current_config->alt_name.tu, \
11457 current_config->alt_name.gmch_m, \
11458 current_config->alt_name.gmch_n, \
11459 current_config->alt_name.link_m, \
11460 current_config->alt_name.link_n, \
11461 pipe_config->name.tu, \
11462 pipe_config->name.gmch_m, \
11463 pipe_config->name.gmch_n, \
11464 pipe_config->name.link_m, \
11465 pipe_config->name.link_n); \
11466 ret = false; \
11467 } \
11468 } while (0)
11469
11470 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
11471 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11472 pipe_config_err(adjust, __stringify(name), \
11473 "(%x) (expected %i, found %i)\n", \
11474 (mask), \
11475 current_config->name & (mask), \
11476 pipe_config->name & (mask)); \
11477 ret = false; \
11478 } \
11479 } while (0)
11480
11481 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
11482 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11483 pipe_config_err(adjust, __stringify(name), \
11484 "(expected %i, found %i)\n", \
11485 current_config->name, \
11486 pipe_config->name); \
11487 ret = false; \
11488 } \
11489 } while (0)
11490
11491 #define PIPE_CONF_QUIRK(quirk) \
11492 ((current_config->quirks | pipe_config->quirks) & (quirk))
11493
11494 PIPE_CONF_CHECK_I(cpu_transcoder);
11495
11496 PIPE_CONF_CHECK_BOOL(has_pch_encoder);
11497 PIPE_CONF_CHECK_I(fdi_lanes);
11498 PIPE_CONF_CHECK_M_N(fdi_m_n);
11499
11500 PIPE_CONF_CHECK_I(lane_count);
11501 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11502
11503 if (INTEL_GEN(dev_priv) < 8) {
11504 PIPE_CONF_CHECK_M_N(dp_m_n);
11505
11506 if (current_config->has_drrs)
11507 PIPE_CONF_CHECK_M_N(dp_m2_n2);
11508 } else
11509 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11510
11511 PIPE_CONF_CHECK_X(output_types);
11512
11513 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11514 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11515 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11516 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11517 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11518 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11519
11520 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11521 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11522 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11523 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11524 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11525 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11526
11527 PIPE_CONF_CHECK_I(pixel_multiplier);
11528 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
11529 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11530 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11531 PIPE_CONF_CHECK_BOOL(limited_color_range);
11532
11533 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
11534 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
11535 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_infoframe);
11536 PIPE_CONF_CHECK_BOOL(ycbcr420);
11537
11538 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
11539
11540 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11541 DRM_MODE_FLAG_INTERLACE);
11542
11543 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11544 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11545 DRM_MODE_FLAG_PHSYNC);
11546 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11547 DRM_MODE_FLAG_NHSYNC);
11548 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11549 DRM_MODE_FLAG_PVSYNC);
11550 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11551 DRM_MODE_FLAG_NVSYNC);
11552 }
11553
11554 PIPE_CONF_CHECK_X(gmch_pfit.control);
11555 /* pfit ratios are autocomputed by the hw on gen4+ */
11556 if (INTEL_GEN(dev_priv) < 4)
11557 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11558 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11559
11560 if (!adjust) {
11561 PIPE_CONF_CHECK_I(pipe_src_w);
11562 PIPE_CONF_CHECK_I(pipe_src_h);
11563
11564 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
11565 if (current_config->pch_pfit.enabled) {
11566 PIPE_CONF_CHECK_X(pch_pfit.pos);
11567 PIPE_CONF_CHECK_X(pch_pfit.size);
11568 }
11569
11570 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11571 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11572 }
11573
11574 PIPE_CONF_CHECK_BOOL(double_wide);
11575
11576 PIPE_CONF_CHECK_P(shared_dpll);
11577 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11578 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11579 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11580 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11581 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11582 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11583 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11584 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11585 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11586 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
11587 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
11588 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
11589 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
11590 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
11591 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
11592 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
11593 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
11594 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
11595 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
11596 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
11597 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
11598 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
11599 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
11600 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
11601 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
11602 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
11603 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
11604 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
11605 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
11606 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
11607 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
11608
11609 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11610 PIPE_CONF_CHECK_X(dsi_pll.div);
11611
11612 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11613 PIPE_CONF_CHECK_I(pipe_bpp);
11614
11615 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11616 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11617
11618 PIPE_CONF_CHECK_I(min_voltage_level);
11619
11620 #undef PIPE_CONF_CHECK_X
11621 #undef PIPE_CONF_CHECK_I
11622 #undef PIPE_CONF_CHECK_BOOL
11623 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
11624 #undef PIPE_CONF_CHECK_P
11625 #undef PIPE_CONF_CHECK_FLAGS
11626 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11627 #undef PIPE_CONF_QUIRK
11628
11629 return ret;
11630 }
11631
11632 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11633 const struct intel_crtc_state *pipe_config)
11634 {
11635 if (pipe_config->has_pch_encoder) {
11636 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11637 &pipe_config->fdi_m_n);
11638 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11639
11640 /*
11641 * FDI already provided one idea for the dotclock.
11642 * Yell if the encoder disagrees.
11643 */
11644 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11645 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11646 fdi_dotclock, dotclock);
11647 }
11648 }
11649
11650 static void verify_wm_state(struct drm_crtc *crtc,
11651 struct drm_crtc_state *new_state)
11652 {
11653 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11654 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11655 struct skl_pipe_wm hw_wm, *sw_wm;
11656 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11657 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11659 const enum pipe pipe = intel_crtc->pipe;
11660 int plane, level, max_level = ilk_wm_max_level(dev_priv);
11661
11662 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11663 return;
11664
11665 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11666 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11667
11668 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11669 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11670
11671 if (INTEL_GEN(dev_priv) >= 11)
11672 if (hw_ddb.enabled_slices != sw_ddb->enabled_slices)
11673 DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
11674 sw_ddb->enabled_slices,
11675 hw_ddb.enabled_slices);
11676 /* planes */
11677 for_each_universal_plane(dev_priv, pipe, plane) {
11678 hw_plane_wm = &hw_wm.planes[plane];
11679 sw_plane_wm = &sw_wm->planes[plane];
11680
11681 /* Watermarks */
11682 for (level = 0; level <= max_level; level++) {
11683 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11684 &sw_plane_wm->wm[level]))
11685 continue;
11686
11687 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11688 pipe_name(pipe), plane + 1, level,
11689 sw_plane_wm->wm[level].plane_en,
11690 sw_plane_wm->wm[level].plane_res_b,
11691 sw_plane_wm->wm[level].plane_res_l,
11692 hw_plane_wm->wm[level].plane_en,
11693 hw_plane_wm->wm[level].plane_res_b,
11694 hw_plane_wm->wm[level].plane_res_l);
11695 }
11696
11697 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11698 &sw_plane_wm->trans_wm)) {
11699 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11700 pipe_name(pipe), plane + 1,
11701 sw_plane_wm->trans_wm.plane_en,
11702 sw_plane_wm->trans_wm.plane_res_b,
11703 sw_plane_wm->trans_wm.plane_res_l,
11704 hw_plane_wm->trans_wm.plane_en,
11705 hw_plane_wm->trans_wm.plane_res_b,
11706 hw_plane_wm->trans_wm.plane_res_l);
11707 }
11708
11709 /* DDB */
11710 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11711 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11712
11713 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11714 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11715 pipe_name(pipe), plane + 1,
11716 sw_ddb_entry->start, sw_ddb_entry->end,
11717 hw_ddb_entry->start, hw_ddb_entry->end);
11718 }
11719 }
11720
11721 /*
11722 * cursor
11723 * If the cursor plane isn't active, we may not have updated it's ddb
11724 * allocation. In that case since the ddb allocation will be updated
11725 * once the plane becomes visible, we can skip this check
11726 */
11727 if (1) {
11728 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11729 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11730
11731 /* Watermarks */
11732 for (level = 0; level <= max_level; level++) {
11733 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11734 &sw_plane_wm->wm[level]))
11735 continue;
11736
11737 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11738 pipe_name(pipe), level,
11739 sw_plane_wm->wm[level].plane_en,
11740 sw_plane_wm->wm[level].plane_res_b,
11741 sw_plane_wm->wm[level].plane_res_l,
11742 hw_plane_wm->wm[level].plane_en,
11743 hw_plane_wm->wm[level].plane_res_b,
11744 hw_plane_wm->wm[level].plane_res_l);
11745 }
11746
11747 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11748 &sw_plane_wm->trans_wm)) {
11749 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11750 pipe_name(pipe),
11751 sw_plane_wm->trans_wm.plane_en,
11752 sw_plane_wm->trans_wm.plane_res_b,
11753 sw_plane_wm->trans_wm.plane_res_l,
11754 hw_plane_wm->trans_wm.plane_en,
11755 hw_plane_wm->trans_wm.plane_res_b,
11756 hw_plane_wm->trans_wm.plane_res_l);
11757 }
11758
11759 /* DDB */
11760 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11761 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11762
11763 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11764 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11765 pipe_name(pipe),
11766 sw_ddb_entry->start, sw_ddb_entry->end,
11767 hw_ddb_entry->start, hw_ddb_entry->end);
11768 }
11769 }
11770 }
11771
11772 static void
11773 verify_connector_state(struct drm_device *dev,
11774 struct drm_atomic_state *state,
11775 struct drm_crtc *crtc)
11776 {
11777 struct drm_connector *connector;
11778 struct drm_connector_state *new_conn_state;
11779 int i;
11780
11781 for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11782 struct drm_encoder *encoder = connector->encoder;
11783 struct drm_crtc_state *crtc_state = NULL;
11784
11785 if (new_conn_state->crtc != crtc)
11786 continue;
11787
11788 if (crtc)
11789 crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
11790
11791 intel_connector_verify_state(crtc_state, new_conn_state);
11792
11793 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11794 "connector's atomic encoder doesn't match legacy encoder\n");
11795 }
11796 }
11797
11798 static void
11799 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11800 {
11801 struct intel_encoder *encoder;
11802 struct drm_connector *connector;
11803 struct drm_connector_state *old_conn_state, *new_conn_state;
11804 int i;
11805
11806 for_each_intel_encoder(dev, encoder) {
11807 bool enabled = false, found = false;
11808 enum pipe pipe;
11809
11810 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11811 encoder->base.base.id,
11812 encoder->base.name);
11813
11814 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11815 new_conn_state, i) {
11816 if (old_conn_state->best_encoder == &encoder->base)
11817 found = true;
11818
11819 if (new_conn_state->best_encoder != &encoder->base)
11820 continue;
11821 found = enabled = true;
11822
11823 I915_STATE_WARN(new_conn_state->crtc !=
11824 encoder->base.crtc,
11825 "connector's crtc doesn't match encoder crtc\n");
11826 }
11827
11828 if (!found)
11829 continue;
11830
11831 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11832 "encoder's enabled state mismatch "
11833 "(expected %i, found %i)\n",
11834 !!encoder->base.crtc, enabled);
11835
11836 if (!encoder->base.crtc) {
11837 bool active;
11838
11839 active = encoder->get_hw_state(encoder, &pipe);
11840 I915_STATE_WARN(active,
11841 "encoder detached but still enabled on pipe %c.\n",
11842 pipe_name(pipe));
11843 }
11844 }
11845 }
11846
11847 static void
11848 verify_crtc_state(struct drm_crtc *crtc,
11849 struct drm_crtc_state *old_crtc_state,
11850 struct drm_crtc_state *new_crtc_state)
11851 {
11852 struct drm_device *dev = crtc->dev;
11853 struct drm_i915_private *dev_priv = to_i915(dev);
11854 struct intel_encoder *encoder;
11855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11856 struct intel_crtc_state *pipe_config, *sw_config;
11857 struct drm_atomic_state *old_state;
11858 bool active;
11859
11860 old_state = old_crtc_state->state;
11861 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
11862 pipe_config = to_intel_crtc_state(old_crtc_state);
11863 memset(pipe_config, 0, sizeof(*pipe_config));
11864 pipe_config->base.crtc = crtc;
11865 pipe_config->base.state = old_state;
11866
11867 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
11868
11869 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
11870
11871 /* we keep both pipes enabled on 830 */
11872 if (IS_I830(dev_priv))
11873 active = new_crtc_state->active;
11874
11875 I915_STATE_WARN(new_crtc_state->active != active,
11876 "crtc active state doesn't match with hw state "
11877 "(expected %i, found %i)\n", new_crtc_state->active, active);
11878
11879 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
11880 "transitional active state does not match atomic hw state "
11881 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
11882
11883 for_each_encoder_on_crtc(dev, crtc, encoder) {
11884 enum pipe pipe;
11885
11886 active = encoder->get_hw_state(encoder, &pipe);
11887 I915_STATE_WARN(active != new_crtc_state->active,
11888 "[ENCODER:%i] active %i with crtc active %i\n",
11889 encoder->base.base.id, active, new_crtc_state->active);
11890
11891 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
11892 "Encoder connected to wrong pipe %c\n",
11893 pipe_name(pipe));
11894
11895 if (active)
11896 encoder->get_config(encoder, pipe_config);
11897 }
11898
11899 intel_crtc_compute_pixel_rate(pipe_config);
11900
11901 if (!new_crtc_state->active)
11902 return;
11903
11904 intel_pipe_config_sanity_check(dev_priv, pipe_config);
11905
11906 sw_config = to_intel_crtc_state(new_crtc_state);
11907 if (!intel_pipe_config_compare(dev_priv, sw_config,
11908 pipe_config, false)) {
11909 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11910 intel_dump_pipe_config(intel_crtc, pipe_config,
11911 "[hw state]");
11912 intel_dump_pipe_config(intel_crtc, sw_config,
11913 "[sw state]");
11914 }
11915 }
11916
11917 static void
11918 intel_verify_planes(struct intel_atomic_state *state)
11919 {
11920 struct intel_plane *plane;
11921 const struct intel_plane_state *plane_state;
11922 int i;
11923
11924 for_each_new_intel_plane_in_state(state, plane,
11925 plane_state, i)
11926 assert_plane(plane, plane_state->base.visible);
11927 }
11928
11929 static void
11930 verify_single_dpll_state(struct drm_i915_private *dev_priv,
11931 struct intel_shared_dpll *pll,
11932 struct drm_crtc *crtc,
11933 struct drm_crtc_state *new_state)
11934 {
11935 struct intel_dpll_hw_state dpll_hw_state;
11936 unsigned int crtc_mask;
11937 bool active;
11938
11939 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11940
11941 DRM_DEBUG_KMS("%s\n", pll->info->name);
11942
11943 active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
11944
11945 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
11946 I915_STATE_WARN(!pll->on && pll->active_mask,
11947 "pll in active use but not on in sw tracking\n");
11948 I915_STATE_WARN(pll->on && !pll->active_mask,
11949 "pll is on but not used by any active crtc\n");
11950 I915_STATE_WARN(pll->on != active,
11951 "pll on state mismatch (expected %i, found %i)\n",
11952 pll->on, active);
11953 }
11954
11955 if (!crtc) {
11956 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
11957 "more active pll users than references: %x vs %x\n",
11958 pll->active_mask, pll->state.crtc_mask);
11959
11960 return;
11961 }
11962
11963 crtc_mask = drm_crtc_mask(crtc);
11964
11965 if (new_state->active)
11966 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
11967 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
11968 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11969 else
11970 I915_STATE_WARN(pll->active_mask & crtc_mask,
11971 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
11972 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11973
11974 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
11975 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
11976 crtc_mask, pll->state.crtc_mask);
11977
11978 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
11979 &dpll_hw_state,
11980 sizeof(dpll_hw_state)),
11981 "pll hw state mismatch\n");
11982 }
11983
11984 static void
11985 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
11986 struct drm_crtc_state *old_crtc_state,
11987 struct drm_crtc_state *new_crtc_state)
11988 {
11989 struct drm_i915_private *dev_priv = to_i915(dev);
11990 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
11991 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
11992
11993 if (new_state->shared_dpll)
11994 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
11995
11996 if (old_state->shared_dpll &&
11997 old_state->shared_dpll != new_state->shared_dpll) {
11998 unsigned int crtc_mask = drm_crtc_mask(crtc);
11999 struct intel_shared_dpll *pll = old_state->shared_dpll;
12000
12001 I915_STATE_WARN(pll->active_mask & crtc_mask,
12002 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12003 pipe_name(drm_crtc_index(crtc)));
12004 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
12005 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12006 pipe_name(drm_crtc_index(crtc)));
12007 }
12008 }
12009
12010 static void
12011 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12012 struct drm_atomic_state *state,
12013 struct drm_crtc_state *old_state,
12014 struct drm_crtc_state *new_state)
12015 {
12016 if (!needs_modeset(new_state) &&
12017 !to_intel_crtc_state(new_state)->update_pipe)
12018 return;
12019
12020 verify_wm_state(crtc, new_state);
12021 verify_connector_state(crtc->dev, state, crtc);
12022 verify_crtc_state(crtc, old_state, new_state);
12023 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12024 }
12025
12026 static void
12027 verify_disabled_dpll_state(struct drm_device *dev)
12028 {
12029 struct drm_i915_private *dev_priv = to_i915(dev);
12030 int i;
12031
12032 for (i = 0; i < dev_priv->num_shared_dpll; i++)
12033 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12034 }
12035
12036 static void
12037 intel_modeset_verify_disabled(struct drm_device *dev,
12038 struct drm_atomic_state *state)
12039 {
12040 verify_encoder_state(dev, state);
12041 verify_connector_state(dev, state, NULL);
12042 verify_disabled_dpll_state(dev);
12043 }
12044
12045 static void update_scanline_offset(struct intel_crtc *crtc)
12046 {
12047 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12048
12049 /*
12050 * The scanline counter increments at the leading edge of hsync.
12051 *
12052 * On most platforms it starts counting from vtotal-1 on the
12053 * first active line. That means the scanline counter value is
12054 * always one less than what we would expect. Ie. just after
12055 * start of vblank, which also occurs at start of hsync (on the
12056 * last active line), the scanline counter will read vblank_start-1.
12057 *
12058 * On gen2 the scanline counter starts counting from 1 instead
12059 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12060 * to keep the value positive), instead of adding one.
12061 *
12062 * On HSW+ the behaviour of the scanline counter depends on the output
12063 * type. For DP ports it behaves like most other platforms, but on HDMI
12064 * there's an extra 1 line difference. So we need to add two instead of
12065 * one to the value.
12066 *
12067 * On VLV/CHV DSI the scanline counter would appear to increment
12068 * approx. 1/3 of a scanline before start of vblank. Unfortunately
12069 * that means we can't tell whether we're in vblank or not while
12070 * we're on that particular line. We must still set scanline_offset
12071 * to 1 so that the vblank timestamps come out correct when we query
12072 * the scanline counter from within the vblank interrupt handler.
12073 * However if queried just before the start of vblank we'll get an
12074 * answer that's slightly in the future.
12075 */
12076 if (IS_GEN2(dev_priv)) {
12077 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12078 int vtotal;
12079
12080 vtotal = adjusted_mode->crtc_vtotal;
12081 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12082 vtotal /= 2;
12083
12084 crtc->scanline_offset = vtotal - 1;
12085 } else if (HAS_DDI(dev_priv) &&
12086 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
12087 crtc->scanline_offset = 2;
12088 } else
12089 crtc->scanline_offset = 1;
12090 }
12091
12092 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12093 {
12094 struct drm_device *dev = state->dev;
12095 struct drm_i915_private *dev_priv = to_i915(dev);
12096 struct drm_crtc *crtc;
12097 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12098 int i;
12099
12100 if (!dev_priv->display.crtc_compute_clock)
12101 return;
12102
12103 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12104 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12105 struct intel_shared_dpll *old_dpll =
12106 to_intel_crtc_state(old_crtc_state)->shared_dpll;
12107
12108 if (!needs_modeset(new_crtc_state))
12109 continue;
12110
12111 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
12112
12113 if (!old_dpll)
12114 continue;
12115
12116 intel_release_shared_dpll(old_dpll, intel_crtc, state);
12117 }
12118 }
12119
12120 /*
12121 * This implements the workaround described in the "notes" section of the mode
12122 * set sequence documentation. When going from no pipes or single pipe to
12123 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12124 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12125 */
12126 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12127 {
12128 struct drm_crtc_state *crtc_state;
12129 struct intel_crtc *intel_crtc;
12130 struct drm_crtc *crtc;
12131 struct intel_crtc_state *first_crtc_state = NULL;
12132 struct intel_crtc_state *other_crtc_state = NULL;
12133 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12134 int i;
12135
12136 /* look at all crtc's that are going to be enabled in during modeset */
12137 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12138 intel_crtc = to_intel_crtc(crtc);
12139
12140 if (!crtc_state->active || !needs_modeset(crtc_state))
12141 continue;
12142
12143 if (first_crtc_state) {
12144 other_crtc_state = to_intel_crtc_state(crtc_state);
12145 break;
12146 } else {
12147 first_crtc_state = to_intel_crtc_state(crtc_state);
12148 first_pipe = intel_crtc->pipe;
12149 }
12150 }
12151
12152 /* No workaround needed? */
12153 if (!first_crtc_state)
12154 return 0;
12155
12156 /* w/a possibly needed, check how many crtc's are already enabled. */
12157 for_each_intel_crtc(state->dev, intel_crtc) {
12158 struct intel_crtc_state *pipe_config;
12159
12160 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12161 if (IS_ERR(pipe_config))
12162 return PTR_ERR(pipe_config);
12163
12164 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12165
12166 if (!pipe_config->base.active ||
12167 needs_modeset(&pipe_config->base))
12168 continue;
12169
12170 /* 2 or more enabled crtcs means no need for w/a */
12171 if (enabled_pipe != INVALID_PIPE)
12172 return 0;
12173
12174 enabled_pipe = intel_crtc->pipe;
12175 }
12176
12177 if (enabled_pipe != INVALID_PIPE)
12178 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12179 else if (other_crtc_state)
12180 other_crtc_state->hsw_workaround_pipe = first_pipe;
12181
12182 return 0;
12183 }
12184
12185 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12186 {
12187 struct drm_crtc *crtc;
12188
12189 /* Add all pipes to the state */
12190 for_each_crtc(state->dev, crtc) {
12191 struct drm_crtc_state *crtc_state;
12192
12193 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12194 if (IS_ERR(crtc_state))
12195 return PTR_ERR(crtc_state);
12196 }
12197
12198 return 0;
12199 }
12200
12201 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12202 {
12203 struct drm_crtc *crtc;
12204
12205 /*
12206 * Add all pipes to the state, and force
12207 * a modeset on all the active ones.
12208 */
12209 for_each_crtc(state->dev, crtc) {
12210 struct drm_crtc_state *crtc_state;
12211 int ret;
12212
12213 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12214 if (IS_ERR(crtc_state))
12215 return PTR_ERR(crtc_state);
12216
12217 if (!crtc_state->active || needs_modeset(crtc_state))
12218 continue;
12219
12220 crtc_state->mode_changed = true;
12221
12222 ret = drm_atomic_add_affected_connectors(state, crtc);
12223 if (ret)
12224 return ret;
12225
12226 ret = drm_atomic_add_affected_planes(state, crtc);
12227 if (ret)
12228 return ret;
12229 }
12230
12231 return 0;
12232 }
12233
12234 static int intel_modeset_checks(struct drm_atomic_state *state)
12235 {
12236 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12237 struct drm_i915_private *dev_priv = to_i915(state->dev);
12238 struct drm_crtc *crtc;
12239 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12240 int ret = 0, i;
12241
12242 if (!check_digital_port_conflicts(state)) {
12243 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12244 return -EINVAL;
12245 }
12246
12247 intel_state->modeset = true;
12248 intel_state->active_crtcs = dev_priv->active_crtcs;
12249 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12250 intel_state->cdclk.actual = dev_priv->cdclk.actual;
12251
12252 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12253 if (new_crtc_state->active)
12254 intel_state->active_crtcs |= 1 << i;
12255 else
12256 intel_state->active_crtcs &= ~(1 << i);
12257
12258 if (old_crtc_state->active != new_crtc_state->active)
12259 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12260 }
12261
12262 /*
12263 * See if the config requires any additional preparation, e.g.
12264 * to adjust global state with pipes off. We need to do this
12265 * here so we can get the modeset_pipe updated config for the new
12266 * mode set on this crtc. For other crtcs we need to use the
12267 * adjusted_mode bits in the crtc directly.
12268 */
12269 if (dev_priv->display.modeset_calc_cdclk) {
12270 ret = dev_priv->display.modeset_calc_cdclk(state);
12271 if (ret < 0)
12272 return ret;
12273
12274 /*
12275 * Writes to dev_priv->cdclk.logical must protected by
12276 * holding all the crtc locks, even if we don't end up
12277 * touching the hardware
12278 */
12279 if (intel_cdclk_changed(&dev_priv->cdclk.logical,
12280 &intel_state->cdclk.logical)) {
12281 ret = intel_lock_all_pipes(state);
12282 if (ret < 0)
12283 return ret;
12284 }
12285
12286 /* All pipes must be switched off while we change the cdclk. */
12287 if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
12288 &intel_state->cdclk.actual)) {
12289 ret = intel_modeset_all_pipes(state);
12290 if (ret < 0)
12291 return ret;
12292 }
12293
12294 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12295 intel_state->cdclk.logical.cdclk,
12296 intel_state->cdclk.actual.cdclk);
12297 DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n",
12298 intel_state->cdclk.logical.voltage_level,
12299 intel_state->cdclk.actual.voltage_level);
12300 } else {
12301 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12302 }
12303
12304 intel_modeset_clear_plls(state);
12305
12306 if (IS_HASWELL(dev_priv))
12307 return haswell_mode_set_planes_workaround(state);
12308
12309 return 0;
12310 }
12311
12312 /*
12313 * Handle calculation of various watermark data at the end of the atomic check
12314 * phase. The code here should be run after the per-crtc and per-plane 'check'
12315 * handlers to ensure that all derived state has been updated.
12316 */
12317 static int calc_watermark_data(struct drm_atomic_state *state)
12318 {
12319 struct drm_device *dev = state->dev;
12320 struct drm_i915_private *dev_priv = to_i915(dev);
12321
12322 /* Is there platform-specific watermark information to calculate? */
12323 if (dev_priv->display.compute_global_watermarks)
12324 return dev_priv->display.compute_global_watermarks(state);
12325
12326 return 0;
12327 }
12328
12329 /**
12330 * intel_atomic_check - validate state object
12331 * @dev: drm device
12332 * @state: state to validate
12333 */
12334 static int intel_atomic_check(struct drm_device *dev,
12335 struct drm_atomic_state *state)
12336 {
12337 struct drm_i915_private *dev_priv = to_i915(dev);
12338 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12339 struct drm_crtc *crtc;
12340 struct drm_crtc_state *old_crtc_state, *crtc_state;
12341 int ret, i;
12342 bool any_ms = false;
12343
12344 /* Catch I915_MODE_FLAG_INHERITED */
12345 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
12346 crtc_state, i) {
12347 if (crtc_state->mode.private_flags !=
12348 old_crtc_state->mode.private_flags)
12349 crtc_state->mode_changed = true;
12350 }
12351
12352 ret = drm_atomic_helper_check_modeset(dev, state);
12353 if (ret)
12354 return ret;
12355
12356 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12357 struct intel_crtc_state *pipe_config =
12358 to_intel_crtc_state(crtc_state);
12359
12360 if (!needs_modeset(crtc_state))
12361 continue;
12362
12363 if (!crtc_state->enable) {
12364 any_ms = true;
12365 continue;
12366 }
12367
12368 ret = intel_modeset_pipe_config(crtc, pipe_config);
12369 if (ret) {
12370 intel_dump_pipe_config(to_intel_crtc(crtc),
12371 pipe_config, "[failed]");
12372 return ret;
12373 }
12374
12375 if (i915_modparams.fastboot &&
12376 intel_pipe_config_compare(dev_priv,
12377 to_intel_crtc_state(old_crtc_state),
12378 pipe_config, true)) {
12379 crtc_state->mode_changed = false;
12380 pipe_config->update_pipe = true;
12381 }
12382
12383 if (needs_modeset(crtc_state))
12384 any_ms = true;
12385
12386 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12387 needs_modeset(crtc_state) ?
12388 "[modeset]" : "[fastset]");
12389 }
12390
12391 if (any_ms) {
12392 ret = intel_modeset_checks(state);
12393
12394 if (ret)
12395 return ret;
12396 } else {
12397 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12398 }
12399
12400 ret = drm_atomic_helper_check_planes(dev, state);
12401 if (ret)
12402 return ret;
12403
12404 intel_fbc_choose_crtc(dev_priv, intel_state);
12405 return calc_watermark_data(state);
12406 }
12407
12408 static int intel_atomic_prepare_commit(struct drm_device *dev,
12409 struct drm_atomic_state *state)
12410 {
12411 return drm_atomic_helper_prepare_planes(dev, state);
12412 }
12413
12414 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12415 {
12416 struct drm_device *dev = crtc->base.dev;
12417
12418 if (!dev->max_vblank_count)
12419 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
12420
12421 return dev->driver->get_vblank_counter(dev, crtc->pipe);
12422 }
12423
12424 static void intel_update_crtc(struct drm_crtc *crtc,
12425 struct drm_atomic_state *state,
12426 struct drm_crtc_state *old_crtc_state,
12427 struct drm_crtc_state *new_crtc_state)
12428 {
12429 struct drm_device *dev = crtc->dev;
12430 struct drm_i915_private *dev_priv = to_i915(dev);
12431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12432 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12433 bool modeset = needs_modeset(new_crtc_state);
12434 struct intel_plane_state *new_plane_state =
12435 intel_atomic_get_new_plane_state(to_intel_atomic_state(state),
12436 to_intel_plane(crtc->primary));
12437
12438 if (modeset) {
12439 update_scanline_offset(intel_crtc);
12440 dev_priv->display.crtc_enable(pipe_config, state);
12441
12442 /* vblanks work again, re-enable pipe CRC. */
12443 intel_crtc_enable_pipe_crc(intel_crtc);
12444 } else {
12445 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12446 pipe_config);
12447 }
12448
12449 if (new_plane_state)
12450 intel_fbc_enable(intel_crtc, pipe_config, new_plane_state);
12451
12452 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12453 }
12454
12455 static void intel_update_crtcs(struct drm_atomic_state *state)
12456 {
12457 struct drm_crtc *crtc;
12458 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12459 int i;
12460
12461 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12462 if (!new_crtc_state->active)
12463 continue;
12464
12465 intel_update_crtc(crtc, state, old_crtc_state,
12466 new_crtc_state);
12467 }
12468 }
12469
12470 static void skl_update_crtcs(struct drm_atomic_state *state)
12471 {
12472 struct drm_i915_private *dev_priv = to_i915(state->dev);
12473 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12474 struct drm_crtc *crtc;
12475 struct intel_crtc *intel_crtc;
12476 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12477 struct intel_crtc_state *cstate;
12478 unsigned int updated = 0;
12479 bool progress;
12480 enum pipe pipe;
12481 int i;
12482 u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
12483 u8 required_slices = intel_state->wm_results.ddb.enabled_slices;
12484
12485 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12486
12487 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12488 /* ignore allocations for crtc's that have been turned off. */
12489 if (new_crtc_state->active)
12490 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12491
12492 /* If 2nd DBuf slice required, enable it here */
12493 if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
12494 icl_dbuf_slices_update(dev_priv, required_slices);
12495
12496 /*
12497 * Whenever the number of active pipes changes, we need to make sure we
12498 * update the pipes in the right order so that their ddb allocations
12499 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12500 * cause pipe underruns and other bad stuff.
12501 */
12502 do {
12503 progress = false;
12504
12505 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12506 bool vbl_wait = false;
12507 unsigned int cmask = drm_crtc_mask(crtc);
12508
12509 intel_crtc = to_intel_crtc(crtc);
12510 cstate = to_intel_crtc_state(new_crtc_state);
12511 pipe = intel_crtc->pipe;
12512
12513 if (updated & cmask || !cstate->base.active)
12514 continue;
12515
12516 if (skl_ddb_allocation_overlaps(dev_priv,
12517 entries,
12518 &cstate->wm.skl.ddb,
12519 i))
12520 continue;
12521
12522 updated |= cmask;
12523 entries[i] = &cstate->wm.skl.ddb;
12524
12525 /*
12526 * If this is an already active pipe, it's DDB changed,
12527 * and this isn't the last pipe that needs updating
12528 * then we need to wait for a vblank to pass for the
12529 * new ddb allocation to take effect.
12530 */
12531 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12532 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12533 !new_crtc_state->active_changed &&
12534 intel_state->wm_results.dirty_pipes != updated)
12535 vbl_wait = true;
12536
12537 intel_update_crtc(crtc, state, old_crtc_state,
12538 new_crtc_state);
12539
12540 if (vbl_wait)
12541 intel_wait_for_vblank(dev_priv, pipe);
12542
12543 progress = true;
12544 }
12545 } while (progress);
12546
12547 /* If 2nd DBuf slice is no more required disable it */
12548 if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
12549 icl_dbuf_slices_update(dev_priv, required_slices);
12550 }
12551
12552 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12553 {
12554 struct intel_atomic_state *state, *next;
12555 struct llist_node *freed;
12556
12557 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12558 llist_for_each_entry_safe(state, next, freed, freed)
12559 drm_atomic_state_put(&state->base);
12560 }
12561
12562 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12563 {
12564 struct drm_i915_private *dev_priv =
12565 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12566
12567 intel_atomic_helper_free_state(dev_priv);
12568 }
12569
12570 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
12571 {
12572 struct wait_queue_entry wait_fence, wait_reset;
12573 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
12574
12575 init_wait_entry(&wait_fence, 0);
12576 init_wait_entry(&wait_reset, 0);
12577 for (;;) {
12578 prepare_to_wait(&intel_state->commit_ready.wait,
12579 &wait_fence, TASK_UNINTERRUPTIBLE);
12580 prepare_to_wait(&dev_priv->gpu_error.wait_queue,
12581 &wait_reset, TASK_UNINTERRUPTIBLE);
12582
12583
12584 if (i915_sw_fence_done(&intel_state->commit_ready)
12585 || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
12586 break;
12587
12588 schedule();
12589 }
12590 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
12591 finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset);
12592 }
12593
12594 static void intel_atomic_cleanup_work(struct work_struct *work)
12595 {
12596 struct drm_atomic_state *state =
12597 container_of(work, struct drm_atomic_state, commit_work);
12598 struct drm_i915_private *i915 = to_i915(state->dev);
12599
12600 drm_atomic_helper_cleanup_planes(&i915->drm, state);
12601 drm_atomic_helper_commit_cleanup_done(state);
12602 drm_atomic_state_put(state);
12603
12604 intel_atomic_helper_free_state(i915);
12605 }
12606
12607 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12608 {
12609 struct drm_device *dev = state->dev;
12610 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12611 struct drm_i915_private *dev_priv = to_i915(dev);
12612 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12613 struct drm_crtc *crtc;
12614 struct intel_crtc_state *intel_cstate;
12615 u64 put_domains[I915_MAX_PIPES] = {};
12616 int i;
12617
12618 intel_atomic_commit_fence_wait(intel_state);
12619
12620 drm_atomic_helper_wait_for_dependencies(state);
12621
12622 if (intel_state->modeset)
12623 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12624
12625 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12627
12628 if (needs_modeset(new_crtc_state) ||
12629 to_intel_crtc_state(new_crtc_state)->update_pipe) {
12630
12631 put_domains[to_intel_crtc(crtc)->pipe] =
12632 modeset_get_crtc_power_domains(crtc,
12633 to_intel_crtc_state(new_crtc_state));
12634 }
12635
12636 if (!needs_modeset(new_crtc_state))
12637 continue;
12638
12639 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12640 to_intel_crtc_state(new_crtc_state));
12641
12642 if (old_crtc_state->active) {
12643 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12644
12645 /*
12646 * We need to disable pipe CRC before disabling the pipe,
12647 * or we race against vblank off.
12648 */
12649 intel_crtc_disable_pipe_crc(intel_crtc);
12650
12651 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12652 intel_crtc->active = false;
12653 intel_fbc_disable(intel_crtc);
12654 intel_disable_shared_dpll(intel_crtc);
12655
12656 /*
12657 * Underruns don't always raise
12658 * interrupts, so check manually.
12659 */
12660 intel_check_cpu_fifo_underruns(dev_priv);
12661 intel_check_pch_fifo_underruns(dev_priv);
12662
12663 /* FIXME unify this for all platforms */
12664 if (!new_crtc_state->active &&
12665 !HAS_GMCH_DISPLAY(dev_priv) &&
12666 dev_priv->display.initial_watermarks)
12667 dev_priv->display.initial_watermarks(intel_state,
12668 to_intel_crtc_state(new_crtc_state));
12669 }
12670 }
12671
12672 /* FIXME: Eventually get rid of our intel_crtc->config pointer */
12673 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i)
12674 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
12675
12676 if (intel_state->modeset) {
12677 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12678
12679 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12680
12681 /*
12682 * SKL workaround: bspec recommends we disable the SAGV when we
12683 * have more then one pipe enabled
12684 */
12685 if (!intel_can_enable_sagv(state))
12686 intel_disable_sagv(dev_priv);
12687
12688 intel_modeset_verify_disabled(dev, state);
12689 }
12690
12691 /* Complete the events for pipes that have now been disabled */
12692 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12693 bool modeset = needs_modeset(new_crtc_state);
12694
12695 /* Complete events for now disable pipes here. */
12696 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12697 spin_lock_irq(&dev->event_lock);
12698 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12699 spin_unlock_irq(&dev->event_lock);
12700
12701 new_crtc_state->event = NULL;
12702 }
12703 }
12704
12705 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12706 dev_priv->display.update_crtcs(state);
12707
12708 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12709 * already, but still need the state for the delayed optimization. To
12710 * fix this:
12711 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12712 * - schedule that vblank worker _before_ calling hw_done
12713 * - at the start of commit_tail, cancel it _synchrously
12714 * - switch over to the vblank wait helper in the core after that since
12715 * we don't need out special handling any more.
12716 */
12717 drm_atomic_helper_wait_for_flip_done(dev, state);
12718
12719 /*
12720 * Now that the vblank has passed, we can go ahead and program the
12721 * optimal watermarks on platforms that need two-step watermark
12722 * programming.
12723 *
12724 * TODO: Move this (and other cleanup) to an async worker eventually.
12725 */
12726 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12727 intel_cstate = to_intel_crtc_state(new_crtc_state);
12728
12729 if (dev_priv->display.optimize_watermarks)
12730 dev_priv->display.optimize_watermarks(intel_state,
12731 intel_cstate);
12732 }
12733
12734 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12735 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12736
12737 if (put_domains[i])
12738 modeset_put_power_domains(dev_priv, put_domains[i]);
12739
12740 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12741 }
12742
12743 if (intel_state->modeset)
12744 intel_verify_planes(intel_state);
12745
12746 if (intel_state->modeset && intel_can_enable_sagv(state))
12747 intel_enable_sagv(dev_priv);
12748
12749 drm_atomic_helper_commit_hw_done(state);
12750
12751 if (intel_state->modeset) {
12752 /* As one of the primary mmio accessors, KMS has a high
12753 * likelihood of triggering bugs in unclaimed access. After we
12754 * finish modesetting, see if an error has been flagged, and if
12755 * so enable debugging for the next modeset - and hope we catch
12756 * the culprit.
12757 */
12758 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12759 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12760 }
12761
12762 /*
12763 * Defer the cleanup of the old state to a separate worker to not
12764 * impede the current task (userspace for blocking modesets) that
12765 * are executed inline. For out-of-line asynchronous modesets/flips,
12766 * deferring to a new worker seems overkill, but we would place a
12767 * schedule point (cond_resched()) here anyway to keep latencies
12768 * down.
12769 */
12770 INIT_WORK(&state->commit_work, intel_atomic_cleanup_work);
12771 schedule_work(&state->commit_work);
12772 }
12773
12774 static void intel_atomic_commit_work(struct work_struct *work)
12775 {
12776 struct drm_atomic_state *state =
12777 container_of(work, struct drm_atomic_state, commit_work);
12778
12779 intel_atomic_commit_tail(state);
12780 }
12781
12782 static int __i915_sw_fence_call
12783 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12784 enum i915_sw_fence_notify notify)
12785 {
12786 struct intel_atomic_state *state =
12787 container_of(fence, struct intel_atomic_state, commit_ready);
12788
12789 switch (notify) {
12790 case FENCE_COMPLETE:
12791 /* we do blocking waits in the worker, nothing to do here */
12792 break;
12793 case FENCE_FREE:
12794 {
12795 struct intel_atomic_helper *helper =
12796 &to_i915(state->base.dev)->atomic_helper;
12797
12798 if (llist_add(&state->freed, &helper->free_list))
12799 schedule_work(&helper->free_work);
12800 break;
12801 }
12802 }
12803
12804 return NOTIFY_DONE;
12805 }
12806
12807 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12808 {
12809 struct drm_plane_state *old_plane_state, *new_plane_state;
12810 struct drm_plane *plane;
12811 int i;
12812
12813 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
12814 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12815 intel_fb_obj(new_plane_state->fb),
12816 to_intel_plane(plane)->frontbuffer_bit);
12817 }
12818
12819 /**
12820 * intel_atomic_commit - commit validated state object
12821 * @dev: DRM device
12822 * @state: the top-level driver state object
12823 * @nonblock: nonblocking commit
12824 *
12825 * This function commits a top-level state object that has been validated
12826 * with drm_atomic_helper_check().
12827 *
12828 * RETURNS
12829 * Zero for success or -errno.
12830 */
12831 static int intel_atomic_commit(struct drm_device *dev,
12832 struct drm_atomic_state *state,
12833 bool nonblock)
12834 {
12835 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12836 struct drm_i915_private *dev_priv = to_i915(dev);
12837 int ret = 0;
12838
12839 drm_atomic_state_get(state);
12840 i915_sw_fence_init(&intel_state->commit_ready,
12841 intel_atomic_commit_ready);
12842
12843 /*
12844 * The intel_legacy_cursor_update() fast path takes care
12845 * of avoiding the vblank waits for simple cursor
12846 * movement and flips. For cursor on/off and size changes,
12847 * we want to perform the vblank waits so that watermark
12848 * updates happen during the correct frames. Gen9+ have
12849 * double buffered watermarks and so shouldn't need this.
12850 *
12851 * Unset state->legacy_cursor_update before the call to
12852 * drm_atomic_helper_setup_commit() because otherwise
12853 * drm_atomic_helper_wait_for_flip_done() is a noop and
12854 * we get FIFO underruns because we didn't wait
12855 * for vblank.
12856 *
12857 * FIXME doing watermarks and fb cleanup from a vblank worker
12858 * (assuming we had any) would solve these problems.
12859 */
12860 if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
12861 struct intel_crtc_state *new_crtc_state;
12862 struct intel_crtc *crtc;
12863 int i;
12864
12865 for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i)
12866 if (new_crtc_state->wm.need_postvbl_update ||
12867 new_crtc_state->update_wm_post)
12868 state->legacy_cursor_update = false;
12869 }
12870
12871 ret = intel_atomic_prepare_commit(dev, state);
12872 if (ret) {
12873 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
12874 i915_sw_fence_commit(&intel_state->commit_ready);
12875 return ret;
12876 }
12877
12878 ret = drm_atomic_helper_setup_commit(state, nonblock);
12879 if (!ret)
12880 ret = drm_atomic_helper_swap_state(state, true);
12881
12882 if (ret) {
12883 i915_sw_fence_commit(&intel_state->commit_ready);
12884
12885 drm_atomic_helper_cleanup_planes(dev, state);
12886 return ret;
12887 }
12888 dev_priv->wm.distrust_bios_wm = false;
12889 intel_shared_dpll_swap_state(state);
12890 intel_atomic_track_fbs(state);
12891
12892 if (intel_state->modeset) {
12893 memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
12894 sizeof(intel_state->min_cdclk));
12895 memcpy(dev_priv->min_voltage_level,
12896 intel_state->min_voltage_level,
12897 sizeof(intel_state->min_voltage_level));
12898 dev_priv->active_crtcs = intel_state->active_crtcs;
12899 dev_priv->cdclk.logical = intel_state->cdclk.logical;
12900 dev_priv->cdclk.actual = intel_state->cdclk.actual;
12901 }
12902
12903 drm_atomic_state_get(state);
12904 INIT_WORK(&state->commit_work, intel_atomic_commit_work);
12905
12906 i915_sw_fence_commit(&intel_state->commit_ready);
12907 if (nonblock && intel_state->modeset) {
12908 queue_work(dev_priv->modeset_wq, &state->commit_work);
12909 } else if (nonblock) {
12910 queue_work(system_unbound_wq, &state->commit_work);
12911 } else {
12912 if (intel_state->modeset)
12913 flush_workqueue(dev_priv->modeset_wq);
12914 intel_atomic_commit_tail(state);
12915 }
12916
12917 return 0;
12918 }
12919
12920 static const struct drm_crtc_funcs intel_crtc_funcs = {
12921 .gamma_set = drm_atomic_helper_legacy_gamma_set,
12922 .set_config = drm_atomic_helper_set_config,
12923 .destroy = intel_crtc_destroy,
12924 .page_flip = drm_atomic_helper_page_flip,
12925 .atomic_duplicate_state = intel_crtc_duplicate_state,
12926 .atomic_destroy_state = intel_crtc_destroy_state,
12927 .set_crc_source = intel_crtc_set_crc_source,
12928 };
12929
12930 struct wait_rps_boost {
12931 struct wait_queue_entry wait;
12932
12933 struct drm_crtc *crtc;
12934 struct i915_request *request;
12935 };
12936
12937 static int do_rps_boost(struct wait_queue_entry *_wait,
12938 unsigned mode, int sync, void *key)
12939 {
12940 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
12941 struct i915_request *rq = wait->request;
12942
12943 /*
12944 * If we missed the vblank, but the request is already running it
12945 * is reasonable to assume that it will complete before the next
12946 * vblank without our intervention, so leave RPS alone.
12947 */
12948 if (!i915_request_started(rq))
12949 gen6_rps_boost(rq, NULL);
12950 i915_request_put(rq);
12951
12952 drm_crtc_vblank_put(wait->crtc);
12953
12954 list_del(&wait->wait.entry);
12955 kfree(wait);
12956 return 1;
12957 }
12958
12959 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
12960 struct dma_fence *fence)
12961 {
12962 struct wait_rps_boost *wait;
12963
12964 if (!dma_fence_is_i915(fence))
12965 return;
12966
12967 if (INTEL_GEN(to_i915(crtc->dev)) < 6)
12968 return;
12969
12970 if (drm_crtc_vblank_get(crtc))
12971 return;
12972
12973 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
12974 if (!wait) {
12975 drm_crtc_vblank_put(crtc);
12976 return;
12977 }
12978
12979 wait->request = to_request(dma_fence_get(fence));
12980 wait->crtc = crtc;
12981
12982 wait->wait.func = do_rps_boost;
12983 wait->wait.flags = 0;
12984
12985 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
12986 }
12987
12988 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
12989 {
12990 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
12991 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
12992 struct drm_framebuffer *fb = plane_state->base.fb;
12993 struct i915_vma *vma;
12994
12995 if (plane->id == PLANE_CURSOR &&
12996 INTEL_INFO(dev_priv)->cursor_needs_physical) {
12997 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12998 const int align = intel_cursor_alignment(dev_priv);
12999
13000 return i915_gem_object_attach_phys(obj, align);
13001 }
13002
13003 vma = intel_pin_and_fence_fb_obj(fb,
13004 plane_state->base.rotation,
13005 intel_plane_uses_fence(plane_state),
13006 &plane_state->flags);
13007 if (IS_ERR(vma))
13008 return PTR_ERR(vma);
13009
13010 plane_state->vma = vma;
13011
13012 return 0;
13013 }
13014
13015 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
13016 {
13017 struct i915_vma *vma;
13018
13019 vma = fetch_and_zero(&old_plane_state->vma);
13020 if (vma)
13021 intel_unpin_fb_vma(vma, old_plane_state->flags);
13022 }
13023
13024 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
13025 {
13026 struct i915_sched_attr attr = {
13027 .priority = I915_PRIORITY_DISPLAY,
13028 };
13029
13030 i915_gem_object_wait_priority(obj, 0, &attr);
13031 }
13032
13033 /**
13034 * intel_prepare_plane_fb - Prepare fb for usage on plane
13035 * @plane: drm plane to prepare for
13036 * @new_state: the plane state being prepared
13037 *
13038 * Prepares a framebuffer for usage on a display plane. Generally this
13039 * involves pinning the underlying object and updating the frontbuffer tracking
13040 * bits. Some older platforms need special physical address handling for
13041 * cursor planes.
13042 *
13043 * Must be called with struct_mutex held.
13044 *
13045 * Returns 0 on success, negative error code on failure.
13046 */
13047 int
13048 intel_prepare_plane_fb(struct drm_plane *plane,
13049 struct drm_plane_state *new_state)
13050 {
13051 struct intel_atomic_state *intel_state =
13052 to_intel_atomic_state(new_state->state);
13053 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13054 struct drm_framebuffer *fb = new_state->fb;
13055 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13056 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13057 int ret;
13058
13059 if (old_obj) {
13060 struct drm_crtc_state *crtc_state =
13061 drm_atomic_get_new_crtc_state(new_state->state,
13062 plane->state->crtc);
13063
13064 /* Big Hammer, we also need to ensure that any pending
13065 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13066 * current scanout is retired before unpinning the old
13067 * framebuffer. Note that we rely on userspace rendering
13068 * into the buffer attached to the pipe they are waiting
13069 * on. If not, userspace generates a GPU hang with IPEHR
13070 * point to the MI_WAIT_FOR_EVENT.
13071 *
13072 * This should only fail upon a hung GPU, in which case we
13073 * can safely continue.
13074 */
13075 if (needs_modeset(crtc_state)) {
13076 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13077 old_obj->resv, NULL,
13078 false, 0,
13079 GFP_KERNEL);
13080 if (ret < 0)
13081 return ret;
13082 }
13083 }
13084
13085 if (new_state->fence) { /* explicit fencing */
13086 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13087 new_state->fence,
13088 I915_FENCE_TIMEOUT,
13089 GFP_KERNEL);
13090 if (ret < 0)
13091 return ret;
13092 }
13093
13094 if (!obj)
13095 return 0;
13096
13097 ret = i915_gem_object_pin_pages(obj);
13098 if (ret)
13099 return ret;
13100
13101 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13102 if (ret) {
13103 i915_gem_object_unpin_pages(obj);
13104 return ret;
13105 }
13106
13107 ret = intel_plane_pin_fb(to_intel_plane_state(new_state));
13108
13109 fb_obj_bump_render_priority(obj);
13110
13111 mutex_unlock(&dev_priv->drm.struct_mutex);
13112 i915_gem_object_unpin_pages(obj);
13113 if (ret)
13114 return ret;
13115
13116 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13117
13118 if (!new_state->fence) { /* implicit fencing */
13119 struct dma_fence *fence;
13120
13121 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13122 obj->resv, NULL,
13123 false, I915_FENCE_TIMEOUT,
13124 GFP_KERNEL);
13125 if (ret < 0)
13126 return ret;
13127
13128 fence = reservation_object_get_excl_rcu(obj->resv);
13129 if (fence) {
13130 add_rps_boost_after_vblank(new_state->crtc, fence);
13131 dma_fence_put(fence);
13132 }
13133 } else {
13134 add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
13135 }
13136
13137 /*
13138 * We declare pageflips to be interactive and so merit a small bias
13139 * towards upclocking to deliver the frame on time. By only changing
13140 * the RPS thresholds to sample more regularly and aim for higher
13141 * clocks we can hopefully deliver low power workloads (like kodi)
13142 * that are not quite steady state without resorting to forcing
13143 * maximum clocks following a vblank miss (see do_rps_boost()).
13144 */
13145 if (!intel_state->rps_interactive) {
13146 intel_rps_mark_interactive(dev_priv, true);
13147 intel_state->rps_interactive = true;
13148 }
13149
13150 return 0;
13151 }
13152
13153 /**
13154 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13155 * @plane: drm plane to clean up for
13156 * @old_state: the state from the previous modeset
13157 *
13158 * Cleans up a framebuffer that has just been removed from a plane.
13159 *
13160 * Must be called with struct_mutex held.
13161 */
13162 void
13163 intel_cleanup_plane_fb(struct drm_plane *plane,
13164 struct drm_plane_state *old_state)
13165 {
13166 struct intel_atomic_state *intel_state =
13167 to_intel_atomic_state(old_state->state);
13168 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13169
13170 if (intel_state->rps_interactive) {
13171 intel_rps_mark_interactive(dev_priv, false);
13172 intel_state->rps_interactive = false;
13173 }
13174
13175 /* Should only be called after a successful intel_prepare_plane_fb()! */
13176 mutex_lock(&dev_priv->drm.struct_mutex);
13177 intel_plane_unpin_fb(to_intel_plane_state(old_state));
13178 mutex_unlock(&dev_priv->drm.struct_mutex);
13179 }
13180
13181 int
13182 skl_max_scale(struct intel_crtc *intel_crtc,
13183 struct intel_crtc_state *crtc_state,
13184 uint32_t pixel_format)
13185 {
13186 struct drm_i915_private *dev_priv;
13187 int max_scale, mult;
13188 int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
13189
13190 if (!intel_crtc || !crtc_state->base.enable)
13191 return DRM_PLANE_HELPER_NO_SCALING;
13192
13193 dev_priv = to_i915(intel_crtc->base.dev);
13194
13195 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13196 max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
13197
13198 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
13199 max_dotclk *= 2;
13200
13201 if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
13202 return DRM_PLANE_HELPER_NO_SCALING;
13203
13204 /*
13205 * skl max scale is lower of:
13206 * close to 3 but not 3, -1 is for that purpose
13207 * or
13208 * cdclk/crtc_clock
13209 */
13210 mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
13211 tmpclk1 = (1 << 16) * mult - 1;
13212 tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
13213 max_scale = min(tmpclk1, tmpclk2);
13214
13215 return max_scale;
13216 }
13217
13218 static int
13219 intel_check_primary_plane(struct intel_plane *plane,
13220 struct intel_crtc_state *crtc_state,
13221 struct intel_plane_state *state)
13222 {
13223 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
13224 struct drm_crtc *crtc = state->base.crtc;
13225 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13226 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13227 bool can_position = false;
13228 int ret;
13229 uint32_t pixel_format = 0;
13230
13231 if (INTEL_GEN(dev_priv) >= 9) {
13232 /* use scaler when colorkey is not required */
13233 if (!state->ckey.flags) {
13234 min_scale = 1;
13235 if (state->base.fb)
13236 pixel_format = state->base.fb->format->format;
13237 max_scale = skl_max_scale(to_intel_crtc(crtc),
13238 crtc_state, pixel_format);
13239 }
13240 can_position = true;
13241 }
13242
13243 ret = drm_atomic_helper_check_plane_state(&state->base,
13244 &crtc_state->base,
13245 min_scale, max_scale,
13246 can_position, true);
13247 if (ret)
13248 return ret;
13249
13250 if (!state->base.fb)
13251 return 0;
13252
13253 if (INTEL_GEN(dev_priv) >= 9) {
13254 ret = skl_check_plane_surface(crtc_state, state);
13255 if (ret)
13256 return ret;
13257
13258 state->ctl = skl_plane_ctl(crtc_state, state);
13259 } else {
13260 ret = i9xx_check_plane_surface(state);
13261 if (ret)
13262 return ret;
13263
13264 state->ctl = i9xx_plane_ctl(crtc_state, state);
13265 }
13266
13267 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
13268 state->color_ctl = glk_plane_color_ctl(crtc_state, state);
13269
13270 return 0;
13271 }
13272
13273 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13274 struct drm_crtc_state *old_crtc_state)
13275 {
13276 struct drm_device *dev = crtc->dev;
13277 struct drm_i915_private *dev_priv = to_i915(dev);
13278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13279 struct intel_crtc_state *old_intel_cstate =
13280 to_intel_crtc_state(old_crtc_state);
13281 struct intel_atomic_state *old_intel_state =
13282 to_intel_atomic_state(old_crtc_state->state);
13283 struct intel_crtc_state *intel_cstate =
13284 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
13285 bool modeset = needs_modeset(&intel_cstate->base);
13286
13287 if (!modeset &&
13288 (intel_cstate->base.color_mgmt_changed ||
13289 intel_cstate->update_pipe)) {
13290 intel_color_set_csc(&intel_cstate->base);
13291 intel_color_load_luts(&intel_cstate->base);
13292 }
13293
13294 /* Perform vblank evasion around commit operation */
13295 intel_pipe_update_start(intel_cstate);
13296
13297 if (modeset)
13298 goto out;
13299
13300 if (intel_cstate->update_pipe)
13301 intel_update_pipe_config(old_intel_cstate, intel_cstate);
13302 else if (INTEL_GEN(dev_priv) >= 9)
13303 skl_detach_scalers(intel_crtc);
13304
13305 out:
13306 if (dev_priv->display.atomic_update_watermarks)
13307 dev_priv->display.atomic_update_watermarks(old_intel_state,
13308 intel_cstate);
13309 }
13310
13311 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
13312 struct intel_crtc_state *crtc_state)
13313 {
13314 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13315
13316 if (!IS_GEN2(dev_priv))
13317 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
13318
13319 if (crtc_state->has_pch_encoder) {
13320 enum pipe pch_transcoder =
13321 intel_crtc_pch_transcoder(crtc);
13322
13323 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
13324 }
13325 }
13326
13327 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13328 struct drm_crtc_state *old_crtc_state)
13329 {
13330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13331 struct intel_atomic_state *old_intel_state =
13332 to_intel_atomic_state(old_crtc_state->state);
13333 struct intel_crtc_state *new_crtc_state =
13334 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
13335
13336 intel_pipe_update_end(new_crtc_state);
13337
13338 if (new_crtc_state->update_pipe &&
13339 !needs_modeset(&new_crtc_state->base) &&
13340 old_crtc_state->mode.private_flags & I915_MODE_FLAG_INHERITED)
13341 intel_crtc_arm_fifo_underrun(intel_crtc, new_crtc_state);
13342 }
13343
13344 /**
13345 * intel_plane_destroy - destroy a plane
13346 * @plane: plane to destroy
13347 *
13348 * Common destruction function for all types of planes (primary, cursor,
13349 * sprite).
13350 */
13351 void intel_plane_destroy(struct drm_plane *plane)
13352 {
13353 drm_plane_cleanup(plane);
13354 kfree(to_intel_plane(plane));
13355 }
13356
13357 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
13358 u32 format, u64 modifier)
13359 {
13360 switch (modifier) {
13361 case DRM_FORMAT_MOD_LINEAR:
13362 case I915_FORMAT_MOD_X_TILED:
13363 break;
13364 default:
13365 return false;
13366 }
13367
13368 switch (format) {
13369 case DRM_FORMAT_C8:
13370 case DRM_FORMAT_RGB565:
13371 case DRM_FORMAT_XRGB1555:
13372 case DRM_FORMAT_XRGB8888:
13373 return modifier == DRM_FORMAT_MOD_LINEAR ||
13374 modifier == I915_FORMAT_MOD_X_TILED;
13375 default:
13376 return false;
13377 }
13378 }
13379
13380 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
13381 u32 format, u64 modifier)
13382 {
13383 switch (modifier) {
13384 case DRM_FORMAT_MOD_LINEAR:
13385 case I915_FORMAT_MOD_X_TILED:
13386 break;
13387 default:
13388 return false;
13389 }
13390
13391 switch (format) {
13392 case DRM_FORMAT_C8:
13393 case DRM_FORMAT_RGB565:
13394 case DRM_FORMAT_XRGB8888:
13395 case DRM_FORMAT_XBGR8888:
13396 case DRM_FORMAT_XRGB2101010:
13397 case DRM_FORMAT_XBGR2101010:
13398 return modifier == DRM_FORMAT_MOD_LINEAR ||
13399 modifier == I915_FORMAT_MOD_X_TILED;
13400 default:
13401 return false;
13402 }
13403 }
13404
13405 static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
13406 u32 format, u64 modifier)
13407 {
13408 struct intel_plane *plane = to_intel_plane(_plane);
13409
13410 switch (modifier) {
13411 case DRM_FORMAT_MOD_LINEAR:
13412 case I915_FORMAT_MOD_X_TILED:
13413 case I915_FORMAT_MOD_Y_TILED:
13414 case I915_FORMAT_MOD_Yf_TILED:
13415 break;
13416 case I915_FORMAT_MOD_Y_TILED_CCS:
13417 case I915_FORMAT_MOD_Yf_TILED_CCS:
13418 if (!plane->has_ccs)
13419 return false;
13420 break;
13421 default:
13422 return false;
13423 }
13424
13425 switch (format) {
13426 case DRM_FORMAT_XRGB8888:
13427 case DRM_FORMAT_XBGR8888:
13428 case DRM_FORMAT_ARGB8888:
13429 case DRM_FORMAT_ABGR8888:
13430 if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
13431 modifier == I915_FORMAT_MOD_Y_TILED_CCS)
13432 return true;
13433 /* fall through */
13434 case DRM_FORMAT_RGB565:
13435 case DRM_FORMAT_XRGB2101010:
13436 case DRM_FORMAT_XBGR2101010:
13437 case DRM_FORMAT_YUYV:
13438 case DRM_FORMAT_YVYU:
13439 case DRM_FORMAT_UYVY:
13440 case DRM_FORMAT_VYUY:
13441 case DRM_FORMAT_NV12:
13442 if (modifier == I915_FORMAT_MOD_Yf_TILED)
13443 return true;
13444 /* fall through */
13445 case DRM_FORMAT_C8:
13446 if (modifier == DRM_FORMAT_MOD_LINEAR ||
13447 modifier == I915_FORMAT_MOD_X_TILED ||
13448 modifier == I915_FORMAT_MOD_Y_TILED)
13449 return true;
13450 /* fall through */
13451 default:
13452 return false;
13453 }
13454 }
13455
13456 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
13457 u32 format, u64 modifier)
13458 {
13459 return modifier == DRM_FORMAT_MOD_LINEAR &&
13460 format == DRM_FORMAT_ARGB8888;
13461 }
13462
13463 static struct drm_plane_funcs skl_plane_funcs = {
13464 .update_plane = drm_atomic_helper_update_plane,
13465 .disable_plane = drm_atomic_helper_disable_plane,
13466 .destroy = intel_plane_destroy,
13467 .atomic_get_property = intel_plane_atomic_get_property,
13468 .atomic_set_property = intel_plane_atomic_set_property,
13469 .atomic_duplicate_state = intel_plane_duplicate_state,
13470 .atomic_destroy_state = intel_plane_destroy_state,
13471 .format_mod_supported = skl_plane_format_mod_supported,
13472 };
13473
13474 static struct drm_plane_funcs i965_plane_funcs = {
13475 .update_plane = drm_atomic_helper_update_plane,
13476 .disable_plane = drm_atomic_helper_disable_plane,
13477 .destroy = intel_plane_destroy,
13478 .atomic_get_property = intel_plane_atomic_get_property,
13479 .atomic_set_property = intel_plane_atomic_set_property,
13480 .atomic_duplicate_state = intel_plane_duplicate_state,
13481 .atomic_destroy_state = intel_plane_destroy_state,
13482 .format_mod_supported = i965_plane_format_mod_supported,
13483 };
13484
13485 static struct drm_plane_funcs i8xx_plane_funcs = {
13486 .update_plane = drm_atomic_helper_update_plane,
13487 .disable_plane = drm_atomic_helper_disable_plane,
13488 .destroy = intel_plane_destroy,
13489 .atomic_get_property = intel_plane_atomic_get_property,
13490 .atomic_set_property = intel_plane_atomic_set_property,
13491 .atomic_duplicate_state = intel_plane_duplicate_state,
13492 .atomic_destroy_state = intel_plane_destroy_state,
13493 .format_mod_supported = i8xx_plane_format_mod_supported,
13494 };
13495
13496 static int
13497 intel_legacy_cursor_update(struct drm_plane *plane,
13498 struct drm_crtc *crtc,
13499 struct drm_framebuffer *fb,
13500 int crtc_x, int crtc_y,
13501 unsigned int crtc_w, unsigned int crtc_h,
13502 uint32_t src_x, uint32_t src_y,
13503 uint32_t src_w, uint32_t src_h,
13504 struct drm_modeset_acquire_ctx *ctx)
13505 {
13506 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13507 int ret;
13508 struct drm_plane_state *old_plane_state, *new_plane_state;
13509 struct intel_plane *intel_plane = to_intel_plane(plane);
13510 struct drm_framebuffer *old_fb;
13511 struct drm_crtc_state *crtc_state = crtc->state;
13512
13513 /*
13514 * When crtc is inactive or there is a modeset pending,
13515 * wait for it to complete in the slowpath
13516 */
13517 if (!crtc_state->active || needs_modeset(crtc_state) ||
13518 to_intel_crtc_state(crtc_state)->update_pipe)
13519 goto slow;
13520
13521 old_plane_state = plane->state;
13522 /*
13523 * Don't do an async update if there is an outstanding commit modifying
13524 * the plane. This prevents our async update's changes from getting
13525 * overridden by a previous synchronous update's state.
13526 */
13527 if (old_plane_state->commit &&
13528 !try_wait_for_completion(&old_plane_state->commit->hw_done))
13529 goto slow;
13530
13531 /*
13532 * If any parameters change that may affect watermarks,
13533 * take the slowpath. Only changing fb or position should be
13534 * in the fastpath.
13535 */
13536 if (old_plane_state->crtc != crtc ||
13537 old_plane_state->src_w != src_w ||
13538 old_plane_state->src_h != src_h ||
13539 old_plane_state->crtc_w != crtc_w ||
13540 old_plane_state->crtc_h != crtc_h ||
13541 !old_plane_state->fb != !fb)
13542 goto slow;
13543
13544 new_plane_state = intel_plane_duplicate_state(plane);
13545 if (!new_plane_state)
13546 return -ENOMEM;
13547
13548 drm_atomic_set_fb_for_plane(new_plane_state, fb);
13549
13550 new_plane_state->src_x = src_x;
13551 new_plane_state->src_y = src_y;
13552 new_plane_state->src_w = src_w;
13553 new_plane_state->src_h = src_h;
13554 new_plane_state->crtc_x = crtc_x;
13555 new_plane_state->crtc_y = crtc_y;
13556 new_plane_state->crtc_w = crtc_w;
13557 new_plane_state->crtc_h = crtc_h;
13558
13559 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13560 to_intel_crtc_state(crtc->state), /* FIXME need a new crtc state? */
13561 to_intel_plane_state(plane->state),
13562 to_intel_plane_state(new_plane_state));
13563 if (ret)
13564 goto out_free;
13565
13566 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13567 if (ret)
13568 goto out_free;
13569
13570 ret = intel_plane_pin_fb(to_intel_plane_state(new_plane_state));
13571 if (ret)
13572 goto out_unlock;
13573
13574 intel_fb_obj_flush(intel_fb_obj(fb), ORIGIN_FLIP);
13575
13576 old_fb = old_plane_state->fb;
13577 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13578 intel_plane->frontbuffer_bit);
13579
13580 /* Swap plane state */
13581 plane->state = new_plane_state;
13582
13583 if (plane->state->visible) {
13584 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13585 intel_plane->update_plane(intel_plane,
13586 to_intel_crtc_state(crtc->state),
13587 to_intel_plane_state(plane->state));
13588 } else {
13589 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13590 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13591 }
13592
13593 intel_plane_unpin_fb(to_intel_plane_state(old_plane_state));
13594
13595 out_unlock:
13596 mutex_unlock(&dev_priv->drm.struct_mutex);
13597 out_free:
13598 if (ret)
13599 intel_plane_destroy_state(plane, new_plane_state);
13600 else
13601 intel_plane_destroy_state(plane, old_plane_state);
13602 return ret;
13603
13604 slow:
13605 return drm_atomic_helper_update_plane(plane, crtc, fb,
13606 crtc_x, crtc_y, crtc_w, crtc_h,
13607 src_x, src_y, src_w, src_h, ctx);
13608 }
13609
13610 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13611 .update_plane = intel_legacy_cursor_update,
13612 .disable_plane = drm_atomic_helper_disable_plane,
13613 .destroy = intel_plane_destroy,
13614 .atomic_get_property = intel_plane_atomic_get_property,
13615 .atomic_set_property = intel_plane_atomic_set_property,
13616 .atomic_duplicate_state = intel_plane_duplicate_state,
13617 .atomic_destroy_state = intel_plane_destroy_state,
13618 .format_mod_supported = intel_cursor_format_mod_supported,
13619 };
13620
13621 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
13622 enum i9xx_plane_id i9xx_plane)
13623 {
13624 if (!HAS_FBC(dev_priv))
13625 return false;
13626
13627 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
13628 return i9xx_plane == PLANE_A; /* tied to pipe A */
13629 else if (IS_IVYBRIDGE(dev_priv))
13630 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
13631 i9xx_plane == PLANE_C;
13632 else if (INTEL_GEN(dev_priv) >= 4)
13633 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
13634 else
13635 return i9xx_plane == PLANE_A;
13636 }
13637
13638 static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
13639 enum pipe pipe, enum plane_id plane_id)
13640 {
13641 if (!HAS_FBC(dev_priv))
13642 return false;
13643
13644 return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
13645 }
13646
13647 bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
13648 enum pipe pipe, enum plane_id plane_id)
13649 {
13650 if (plane_id == PLANE_PRIMARY) {
13651 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
13652 return false;
13653 else if ((INTEL_GEN(dev_priv) == 9 && pipe == PIPE_C) &&
13654 !IS_GEMINILAKE(dev_priv))
13655 return false;
13656 } else if (plane_id >= PLANE_SPRITE0) {
13657 if (plane_id == PLANE_CURSOR)
13658 return false;
13659 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) == 10) {
13660 if (plane_id != PLANE_SPRITE0)
13661 return false;
13662 } else {
13663 if (plane_id != PLANE_SPRITE0 || pipe == PIPE_C ||
13664 IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
13665 return false;
13666 }
13667 }
13668 return true;
13669 }
13670
13671 static struct intel_plane *
13672 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13673 {
13674 struct intel_plane *primary = NULL;
13675 struct intel_plane_state *state = NULL;
13676 const struct drm_plane_funcs *plane_funcs;
13677 const uint32_t *intel_primary_formats;
13678 unsigned int supported_rotations;
13679 unsigned int num_formats;
13680 const uint64_t *modifiers;
13681 int ret;
13682
13683 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13684 if (!primary) {
13685 ret = -ENOMEM;
13686 goto fail;
13687 }
13688
13689 state = intel_create_plane_state(&primary->base);
13690 if (!state) {
13691 ret = -ENOMEM;
13692 goto fail;
13693 }
13694
13695 primary->base.state = &state->base;
13696
13697 primary->can_scale = false;
13698 primary->max_downscale = 1;
13699 if (INTEL_GEN(dev_priv) >= 9) {
13700 primary->can_scale = true;
13701 state->scaler_id = -1;
13702 }
13703 primary->pipe = pipe;
13704 /*
13705 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13706 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13707 */
13708 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13709 primary->i9xx_plane = (enum i9xx_plane_id) !pipe;
13710 else
13711 primary->i9xx_plane = (enum i9xx_plane_id) pipe;
13712 primary->id = PLANE_PRIMARY;
13713 primary->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, primary->id);
13714
13715 if (INTEL_GEN(dev_priv) >= 9)
13716 primary->has_fbc = skl_plane_has_fbc(dev_priv,
13717 primary->pipe,
13718 primary->id);
13719 else
13720 primary->has_fbc = i9xx_plane_has_fbc(dev_priv,
13721 primary->i9xx_plane);
13722
13723 if (primary->has_fbc) {
13724 struct intel_fbc *fbc = &dev_priv->fbc;
13725
13726 fbc->possible_framebuffer_bits |= primary->frontbuffer_bit;
13727 }
13728
13729 primary->check_plane = intel_check_primary_plane;
13730
13731 if (INTEL_GEN(dev_priv) >= 9) {
13732 primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
13733 PLANE_PRIMARY);
13734
13735 if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
13736 intel_primary_formats = skl_pri_planar_formats;
13737 num_formats = ARRAY_SIZE(skl_pri_planar_formats);
13738 } else {
13739 intel_primary_formats = skl_primary_formats;
13740 num_formats = ARRAY_SIZE(skl_primary_formats);
13741 }
13742
13743 if (primary->has_ccs)
13744 modifiers = skl_format_modifiers_ccs;
13745 else
13746 modifiers = skl_format_modifiers_noccs;
13747
13748 primary->update_plane = skl_update_plane;
13749 primary->disable_plane = skl_disable_plane;
13750 primary->get_hw_state = skl_plane_get_hw_state;
13751
13752 plane_funcs = &skl_plane_funcs;
13753 } else if (INTEL_GEN(dev_priv) >= 4) {
13754 intel_primary_formats = i965_primary_formats;
13755 num_formats = ARRAY_SIZE(i965_primary_formats);
13756 modifiers = i9xx_format_modifiers;
13757
13758 primary->update_plane = i9xx_update_plane;
13759 primary->disable_plane = i9xx_disable_plane;
13760 primary->get_hw_state = i9xx_plane_get_hw_state;
13761
13762 plane_funcs = &i965_plane_funcs;
13763 } else {
13764 intel_primary_formats = i8xx_primary_formats;
13765 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13766 modifiers = i9xx_format_modifiers;
13767
13768 primary->update_plane = i9xx_update_plane;
13769 primary->disable_plane = i9xx_disable_plane;
13770 primary->get_hw_state = i9xx_plane_get_hw_state;
13771
13772 plane_funcs = &i8xx_plane_funcs;
13773 }
13774
13775 if (INTEL_GEN(dev_priv) >= 9)
13776 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13777 0, plane_funcs,
13778 intel_primary_formats, num_formats,
13779 modifiers,
13780 DRM_PLANE_TYPE_PRIMARY,
13781 "plane 1%c", pipe_name(pipe));
13782 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13783 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13784 0, plane_funcs,
13785 intel_primary_formats, num_formats,
13786 modifiers,
13787 DRM_PLANE_TYPE_PRIMARY,
13788 "primary %c", pipe_name(pipe));
13789 else
13790 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13791 0, plane_funcs,
13792 intel_primary_formats, num_formats,
13793 modifiers,
13794 DRM_PLANE_TYPE_PRIMARY,
13795 "plane %c",
13796 plane_name(primary->i9xx_plane));
13797 if (ret)
13798 goto fail;
13799
13800 if (INTEL_GEN(dev_priv) >= 10) {
13801 supported_rotations =
13802 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13803 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270 |
13804 DRM_MODE_REFLECT_X;
13805 } else if (INTEL_GEN(dev_priv) >= 9) {
13806 supported_rotations =
13807 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13808 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13809 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13810 supported_rotations =
13811 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13812 DRM_MODE_REFLECT_X;
13813 } else if (INTEL_GEN(dev_priv) >= 4) {
13814 supported_rotations =
13815 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13816 } else {
13817 supported_rotations = DRM_MODE_ROTATE_0;
13818 }
13819
13820 if (INTEL_GEN(dev_priv) >= 4)
13821 drm_plane_create_rotation_property(&primary->base,
13822 DRM_MODE_ROTATE_0,
13823 supported_rotations);
13824
13825 if (INTEL_GEN(dev_priv) >= 9)
13826 drm_plane_create_color_properties(&primary->base,
13827 BIT(DRM_COLOR_YCBCR_BT601) |
13828 BIT(DRM_COLOR_YCBCR_BT709),
13829 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
13830 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
13831 DRM_COLOR_YCBCR_BT709,
13832 DRM_COLOR_YCBCR_LIMITED_RANGE);
13833
13834 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13835
13836 return primary;
13837
13838 fail:
13839 kfree(state);
13840 kfree(primary);
13841
13842 return ERR_PTR(ret);
13843 }
13844
13845 static struct intel_plane *
13846 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13847 enum pipe pipe)
13848 {
13849 struct intel_plane *cursor = NULL;
13850 struct intel_plane_state *state = NULL;
13851 int ret;
13852
13853 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13854 if (!cursor) {
13855 ret = -ENOMEM;
13856 goto fail;
13857 }
13858
13859 state = intel_create_plane_state(&cursor->base);
13860 if (!state) {
13861 ret = -ENOMEM;
13862 goto fail;
13863 }
13864
13865 cursor->base.state = &state->base;
13866
13867 cursor->can_scale = false;
13868 cursor->max_downscale = 1;
13869 cursor->pipe = pipe;
13870 cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
13871 cursor->id = PLANE_CURSOR;
13872 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
13873
13874 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13875 cursor->update_plane = i845_update_cursor;
13876 cursor->disable_plane = i845_disable_cursor;
13877 cursor->get_hw_state = i845_cursor_get_hw_state;
13878 cursor->check_plane = i845_check_cursor;
13879 } else {
13880 cursor->update_plane = i9xx_update_cursor;
13881 cursor->disable_plane = i9xx_disable_cursor;
13882 cursor->get_hw_state = i9xx_cursor_get_hw_state;
13883 cursor->check_plane = i9xx_check_cursor;
13884 }
13885
13886 cursor->cursor.base = ~0;
13887 cursor->cursor.cntl = ~0;
13888
13889 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13890 cursor->cursor.size = ~0;
13891
13892 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13893 0, &intel_cursor_plane_funcs,
13894 intel_cursor_formats,
13895 ARRAY_SIZE(intel_cursor_formats),
13896 cursor_format_modifiers,
13897 DRM_PLANE_TYPE_CURSOR,
13898 "cursor %c", pipe_name(pipe));
13899 if (ret)
13900 goto fail;
13901
13902 if (INTEL_GEN(dev_priv) >= 4)
13903 drm_plane_create_rotation_property(&cursor->base,
13904 DRM_MODE_ROTATE_0,
13905 DRM_MODE_ROTATE_0 |
13906 DRM_MODE_ROTATE_180);
13907
13908 if (INTEL_GEN(dev_priv) >= 9)
13909 state->scaler_id = -1;
13910
13911 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13912
13913 return cursor;
13914
13915 fail:
13916 kfree(state);
13917 kfree(cursor);
13918
13919 return ERR_PTR(ret);
13920 }
13921
13922 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13923 struct intel_crtc_state *crtc_state)
13924 {
13925 struct intel_crtc_scaler_state *scaler_state =
13926 &crtc_state->scaler_state;
13927 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13928 int i;
13929
13930 crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13931 if (!crtc->num_scalers)
13932 return;
13933
13934 for (i = 0; i < crtc->num_scalers; i++) {
13935 struct intel_scaler *scaler = &scaler_state->scalers[i];
13936
13937 scaler->in_use = 0;
13938 scaler->mode = PS_SCALER_MODE_DYN;
13939 }
13940
13941 scaler_state->scaler_id = -1;
13942 }
13943
13944 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13945 {
13946 struct intel_crtc *intel_crtc;
13947 struct intel_crtc_state *crtc_state = NULL;
13948 struct intel_plane *primary = NULL;
13949 struct intel_plane *cursor = NULL;
13950 int sprite, ret;
13951
13952 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13953 if (!intel_crtc)
13954 return -ENOMEM;
13955
13956 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13957 if (!crtc_state) {
13958 ret = -ENOMEM;
13959 goto fail;
13960 }
13961 intel_crtc->config = crtc_state;
13962 intel_crtc->base.state = &crtc_state->base;
13963 crtc_state->base.crtc = &intel_crtc->base;
13964
13965 primary = intel_primary_plane_create(dev_priv, pipe);
13966 if (IS_ERR(primary)) {
13967 ret = PTR_ERR(primary);
13968 goto fail;
13969 }
13970 intel_crtc->plane_ids_mask |= BIT(primary->id);
13971
13972 for_each_sprite(dev_priv, pipe, sprite) {
13973 struct intel_plane *plane;
13974
13975 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13976 if (IS_ERR(plane)) {
13977 ret = PTR_ERR(plane);
13978 goto fail;
13979 }
13980 intel_crtc->plane_ids_mask |= BIT(plane->id);
13981 }
13982
13983 cursor = intel_cursor_plane_create(dev_priv, pipe);
13984 if (IS_ERR(cursor)) {
13985 ret = PTR_ERR(cursor);
13986 goto fail;
13987 }
13988 intel_crtc->plane_ids_mask |= BIT(cursor->id);
13989
13990 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13991 &primary->base, &cursor->base,
13992 &intel_crtc_funcs,
13993 "pipe %c", pipe_name(pipe));
13994 if (ret)
13995 goto fail;
13996
13997 intel_crtc->pipe = pipe;
13998
13999 /* initialize shared scalers */
14000 intel_crtc_init_scalers(intel_crtc, crtc_state);
14001
14002 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
14003 dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
14004 dev_priv->pipe_to_crtc_mapping[pipe] = intel_crtc;
14005
14006 if (INTEL_GEN(dev_priv) < 9) {
14007 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
14008
14009 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14010 dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
14011 dev_priv->plane_to_crtc_mapping[i9xx_plane] = intel_crtc;
14012 }
14013
14014 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14015
14016 intel_color_init(&intel_crtc->base);
14017
14018 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14019
14020 return 0;
14021
14022 fail:
14023 /*
14024 * drm_mode_config_cleanup() will free up any
14025 * crtcs/planes already initialized.
14026 */
14027 kfree(crtc_state);
14028 kfree(intel_crtc);
14029
14030 return ret;
14031 }
14032
14033 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14034 {
14035 struct drm_device *dev = connector->base.dev;
14036
14037 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14038
14039 if (!connector->base.state->crtc)
14040 return INVALID_PIPE;
14041
14042 return to_intel_crtc(connector->base.state->crtc)->pipe;
14043 }
14044
14045 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
14046 struct drm_file *file)
14047 {
14048 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14049 struct drm_crtc *drmmode_crtc;
14050 struct intel_crtc *crtc;
14051
14052 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
14053 if (!drmmode_crtc)
14054 return -ENOENT;
14055
14056 crtc = to_intel_crtc(drmmode_crtc);
14057 pipe_from_crtc_id->pipe = crtc->pipe;
14058
14059 return 0;
14060 }
14061
14062 static int intel_encoder_clones(struct intel_encoder *encoder)
14063 {
14064 struct drm_device *dev = encoder->base.dev;
14065 struct intel_encoder *source_encoder;
14066 int index_mask = 0;
14067 int entry = 0;
14068
14069 for_each_intel_encoder(dev, source_encoder) {
14070 if (encoders_cloneable(encoder, source_encoder))
14071 index_mask |= (1 << entry);
14072
14073 entry++;
14074 }
14075
14076 return index_mask;
14077 }
14078
14079 static bool has_edp_a(struct drm_i915_private *dev_priv)
14080 {
14081 if (!IS_MOBILE(dev_priv))
14082 return false;
14083
14084 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14085 return false;
14086
14087 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14088 return false;
14089
14090 return true;
14091 }
14092
14093 static bool intel_crt_present(struct drm_i915_private *dev_priv)
14094 {
14095 if (INTEL_GEN(dev_priv) >= 9)
14096 return false;
14097
14098 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
14099 return false;
14100
14101 if (IS_CHERRYVIEW(dev_priv))
14102 return false;
14103
14104 if (HAS_PCH_LPT_H(dev_priv) &&
14105 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14106 return false;
14107
14108 /* DDI E can't be used if DDI A requires 4 lanes */
14109 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14110 return false;
14111
14112 if (!dev_priv->vbt.int_crt_support)
14113 return false;
14114
14115 return true;
14116 }
14117
14118 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
14119 {
14120 int pps_num;
14121 int pps_idx;
14122
14123 if (HAS_DDI(dev_priv))
14124 return;
14125 /*
14126 * This w/a is needed at least on CPT/PPT, but to be sure apply it
14127 * everywhere where registers can be write protected.
14128 */
14129 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14130 pps_num = 2;
14131 else
14132 pps_num = 1;
14133
14134 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14135 u32 val = I915_READ(PP_CONTROL(pps_idx));
14136
14137 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14138 I915_WRITE(PP_CONTROL(pps_idx), val);
14139 }
14140 }
14141
14142 static void intel_pps_init(struct drm_i915_private *dev_priv)
14143 {
14144 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
14145 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14146 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14147 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14148 else
14149 dev_priv->pps_mmio_base = PPS_BASE;
14150
14151 intel_pps_unlock_regs_wa(dev_priv);
14152 }
14153
14154 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14155 {
14156 struct intel_encoder *encoder;
14157 bool dpd_is_edp = false;
14158
14159 intel_pps_init(dev_priv);
14160
14161 /*
14162 * intel_edp_init_connector() depends on this completing first, to
14163 * prevent the registeration of both eDP and LVDS and the incorrect
14164 * sharing of the PPS.
14165 */
14166 intel_lvds_init(dev_priv);
14167
14168 if (intel_crt_present(dev_priv))
14169 intel_crt_init(dev_priv);
14170
14171 if (IS_ICELAKE(dev_priv)) {
14172 intel_ddi_init(dev_priv, PORT_A);
14173 intel_ddi_init(dev_priv, PORT_B);
14174 intel_ddi_init(dev_priv, PORT_C);
14175 intel_ddi_init(dev_priv, PORT_D);
14176 intel_ddi_init(dev_priv, PORT_E);
14177 intel_ddi_init(dev_priv, PORT_F);
14178 } else if (IS_GEN9_LP(dev_priv)) {
14179 /*
14180 * FIXME: Broxton doesn't support port detection via the
14181 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14182 * detect the ports.
14183 */
14184 intel_ddi_init(dev_priv, PORT_A);
14185 intel_ddi_init(dev_priv, PORT_B);
14186 intel_ddi_init(dev_priv, PORT_C);
14187
14188 vlv_dsi_init(dev_priv);
14189 } else if (HAS_DDI(dev_priv)) {
14190 int found;
14191
14192 /*
14193 * Haswell uses DDI functions to detect digital outputs.
14194 * On SKL pre-D0 the strap isn't connected, so we assume
14195 * it's there.
14196 */
14197 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14198 /* WaIgnoreDDIAStrap: skl */
14199 if (found || IS_GEN9_BC(dev_priv))
14200 intel_ddi_init(dev_priv, PORT_A);
14201
14202 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
14203 * register */
14204 found = I915_READ(SFUSE_STRAP);
14205
14206 if (found & SFUSE_STRAP_DDIB_DETECTED)
14207 intel_ddi_init(dev_priv, PORT_B);
14208 if (found & SFUSE_STRAP_DDIC_DETECTED)
14209 intel_ddi_init(dev_priv, PORT_C);
14210 if (found & SFUSE_STRAP_DDID_DETECTED)
14211 intel_ddi_init(dev_priv, PORT_D);
14212 if (found & SFUSE_STRAP_DDIF_DETECTED)
14213 intel_ddi_init(dev_priv, PORT_F);
14214 /*
14215 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14216 */
14217 if (IS_GEN9_BC(dev_priv) &&
14218 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14219 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14220 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14221 intel_ddi_init(dev_priv, PORT_E);
14222
14223 } else if (HAS_PCH_SPLIT(dev_priv)) {
14224 int found;
14225 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
14226
14227 if (has_edp_a(dev_priv))
14228 intel_dp_init(dev_priv, DP_A, PORT_A);
14229
14230 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14231 /* PCH SDVOB multiplex with HDMIB */
14232 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14233 if (!found)
14234 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14235 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14236 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14237 }
14238
14239 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14240 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14241
14242 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14243 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14244
14245 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14246 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14247
14248 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14249 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14250 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14251 bool has_edp, has_port;
14252
14253 /*
14254 * The DP_DETECTED bit is the latched state of the DDC
14255 * SDA pin at boot. However since eDP doesn't require DDC
14256 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14257 * eDP ports may have been muxed to an alternate function.
14258 * Thus we can't rely on the DP_DETECTED bit alone to detect
14259 * eDP ports. Consult the VBT as well as DP_DETECTED to
14260 * detect eDP ports.
14261 *
14262 * Sadly the straps seem to be missing sometimes even for HDMI
14263 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14264 * and VBT for the presence of the port. Additionally we can't
14265 * trust the port type the VBT declares as we've seen at least
14266 * HDMI ports that the VBT claim are DP or eDP.
14267 */
14268 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
14269 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14270 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14271 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14272 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14273 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14274
14275 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
14276 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14277 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14278 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14279 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14280 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14281
14282 if (IS_CHERRYVIEW(dev_priv)) {
14283 /*
14284 * eDP not supported on port D,
14285 * so no need to worry about it
14286 */
14287 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14288 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14289 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14290 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14291 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14292 }
14293
14294 vlv_dsi_init(dev_priv);
14295 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
14296 bool found = false;
14297
14298 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14299 DRM_DEBUG_KMS("probing SDVOB\n");
14300 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14301 if (!found && IS_G4X(dev_priv)) {
14302 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14303 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14304 }
14305
14306 if (!found && IS_G4X(dev_priv))
14307 intel_dp_init(dev_priv, DP_B, PORT_B);
14308 }
14309
14310 /* Before G4X SDVOC doesn't have its own detect register */
14311
14312 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14313 DRM_DEBUG_KMS("probing SDVOC\n");
14314 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14315 }
14316
14317 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14318
14319 if (IS_G4X(dev_priv)) {
14320 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14321 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14322 }
14323 if (IS_G4X(dev_priv))
14324 intel_dp_init(dev_priv, DP_C, PORT_C);
14325 }
14326
14327 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14328 intel_dp_init(dev_priv, DP_D, PORT_D);
14329 } else if (IS_GEN2(dev_priv))
14330 intel_dvo_init(dev_priv);
14331
14332 if (SUPPORTS_TV(dev_priv))
14333 intel_tv_init(dev_priv);
14334
14335 intel_psr_init(dev_priv);
14336
14337 for_each_intel_encoder(&dev_priv->drm, encoder) {
14338 encoder->base.possible_crtcs = encoder->crtc_mask;
14339 encoder->base.possible_clones =
14340 intel_encoder_clones(encoder);
14341 }
14342
14343 intel_init_pch_refclk(dev_priv);
14344
14345 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14346 }
14347
14348 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14349 {
14350 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14351 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14352
14353 drm_framebuffer_cleanup(fb);
14354
14355 i915_gem_object_lock(obj);
14356 WARN_ON(!obj->framebuffer_references--);
14357 i915_gem_object_unlock(obj);
14358
14359 i915_gem_object_put(obj);
14360
14361 kfree(intel_fb);
14362 }
14363
14364 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14365 struct drm_file *file,
14366 unsigned int *handle)
14367 {
14368 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14369
14370 if (obj->userptr.mm) {
14371 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14372 return -EINVAL;
14373 }
14374
14375 return drm_gem_handle_create(file, &obj->base, handle);
14376 }
14377
14378 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14379 struct drm_file *file,
14380 unsigned flags, unsigned color,
14381 struct drm_clip_rect *clips,
14382 unsigned num_clips)
14383 {
14384 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14385
14386 i915_gem_object_flush_if_display(obj);
14387 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
14388
14389 return 0;
14390 }
14391
14392 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14393 .destroy = intel_user_framebuffer_destroy,
14394 .create_handle = intel_user_framebuffer_create_handle,
14395 .dirty = intel_user_framebuffer_dirty,
14396 };
14397
14398 static
14399 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14400 uint64_t fb_modifier, uint32_t pixel_format)
14401 {
14402 u32 gen = INTEL_GEN(dev_priv);
14403
14404 if (gen >= 9) {
14405 int cpp = drm_format_plane_cpp(pixel_format, 0);
14406
14407 /* "The stride in bytes must not exceed the of the size of 8K
14408 * pixels and 32K bytes."
14409 */
14410 return min(8192 * cpp, 32768);
14411 } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
14412 return 32*1024;
14413 } else if (gen >= 4) {
14414 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14415 return 16*1024;
14416 else
14417 return 32*1024;
14418 } else if (gen >= 3) {
14419 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14420 return 8*1024;
14421 else
14422 return 16*1024;
14423 } else {
14424 /* XXX DSPC is limited to 4k tiled */
14425 return 8*1024;
14426 }
14427 }
14428
14429 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14430 struct drm_i915_gem_object *obj,
14431 struct drm_mode_fb_cmd2 *mode_cmd)
14432 {
14433 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14434 struct drm_framebuffer *fb = &intel_fb->base;
14435 struct drm_format_name_buf format_name;
14436 u32 pitch_limit;
14437 unsigned int tiling, stride;
14438 int ret = -EINVAL;
14439 int i;
14440
14441 i915_gem_object_lock(obj);
14442 obj->framebuffer_references++;
14443 tiling = i915_gem_object_get_tiling(obj);
14444 stride = i915_gem_object_get_stride(obj);
14445 i915_gem_object_unlock(obj);
14446
14447 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14448 /*
14449 * If there's a fence, enforce that
14450 * the fb modifier and tiling mode match.
14451 */
14452 if (tiling != I915_TILING_NONE &&
14453 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14454 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
14455 goto err;
14456 }
14457 } else {
14458 if (tiling == I915_TILING_X) {
14459 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14460 } else if (tiling == I915_TILING_Y) {
14461 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
14462 goto err;
14463 }
14464 }
14465
14466 /* Passed in modifier sanity checking. */
14467 switch (mode_cmd->modifier[0]) {
14468 case I915_FORMAT_MOD_Y_TILED_CCS:
14469 case I915_FORMAT_MOD_Yf_TILED_CCS:
14470 switch (mode_cmd->pixel_format) {
14471 case DRM_FORMAT_XBGR8888:
14472 case DRM_FORMAT_ABGR8888:
14473 case DRM_FORMAT_XRGB8888:
14474 case DRM_FORMAT_ARGB8888:
14475 break;
14476 default:
14477 DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n");
14478 goto err;
14479 }
14480 /* fall through */
14481 case I915_FORMAT_MOD_Y_TILED:
14482 case I915_FORMAT_MOD_Yf_TILED:
14483 if (INTEL_GEN(dev_priv) < 9) {
14484 DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
14485 mode_cmd->modifier[0]);
14486 goto err;
14487 }
14488 case DRM_FORMAT_MOD_LINEAR:
14489 case I915_FORMAT_MOD_X_TILED:
14490 break;
14491 default:
14492 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
14493 mode_cmd->modifier[0]);
14494 goto err;
14495 }
14496
14497 /*
14498 * gen2/3 display engine uses the fence if present,
14499 * so the tiling mode must match the fb modifier exactly.
14500 */
14501 if (INTEL_GEN(dev_priv) < 4 &&
14502 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14503 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
14504 goto err;
14505 }
14506
14507 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14508 mode_cmd->pixel_format);
14509 if (mode_cmd->pitches[0] > pitch_limit) {
14510 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
14511 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
14512 "tiled" : "linear",
14513 mode_cmd->pitches[0], pitch_limit);
14514 goto err;
14515 }
14516
14517 /*
14518 * If there's a fence, enforce that
14519 * the fb pitch and fence stride match.
14520 */
14521 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14522 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14523 mode_cmd->pitches[0], stride);
14524 goto err;
14525 }
14526
14527 /* Reject formats not supported by any plane early. */
14528 switch (mode_cmd->pixel_format) {
14529 case DRM_FORMAT_C8:
14530 case DRM_FORMAT_RGB565:
14531 case DRM_FORMAT_XRGB8888:
14532 case DRM_FORMAT_ARGB8888:
14533 break;
14534 case DRM_FORMAT_XRGB1555:
14535 if (INTEL_GEN(dev_priv) > 3) {
14536 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14537 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14538 goto err;
14539 }
14540 break;
14541 case DRM_FORMAT_ABGR8888:
14542 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14543 INTEL_GEN(dev_priv) < 9) {
14544 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14545 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14546 goto err;
14547 }
14548 break;
14549 case DRM_FORMAT_XBGR8888:
14550 case DRM_FORMAT_XRGB2101010:
14551 case DRM_FORMAT_XBGR2101010:
14552 if (INTEL_GEN(dev_priv) < 4) {
14553 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14554 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14555 goto err;
14556 }
14557 break;
14558 case DRM_FORMAT_ABGR2101010:
14559 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14560 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14561 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14562 goto err;
14563 }
14564 break;
14565 case DRM_FORMAT_YUYV:
14566 case DRM_FORMAT_UYVY:
14567 case DRM_FORMAT_YVYU:
14568 case DRM_FORMAT_VYUY:
14569 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
14570 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14571 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14572 goto err;
14573 }
14574 break;
14575 case DRM_FORMAT_NV12:
14576 if (INTEL_GEN(dev_priv) < 9 || IS_SKYLAKE(dev_priv) ||
14577 IS_BROXTON(dev_priv)) {
14578 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14579 drm_get_format_name(mode_cmd->pixel_format,
14580 &format_name));
14581 goto err;
14582 }
14583 break;
14584 default:
14585 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14586 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14587 goto err;
14588 }
14589
14590 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14591 if (mode_cmd->offsets[0] != 0)
14592 goto err;
14593
14594 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
14595
14596 if (fb->format->format == DRM_FORMAT_NV12 &&
14597 (fb->width < SKL_MIN_YUV_420_SRC_W ||
14598 fb->height < SKL_MIN_YUV_420_SRC_H ||
14599 (fb->width % 4) != 0 || (fb->height % 4) != 0)) {
14600 DRM_DEBUG_KMS("src dimensions not correct for NV12\n");
14601 goto err;
14602 }
14603
14604 for (i = 0; i < fb->format->num_planes; i++) {
14605 u32 stride_alignment;
14606
14607 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
14608 DRM_DEBUG_KMS("bad plane %d handle\n", i);
14609 goto err;
14610 }
14611
14612 stride_alignment = intel_fb_stride_alignment(fb, i);
14613
14614 /*
14615 * Display WA #0531: skl,bxt,kbl,glk
14616 *
14617 * Render decompression and plane width > 3840
14618 * combined with horizontal panning requires the
14619 * plane stride to be a multiple of 4. We'll just
14620 * require the entire fb to accommodate that to avoid
14621 * potential runtime errors at plane configuration time.
14622 */
14623 if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 &&
14624 (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
14625 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
14626 stride_alignment *= 4;
14627
14628 if (fb->pitches[i] & (stride_alignment - 1)) {
14629 DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
14630 i, fb->pitches[i], stride_alignment);
14631 goto err;
14632 }
14633
14634 fb->obj[i] = &obj->base;
14635 }
14636
14637 ret = intel_fill_fb_info(dev_priv, fb);
14638 if (ret)
14639 goto err;
14640
14641 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
14642 if (ret) {
14643 DRM_ERROR("framebuffer init failed %d\n", ret);
14644 goto err;
14645 }
14646
14647 return 0;
14648
14649 err:
14650 i915_gem_object_lock(obj);
14651 obj->framebuffer_references--;
14652 i915_gem_object_unlock(obj);
14653 return ret;
14654 }
14655
14656 static struct drm_framebuffer *
14657 intel_user_framebuffer_create(struct drm_device *dev,
14658 struct drm_file *filp,
14659 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14660 {
14661 struct drm_framebuffer *fb;
14662 struct drm_i915_gem_object *obj;
14663 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14664
14665 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14666 if (!obj)
14667 return ERR_PTR(-ENOENT);
14668
14669 fb = intel_framebuffer_create(obj, &mode_cmd);
14670 if (IS_ERR(fb))
14671 i915_gem_object_put(obj);
14672
14673 return fb;
14674 }
14675
14676 static void intel_atomic_state_free(struct drm_atomic_state *state)
14677 {
14678 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14679
14680 drm_atomic_state_default_release(state);
14681
14682 i915_sw_fence_fini(&intel_state->commit_ready);
14683
14684 kfree(state);
14685 }
14686
14687 static enum drm_mode_status
14688 intel_mode_valid(struct drm_device *dev,
14689 const struct drm_display_mode *mode)
14690 {
14691 struct drm_i915_private *dev_priv = to_i915(dev);
14692 int hdisplay_max, htotal_max;
14693 int vdisplay_max, vtotal_max;
14694
14695 /*
14696 * Can't reject DBLSCAN here because Xorg ddxen can add piles
14697 * of DBLSCAN modes to the output's mode list when they detect
14698 * the scaling mode property on the connector. And they don't
14699 * ask the kernel to validate those modes in any way until
14700 * modeset time at which point the client gets a protocol error.
14701 * So in order to not upset those clients we silently ignore the
14702 * DBLSCAN flag on such connectors. For other connectors we will
14703 * reject modes with the DBLSCAN flag in encoder->compute_config().
14704 * And we always reject DBLSCAN modes in connector->mode_valid()
14705 * as we never want such modes on the connector's mode list.
14706 */
14707
14708 if (mode->vscan > 1)
14709 return MODE_NO_VSCAN;
14710
14711 if (mode->flags & DRM_MODE_FLAG_HSKEW)
14712 return MODE_H_ILLEGAL;
14713
14714 if (mode->flags & (DRM_MODE_FLAG_CSYNC |
14715 DRM_MODE_FLAG_NCSYNC |
14716 DRM_MODE_FLAG_PCSYNC))
14717 return MODE_HSYNC;
14718
14719 if (mode->flags & (DRM_MODE_FLAG_BCAST |
14720 DRM_MODE_FLAG_PIXMUX |
14721 DRM_MODE_FLAG_CLKDIV2))
14722 return MODE_BAD;
14723
14724 if (INTEL_GEN(dev_priv) >= 9 ||
14725 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
14726 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
14727 vdisplay_max = 4096;
14728 htotal_max = 8192;
14729 vtotal_max = 8192;
14730 } else if (INTEL_GEN(dev_priv) >= 3) {
14731 hdisplay_max = 4096;
14732 vdisplay_max = 4096;
14733 htotal_max = 8192;
14734 vtotal_max = 8192;
14735 } else {
14736 hdisplay_max = 2048;
14737 vdisplay_max = 2048;
14738 htotal_max = 4096;
14739 vtotal_max = 4096;
14740 }
14741
14742 if (mode->hdisplay > hdisplay_max ||
14743 mode->hsync_start > htotal_max ||
14744 mode->hsync_end > htotal_max ||
14745 mode->htotal > htotal_max)
14746 return MODE_H_ILLEGAL;
14747
14748 if (mode->vdisplay > vdisplay_max ||
14749 mode->vsync_start > vtotal_max ||
14750 mode->vsync_end > vtotal_max ||
14751 mode->vtotal > vtotal_max)
14752 return MODE_V_ILLEGAL;
14753
14754 return MODE_OK;
14755 }
14756
14757 static const struct drm_mode_config_funcs intel_mode_funcs = {
14758 .fb_create = intel_user_framebuffer_create,
14759 .get_format_info = intel_get_format_info,
14760 .output_poll_changed = intel_fbdev_output_poll_changed,
14761 .mode_valid = intel_mode_valid,
14762 .atomic_check = intel_atomic_check,
14763 .atomic_commit = intel_atomic_commit,
14764 .atomic_state_alloc = intel_atomic_state_alloc,
14765 .atomic_state_clear = intel_atomic_state_clear,
14766 .atomic_state_free = intel_atomic_state_free,
14767 };
14768
14769 /**
14770 * intel_init_display_hooks - initialize the display modesetting hooks
14771 * @dev_priv: device private
14772 */
14773 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14774 {
14775 intel_init_cdclk_hooks(dev_priv);
14776
14777 if (INTEL_GEN(dev_priv) >= 9) {
14778 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14779 dev_priv->display.get_initial_plane_config =
14780 skylake_get_initial_plane_config;
14781 dev_priv->display.crtc_compute_clock =
14782 haswell_crtc_compute_clock;
14783 dev_priv->display.crtc_enable = haswell_crtc_enable;
14784 dev_priv->display.crtc_disable = haswell_crtc_disable;
14785 } else if (HAS_DDI(dev_priv)) {
14786 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14787 dev_priv->display.get_initial_plane_config =
14788 i9xx_get_initial_plane_config;
14789 dev_priv->display.crtc_compute_clock =
14790 haswell_crtc_compute_clock;
14791 dev_priv->display.crtc_enable = haswell_crtc_enable;
14792 dev_priv->display.crtc_disable = haswell_crtc_disable;
14793 } else if (HAS_PCH_SPLIT(dev_priv)) {
14794 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14795 dev_priv->display.get_initial_plane_config =
14796 i9xx_get_initial_plane_config;
14797 dev_priv->display.crtc_compute_clock =
14798 ironlake_crtc_compute_clock;
14799 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14800 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14801 } else if (IS_CHERRYVIEW(dev_priv)) {
14802 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14803 dev_priv->display.get_initial_plane_config =
14804 i9xx_get_initial_plane_config;
14805 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14806 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14807 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14808 } else if (IS_VALLEYVIEW(dev_priv)) {
14809 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14810 dev_priv->display.get_initial_plane_config =
14811 i9xx_get_initial_plane_config;
14812 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14813 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14814 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14815 } else if (IS_G4X(dev_priv)) {
14816 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14817 dev_priv->display.get_initial_plane_config =
14818 i9xx_get_initial_plane_config;
14819 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14820 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14821 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14822 } else if (IS_PINEVIEW(dev_priv)) {
14823 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14824 dev_priv->display.get_initial_plane_config =
14825 i9xx_get_initial_plane_config;
14826 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14827 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14828 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14829 } else if (!IS_GEN2(dev_priv)) {
14830 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14831 dev_priv->display.get_initial_plane_config =
14832 i9xx_get_initial_plane_config;
14833 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14834 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14835 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14836 } else {
14837 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14838 dev_priv->display.get_initial_plane_config =
14839 i9xx_get_initial_plane_config;
14840 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14841 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14842 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14843 }
14844
14845 if (IS_GEN5(dev_priv)) {
14846 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14847 } else if (IS_GEN6(dev_priv)) {
14848 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14849 } else if (IS_IVYBRIDGE(dev_priv)) {
14850 /* FIXME: detect B0+ stepping and use auto training */
14851 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14852 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14853 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14854 }
14855
14856 if (INTEL_GEN(dev_priv) >= 9)
14857 dev_priv->display.update_crtcs = skl_update_crtcs;
14858 else
14859 dev_priv->display.update_crtcs = intel_update_crtcs;
14860 }
14861
14862 /*
14863 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14864 */
14865 static void quirk_ssc_force_disable(struct drm_device *dev)
14866 {
14867 struct drm_i915_private *dev_priv = to_i915(dev);
14868 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14869 DRM_INFO("applying lvds SSC disable quirk\n");
14870 }
14871
14872 /*
14873 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14874 * brightness value
14875 */
14876 static void quirk_invert_brightness(struct drm_device *dev)
14877 {
14878 struct drm_i915_private *dev_priv = to_i915(dev);
14879 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14880 DRM_INFO("applying inverted panel brightness quirk\n");
14881 }
14882
14883 /* Some VBT's incorrectly indicate no backlight is present */
14884 static void quirk_backlight_present(struct drm_device *dev)
14885 {
14886 struct drm_i915_private *dev_priv = to_i915(dev);
14887 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14888 DRM_INFO("applying backlight present quirk\n");
14889 }
14890
14891 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
14892 * which is 300 ms greater than eDP spec T12 min.
14893 */
14894 static void quirk_increase_t12_delay(struct drm_device *dev)
14895 {
14896 struct drm_i915_private *dev_priv = to_i915(dev);
14897
14898 dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
14899 DRM_INFO("Applying T12 delay quirk\n");
14900 }
14901
14902 /*
14903 * GeminiLake NUC HDMI outputs require additional off time
14904 * this allows the onboard retimer to correctly sync to signal
14905 */
14906 static void quirk_increase_ddi_disabled_time(struct drm_device *dev)
14907 {
14908 struct drm_i915_private *dev_priv = to_i915(dev);
14909
14910 dev_priv->quirks |= QUIRK_INCREASE_DDI_DISABLED_TIME;
14911 DRM_INFO("Applying Increase DDI Disabled quirk\n");
14912 }
14913
14914 struct intel_quirk {
14915 int device;
14916 int subsystem_vendor;
14917 int subsystem_device;
14918 void (*hook)(struct drm_device *dev);
14919 };
14920
14921 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14922 struct intel_dmi_quirk {
14923 void (*hook)(struct drm_device *dev);
14924 const struct dmi_system_id (*dmi_id_list)[];
14925 };
14926
14927 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14928 {
14929 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14930 return 1;
14931 }
14932
14933 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14934 {
14935 .dmi_id_list = &(const struct dmi_system_id[]) {
14936 {
14937 .callback = intel_dmi_reverse_brightness,
14938 .ident = "NCR Corporation",
14939 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14940 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14941 },
14942 },
14943 { } /* terminating entry */
14944 },
14945 .hook = quirk_invert_brightness,
14946 },
14947 };
14948
14949 static struct intel_quirk intel_quirks[] = {
14950 /* Lenovo U160 cannot use SSC on LVDS */
14951 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14952
14953 /* Sony Vaio Y cannot use SSC on LVDS */
14954 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14955
14956 /* Acer Aspire 5734Z must invert backlight brightness */
14957 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14958
14959 /* Acer/eMachines G725 */
14960 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14961
14962 /* Acer/eMachines e725 */
14963 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14964
14965 /* Acer/Packard Bell NCL20 */
14966 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14967
14968 /* Acer Aspire 4736Z */
14969 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14970
14971 /* Acer Aspire 5336 */
14972 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14973
14974 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14975 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14976
14977 /* Acer C720 Chromebook (Core i3 4005U) */
14978 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14979
14980 /* Apple Macbook 2,1 (Core 2 T7400) */
14981 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14982
14983 /* Apple Macbook 4,1 */
14984 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14985
14986 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14987 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14988
14989 /* HP Chromebook 14 (Celeron 2955U) */
14990 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14991
14992 /* Dell Chromebook 11 */
14993 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14994
14995 /* Dell Chromebook 11 (2015 version) */
14996 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14997
14998 /* Toshiba Satellite P50-C-18C */
14999 { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
15000
15001 /* GeminiLake NUC */
15002 { 0x3185, 0x8086, 0x2072, quirk_increase_ddi_disabled_time },
15003 { 0x3184, 0x8086, 0x2072, quirk_increase_ddi_disabled_time },
15004 /* ASRock ITX*/
15005 { 0x3185, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
15006 { 0x3184, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
15007 };
15008
15009 static void intel_init_quirks(struct drm_device *dev)
15010 {
15011 struct pci_dev *d = dev->pdev;
15012 int i;
15013
15014 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15015 struct intel_quirk *q = &intel_quirks[i];
15016
15017 if (d->device == q->device &&
15018 (d->subsystem_vendor == q->subsystem_vendor ||
15019 q->subsystem_vendor == PCI_ANY_ID) &&
15020 (d->subsystem_device == q->subsystem_device ||
15021 q->subsystem_device == PCI_ANY_ID))
15022 q->hook(dev);
15023 }
15024 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15025 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15026 intel_dmi_quirks[i].hook(dev);
15027 }
15028 }
15029
15030 /* Disable the VGA plane that we never use */
15031 static void i915_disable_vga(struct drm_i915_private *dev_priv)
15032 {
15033 struct pci_dev *pdev = dev_priv->drm.pdev;
15034 u8 sr1;
15035 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15036
15037 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15038 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
15039 outb(SR01, VGA_SR_INDEX);
15040 sr1 = inb(VGA_SR_DATA);
15041 outb(sr1 | 1<<5, VGA_SR_DATA);
15042 vga_put(pdev, VGA_RSRC_LEGACY_IO);
15043 udelay(300);
15044
15045 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15046 POSTING_READ(vga_reg);
15047 }
15048
15049 void intel_modeset_init_hw(struct drm_device *dev)
15050 {
15051 struct drm_i915_private *dev_priv = to_i915(dev);
15052
15053 intel_update_cdclk(dev_priv);
15054 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
15055 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
15056 }
15057
15058 /*
15059 * Calculate what we think the watermarks should be for the state we've read
15060 * out of the hardware and then immediately program those watermarks so that
15061 * we ensure the hardware settings match our internal state.
15062 *
15063 * We can calculate what we think WM's should be by creating a duplicate of the
15064 * current state (which was constructed during hardware readout) and running it
15065 * through the atomic check code to calculate new watermark values in the
15066 * state object.
15067 */
15068 static void sanitize_watermarks(struct drm_device *dev)
15069 {
15070 struct drm_i915_private *dev_priv = to_i915(dev);
15071 struct drm_atomic_state *state;
15072 struct intel_atomic_state *intel_state;
15073 struct drm_crtc *crtc;
15074 struct drm_crtc_state *cstate;
15075 struct drm_modeset_acquire_ctx ctx;
15076 int ret;
15077 int i;
15078
15079 /* Only supported on platforms that use atomic watermark design */
15080 if (!dev_priv->display.optimize_watermarks)
15081 return;
15082
15083 /*
15084 * We need to hold connection_mutex before calling duplicate_state so
15085 * that the connector loop is protected.
15086 */
15087 drm_modeset_acquire_init(&ctx, 0);
15088 retry:
15089 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15090 if (ret == -EDEADLK) {
15091 drm_modeset_backoff(&ctx);
15092 goto retry;
15093 } else if (WARN_ON(ret)) {
15094 goto fail;
15095 }
15096
15097 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15098 if (WARN_ON(IS_ERR(state)))
15099 goto fail;
15100
15101 intel_state = to_intel_atomic_state(state);
15102
15103 /*
15104 * Hardware readout is the only time we don't want to calculate
15105 * intermediate watermarks (since we don't trust the current
15106 * watermarks).
15107 */
15108 if (!HAS_GMCH_DISPLAY(dev_priv))
15109 intel_state->skip_intermediate_wm = true;
15110
15111 ret = intel_atomic_check(dev, state);
15112 if (ret) {
15113 /*
15114 * If we fail here, it means that the hardware appears to be
15115 * programmed in a way that shouldn't be possible, given our
15116 * understanding of watermark requirements. This might mean a
15117 * mistake in the hardware readout code or a mistake in the
15118 * watermark calculations for a given platform. Raise a WARN
15119 * so that this is noticeable.
15120 *
15121 * If this actually happens, we'll have to just leave the
15122 * BIOS-programmed watermarks untouched and hope for the best.
15123 */
15124 WARN(true, "Could not determine valid watermarks for inherited state\n");
15125 goto put_state;
15126 }
15127
15128 /* Write calculated watermark values back */
15129 for_each_new_crtc_in_state(state, crtc, cstate, i) {
15130 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15131
15132 cs->wm.need_postvbl_update = true;
15133 dev_priv->display.optimize_watermarks(intel_state, cs);
15134
15135 to_intel_crtc_state(crtc->state)->wm = cs->wm;
15136 }
15137
15138 put_state:
15139 drm_atomic_state_put(state);
15140 fail:
15141 drm_modeset_drop_locks(&ctx);
15142 drm_modeset_acquire_fini(&ctx);
15143 }
15144
15145 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
15146 {
15147 if (IS_GEN5(dev_priv)) {
15148 u32 fdi_pll_clk =
15149 I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
15150
15151 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
15152 } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
15153 dev_priv->fdi_pll_freq = 270000;
15154 } else {
15155 return;
15156 }
15157
15158 DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
15159 }
15160
15161 int intel_modeset_init(struct drm_device *dev)
15162 {
15163 struct drm_i915_private *dev_priv = to_i915(dev);
15164 struct i915_ggtt *ggtt = &dev_priv->ggtt;
15165 enum pipe pipe;
15166 struct intel_crtc *crtc;
15167
15168 dev_priv->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
15169
15170 drm_mode_config_init(dev);
15171
15172 dev->mode_config.min_width = 0;
15173 dev->mode_config.min_height = 0;
15174
15175 dev->mode_config.preferred_depth = 24;
15176 dev->mode_config.prefer_shadow = 1;
15177
15178 dev->mode_config.allow_fb_modifiers = true;
15179
15180 dev->mode_config.funcs = &intel_mode_funcs;
15181
15182 init_llist_head(&dev_priv->atomic_helper.free_list);
15183 INIT_WORK(&dev_priv->atomic_helper.free_work,
15184 intel_atomic_helper_free_state_worker);
15185
15186 intel_init_quirks(dev);
15187
15188 intel_init_pm(dev_priv);
15189
15190 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15191 return 0;
15192
15193 /*
15194 * There may be no VBT; and if the BIOS enabled SSC we can
15195 * just keep using it to avoid unnecessary flicker. Whereas if the
15196 * BIOS isn't using it, don't assume it will work even if the VBT
15197 * indicates as much.
15198 */
15199 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
15200 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15201 DREF_SSC1_ENABLE);
15202
15203 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15204 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15205 bios_lvds_use_ssc ? "en" : "dis",
15206 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15207 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15208 }
15209 }
15210
15211 /* maximum framebuffer dimensions */
15212 if (IS_GEN2(dev_priv)) {
15213 dev->mode_config.max_width = 2048;
15214 dev->mode_config.max_height = 2048;
15215 } else if (IS_GEN3(dev_priv)) {
15216 dev->mode_config.max_width = 4096;
15217 dev->mode_config.max_height = 4096;
15218 } else {
15219 dev->mode_config.max_width = 8192;
15220 dev->mode_config.max_height = 8192;
15221 }
15222
15223 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15224 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
15225 dev->mode_config.cursor_height = 1023;
15226 } else if (IS_GEN2(dev_priv)) {
15227 dev->mode_config.cursor_width = 64;
15228 dev->mode_config.cursor_height = 64;
15229 } else {
15230 dev->mode_config.cursor_width = 256;
15231 dev->mode_config.cursor_height = 256;
15232 }
15233
15234 dev->mode_config.fb_base = ggtt->gmadr.start;
15235
15236 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15237 INTEL_INFO(dev_priv)->num_pipes,
15238 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
15239
15240 for_each_pipe(dev_priv, pipe) {
15241 int ret;
15242
15243 ret = intel_crtc_init(dev_priv, pipe);
15244 if (ret) {
15245 drm_mode_config_cleanup(dev);
15246 return ret;
15247 }
15248 }
15249
15250 intel_shared_dpll_init(dev);
15251 intel_update_fdi_pll_freq(dev_priv);
15252
15253 intel_update_czclk(dev_priv);
15254 intel_modeset_init_hw(dev);
15255
15256 if (dev_priv->max_cdclk_freq == 0)
15257 intel_update_max_cdclk(dev_priv);
15258
15259 /* Just disable it once at startup */
15260 i915_disable_vga(dev_priv);
15261 intel_setup_outputs(dev_priv);
15262
15263 drm_modeset_lock_all(dev);
15264 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
15265 drm_modeset_unlock_all(dev);
15266
15267 for_each_intel_crtc(dev, crtc) {
15268 struct intel_initial_plane_config plane_config = {};
15269
15270 if (!crtc->active)
15271 continue;
15272
15273 /*
15274 * Note that reserving the BIOS fb up front prevents us
15275 * from stuffing other stolen allocations like the ring
15276 * on top. This prevents some ugliness at boot time, and
15277 * can even allow for smooth boot transitions if the BIOS
15278 * fb is large enough for the active pipe configuration.
15279 */
15280 dev_priv->display.get_initial_plane_config(crtc,
15281 &plane_config);
15282
15283 /*
15284 * If the fb is shared between multiple heads, we'll
15285 * just get the first one.
15286 */
15287 intel_find_initial_plane_obj(crtc, &plane_config);
15288 }
15289
15290 /*
15291 * Make sure hardware watermarks really match the state we read out.
15292 * Note that we need to do this after reconstructing the BIOS fb's
15293 * since the watermark calculation done here will use pstate->fb.
15294 */
15295 if (!HAS_GMCH_DISPLAY(dev_priv))
15296 sanitize_watermarks(dev);
15297
15298 return 0;
15299 }
15300
15301 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15302 {
15303 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15304 /* 640x480@60Hz, ~25175 kHz */
15305 struct dpll clock = {
15306 .m1 = 18,
15307 .m2 = 7,
15308 .p1 = 13,
15309 .p2 = 4,
15310 .n = 2,
15311 };
15312 u32 dpll, fp;
15313 int i;
15314
15315 WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
15316
15317 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
15318 pipe_name(pipe), clock.vco, clock.dot);
15319
15320 fp = i9xx_dpll_compute_fp(&clock);
15321 dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
15322 DPLL_VGA_MODE_DIS |
15323 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
15324 PLL_P2_DIVIDE_BY_4 |
15325 PLL_REF_INPUT_DREFCLK |
15326 DPLL_VCO_ENABLE;
15327
15328 I915_WRITE(FP0(pipe), fp);
15329 I915_WRITE(FP1(pipe), fp);
15330
15331 I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
15332 I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
15333 I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
15334 I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
15335 I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
15336 I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
15337 I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
15338
15339 /*
15340 * Apparently we need to have VGA mode enabled prior to changing
15341 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
15342 * dividers, even though the register value does change.
15343 */
15344 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
15345 I915_WRITE(DPLL(pipe), dpll);
15346
15347 /* Wait for the clocks to stabilize. */
15348 POSTING_READ(DPLL(pipe));
15349 udelay(150);
15350
15351 /* The pixel multiplier can only be updated once the
15352 * DPLL is enabled and the clocks are stable.
15353 *
15354 * So write it again.
15355 */
15356 I915_WRITE(DPLL(pipe), dpll);
15357
15358 /* We do this three times for luck */
15359 for (i = 0; i < 3 ; i++) {
15360 I915_WRITE(DPLL(pipe), dpll);
15361 POSTING_READ(DPLL(pipe));
15362 udelay(150); /* wait for warmup */
15363 }
15364
15365 I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
15366 POSTING_READ(PIPECONF(pipe));
15367
15368 intel_wait_for_pipe_scanline_moving(crtc);
15369 }
15370
15371 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15372 {
15373 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15374
15375 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
15376 pipe_name(pipe));
15377
15378 WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
15379 WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
15380 WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
15381 WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE);
15382 WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE);
15383
15384 I915_WRITE(PIPECONF(pipe), 0);
15385 POSTING_READ(PIPECONF(pipe));
15386
15387 intel_wait_for_pipe_scanline_stopped(crtc);
15388
15389 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
15390 POSTING_READ(DPLL(pipe));
15391 }
15392
15393 static void
15394 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
15395 {
15396 struct intel_crtc *crtc;
15397
15398 if (INTEL_GEN(dev_priv) >= 4)
15399 return;
15400
15401 for_each_intel_crtc(&dev_priv->drm, crtc) {
15402 struct intel_plane *plane =
15403 to_intel_plane(crtc->base.primary);
15404 struct intel_crtc *plane_crtc;
15405 enum pipe pipe;
15406
15407 if (!plane->get_hw_state(plane, &pipe))
15408 continue;
15409
15410 if (pipe == crtc->pipe)
15411 continue;
15412
15413 DRM_DEBUG_KMS("%s attached to the wrong pipe, disabling plane\n",
15414 plane->base.name);
15415
15416 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15417 intel_plane_disable_noatomic(plane_crtc, plane);
15418 }
15419 }
15420
15421 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15422 {
15423 struct drm_device *dev = crtc->base.dev;
15424 struct intel_encoder *encoder;
15425
15426 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15427 return true;
15428
15429 return false;
15430 }
15431
15432 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15433 {
15434 struct drm_device *dev = encoder->base.dev;
15435 struct intel_connector *connector;
15436
15437 for_each_connector_on_encoder(dev, &encoder->base, connector)
15438 return connector;
15439
15440 return NULL;
15441 }
15442
15443 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15444 enum pipe pch_transcoder)
15445 {
15446 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15447 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
15448 }
15449
15450 static void intel_sanitize_crtc(struct intel_crtc *crtc,
15451 struct drm_modeset_acquire_ctx *ctx)
15452 {
15453 struct drm_device *dev = crtc->base.dev;
15454 struct drm_i915_private *dev_priv = to_i915(dev);
15455 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15456
15457 /* Clear any frame start delays used for debugging left by the BIOS */
15458 if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) {
15459 i915_reg_t reg = PIPECONF(cpu_transcoder);
15460
15461 I915_WRITE(reg,
15462 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15463 }
15464
15465 if (crtc->active) {
15466 struct intel_plane *plane;
15467
15468 /* Disable everything but the primary plane */
15469 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15470 const struct intel_plane_state *plane_state =
15471 to_intel_plane_state(plane->base.state);
15472
15473 if (plane_state->base.visible &&
15474 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
15475 intel_plane_disable_noatomic(crtc, plane);
15476 }
15477 }
15478
15479 /* Adjust the state of the output pipe according to whether we
15480 * have active connectors/encoders. */
15481 if (crtc->active && !intel_crtc_has_encoders(crtc))
15482 intel_crtc_disable_noatomic(&crtc->base, ctx);
15483
15484 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
15485 /*
15486 * We start out with underrun reporting disabled to avoid races.
15487 * For correct bookkeeping mark this on active crtcs.
15488 *
15489 * Also on gmch platforms we dont have any hardware bits to
15490 * disable the underrun reporting. Which means we need to start
15491 * out with underrun reporting disabled also on inactive pipes,
15492 * since otherwise we'll complain about the garbage we read when
15493 * e.g. coming up after runtime pm.
15494 *
15495 * No protection against concurrent access is required - at
15496 * worst a fifo underrun happens which also sets this to false.
15497 */
15498 crtc->cpu_fifo_underrun_disabled = true;
15499 /*
15500 * We track the PCH trancoder underrun reporting state
15501 * within the crtc. With crtc for pipe A housing the underrun
15502 * reporting state for PCH transcoder A, crtc for pipe B housing
15503 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15504 * and marking underrun reporting as disabled for the non-existing
15505 * PCH transcoders B and C would prevent enabling the south
15506 * error interrupt (see cpt_can_enable_serr_int()).
15507 */
15508 if (has_pch_trancoder(dev_priv, crtc->pipe))
15509 crtc->pch_fifo_underrun_disabled = true;
15510 }
15511 }
15512
15513 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15514 {
15515 struct intel_connector *connector;
15516
15517 /* We need to check both for a crtc link (meaning that the
15518 * encoder is active and trying to read from a pipe) and the
15519 * pipe itself being active. */
15520 bool has_active_crtc = encoder->base.crtc &&
15521 to_intel_crtc(encoder->base.crtc)->active;
15522
15523 connector = intel_encoder_find_connector(encoder);
15524 if (connector && !has_active_crtc) {
15525 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15526 encoder->base.base.id,
15527 encoder->base.name);
15528
15529 /* Connector is active, but has no active pipe. This is
15530 * fallout from our resume register restoring. Disable
15531 * the encoder manually again. */
15532 if (encoder->base.crtc) {
15533 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
15534
15535 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15536 encoder->base.base.id,
15537 encoder->base.name);
15538 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15539 if (encoder->post_disable)
15540 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15541 }
15542 encoder->base.crtc = NULL;
15543
15544 /* Inconsistent output/port/pipe state happens presumably due to
15545 * a bug in one of the get_hw_state functions. Or someplace else
15546 * in our code, like the register restore mess on resume. Clamp
15547 * things to off as a safer default. */
15548
15549 connector->base.dpms = DRM_MODE_DPMS_OFF;
15550 connector->base.encoder = NULL;
15551 }
15552
15553 /* notify opregion of the sanitized encoder state */
15554 intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
15555 }
15556
15557 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15558 {
15559 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15560
15561 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15562 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15563 i915_disable_vga(dev_priv);
15564 }
15565 }
15566
15567 void i915_redisable_vga(struct drm_i915_private *dev_priv)
15568 {
15569 /* This function can be called both from intel_modeset_setup_hw_state or
15570 * at a very early point in our resume sequence, where the power well
15571 * structures are not yet restored. Since this function is at a very
15572 * paranoid "someone might have enabled VGA while we were not looking"
15573 * level, just check if the power well is enabled instead of trying to
15574 * follow the "don't touch the power well if we don't need it" policy
15575 * the rest of the driver uses. */
15576 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15577 return;
15578
15579 i915_redisable_vga_power_on(dev_priv);
15580
15581 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15582 }
15583
15584 /* FIXME read out full plane state for all planes */
15585 static void readout_plane_state(struct drm_i915_private *dev_priv)
15586 {
15587 struct intel_plane *plane;
15588 struct intel_crtc *crtc;
15589
15590 for_each_intel_plane(&dev_priv->drm, plane) {
15591 struct intel_plane_state *plane_state =
15592 to_intel_plane_state(plane->base.state);
15593 struct intel_crtc_state *crtc_state;
15594 enum pipe pipe = PIPE_A;
15595 bool visible;
15596
15597 visible = plane->get_hw_state(plane, &pipe);
15598
15599 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15600 crtc_state = to_intel_crtc_state(crtc->base.state);
15601
15602 intel_set_plane_visible(crtc_state, plane_state, visible);
15603 }
15604
15605 for_each_intel_crtc(&dev_priv->drm, crtc) {
15606 struct intel_crtc_state *crtc_state =
15607 to_intel_crtc_state(crtc->base.state);
15608
15609 fixup_active_planes(crtc_state);
15610 }
15611 }
15612
15613 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15614 {
15615 struct drm_i915_private *dev_priv = to_i915(dev);
15616 enum pipe pipe;
15617 struct intel_crtc *crtc;
15618 struct intel_encoder *encoder;
15619 struct intel_connector *connector;
15620 struct drm_connector_list_iter conn_iter;
15621 int i;
15622
15623 dev_priv->active_crtcs = 0;
15624
15625 for_each_intel_crtc(dev, crtc) {
15626 struct intel_crtc_state *crtc_state =
15627 to_intel_crtc_state(crtc->base.state);
15628
15629 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15630 memset(crtc_state, 0, sizeof(*crtc_state));
15631 crtc_state->base.crtc = &crtc->base;
15632
15633 crtc_state->base.active = crtc_state->base.enable =
15634 dev_priv->display.get_pipe_config(crtc, crtc_state);
15635
15636 crtc->base.enabled = crtc_state->base.enable;
15637 crtc->active = crtc_state->base.active;
15638
15639 if (crtc_state->base.active)
15640 dev_priv->active_crtcs |= 1 << crtc->pipe;
15641
15642 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15643 crtc->base.base.id, crtc->base.name,
15644 enableddisabled(crtc_state->base.active));
15645 }
15646
15647 readout_plane_state(dev_priv);
15648
15649 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15650 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15651
15652 pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
15653 &pll->state.hw_state);
15654 pll->state.crtc_mask = 0;
15655 for_each_intel_crtc(dev, crtc) {
15656 struct intel_crtc_state *crtc_state =
15657 to_intel_crtc_state(crtc->base.state);
15658
15659 if (crtc_state->base.active &&
15660 crtc_state->shared_dpll == pll)
15661 pll->state.crtc_mask |= 1 << crtc->pipe;
15662 }
15663 pll->active_mask = pll->state.crtc_mask;
15664
15665 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15666 pll->info->name, pll->state.crtc_mask, pll->on);
15667 }
15668
15669 for_each_intel_encoder(dev, encoder) {
15670 pipe = 0;
15671
15672 if (encoder->get_hw_state(encoder, &pipe)) {
15673 struct intel_crtc_state *crtc_state;
15674
15675 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15676 crtc_state = to_intel_crtc_state(crtc->base.state);
15677
15678 encoder->base.crtc = &crtc->base;
15679 encoder->get_config(encoder, crtc_state);
15680 } else {
15681 encoder->base.crtc = NULL;
15682 }
15683
15684 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15685 encoder->base.base.id, encoder->base.name,
15686 enableddisabled(encoder->base.crtc),
15687 pipe_name(pipe));
15688 }
15689
15690 drm_connector_list_iter_begin(dev, &conn_iter);
15691 for_each_intel_connector_iter(connector, &conn_iter) {
15692 if (connector->get_hw_state(connector)) {
15693 connector->base.dpms = DRM_MODE_DPMS_ON;
15694
15695 encoder = connector->encoder;
15696 connector->base.encoder = &encoder->base;
15697
15698 if (encoder->base.crtc &&
15699 encoder->base.crtc->state->active) {
15700 /*
15701 * This has to be done during hardware readout
15702 * because anything calling .crtc_disable may
15703 * rely on the connector_mask being accurate.
15704 */
15705 encoder->base.crtc->state->connector_mask |=
15706 drm_connector_mask(&connector->base);
15707 encoder->base.crtc->state->encoder_mask |=
15708 drm_encoder_mask(&encoder->base);
15709 }
15710
15711 } else {
15712 connector->base.dpms = DRM_MODE_DPMS_OFF;
15713 connector->base.encoder = NULL;
15714 }
15715 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15716 connector->base.base.id, connector->base.name,
15717 enableddisabled(connector->base.encoder));
15718 }
15719 drm_connector_list_iter_end(&conn_iter);
15720
15721 for_each_intel_crtc(dev, crtc) {
15722 struct intel_crtc_state *crtc_state =
15723 to_intel_crtc_state(crtc->base.state);
15724 int min_cdclk = 0;
15725
15726 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15727 if (crtc_state->base.active) {
15728 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15729 crtc->base.mode.hdisplay = crtc_state->pipe_src_w;
15730 crtc->base.mode.vdisplay = crtc_state->pipe_src_h;
15731 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15732 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15733
15734 /*
15735 * The initial mode needs to be set in order to keep
15736 * the atomic core happy. It wants a valid mode if the
15737 * crtc's enabled, so we do the above call.
15738 *
15739 * But we don't set all the derived state fully, hence
15740 * set a flag to indicate that a full recalculation is
15741 * needed on the next commit.
15742 */
15743 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15744
15745 intel_crtc_compute_pixel_rate(crtc_state);
15746
15747 if (dev_priv->display.modeset_calc_cdclk) {
15748 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
15749 if (WARN_ON(min_cdclk < 0))
15750 min_cdclk = 0;
15751 }
15752
15753 drm_calc_timestamping_constants(&crtc->base,
15754 &crtc_state->base.adjusted_mode);
15755 update_scanline_offset(crtc);
15756 }
15757
15758 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
15759 dev_priv->min_voltage_level[crtc->pipe] =
15760 crtc_state->min_voltage_level;
15761
15762 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15763 }
15764 }
15765
15766 static void
15767 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15768 {
15769 struct intel_encoder *encoder;
15770
15771 for_each_intel_encoder(&dev_priv->drm, encoder) {
15772 u64 get_domains;
15773 enum intel_display_power_domain domain;
15774 struct intel_crtc_state *crtc_state;
15775
15776 if (!encoder->get_power_domains)
15777 continue;
15778
15779 /*
15780 * MST-primary and inactive encoders don't have a crtc state
15781 * and neither of these require any power domain references.
15782 */
15783 if (!encoder->base.crtc)
15784 continue;
15785
15786 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
15787 get_domains = encoder->get_power_domains(encoder, crtc_state);
15788 for_each_power_domain(domain, get_domains)
15789 intel_display_power_get(dev_priv, domain);
15790 }
15791 }
15792
15793 static void intel_early_display_was(struct drm_i915_private *dev_priv)
15794 {
15795 /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
15796 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
15797 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
15798 DARBF_GATING_DIS);
15799
15800 if (IS_HASWELL(dev_priv)) {
15801 /*
15802 * WaRsPkgCStateDisplayPMReq:hsw
15803 * System hang if this isn't done before disabling all planes!
15804 */
15805 I915_WRITE(CHICKEN_PAR1_1,
15806 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
15807 }
15808 }
15809
15810 /* Scan out the current hw modeset state,
15811 * and sanitizes it to the current state
15812 */
15813 static void
15814 intel_modeset_setup_hw_state(struct drm_device *dev,
15815 struct drm_modeset_acquire_ctx *ctx)
15816 {
15817 struct drm_i915_private *dev_priv = to_i915(dev);
15818 struct intel_crtc *crtc;
15819 struct intel_encoder *encoder;
15820 int i;
15821
15822 intel_early_display_was(dev_priv);
15823 intel_modeset_readout_hw_state(dev);
15824
15825 /* HW state is read out, now we need to sanitize this mess. */
15826 get_encoder_power_domains(dev_priv);
15827
15828 /*
15829 * intel_sanitize_plane_mapping() may need to do vblank
15830 * waits, so we need vblank interrupts restored beforehand.
15831 */
15832 for_each_intel_crtc(&dev_priv->drm, crtc) {
15833 drm_crtc_vblank_reset(&crtc->base);
15834
15835 if (crtc->active)
15836 drm_crtc_vblank_on(&crtc->base);
15837 }
15838
15839 intel_sanitize_plane_mapping(dev_priv);
15840
15841 for_each_intel_encoder(dev, encoder)
15842 intel_sanitize_encoder(encoder);
15843
15844 for_each_intel_crtc(&dev_priv->drm, crtc) {
15845 intel_sanitize_crtc(crtc, ctx);
15846 intel_dump_pipe_config(crtc, crtc->config,
15847 "[setup_hw_state]");
15848 }
15849
15850 intel_modeset_update_connector_atomic_state(dev);
15851
15852 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15853 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15854
15855 if (!pll->on || pll->active_mask)
15856 continue;
15857
15858 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n",
15859 pll->info->name);
15860
15861 pll->info->funcs->disable(dev_priv, pll);
15862 pll->on = false;
15863 }
15864
15865 if (IS_G4X(dev_priv)) {
15866 g4x_wm_get_hw_state(dev);
15867 g4x_wm_sanitize(dev_priv);
15868 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15869 vlv_wm_get_hw_state(dev);
15870 vlv_wm_sanitize(dev_priv);
15871 } else if (INTEL_GEN(dev_priv) >= 9) {
15872 skl_wm_get_hw_state(dev);
15873 } else if (HAS_PCH_SPLIT(dev_priv)) {
15874 ilk_wm_get_hw_state(dev);
15875 }
15876
15877 for_each_intel_crtc(dev, crtc) {
15878 u64 put_domains;
15879
15880 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15881 if (WARN_ON(put_domains))
15882 modeset_put_power_domains(dev_priv, put_domains);
15883 }
15884 intel_display_set_init_power(dev_priv, false);
15885
15886 intel_power_domains_verify_state(dev_priv);
15887
15888 intel_fbc_init_pipe_state(dev_priv);
15889 }
15890
15891 void intel_display_resume(struct drm_device *dev)
15892 {
15893 struct drm_i915_private *dev_priv = to_i915(dev);
15894 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15895 struct drm_modeset_acquire_ctx ctx;
15896 int ret;
15897
15898 dev_priv->modeset_restore_state = NULL;
15899 if (state)
15900 state->acquire_ctx = &ctx;
15901
15902 drm_modeset_acquire_init(&ctx, 0);
15903
15904 while (1) {
15905 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15906 if (ret != -EDEADLK)
15907 break;
15908
15909 drm_modeset_backoff(&ctx);
15910 }
15911
15912 if (!ret)
15913 ret = __intel_display_resume(dev, state, &ctx);
15914
15915 intel_enable_ipc(dev_priv);
15916 drm_modeset_drop_locks(&ctx);
15917 drm_modeset_acquire_fini(&ctx);
15918
15919 if (ret)
15920 DRM_ERROR("Restoring old state failed with %i\n", ret);
15921 if (state)
15922 drm_atomic_state_put(state);
15923 }
15924
15925 int intel_connector_register(struct drm_connector *connector)
15926 {
15927 struct intel_connector *intel_connector = to_intel_connector(connector);
15928 int ret;
15929
15930 ret = intel_backlight_device_register(intel_connector);
15931 if (ret)
15932 goto err;
15933
15934 return 0;
15935
15936 err:
15937 return ret;
15938 }
15939
15940 void intel_connector_unregister(struct drm_connector *connector)
15941 {
15942 struct intel_connector *intel_connector = to_intel_connector(connector);
15943
15944 intel_backlight_device_unregister(intel_connector);
15945 intel_panel_destroy_backlight(connector);
15946 }
15947
15948 static void intel_hpd_poll_fini(struct drm_device *dev)
15949 {
15950 struct intel_connector *connector;
15951 struct drm_connector_list_iter conn_iter;
15952
15953 /* Kill all the work that may have been queued by hpd. */
15954 drm_connector_list_iter_begin(dev, &conn_iter);
15955 for_each_intel_connector_iter(connector, &conn_iter) {
15956 if (connector->modeset_retry_work.func)
15957 cancel_work_sync(&connector->modeset_retry_work);
15958 if (connector->hdcp_shim) {
15959 cancel_delayed_work_sync(&connector->hdcp_check_work);
15960 cancel_work_sync(&connector->hdcp_prop_work);
15961 }
15962 }
15963 drm_connector_list_iter_end(&conn_iter);
15964 }
15965
15966 void intel_modeset_cleanup(struct drm_device *dev)
15967 {
15968 struct drm_i915_private *dev_priv = to_i915(dev);
15969
15970 flush_workqueue(dev_priv->modeset_wq);
15971
15972 flush_work(&dev_priv->atomic_helper.free_work);
15973 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15974
15975 /*
15976 * Interrupts and polling as the first thing to avoid creating havoc.
15977 * Too much stuff here (turning of connectors, ...) would
15978 * experience fancy races otherwise.
15979 */
15980 intel_irq_uninstall(dev_priv);
15981
15982 /*
15983 * Due to the hpd irq storm handling the hotplug work can re-arm the
15984 * poll handlers. Hence disable polling after hpd handling is shut down.
15985 */
15986 intel_hpd_poll_fini(dev);
15987
15988 /* poll work can call into fbdev, hence clean that up afterwards */
15989 intel_fbdev_fini(dev_priv);
15990
15991 intel_unregister_dsm_handler();
15992
15993 intel_fbc_global_disable(dev_priv);
15994
15995 /* flush any delayed tasks or pending work */
15996 flush_scheduled_work();
15997
15998 drm_mode_config_cleanup(dev);
15999
16000 intel_cleanup_overlay(dev_priv);
16001
16002 intel_teardown_gmbus(dev_priv);
16003
16004 destroy_workqueue(dev_priv->modeset_wq);
16005 }
16006
16007 void intel_connector_attach_encoder(struct intel_connector *connector,
16008 struct intel_encoder *encoder)
16009 {
16010 connector->encoder = encoder;
16011 drm_connector_attach_encoder(&connector->base, &encoder->base);
16012 }
16013
16014 /*
16015 * set vga decode state - true == enable VGA decode
16016 */
16017 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
16018 {
16019 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16020 u16 gmch_ctrl;
16021
16022 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16023 DRM_ERROR("failed to read control word\n");
16024 return -EIO;
16025 }
16026
16027 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16028 return 0;
16029
16030 if (state)
16031 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16032 else
16033 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16034
16035 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16036 DRM_ERROR("failed to write control word\n");
16037 return -EIO;
16038 }
16039
16040 return 0;
16041 }
16042
16043 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
16044
16045 struct intel_display_error_state {
16046
16047 u32 power_well_driver;
16048
16049 int num_transcoders;
16050
16051 struct intel_cursor_error_state {
16052 u32 control;
16053 u32 position;
16054 u32 base;
16055 u32 size;
16056 } cursor[I915_MAX_PIPES];
16057
16058 struct intel_pipe_error_state {
16059 bool power_domain_on;
16060 u32 source;
16061 u32 stat;
16062 } pipe[I915_MAX_PIPES];
16063
16064 struct intel_plane_error_state {
16065 u32 control;
16066 u32 stride;
16067 u32 size;
16068 u32 pos;
16069 u32 addr;
16070 u32 surface;
16071 u32 tile_offset;
16072 } plane[I915_MAX_PIPES];
16073
16074 struct intel_transcoder_error_state {
16075 bool power_domain_on;
16076 enum transcoder cpu_transcoder;
16077
16078 u32 conf;
16079
16080 u32 htotal;
16081 u32 hblank;
16082 u32 hsync;
16083 u32 vtotal;
16084 u32 vblank;
16085 u32 vsync;
16086 } transcoder[4];
16087 };
16088
16089 struct intel_display_error_state *
16090 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16091 {
16092 struct intel_display_error_state *error;
16093 int transcoders[] = {
16094 TRANSCODER_A,
16095 TRANSCODER_B,
16096 TRANSCODER_C,
16097 TRANSCODER_EDP,
16098 };
16099 int i;
16100
16101 if (INTEL_INFO(dev_priv)->num_pipes == 0)
16102 return NULL;
16103
16104 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16105 if (error == NULL)
16106 return NULL;
16107
16108 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16109 error->power_well_driver =
16110 I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL));
16111
16112 for_each_pipe(dev_priv, i) {
16113 error->pipe[i].power_domain_on =
16114 __intel_display_power_is_enabled(dev_priv,
16115 POWER_DOMAIN_PIPE(i));
16116 if (!error->pipe[i].power_domain_on)
16117 continue;
16118
16119 error->cursor[i].control = I915_READ(CURCNTR(i));
16120 error->cursor[i].position = I915_READ(CURPOS(i));
16121 error->cursor[i].base = I915_READ(CURBASE(i));
16122
16123 error->plane[i].control = I915_READ(DSPCNTR(i));
16124 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16125 if (INTEL_GEN(dev_priv) <= 3) {
16126 error->plane[i].size = I915_READ(DSPSIZE(i));
16127 error->plane[i].pos = I915_READ(DSPPOS(i));
16128 }
16129 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16130 error->plane[i].addr = I915_READ(DSPADDR(i));
16131 if (INTEL_GEN(dev_priv) >= 4) {
16132 error->plane[i].surface = I915_READ(DSPSURF(i));
16133 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16134 }
16135
16136 error->pipe[i].source = I915_READ(PIPESRC(i));
16137
16138 if (HAS_GMCH_DISPLAY(dev_priv))
16139 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16140 }
16141
16142 /* Note: this does not include DSI transcoders. */
16143 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
16144 if (HAS_DDI(dev_priv))
16145 error->num_transcoders++; /* Account for eDP. */
16146
16147 for (i = 0; i < error->num_transcoders; i++) {
16148 enum transcoder cpu_transcoder = transcoders[i];
16149
16150 error->transcoder[i].power_domain_on =
16151 __intel_display_power_is_enabled(dev_priv,
16152 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16153 if (!error->transcoder[i].power_domain_on)
16154 continue;
16155
16156 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16157
16158 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16159 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16160 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16161 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16162 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16163 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16164 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16165 }
16166
16167 return error;
16168 }
16169
16170 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16171
16172 void
16173 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16174 struct intel_display_error_state *error)
16175 {
16176 struct drm_i915_private *dev_priv = m->i915;
16177 int i;
16178
16179 if (!error)
16180 return;
16181
16182 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
16183 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16184 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16185 error->power_well_driver);
16186 for_each_pipe(dev_priv, i) {
16187 err_printf(m, "Pipe [%d]:\n", i);
16188 err_printf(m, " Power: %s\n",
16189 onoff(error->pipe[i].power_domain_on));
16190 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16191 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16192
16193 err_printf(m, "Plane [%d]:\n", i);
16194 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16195 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16196 if (INTEL_GEN(dev_priv) <= 3) {
16197 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16198 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16199 }
16200 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16201 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16202 if (INTEL_GEN(dev_priv) >= 4) {
16203 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16204 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16205 }
16206
16207 err_printf(m, "Cursor [%d]:\n", i);
16208 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16209 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16210 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16211 }
16212
16213 for (i = 0; i < error->num_transcoders; i++) {
16214 err_printf(m, "CPU transcoder: %s\n",
16215 transcoder_name(error->transcoder[i].cpu_transcoder));
16216 err_printf(m, " Power: %s\n",
16217 onoff(error->transcoder[i].power_domain_on));
16218 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16219 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16220 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16221 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16222 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16223 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16224 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16225 }
16226 }
16227
16228 #endif
Linux with added FPC-III support