drivers/i2c/busses/i2c-pnx.c

   1 /*
   2  * Provides I2C support for Philips PNX010x/PNX4008 boards.
   3  *
   4  * Authors: Dennis Kovalev <dkovalev@ru.mvista.com>
   5  *          Vitaly Wool <vwool@ru.mvista.com>
   6  *
   7  * 2004-2006 (c) MontaVista Software, Inc. This file is licensed under
   8  * the terms of the GNU General Public License version 2. This program
   9  * is licensed "as is" without any warranty of any kind, whether express
  10  * or implied.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/ioport.h>
  16 #include <linux/delay.h>
  17 #include <linux/i2c.h>
  18 #include <linux/timer.h>
  19 #include <linux/completion.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/io.h>
  22 #include <linux/err.h>
  23 #include <linux/clk.h>
  24 #include <linux/slab.h>
  25 #include <linux/of.h>
  26
  27 #define I2C_PNX_TIMEOUT_DEFAULT         10 /* msec */
  28 #define I2C_PNX_SPEED_KHZ_DEFAULT       100
  29 #define I2C_PNX_REGION_SIZE             0x100
  30
  31 struct i2c_pnx_mif {
  32         int                     ret;            /* Return value */
  33         int                     mode;           /* Interface mode */
  34         struct completion       complete;       /* I/O completion */
  35         struct timer_list       timer;          /* Timeout */
  36         u8 *                    buf;            /* Data buffer */
  37         int                     len;            /* Length of data buffer */
  38         int                     order;          /* RX Bytes to order via TX */
  39 };
  40
  41 struct i2c_pnx_algo_data {
  42         void __iomem            *ioaddr;
  43         struct i2c_pnx_mif      mif;
  44         int                     last;
  45         struct clk              *clk;
  46         struct i2c_adapter      adapter;
  47         int                     irq;
  48         u32                     timeout;
  49 };
  50
  51 enum {
  52         mstatus_tdi = 0x00000001,
  53         mstatus_afi = 0x00000002,
  54         mstatus_nai = 0x00000004,
  55         mstatus_drmi = 0x00000008,
  56         mstatus_active = 0x00000020,
  57         mstatus_scl = 0x00000040,
  58         mstatus_sda = 0x00000080,
  59         mstatus_rff = 0x00000100,
  60         mstatus_rfe = 0x00000200,
  61         mstatus_tff = 0x00000400,
  62         mstatus_tfe = 0x00000800,
  63 };
  64
  65 enum {
  66         mcntrl_tdie = 0x00000001,
  67         mcntrl_afie = 0x00000002,
  68         mcntrl_naie = 0x00000004,
  69         mcntrl_drmie = 0x00000008,
  70         mcntrl_drsie = 0x00000010,
  71         mcntrl_rffie = 0x00000020,
  72         mcntrl_daie = 0x00000040,
  73         mcntrl_tffie = 0x00000080,
  74         mcntrl_reset = 0x00000100,
  75         mcntrl_cdbmode = 0x00000400,
  76 };
  77
  78 enum {
  79         rw_bit = 1 << 0,
  80         start_bit = 1 << 8,
  81         stop_bit = 1 << 9,
  82 };
  83
  84 #define I2C_REG_RX(a)   ((a)->ioaddr)           /* Rx FIFO reg (RO) */
  85 #define I2C_REG_TX(a)   ((a)->ioaddr)           /* Tx FIFO reg (WO) */
  86 #define I2C_REG_STS(a)  ((a)->ioaddr + 0x04)    /* Status reg (RO) */
  87 #define I2C_REG_CTL(a)  ((a)->ioaddr + 0x08)    /* Ctl reg */
  88 #define I2C_REG_CKL(a)  ((a)->ioaddr + 0x0c)    /* Clock divider low */
  89 #define I2C_REG_CKH(a)  ((a)->ioaddr + 0x10)    /* Clock divider high */
  90 #define I2C_REG_ADR(a)  ((a)->ioaddr + 0x14)    /* I2C address */
  91 #define I2C_REG_RFL(a)  ((a)->ioaddr + 0x18)    /* Rx FIFO level (RO) */
  92 #define I2C_REG_TFL(a)  ((a)->ioaddr + 0x1c)    /* Tx FIFO level (RO) */
  93 #define I2C_REG_RXB(a)  ((a)->ioaddr + 0x20)    /* Num of bytes Rx-ed (RO) */
  94 #define I2C_REG_TXB(a)  ((a)->ioaddr + 0x24)    /* Num of bytes Tx-ed (RO) */
  95 #define I2C_REG_TXS(a)  ((a)->ioaddr + 0x28)    /* Tx slave FIFO (RO) */
  96 #define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c)    /* Tx slave FIFO level (RO) */
  97
  98 static inline int wait_timeout(struct i2c_pnx_algo_data *data)
  99 {
 100         long timeout = data->timeout;
 101         while (timeout > 0 &&
 102                         (ioread32(I2C_REG_STS(data)) & mstatus_active)) {
 103                 mdelay(1);
 104                 timeout--;
 105         }
 106         return (timeout <= 0);
 107 }
 108
 109 static inline int wait_reset(struct i2c_pnx_algo_data *data)
 110 {
 111         long timeout = data->timeout;
 112         while (timeout > 0 &&
 113                         (ioread32(I2C_REG_CTL(data)) & mcntrl_reset)) {
 114                 mdelay(1);
 115                 timeout--;
 116         }
 117         return (timeout <= 0);
 118 }
 119
 120 static inline void i2c_pnx_arm_timer(struct i2c_pnx_algo_data *alg_data)
 121 {
 122         struct timer_list *timer = &alg_data->mif.timer;
 123         unsigned long expires = msecs_to_jiffies(alg_data->timeout);
 124
 125         if (expires <= 1)
 126                 expires = 2;
 127
 128         del_timer_sync(timer);
 129
 130         dev_dbg(&alg_data->adapter.dev, "Timer armed at %lu plus %lu jiffies.\n",
 131                 jiffies, expires);
 132
 133         timer->expires = jiffies + expires;
 134
 135         add_timer(timer);
 136 }
 137
 138 /**
 139  * i2c_pnx_start - start a device
 140  * @slave_addr:         slave address
 141  * @adap:               pointer to adapter structure
 142  *
 143  * Generate a START signal in the desired mode.
 144  */
 145 static int i2c_pnx_start(unsigned char slave_addr,
 146         struct i2c_pnx_algo_data *alg_data)
 147 {
 148         dev_dbg(&alg_data->adapter.dev, "%s(): addr 0x%x mode %d\n", __func__,
 149                 slave_addr, alg_data->mif.mode);
 150
 151         /* Check for 7 bit slave addresses only */
 152         if (slave_addr & ~0x7f) {
 153                 dev_err(&alg_data->adapter.dev,
 154                         "%s: Invalid slave address %x. Only 7-bit addresses are supported\n",
 155                         alg_data->adapter.name, slave_addr);
 156                 return -EINVAL;
 157         }
 158
 159         /* First, make sure bus is idle */
 160         if (wait_timeout(alg_data)) {
 161                 /* Somebody else is monopolizing the bus */
 162                 dev_err(&alg_data->adapter.dev,
 163                         "%s: Bus busy. Slave addr = %02x, cntrl = %x, stat = %x\n",
 164                         alg_data->adapter.name, slave_addr,
 165                         ioread32(I2C_REG_CTL(alg_data)),
 166                         ioread32(I2C_REG_STS(alg_data)));
 167                 return -EBUSY;
 168         } else if (ioread32(I2C_REG_STS(alg_data)) & mstatus_afi) {
 169                 /* Sorry, we lost the bus */
 170                 dev_err(&alg_data->adapter.dev,
 171                         "%s: Arbitration failure. Slave addr = %02x\n",
 172                         alg_data->adapter.name, slave_addr);
 173                 return -EIO;
 174         }
 175
 176         /*
 177          * OK, I2C is enabled and we have the bus.
 178          * Clear the current TDI and AFI status flags.
 179          */
 180         iowrite32(ioread32(I2C_REG_STS(alg_data)) | mstatus_tdi | mstatus_afi,
 181                   I2C_REG_STS(alg_data));
 182
 183         dev_dbg(&alg_data->adapter.dev, "%s(): sending %#x\n", __func__,
 184                 (slave_addr << 1) | start_bit | alg_data->mif.mode);
 185
 186         /* Write the slave address, START bit and R/W bit */
 187         iowrite32((slave_addr << 1) | start_bit | alg_data->mif.mode,
 188                   I2C_REG_TX(alg_data));
 189
 190         dev_dbg(&alg_data->adapter.dev, "%s(): exit\n", __func__);
 191
 192         return 0;
 193 }
 194
 195 /**
 196  * i2c_pnx_stop - stop a device
 197  * @adap:               pointer to I2C adapter structure
 198  *
 199  * Generate a STOP signal to terminate the master transaction.
 200  */
 201 static void i2c_pnx_stop(struct i2c_pnx_algo_data *alg_data)
 202 {
 203         /* Only 1 msec max timeout due to interrupt context */
 204         long timeout = 1000;
 205
 206         dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
 207                 __func__, ioread32(I2C_REG_STS(alg_data)));
 208
 209         /* Write a STOP bit to TX FIFO */
 210         iowrite32(0xff | stop_bit, I2C_REG_TX(alg_data));
 211
 212         /* Wait until the STOP is seen. */
 213         while (timeout > 0 &&
 214                (ioread32(I2C_REG_STS(alg_data)) & mstatus_active)) {
 215                 /* may be called from interrupt context */
 216                 udelay(1);
 217                 timeout--;
 218         }
 219
 220         dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
 221                 __func__, ioread32(I2C_REG_STS(alg_data)));
 222 }
 223
 224 /**
 225  * i2c_pnx_master_xmit - transmit data to slave
 226  * @adap:               pointer to I2C adapter structure
 227  *
 228  * Sends one byte of data to the slave
 229  */
 230 static int i2c_pnx_master_xmit(struct i2c_pnx_algo_data *alg_data)
 231 {
 232         u32 val;
 233
 234         dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
 235                 __func__, ioread32(I2C_REG_STS(alg_data)));
 236
 237         if (alg_data->mif.len > 0) {
 238                 /* We still have something to talk about... */
 239                 val = *alg_data->mif.buf++;
 240
 241                 if (alg_data->mif.len == 1)
 242                         val |= stop_bit;
 243
 244                 alg_data->mif.len--;
 245                 iowrite32(val, I2C_REG_TX(alg_data));
 246
 247                 dev_dbg(&alg_data->adapter.dev, "%s(): xmit %#x [%d]\n",
 248                         __func__, val, alg_data->mif.len + 1);
 249
 250                 if (alg_data->mif.len == 0) {
 251                         if (alg_data->last) {
 252                                 /* Wait until the STOP is seen. */
 253                                 if (wait_timeout(alg_data))
 254                                         dev_err(&alg_data->adapter.dev,
 255                                                 "The bus is still active after timeout\n");
 256                         }
 257                         /* Disable master interrupts */
 258                         iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
 259                                 ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie),
 260                                   I2C_REG_CTL(alg_data));
 261
 262                         del_timer_sync(&alg_data->mif.timer);
 263
 264                         dev_dbg(&alg_data->adapter.dev,
 265                                 "%s(): Waking up xfer routine.\n",
 266                                 __func__);
 267
 268                         complete(&alg_data->mif.complete);
 269                 }
 270         } else if (alg_data->mif.len == 0) {
 271                 /* zero-sized transfer */
 272                 i2c_pnx_stop(alg_data);
 273
 274                 /* Disable master interrupts. */
 275                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
 276                         ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie),
 277                           I2C_REG_CTL(alg_data));
 278
 279                 /* Stop timer. */
 280                 del_timer_sync(&alg_data->mif.timer);
 281                 dev_dbg(&alg_data->adapter.dev,
 282                         "%s(): Waking up xfer routine after zero-xfer.\n",
 283                         __func__);
 284
 285                 complete(&alg_data->mif.complete);
 286         }
 287
 288         dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
 289                 __func__, ioread32(I2C_REG_STS(alg_data)));
 290
 291         return 0;
 292 }
 293
 294 /**
 295  * i2c_pnx_master_rcv - receive data from slave
 296  * @adap:               pointer to I2C adapter structure
 297  *
 298  * Reads one byte data from the slave
 299  */
 300 static int i2c_pnx_master_rcv(struct i2c_pnx_algo_data *alg_data)
 301 {
 302         unsigned int val = 0;
 303         u32 ctl = 0;
 304
 305         dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
 306                 __func__, ioread32(I2C_REG_STS(alg_data)));
 307
 308         /* Check, whether there is already data,
 309          * or we didn't 'ask' for it yet.
 310          */
 311         if (ioread32(I2C_REG_STS(alg_data)) & mstatus_rfe) {
 312                 /* 'Asking' is done asynchronously, e.g. dummy TX of several
 313                  * bytes is done before the first actual RX arrives in FIFO.
 314                  * Therefore, ordered bytes (via TX) are counted separately.
 315                  */
 316                 if (alg_data->mif.order) {
 317                         dev_dbg(&alg_data->adapter.dev,
 318                                 "%s(): Write dummy data to fill Rx-fifo...\n",
 319                                 __func__);
 320
 321                         if (alg_data->mif.order == 1) {
 322                                 /* Last byte, do not acknowledge next rcv. */
 323                                 val |= stop_bit;
 324
 325                                 /*
 326                                  * Enable interrupt RFDAIE (data in Rx fifo),
 327                                  * and disable DRMIE (need data for Tx)
 328                                  */
 329                                 ctl = ioread32(I2C_REG_CTL(alg_data));
 330                                 ctl |= mcntrl_rffie | mcntrl_daie;
 331                                 ctl &= ~mcntrl_drmie;
 332                                 iowrite32(ctl, I2C_REG_CTL(alg_data));
 333                         }
 334
 335                         /*
 336                          * Now we'll 'ask' for data:
 337                          * For each byte we want to receive, we must
 338                          * write a (dummy) byte to the Tx-FIFO.
 339                          */
 340                         iowrite32(val, I2C_REG_TX(alg_data));
 341                         alg_data->mif.order--;
 342                 }
 343                 return 0;
 344         }
 345
 346         /* Handle data. */
 347         if (alg_data->mif.len > 0) {
 348                 val = ioread32(I2C_REG_RX(alg_data));
 349                 *alg_data->mif.buf++ = (u8) (val & 0xff);
 350                 dev_dbg(&alg_data->adapter.dev, "%s(): rcv 0x%x [%d]\n",
 351                         __func__, val, alg_data->mif.len);
 352
 353                 alg_data->mif.len--;
 354                 if (alg_data->mif.len == 0) {
 355                         if (alg_data->last)
 356                                 /* Wait until the STOP is seen. */
 357                                 if (wait_timeout(alg_data))
 358                                         dev_err(&alg_data->adapter.dev,
 359                                                 "The bus is still active after timeout\n");
 360
 361                         /* Disable master interrupts */
 362                         ctl = ioread32(I2C_REG_CTL(alg_data));
 363                         ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
 364                                  mcntrl_drmie | mcntrl_daie);
 365                         iowrite32(ctl, I2C_REG_CTL(alg_data));
 366
 367                         /* Kill timer. */
 368                         del_timer_sync(&alg_data->mif.timer);
 369                         complete(&alg_data->mif.complete);
 370                 }
 371         }
 372
 373         dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
 374                 __func__, ioread32(I2C_REG_STS(alg_data)));
 375
 376         return 0;
 377 }
 378
 379 static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id)
 380 {
 381         struct i2c_pnx_algo_data *alg_data = dev_id;
 382         u32 stat, ctl;
 383
 384         dev_dbg(&alg_data->adapter.dev,
 385                 "%s(): mstat = %x mctrl = %x, mode = %d\n",
 386                 __func__,
 387                 ioread32(I2C_REG_STS(alg_data)),
 388                 ioread32(I2C_REG_CTL(alg_data)),
 389                 alg_data->mif.mode);
 390         stat = ioread32(I2C_REG_STS(alg_data));
 391
 392         /* let's see what kind of event this is */
 393         if (stat & mstatus_afi) {
 394                 /* We lost arbitration in the midst of a transfer */
 395                 alg_data->mif.ret = -EIO;
 396
 397                 /* Disable master interrupts. */
 398                 ctl = ioread32(I2C_REG_CTL(alg_data));
 399                 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
 400                          mcntrl_drmie);
 401                 iowrite32(ctl, I2C_REG_CTL(alg_data));
 402
 403                 /* Stop timer, to prevent timeout. */
 404                 del_timer_sync(&alg_data->mif.timer);
 405                 complete(&alg_data->mif.complete);
 406         } else if (stat & mstatus_nai) {
 407                 /* Slave did not acknowledge, generate a STOP */
 408                 dev_dbg(&alg_data->adapter.dev,
 409                         "%s(): Slave did not acknowledge, generating a STOP.\n",
 410                         __func__);
 411                 i2c_pnx_stop(alg_data);
 412
 413                 /* Disable master interrupts. */
 414                 ctl = ioread32(I2C_REG_CTL(alg_data));
 415                 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
 416                          mcntrl_drmie);
 417                 iowrite32(ctl, I2C_REG_CTL(alg_data));
 418
 419                 /* Our return value. */
 420                 alg_data->mif.ret = -EIO;
 421
 422                 /* Stop timer, to prevent timeout. */
 423                 del_timer_sync(&alg_data->mif.timer);
 424                 complete(&alg_data->mif.complete);
 425         } else {
 426                 /*
 427                  * Two options:
 428                  * - Master Tx needs data.
 429                  * - There is data in the Rx-fifo
 430                  * The latter is only the case if we have requested for data,
 431                  * via a dummy write. (See 'i2c_pnx_master_rcv'.)
 432                  * We therefore check, as a sanity check, whether that interrupt
 433                  * has been enabled.
 434                  */
 435                 if ((stat & mstatus_drmi) || !(stat & mstatus_rfe)) {
 436                         if (alg_data->mif.mode == I2C_SMBUS_WRITE) {
 437                                 i2c_pnx_master_xmit(alg_data);
 438                         } else if (alg_data->mif.mode == I2C_SMBUS_READ) {
 439                                 i2c_pnx_master_rcv(alg_data);
 440                         }
 441                 }
 442         }
 443
 444         /* Clear TDI and AFI bits */
 445         stat = ioread32(I2C_REG_STS(alg_data));
 446         iowrite32(stat | mstatus_tdi | mstatus_afi, I2C_REG_STS(alg_data));
 447
 448         dev_dbg(&alg_data->adapter.dev,
 449                 "%s(): exiting, stat = %x ctrl = %x.\n",
 450                  __func__, ioread32(I2C_REG_STS(alg_data)),
 451                  ioread32(I2C_REG_CTL(alg_data)));
 452
 453         return IRQ_HANDLED;
 454 }
 455
 456 static void i2c_pnx_timeout(struct timer_list *t)
 457 {
 458         struct i2c_pnx_algo_data *alg_data = from_timer(alg_data, t, mif.timer);
 459         u32 ctl;
 460
 461         dev_err(&alg_data->adapter.dev,
 462                 "Master timed out. stat = %04x, cntrl = %04x. Resetting master...\n",
 463                 ioread32(I2C_REG_STS(alg_data)),
 464                 ioread32(I2C_REG_CTL(alg_data)));
 465
 466         /* Reset master and disable interrupts */
 467         ctl = ioread32(I2C_REG_CTL(alg_data));
 468         ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | mcntrl_drmie);
 469         iowrite32(ctl, I2C_REG_CTL(alg_data));
 470
 471         ctl |= mcntrl_reset;
 472         iowrite32(ctl, I2C_REG_CTL(alg_data));
 473         wait_reset(alg_data);
 474         alg_data->mif.ret = -EIO;
 475         complete(&alg_data->mif.complete);
 476 }
 477
 478 static inline void bus_reset_if_active(struct i2c_pnx_algo_data *alg_data)
 479 {
 480         u32 stat;
 481
 482         if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_active) {
 483                 dev_err(&alg_data->adapter.dev,
 484                         "%s: Bus is still active after xfer. Reset it...\n",
 485                         alg_data->adapter.name);
 486                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
 487                           I2C_REG_CTL(alg_data));
 488                 wait_reset(alg_data);
 489         } else if (!(stat & mstatus_rfe) || !(stat & mstatus_tfe)) {
 490                 /* If there is data in the fifo's after transfer,
 491                  * flush fifo's by reset.
 492                  */
 493                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
 494                           I2C_REG_CTL(alg_data));
 495                 wait_reset(alg_data);
 496         } else if (stat & mstatus_nai) {
 497                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
 498                           I2C_REG_CTL(alg_data));
 499                 wait_reset(alg_data);
 500         }
 501 }
 502
 503 /**
 504  * i2c_pnx_xfer - generic transfer entry point
 505  * @adap:               pointer to I2C adapter structure
 506  * @msgs:               array of messages
 507  * @num:                number of messages
 508  *
 509  * Initiates the transfer
 510  */
 511 static int
 512 i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 513 {
 514         struct i2c_msg *pmsg;
 515         int rc = 0, completed = 0, i;
 516         struct i2c_pnx_algo_data *alg_data = adap->algo_data;
 517         u32 stat;
 518
 519         dev_dbg(&alg_data->adapter.dev,
 520                 "%s(): entering: %d messages, stat = %04x.\n",
 521                 __func__, num, ioread32(I2C_REG_STS(alg_data)));
 522
 523         bus_reset_if_active(alg_data);
 524
 525         /* Process transactions in a loop. */
 526         for (i = 0; rc >= 0 && i < num; i++) {
 527                 u8 addr;
 528
 529                 pmsg = &msgs[i];
 530                 addr = pmsg->addr;
 531
 532                 if (pmsg->flags & I2C_M_TEN) {
 533                         dev_err(&alg_data->adapter.dev,
 534                                 "%s: 10 bits addr not supported!\n",
 535                                 alg_data->adapter.name);
 536                         rc = -EINVAL;
 537                         break;
 538                 }
 539
 540                 alg_data->mif.buf = pmsg->buf;
 541                 alg_data->mif.len = pmsg->len;
 542                 alg_data->mif.order = pmsg->len;
 543                 alg_data->mif.mode = (pmsg->flags & I2C_M_RD) ?
 544                         I2C_SMBUS_READ : I2C_SMBUS_WRITE;
 545                 alg_data->mif.ret = 0;
 546                 alg_data->last = (i == num - 1);
 547
 548                 dev_dbg(&alg_data->adapter.dev, "%s(): mode %d, %d bytes\n",
 549                         __func__, alg_data->mif.mode, alg_data->mif.len);
 550
 551                 i2c_pnx_arm_timer(alg_data);
 552
 553                 /* initialize the completion var */
 554                 init_completion(&alg_data->mif.complete);
 555
 556                 /* Enable master interrupt */
 557                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_afie |
 558                                 mcntrl_naie | mcntrl_drmie,
 559                           I2C_REG_CTL(alg_data));
 560
 561                 /* Put start-code and slave-address on the bus. */
 562                 rc = i2c_pnx_start(addr, alg_data);
 563                 if (rc < 0)
 564                         break;
 565
 566                 /* Wait for completion */
 567                 wait_for_completion(&alg_data->mif.complete);
 568
 569                 if (!(rc = alg_data->mif.ret))
 570                         completed++;
 571                 dev_dbg(&alg_data->adapter.dev,
 572                         "%s(): Complete, return code = %d.\n",
 573                         __func__, rc);
 574
 575                 /* Clear TDI and AFI bits in case they are set. */
 576                 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_tdi) {
 577                         dev_dbg(&alg_data->adapter.dev,
 578                                 "%s: TDI still set... clearing now.\n",
 579                                 alg_data->adapter.name);
 580                         iowrite32(stat, I2C_REG_STS(alg_data));
 581                 }
 582                 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_afi) {
 583                         dev_dbg(&alg_data->adapter.dev,
 584                                 "%s: AFI still set... clearing now.\n",
 585                                 alg_data->adapter.name);
 586                         iowrite32(stat, I2C_REG_STS(alg_data));
 587                 }
 588         }
 589
 590         bus_reset_if_active(alg_data);
 591
 592         /* Cleanup to be sure... */
 593         alg_data->mif.buf = NULL;
 594         alg_data->mif.len = 0;
 595         alg_data->mif.order = 0;
 596
 597         dev_dbg(&alg_data->adapter.dev, "%s(): exiting, stat = %x\n",
 598                 __func__, ioread32(I2C_REG_STS(alg_data)));
 599
 600         if (completed != num)
 601                 return ((rc < 0) ? rc : -EREMOTEIO);
 602
 603         return num;
 604 }
 605
 606 static u32 i2c_pnx_func(struct i2c_adapter *adapter)
 607 {
 608         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 609 }
 610
 611 static const struct i2c_algorithm pnx_algorithm = {
 612         .master_xfer = i2c_pnx_xfer,
 613         .functionality = i2c_pnx_func,
 614 };
 615
 616 #ifdef CONFIG_PM_SLEEP
 617 static int i2c_pnx_controller_suspend(struct device *dev)
 618 {
 619         struct i2c_pnx_algo_data *alg_data = dev_get_drvdata(dev);
 620
 621         clk_disable_unprepare(alg_data->clk);
 622
 623         return 0;
 624 }
 625
 626 static int i2c_pnx_controller_resume(struct device *dev)
 627 {
 628         struct i2c_pnx_algo_data *alg_data = dev_get_drvdata(dev);
 629
 630         return clk_prepare_enable(alg_data->clk);
 631 }
 632
 633 static SIMPLE_DEV_PM_OPS(i2c_pnx_pm,
 634                          i2c_pnx_controller_suspend, i2c_pnx_controller_resume);
 635 #define PNX_I2C_PM      (&i2c_pnx_pm)
 636 #else
 637 #define PNX_I2C_PM      NULL
 638 #endif
 639
 640 static int i2c_pnx_probe(struct platform_device *pdev)
 641 {
 642         unsigned long tmp;
 643         int ret = 0;
 644         struct i2c_pnx_algo_data *alg_data;
 645         unsigned long freq;
 646         struct resource *res;
 647         u32 speed = I2C_PNX_SPEED_KHZ_DEFAULT * 1000;
 648
 649         alg_data = devm_kzalloc(&pdev->dev, sizeof(*alg_data), GFP_KERNEL);
 650         if (!alg_data)
 651                 return -ENOMEM;
 652
 653         platform_set_drvdata(pdev, alg_data);
 654
 655         alg_data->adapter.dev.parent = &pdev->dev;
 656         alg_data->adapter.algo = &pnx_algorithm;
 657         alg_data->adapter.algo_data = alg_data;
 658         alg_data->adapter.nr = pdev->id;
 659
 660         alg_data->timeout = I2C_PNX_TIMEOUT_DEFAULT;
 661 #ifdef CONFIG_OF
 662         alg_data->adapter.dev.of_node = of_node_get(pdev->dev.of_node);
 663         if (pdev->dev.of_node) {
 664                 of_property_read_u32(pdev->dev.of_node, "clock-frequency",
 665                                      &speed);
 666                 /*
 667                  * At this point, it is planned to add an OF timeout property.
 668                  * As soon as there is a consensus about how to call and handle
 669                  * this, sth. like the following can be put here:
 670                  *
 671                  * of_property_read_u32(pdev->dev.of_node, "timeout",
 672                  *                      &alg_data->timeout);
 673                  */
 674         }
 675 #endif
 676         alg_data->clk = devm_clk_get(&pdev->dev, NULL);
 677         if (IS_ERR(alg_data->clk))
 678                 return PTR_ERR(alg_data->clk);
 679
 680         timer_setup(&alg_data->mif.timer, i2c_pnx_timeout, 0);
 681
 682         snprintf(alg_data->adapter.name, sizeof(alg_data->adapter.name),
 683                  "%s", pdev->name);
 684
 685         /* Register I/O resource */
 686         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 687         alg_data->ioaddr = devm_ioremap_resource(&pdev->dev, res);
 688         if (IS_ERR(alg_data->ioaddr))
 689                 return PTR_ERR(alg_data->ioaddr);
 690
 691         ret = clk_prepare_enable(alg_data->clk);
 692         if (ret)
 693                 return ret;
 694
 695         freq = clk_get_rate(alg_data->clk);
 696
 697         /*
 698          * Clock Divisor High This value is the number of system clocks
 699          * the serial clock (SCL) will be high.
 700          * For example, if the system clock period is 50 ns and the maximum
 701          * desired serial period is 10000 ns (100 kHz), then CLKHI would be
 702          * set to 0.5*(f_sys/f_i2c)-2=0.5*(20e6/100e3)-2=98. The actual value
 703          * programmed into CLKHI will vary from this slightly due to
 704          * variations in the output pad's rise and fall times as well as
 705          * the deglitching filter length.
 706          */
 707
 708         tmp = (freq / speed) / 2 - 2;
 709         if (tmp > 0x3FF)
 710                 tmp = 0x3FF;
 711         iowrite32(tmp, I2C_REG_CKH(alg_data));
 712         iowrite32(tmp, I2C_REG_CKL(alg_data));
 713
 714         iowrite32(mcntrl_reset, I2C_REG_CTL(alg_data));
 715         if (wait_reset(alg_data)) {
 716                 ret = -ENODEV;
 717                 goto out_clock;
 718         }
 719         init_completion(&alg_data->mif.complete);
 720
 721         alg_data->irq = platform_get_irq(pdev, 0);
 722         if (alg_data->irq < 0) {
 723                 dev_err(&pdev->dev, "Failed to get IRQ from platform resource\n");
 724                 ret = alg_data->irq;
 725                 goto out_clock;
 726         }
 727         ret = devm_request_irq(&pdev->dev, alg_data->irq, i2c_pnx_interrupt,
 728                                0, pdev->name, alg_data);
 729         if (ret)
 730                 goto out_clock;
 731
 732         /* Register this adapter with the I2C subsystem */
 733         ret = i2c_add_numbered_adapter(&alg_data->adapter);
 734         if (ret < 0)
 735                 goto out_clock;
 736
 737         dev_dbg(&pdev->dev, "%s: Master at %#8x, irq %d.\n",
 738                 alg_data->adapter.name, res->start, alg_data->irq);
 739
 740         return 0;
 741
 742 out_clock:
 743         clk_disable_unprepare(alg_data->clk);
 744         return ret;
 745 }
 746
 747 static int i2c_pnx_remove(struct platform_device *pdev)
 748 {
 749         struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev);
 750
 751         i2c_del_adapter(&alg_data->adapter);
 752         clk_disable_unprepare(alg_data->clk);
 753
 754         return 0;
 755 }
 756
 757 #ifdef CONFIG_OF
 758 static const struct of_device_id i2c_pnx_of_match[] = {
 759         { .compatible = "nxp,pnx-i2c" },
 760         { },
 761 };
 762 MODULE_DEVICE_TABLE(of, i2c_pnx_of_match);
 763 #endif
 764
 765 static struct platform_driver i2c_pnx_driver = {
 766         .driver = {
 767                 .name = "pnx-i2c",
 768                 .of_match_table = of_match_ptr(i2c_pnx_of_match),
 769                 .pm = PNX_I2C_PM,
 770         },
 771         .probe = i2c_pnx_probe,
 772         .remove = i2c_pnx_remove,
 773 };
 774
 775 static int __init i2c_adap_pnx_init(void)
 776 {
 777         return platform_driver_register(&i2c_pnx_driver);
 778 }
 779
 780 static void __exit i2c_adap_pnx_exit(void)
 781 {
 782         platform_driver_unregister(&i2c_pnx_driver);
 783 }
 784
 785 MODULE_AUTHOR("Vitaly Wool, Dennis Kovalev <source@mvista.com>");
 786 MODULE_DESCRIPTION("I2C driver for Philips IP3204-based I2C busses");
 787 MODULE_LICENSE("GPL");
 788 MODULE_ALIAS("platform:pnx-i2c");
 789
 790 /* We need to make sure I2C is initialized before USB */
 791 subsys_initcall(i2c_adap_pnx_init);
 792 module_exit(i2c_adap_pnx_exit);