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vt: vt_ioctl: fix VT_DISALLOCATE freeing in-use virtual console
[linux/fpc-iii.git] / drivers / media / i2c / mt9v032.c
blob04788692c9ff4efe6cf2f3edd66304d0568c5d76
1 /*
2 * Driver for MT9V022, MT9V024, MT9V032, and MT9V034 CMOS Image Sensors
3 *
4 * Copyright (C) 2010, Laurent Pinchart <laurent.pinchart@ideasonboard.com>
5 *
6 * Based on the MT9M001 driver,
7 *
8 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/gpio/consumer.h>
18 #include <linux/i2c.h>
19 #include <linux/log2.h>
20 #include <linux/mutex.h>
21 #include <linux/of.h>
22 #include <linux/of_graph.h>
23 #include <linux/regmap.h>
24 #include <linux/slab.h>
25 #include <linux/videodev2.h>
26 #include <linux/v4l2-mediabus.h>
27 #include <linux/module.h>
28
29 #include <media/i2c/mt9v032.h>
30 #include <media/v4l2-ctrls.h>
31 #include <media/v4l2-device.h>
32 #include <media/v4l2-fwnode.h>
33 #include <media/v4l2-subdev.h>
34
35 /* The first four rows are black rows. The active area spans 753x481 pixels. */
36 #define MT9V032_PIXEL_ARRAY_HEIGHT 485
37 #define MT9V032_PIXEL_ARRAY_WIDTH 753
38
39 #define MT9V032_SYSCLK_FREQ_DEF 26600000
40
41 #define MT9V032_CHIP_VERSION 0x00
42 #define MT9V032_CHIP_ID_REV1 0x1311
43 #define MT9V032_CHIP_ID_REV3 0x1313
44 #define MT9V034_CHIP_ID_REV1 0X1324
45 #define MT9V032_COLUMN_START 0x01
46 #define MT9V032_COLUMN_START_MIN 1
47 #define MT9V032_COLUMN_START_DEF 1
48 #define MT9V032_COLUMN_START_MAX 752
49 #define MT9V032_ROW_START 0x02
50 #define MT9V032_ROW_START_MIN 4
51 #define MT9V032_ROW_START_DEF 5
52 #define MT9V032_ROW_START_MAX 482
53 #define MT9V032_WINDOW_HEIGHT 0x03
54 #define MT9V032_WINDOW_HEIGHT_MIN 1
55 #define MT9V032_WINDOW_HEIGHT_DEF 480
56 #define MT9V032_WINDOW_HEIGHT_MAX 480
57 #define MT9V032_WINDOW_WIDTH 0x04
58 #define MT9V032_WINDOW_WIDTH_MIN 1
59 #define MT9V032_WINDOW_WIDTH_DEF 752
60 #define MT9V032_WINDOW_WIDTH_MAX 752
61 #define MT9V032_HORIZONTAL_BLANKING 0x05
62 #define MT9V032_HORIZONTAL_BLANKING_MIN 43
63 #define MT9V034_HORIZONTAL_BLANKING_MIN 61
64 #define MT9V032_HORIZONTAL_BLANKING_DEF 94
65 #define MT9V032_HORIZONTAL_BLANKING_MAX 1023
66 #define MT9V032_VERTICAL_BLANKING 0x06
67 #define MT9V032_VERTICAL_BLANKING_MIN 4
68 #define MT9V034_VERTICAL_BLANKING_MIN 2
69 #define MT9V032_VERTICAL_BLANKING_DEF 45
70 #define MT9V032_VERTICAL_BLANKING_MAX 3000
71 #define MT9V034_VERTICAL_BLANKING_MAX 32288
72 #define MT9V032_CHIP_CONTROL 0x07
73 #define MT9V032_CHIP_CONTROL_MASTER_MODE (1 << 3)
74 #define MT9V032_CHIP_CONTROL_DOUT_ENABLE (1 << 7)
75 #define MT9V032_CHIP_CONTROL_SEQUENTIAL (1 << 8)
76 #define MT9V032_SHUTTER_WIDTH1 0x08
77 #define MT9V032_SHUTTER_WIDTH2 0x09
78 #define MT9V032_SHUTTER_WIDTH_CONTROL 0x0a
79 #define MT9V032_TOTAL_SHUTTER_WIDTH 0x0b
80 #define MT9V032_TOTAL_SHUTTER_WIDTH_MIN 1
81 #define MT9V034_TOTAL_SHUTTER_WIDTH_MIN 0
82 #define MT9V032_TOTAL_SHUTTER_WIDTH_DEF 480
83 #define MT9V032_TOTAL_SHUTTER_WIDTH_MAX 32767
84 #define MT9V034_TOTAL_SHUTTER_WIDTH_MAX 32765
85 #define MT9V032_RESET 0x0c
86 #define MT9V032_READ_MODE 0x0d
87 #define MT9V032_READ_MODE_ROW_BIN_MASK (3 << 0)
88 #define MT9V032_READ_MODE_ROW_BIN_SHIFT 0
89 #define MT9V032_READ_MODE_COLUMN_BIN_MASK (3 << 2)
90 #define MT9V032_READ_MODE_COLUMN_BIN_SHIFT 2
91 #define MT9V032_READ_MODE_ROW_FLIP (1 << 4)
92 #define MT9V032_READ_MODE_COLUMN_FLIP (1 << 5)
93 #define MT9V032_READ_MODE_DARK_COLUMNS (1 << 6)
94 #define MT9V032_READ_MODE_DARK_ROWS (1 << 7)
95 #define MT9V032_READ_MODE_RESERVED 0x0300
96 #define MT9V032_PIXEL_OPERATION_MODE 0x0f
97 #define MT9V034_PIXEL_OPERATION_MODE_HDR (1 << 0)
98 #define MT9V034_PIXEL_OPERATION_MODE_COLOR (1 << 1)
99 #define MT9V032_PIXEL_OPERATION_MODE_COLOR (1 << 2)
100 #define MT9V032_PIXEL_OPERATION_MODE_HDR (1 << 6)
101 #define MT9V032_ANALOG_GAIN 0x35
102 #define MT9V032_ANALOG_GAIN_MIN 16
103 #define MT9V032_ANALOG_GAIN_DEF 16
104 #define MT9V032_ANALOG_GAIN_MAX 64
105 #define MT9V032_MAX_ANALOG_GAIN 0x36
106 #define MT9V032_MAX_ANALOG_GAIN_MAX 127
107 #define MT9V032_FRAME_DARK_AVERAGE 0x42
108 #define MT9V032_DARK_AVG_THRESH 0x46
109 #define MT9V032_DARK_AVG_LOW_THRESH_MASK (255 << 0)
110 #define MT9V032_DARK_AVG_LOW_THRESH_SHIFT 0
111 #define MT9V032_DARK_AVG_HIGH_THRESH_MASK (255 << 8)
112 #define MT9V032_DARK_AVG_HIGH_THRESH_SHIFT 8
113 #define MT9V032_ROW_NOISE_CORR_CONTROL 0x70
114 #define MT9V034_ROW_NOISE_CORR_ENABLE (1 << 0)
115 #define MT9V034_ROW_NOISE_CORR_USE_BLK_AVG (1 << 1)
116 #define MT9V032_ROW_NOISE_CORR_ENABLE (1 << 5)
117 #define MT9V032_ROW_NOISE_CORR_USE_BLK_AVG (1 << 7)
118 #define MT9V032_PIXEL_CLOCK 0x74
119 #define MT9V034_PIXEL_CLOCK 0x72
120 #define MT9V032_PIXEL_CLOCK_INV_LINE (1 << 0)
121 #define MT9V032_PIXEL_CLOCK_INV_FRAME (1 << 1)
122 #define MT9V032_PIXEL_CLOCK_XOR_LINE (1 << 2)
123 #define MT9V032_PIXEL_CLOCK_CONT_LINE (1 << 3)
124 #define MT9V032_PIXEL_CLOCK_INV_PXL_CLK (1 << 4)
125 #define MT9V032_TEST_PATTERN 0x7f
126 #define MT9V032_TEST_PATTERN_DATA_MASK (1023 << 0)
127 #define MT9V032_TEST_PATTERN_DATA_SHIFT 0
128 #define MT9V032_TEST_PATTERN_USE_DATA (1 << 10)
129 #define MT9V032_TEST_PATTERN_GRAY_MASK (3 << 11)
130 #define MT9V032_TEST_PATTERN_GRAY_NONE (0 << 11)
131 #define MT9V032_TEST_PATTERN_GRAY_VERTICAL (1 << 11)
132 #define MT9V032_TEST_PATTERN_GRAY_HORIZONTAL (2 << 11)
133 #define MT9V032_TEST_PATTERN_GRAY_DIAGONAL (3 << 11)
134 #define MT9V032_TEST_PATTERN_ENABLE (1 << 13)
135 #define MT9V032_TEST_PATTERN_FLIP (1 << 14)
136 #define MT9V032_AEGC_DESIRED_BIN 0xa5
137 #define MT9V032_AEC_UPDATE_FREQUENCY 0xa6
138 #define MT9V032_AEC_LPF 0xa8
139 #define MT9V032_AGC_UPDATE_FREQUENCY 0xa9
140 #define MT9V032_AGC_LPF 0xaa
141 #define MT9V032_AEC_AGC_ENABLE 0xaf
142 #define MT9V032_AEC_ENABLE (1 << 0)
143 #define MT9V032_AGC_ENABLE (1 << 1)
144 #define MT9V034_AEC_MAX_SHUTTER_WIDTH 0xad
145 #define MT9V032_AEC_MAX_SHUTTER_WIDTH 0xbd
146 #define MT9V032_THERMAL_INFO 0xc1
147
148 enum mt9v032_model {
149 MT9V032_MODEL_V022_COLOR, /* MT9V022IX7ATC */
150 MT9V032_MODEL_V022_MONO, /* MT9V022IX7ATM */
151 MT9V032_MODEL_V024_COLOR, /* MT9V024IA7XTC */
152 MT9V032_MODEL_V024_MONO, /* MT9V024IA7XTM */
153 MT9V032_MODEL_V032_COLOR, /* MT9V032C12STM */
154 MT9V032_MODEL_V032_MONO, /* MT9V032C12STC */
155 MT9V032_MODEL_V034_COLOR,
156 MT9V032_MODEL_V034_MONO,
157 };
158
159 struct mt9v032_model_version {
160 unsigned int version;
161 const char *name;
162 };
163
164 struct mt9v032_model_data {
165 unsigned int min_row_time;
166 unsigned int min_hblank;
167 unsigned int min_vblank;
168 unsigned int max_vblank;
169 unsigned int min_shutter;
170 unsigned int max_shutter;
171 unsigned int pclk_reg;
172 unsigned int aec_max_shutter_reg;
173 const struct v4l2_ctrl_config * const aec_max_shutter_v4l2_ctrl;
174 };
175
176 struct mt9v032_model_info {
177 const struct mt9v032_model_data *data;
178 bool color;
179 };
180
181 static const struct mt9v032_model_version mt9v032_versions[] = {
182 { MT9V032_CHIP_ID_REV1, "MT9V022/MT9V032 rev1/2" },
183 { MT9V032_CHIP_ID_REV3, "MT9V022/MT9V032 rev3" },
184 { MT9V034_CHIP_ID_REV1, "MT9V024/MT9V034 rev1" },
185 };
186
187 struct mt9v032 {
188 struct v4l2_subdev subdev;
189 struct media_pad pad;
190
191 struct v4l2_mbus_framefmt format;
192 struct v4l2_rect crop;
193 unsigned int hratio;
194 unsigned int vratio;
195
196 struct v4l2_ctrl_handler ctrls;
197 struct {
198 struct v4l2_ctrl *link_freq;
199 struct v4l2_ctrl *pixel_rate;
200 };
201
202 struct mutex power_lock;
203 int power_count;
204
205 struct regmap *regmap;
206 struct clk *clk;
207 struct gpio_desc *reset_gpio;
208 struct gpio_desc *standby_gpio;
209
210 struct mt9v032_platform_data *pdata;
211 const struct mt9v032_model_info *model;
212 const struct mt9v032_model_version *version;
213
214 u32 sysclk;
215 u16 aec_agc;
216 u16 hblank;
217 struct {
218 struct v4l2_ctrl *test_pattern;
219 struct v4l2_ctrl *test_pattern_color;
220 };
221 };
222
223 static struct mt9v032 *to_mt9v032(struct v4l2_subdev *sd)
224 {
225 return container_of(sd, struct mt9v032, subdev);
226 }
227
228 static int
229 mt9v032_update_aec_agc(struct mt9v032 *mt9v032, u16 which, int enable)
230 {
231 struct regmap *map = mt9v032->regmap;
232 u16 value = mt9v032->aec_agc;
233 int ret;
234
235 if (enable)
236 value |= which;
237 else
238 value &= ~which;
239
240 ret = regmap_write(map, MT9V032_AEC_AGC_ENABLE, value);
241 if (ret < 0)
242 return ret;
243
244 mt9v032->aec_agc = value;
245 return 0;
246 }
247
248 static int
249 mt9v032_update_hblank(struct mt9v032 *mt9v032)
250 {
251 struct v4l2_rect *crop = &mt9v032->crop;
252 unsigned int min_hblank = mt9v032->model->data->min_hblank;
253 unsigned int hblank;
254
255 if (mt9v032->version->version == MT9V034_CHIP_ID_REV1)
256 min_hblank += (mt9v032->hratio - 1) * 10;
257 min_hblank = max_t(int, mt9v032->model->data->min_row_time - crop->width,
258 min_hblank);
259 hblank = max_t(unsigned int, mt9v032->hblank, min_hblank);
260
261 return regmap_write(mt9v032->regmap, MT9V032_HORIZONTAL_BLANKING,
262 hblank);
263 }
264
265 static int mt9v032_power_on(struct mt9v032 *mt9v032)
266 {
267 struct regmap *map = mt9v032->regmap;
268 int ret;
269
270 gpiod_set_value_cansleep(mt9v032->reset_gpio, 1);
271
272 ret = clk_set_rate(mt9v032->clk, mt9v032->sysclk);
273 if (ret < 0)
274 return ret;
275
276 /* System clock has to be enabled before releasing the reset */
277 ret = clk_prepare_enable(mt9v032->clk);
278 if (ret)
279 return ret;
280
281 udelay(1);
282
283 if (mt9v032->reset_gpio) {
284 gpiod_set_value_cansleep(mt9v032->reset_gpio, 0);
285
286 /* After releasing reset we need to wait 10 clock cycles
287 * before accessing the sensor over I2C. As the minimum SYSCLK
288 * frequency is 13MHz, waiting 1µs will be enough in the worst
289 * case.
290 */
291 udelay(1);
292 }
293
294 /* Reset the chip and stop data read out */
295 ret = regmap_write(map, MT9V032_RESET, 1);
296 if (ret < 0)
297 goto err;
298
299 ret = regmap_write(map, MT9V032_RESET, 0);
300 if (ret < 0)
301 goto err;
302
303 ret = regmap_write(map, MT9V032_CHIP_CONTROL,
304 MT9V032_CHIP_CONTROL_MASTER_MODE);
305 if (ret < 0)
306 goto err;
307
308 return 0;
309
310 err:
311 clk_disable_unprepare(mt9v032->clk);
312 return ret;
313 }
314
315 static void mt9v032_power_off(struct mt9v032 *mt9v032)
316 {
317 clk_disable_unprepare(mt9v032->clk);
318 }
319
320 static int __mt9v032_set_power(struct mt9v032 *mt9v032, bool on)
321 {
322 struct regmap *map = mt9v032->regmap;
323 int ret;
324
325 if (!on) {
326 mt9v032_power_off(mt9v032);
327 return 0;
328 }
329
330 ret = mt9v032_power_on(mt9v032);
331 if (ret < 0)
332 return ret;
333
334 /* Configure the pixel clock polarity */
335 if (mt9v032->pdata && mt9v032->pdata->clk_pol) {
336 ret = regmap_write(map, mt9v032->model->data->pclk_reg,
337 MT9V032_PIXEL_CLOCK_INV_PXL_CLK);
338 if (ret < 0)
339 return ret;
340 }
341
342 /* Disable the noise correction algorithm and restore the controls. */
343 ret = regmap_write(map, MT9V032_ROW_NOISE_CORR_CONTROL, 0);
344 if (ret < 0)
345 return ret;
346
347 return v4l2_ctrl_handler_setup(&mt9v032->ctrls);
348 }
349
350 /* -----------------------------------------------------------------------------
351 * V4L2 subdev video operations
352 */
353
354 static struct v4l2_mbus_framefmt *
355 __mt9v032_get_pad_format(struct mt9v032 *mt9v032, struct v4l2_subdev_pad_config *cfg,
356 unsigned int pad, enum v4l2_subdev_format_whence which)
357 {
358 switch (which) {
359 case V4L2_SUBDEV_FORMAT_TRY:
360 return v4l2_subdev_get_try_format(&mt9v032->subdev, cfg, pad);
361 case V4L2_SUBDEV_FORMAT_ACTIVE:
362 return &mt9v032->format;
363 default:
364 return NULL;
365 }
366 }
367
368 static struct v4l2_rect *
369 __mt9v032_get_pad_crop(struct mt9v032 *mt9v032, struct v4l2_subdev_pad_config *cfg,
370 unsigned int pad, enum v4l2_subdev_format_whence which)
371 {
372 switch (which) {
373 case V4L2_SUBDEV_FORMAT_TRY:
374 return v4l2_subdev_get_try_crop(&mt9v032->subdev, cfg, pad);
375 case V4L2_SUBDEV_FORMAT_ACTIVE:
376 return &mt9v032->crop;
377 default:
378 return NULL;
379 }
380 }
381
382 static int mt9v032_s_stream(struct v4l2_subdev *subdev, int enable)
383 {
384 const u16 mode = MT9V032_CHIP_CONTROL_DOUT_ENABLE
385 | MT9V032_CHIP_CONTROL_SEQUENTIAL;
386 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
387 struct v4l2_rect *crop = &mt9v032->crop;
388 struct regmap *map = mt9v032->regmap;
389 unsigned int hbin;
390 unsigned int vbin;
391 int ret;
392
393 if (!enable)
394 return regmap_update_bits(map, MT9V032_CHIP_CONTROL, mode, 0);
395
396 /* Configure the window size and row/column bin */
397 hbin = fls(mt9v032->hratio) - 1;
398 vbin = fls(mt9v032->vratio) - 1;
399 ret = regmap_update_bits(map, MT9V032_READ_MODE,
400 ~MT9V032_READ_MODE_RESERVED,
401 hbin << MT9V032_READ_MODE_COLUMN_BIN_SHIFT |
402 vbin << MT9V032_READ_MODE_ROW_BIN_SHIFT);
403 if (ret < 0)
404 return ret;
405
406 ret = regmap_write(map, MT9V032_COLUMN_START, crop->left);
407 if (ret < 0)
408 return ret;
409
410 ret = regmap_write(map, MT9V032_ROW_START, crop->top);
411 if (ret < 0)
412 return ret;
413
414 ret = regmap_write(map, MT9V032_WINDOW_WIDTH, crop->width);
415 if (ret < 0)
416 return ret;
417
418 ret = regmap_write(map, MT9V032_WINDOW_HEIGHT, crop->height);
419 if (ret < 0)
420 return ret;
421
422 ret = mt9v032_update_hblank(mt9v032);
423 if (ret < 0)
424 return ret;
425
426 /* Switch to master "normal" mode */
427 return regmap_update_bits(map, MT9V032_CHIP_CONTROL, mode, mode);
428 }
429
430 static int mt9v032_enum_mbus_code(struct v4l2_subdev *subdev,
431 struct v4l2_subdev_pad_config *cfg,
432 struct v4l2_subdev_mbus_code_enum *code)
433 {
434 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
435
436 if (code->index > 0)
437 return -EINVAL;
438
439 code->code = mt9v032->format.code;
440 return 0;
441 }
442
443 static int mt9v032_enum_frame_size(struct v4l2_subdev *subdev,
444 struct v4l2_subdev_pad_config *cfg,
445 struct v4l2_subdev_frame_size_enum *fse)
446 {
447 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
448
449 if (fse->index >= 3)
450 return -EINVAL;
451 if (mt9v032->format.code != fse->code)
452 return -EINVAL;
453
454 fse->min_width = MT9V032_WINDOW_WIDTH_DEF / (1 << fse->index);
455 fse->max_width = fse->min_width;
456 fse->min_height = MT9V032_WINDOW_HEIGHT_DEF / (1 << fse->index);
457 fse->max_height = fse->min_height;
458
459 return 0;
460 }
461
462 static int mt9v032_get_format(struct v4l2_subdev *subdev,
463 struct v4l2_subdev_pad_config *cfg,
464 struct v4l2_subdev_format *format)
465 {
466 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
467
468 format->format = *__mt9v032_get_pad_format(mt9v032, cfg, format->pad,
469 format->which);
470 return 0;
471 }
472
473 static void mt9v032_configure_pixel_rate(struct mt9v032 *mt9v032)
474 {
475 struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
476 int ret;
477
478 ret = v4l2_ctrl_s_ctrl_int64(mt9v032->pixel_rate,
479 mt9v032->sysclk / mt9v032->hratio);
480 if (ret < 0)
481 dev_warn(&client->dev, "failed to set pixel rate (%d)\n", ret);
482 }
483
484 static unsigned int mt9v032_calc_ratio(unsigned int input, unsigned int output)
485 {
486 /* Compute the power-of-two binning factor closest to the input size to
487 * output size ratio. Given that the output size is bounded by input/4
488 * and input, a generic implementation would be an ineffective luxury.
489 */
490 if (output * 3 > input * 2)
491 return 1;
492 if (output * 3 > input)
493 return 2;
494 return 4;
495 }
496
497 static int mt9v032_set_format(struct v4l2_subdev *subdev,
498 struct v4l2_subdev_pad_config *cfg,
499 struct v4l2_subdev_format *format)
500 {
501 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
502 struct v4l2_mbus_framefmt *__format;
503 struct v4l2_rect *__crop;
504 unsigned int width;
505 unsigned int height;
506 unsigned int hratio;
507 unsigned int vratio;
508
509 __crop = __mt9v032_get_pad_crop(mt9v032, cfg, format->pad,
510 format->which);
511
512 /* Clamp the width and height to avoid dividing by zero. */
513 width = clamp(ALIGN(format->format.width, 2),
514 max_t(unsigned int, __crop->width / 4,
515 MT9V032_WINDOW_WIDTH_MIN),
516 __crop->width);
517 height = clamp(ALIGN(format->format.height, 2),
518 max_t(unsigned int, __crop->height / 4,
519 MT9V032_WINDOW_HEIGHT_MIN),
520 __crop->height);
521
522 hratio = mt9v032_calc_ratio(__crop->width, width);
523 vratio = mt9v032_calc_ratio(__crop->height, height);
524
525 __format = __mt9v032_get_pad_format(mt9v032, cfg, format->pad,
526 format->which);
527 __format->width = __crop->width / hratio;
528 __format->height = __crop->height / vratio;
529
530 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
531 mt9v032->hratio = hratio;
532 mt9v032->vratio = vratio;
533 mt9v032_configure_pixel_rate(mt9v032);
534 }
535
536 format->format = *__format;
537
538 return 0;
539 }
540
541 static int mt9v032_get_selection(struct v4l2_subdev *subdev,
542 struct v4l2_subdev_pad_config *cfg,
543 struct v4l2_subdev_selection *sel)
544 {
545 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
546
547 if (sel->target != V4L2_SEL_TGT_CROP)
548 return -EINVAL;
549
550 sel->r = *__mt9v032_get_pad_crop(mt9v032, cfg, sel->pad, sel->which);
551 return 0;
552 }
553
554 static int mt9v032_set_selection(struct v4l2_subdev *subdev,
555 struct v4l2_subdev_pad_config *cfg,
556 struct v4l2_subdev_selection *sel)
557 {
558 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
559 struct v4l2_mbus_framefmt *__format;
560 struct v4l2_rect *__crop;
561 struct v4l2_rect rect;
562
563 if (sel->target != V4L2_SEL_TGT_CROP)
564 return -EINVAL;
565
566 /* Clamp the crop rectangle boundaries and align them to a non multiple
567 * of 2 pixels to ensure a GRBG Bayer pattern.
568 */
569 rect.left = clamp(ALIGN(sel->r.left + 1, 2) - 1,
570 MT9V032_COLUMN_START_MIN,
571 MT9V032_COLUMN_START_MAX);
572 rect.top = clamp(ALIGN(sel->r.top + 1, 2) - 1,
573 MT9V032_ROW_START_MIN,
574 MT9V032_ROW_START_MAX);
575 rect.width = clamp_t(unsigned int, ALIGN(sel->r.width, 2),
576 MT9V032_WINDOW_WIDTH_MIN,
577 MT9V032_WINDOW_WIDTH_MAX);
578 rect.height = clamp_t(unsigned int, ALIGN(sel->r.height, 2),
579 MT9V032_WINDOW_HEIGHT_MIN,
580 MT9V032_WINDOW_HEIGHT_MAX);
581
582 rect.width = min_t(unsigned int,
583 rect.width, MT9V032_PIXEL_ARRAY_WIDTH - rect.left);
584 rect.height = min_t(unsigned int,
585 rect.height, MT9V032_PIXEL_ARRAY_HEIGHT - rect.top);
586
587 __crop = __mt9v032_get_pad_crop(mt9v032, cfg, sel->pad, sel->which);
588
589 if (rect.width != __crop->width || rect.height != __crop->height) {
590 /* Reset the output image size if the crop rectangle size has
591 * been modified.
592 */
593 __format = __mt9v032_get_pad_format(mt9v032, cfg, sel->pad,
594 sel->which);
595 __format->width = rect.width;
596 __format->height = rect.height;
597 if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
598 mt9v032->hratio = 1;
599 mt9v032->vratio = 1;
600 mt9v032_configure_pixel_rate(mt9v032);
601 }
602 }
603
604 *__crop = rect;
605 sel->r = rect;
606
607 return 0;
608 }
609
610 /* -----------------------------------------------------------------------------
611 * V4L2 subdev control operations
612 */
613
614 #define V4L2_CID_TEST_PATTERN_COLOR (V4L2_CID_USER_BASE | 0x1001)
615 /*
616 * Value between 1 and 64 to set the desired bin. This is effectively a measure
617 * of how bright the image is supposed to be. Both AGC and AEC try to reach
618 * this.
619 */
620 #define V4L2_CID_AEGC_DESIRED_BIN (V4L2_CID_USER_BASE | 0x1002)
621 /*
622 * LPF is the low pass filter capability of the chip. Both AEC and AGC have
623 * this setting. This limits the speed in which AGC/AEC adjust their settings.
624 * Possible values are 0-2. 0 means no LPF. For 1 and 2 this equation is used:
625 *
626 * if |(calculated new exp - current exp)| > (current exp / 4)
627 * next exp = calculated new exp
628 * else
629 * next exp = current exp + ((calculated new exp - current exp) / 2^LPF)
630 */
631 #define V4L2_CID_AEC_LPF (V4L2_CID_USER_BASE | 0x1003)
632 #define V4L2_CID_AGC_LPF (V4L2_CID_USER_BASE | 0x1004)
633 /*
634 * Value between 0 and 15. This is the number of frames being skipped before
635 * updating the auto exposure/gain.
636 */
637 #define V4L2_CID_AEC_UPDATE_INTERVAL (V4L2_CID_USER_BASE | 0x1005)
638 #define V4L2_CID_AGC_UPDATE_INTERVAL (V4L2_CID_USER_BASE | 0x1006)
639 /*
640 * Maximum shutter width used for AEC.
641 */
642 #define V4L2_CID_AEC_MAX_SHUTTER_WIDTH (V4L2_CID_USER_BASE | 0x1007)
643
644 static int mt9v032_s_ctrl(struct v4l2_ctrl *ctrl)
645 {
646 struct mt9v032 *mt9v032 =
647 container_of(ctrl->handler, struct mt9v032, ctrls);
648 struct regmap *map = mt9v032->regmap;
649 u32 freq;
650 u16 data;
651
652 switch (ctrl->id) {
653 case V4L2_CID_AUTOGAIN:
654 return mt9v032_update_aec_agc(mt9v032, MT9V032_AGC_ENABLE,
655 ctrl->val);
656
657 case V4L2_CID_GAIN:
658 return regmap_write(map, MT9V032_ANALOG_GAIN, ctrl->val);
659
660 case V4L2_CID_EXPOSURE_AUTO:
661 return mt9v032_update_aec_agc(mt9v032, MT9V032_AEC_ENABLE,
662 !ctrl->val);
663
664 case V4L2_CID_EXPOSURE:
665 return regmap_write(map, MT9V032_TOTAL_SHUTTER_WIDTH,
666 ctrl->val);
667
668 case V4L2_CID_HBLANK:
669 mt9v032->hblank = ctrl->val;
670 return mt9v032_update_hblank(mt9v032);
671
672 case V4L2_CID_VBLANK:
673 return regmap_write(map, MT9V032_VERTICAL_BLANKING,
674 ctrl->val);
675
676 case V4L2_CID_PIXEL_RATE:
677 case V4L2_CID_LINK_FREQ:
678 if (mt9v032->link_freq == NULL)
679 break;
680
681 freq = mt9v032->pdata->link_freqs[mt9v032->link_freq->val];
682 *mt9v032->pixel_rate->p_new.p_s64 = freq;
683 mt9v032->sysclk = freq;
684 break;
685
686 case V4L2_CID_TEST_PATTERN:
687 switch (mt9v032->test_pattern->val) {
688 case 0:
689 data = 0;
690 break;
691 case 1:
692 data = MT9V032_TEST_PATTERN_GRAY_VERTICAL
693 | MT9V032_TEST_PATTERN_ENABLE;
694 break;
695 case 2:
696 data = MT9V032_TEST_PATTERN_GRAY_HORIZONTAL
697 | MT9V032_TEST_PATTERN_ENABLE;
698 break;
699 case 3:
700 data = MT9V032_TEST_PATTERN_GRAY_DIAGONAL
701 | MT9V032_TEST_PATTERN_ENABLE;
702 break;
703 default:
704 data = (mt9v032->test_pattern_color->val <<
705 MT9V032_TEST_PATTERN_DATA_SHIFT)
706 | MT9V032_TEST_PATTERN_USE_DATA
707 | MT9V032_TEST_PATTERN_ENABLE
708 | MT9V032_TEST_PATTERN_FLIP;
709 break;
710 }
711 return regmap_write(map, MT9V032_TEST_PATTERN, data);
712
713 case V4L2_CID_AEGC_DESIRED_BIN:
714 return regmap_write(map, MT9V032_AEGC_DESIRED_BIN, ctrl->val);
715
716 case V4L2_CID_AEC_LPF:
717 return regmap_write(map, MT9V032_AEC_LPF, ctrl->val);
718
719 case V4L2_CID_AGC_LPF:
720 return regmap_write(map, MT9V032_AGC_LPF, ctrl->val);
721
722 case V4L2_CID_AEC_UPDATE_INTERVAL:
723 return regmap_write(map, MT9V032_AEC_UPDATE_FREQUENCY,
724 ctrl->val);
725
726 case V4L2_CID_AGC_UPDATE_INTERVAL:
727 return regmap_write(map, MT9V032_AGC_UPDATE_FREQUENCY,
728 ctrl->val);
729
730 case V4L2_CID_AEC_MAX_SHUTTER_WIDTH:
731 return regmap_write(map,
732 mt9v032->model->data->aec_max_shutter_reg,
733 ctrl->val);
734 }
735
736 return 0;
737 }
738
739 static const struct v4l2_ctrl_ops mt9v032_ctrl_ops = {
740 .s_ctrl = mt9v032_s_ctrl,
741 };
742
743 static const char * const mt9v032_test_pattern_menu[] = {
744 "Disabled",
745 "Gray Vertical Shade",
746 "Gray Horizontal Shade",
747 "Gray Diagonal Shade",
748 "Plain",
749 };
750
751 static const struct v4l2_ctrl_config mt9v032_test_pattern_color = {
752 .ops = &mt9v032_ctrl_ops,
753 .id = V4L2_CID_TEST_PATTERN_COLOR,
754 .type = V4L2_CTRL_TYPE_INTEGER,
755 .name = "Test Pattern Color",
756 .min = 0,
757 .max = 1023,
758 .step = 1,
759 .def = 0,
760 .flags = 0,
761 };
762
763 static const struct v4l2_ctrl_config mt9v032_aegc_controls[] = {
764 {
765 .ops = &mt9v032_ctrl_ops,
766 .id = V4L2_CID_AEGC_DESIRED_BIN,
767 .type = V4L2_CTRL_TYPE_INTEGER,
768 .name = "AEC/AGC Desired Bin",
769 .min = 1,
770 .max = 64,
771 .step = 1,
772 .def = 58,
773 .flags = 0,
774 }, {
775 .ops = &mt9v032_ctrl_ops,
776 .id = V4L2_CID_AEC_LPF,
777 .type = V4L2_CTRL_TYPE_INTEGER,
778 .name = "AEC Low Pass Filter",
779 .min = 0,
780 .max = 2,
781 .step = 1,
782 .def = 0,
783 .flags = 0,
784 }, {
785 .ops = &mt9v032_ctrl_ops,
786 .id = V4L2_CID_AGC_LPF,
787 .type = V4L2_CTRL_TYPE_INTEGER,
788 .name = "AGC Low Pass Filter",
789 .min = 0,
790 .max = 2,
791 .step = 1,
792 .def = 2,
793 .flags = 0,
794 }, {
795 .ops = &mt9v032_ctrl_ops,
796 .id = V4L2_CID_AEC_UPDATE_INTERVAL,
797 .type = V4L2_CTRL_TYPE_INTEGER,
798 .name = "AEC Update Interval",
799 .min = 0,
800 .max = 16,
801 .step = 1,
802 .def = 2,
803 .flags = 0,
804 }, {
805 .ops = &mt9v032_ctrl_ops,
806 .id = V4L2_CID_AGC_UPDATE_INTERVAL,
807 .type = V4L2_CTRL_TYPE_INTEGER,
808 .name = "AGC Update Interval",
809 .min = 0,
810 .max = 16,
811 .step = 1,
812 .def = 2,
813 .flags = 0,
814 }
815 };
816
817 static const struct v4l2_ctrl_config mt9v032_aec_max_shutter_width = {
818 .ops = &mt9v032_ctrl_ops,
819 .id = V4L2_CID_AEC_MAX_SHUTTER_WIDTH,
820 .type = V4L2_CTRL_TYPE_INTEGER,
821 .name = "AEC Max Shutter Width",
822 .min = 1,
823 .max = 2047,
824 .step = 1,
825 .def = 480,
826 .flags = 0,
827 };
828
829 static const struct v4l2_ctrl_config mt9v034_aec_max_shutter_width = {
830 .ops = &mt9v032_ctrl_ops,
831 .id = V4L2_CID_AEC_MAX_SHUTTER_WIDTH,
832 .type = V4L2_CTRL_TYPE_INTEGER,
833 .name = "AEC Max Shutter Width",
834 .min = 1,
835 .max = 32765,
836 .step = 1,
837 .def = 480,
838 .flags = 0,
839 };
840
841 /* -----------------------------------------------------------------------------
842 * V4L2 subdev core operations
843 */
844
845 static int mt9v032_set_power(struct v4l2_subdev *subdev, int on)
846 {
847 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
848 int ret = 0;
849
850 mutex_lock(&mt9v032->power_lock);
851
852 /* If the power count is modified from 0 to != 0 or from != 0 to 0,
853 * update the power state.
854 */
855 if (mt9v032->power_count == !on) {
856 ret = __mt9v032_set_power(mt9v032, !!on);
857 if (ret < 0)
858 goto done;
859 }
860
861 /* Update the power count. */
862 mt9v032->power_count += on ? 1 : -1;
863 WARN_ON(mt9v032->power_count < 0);
864
865 done:
866 mutex_unlock(&mt9v032->power_lock);
867 return ret;
868 }
869
870 /* -----------------------------------------------------------------------------
871 * V4L2 subdev internal operations
872 */
873
874 static int mt9v032_registered(struct v4l2_subdev *subdev)
875 {
876 struct i2c_client *client = v4l2_get_subdevdata(subdev);
877 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
878 unsigned int i;
879 u32 version;
880 int ret;
881
882 dev_info(&client->dev, "Probing MT9V032 at address 0x%02x\n",
883 client->addr);
884
885 ret = mt9v032_power_on(mt9v032);
886 if (ret < 0) {
887 dev_err(&client->dev, "MT9V032 power up failed\n");
888 return ret;
889 }
890
891 /* Read and check the sensor version */
892 ret = regmap_read(mt9v032->regmap, MT9V032_CHIP_VERSION, &version);
893
894 mt9v032_power_off(mt9v032);
895
896 if (ret < 0) {
897 dev_err(&client->dev, "Failed reading chip version\n");
898 return ret;
899 }
900
901 for (i = 0; i < ARRAY_SIZE(mt9v032_versions); ++i) {
902 if (mt9v032_versions[i].version == version) {
903 mt9v032->version = &mt9v032_versions[i];
904 break;
905 }
906 }
907
908 if (mt9v032->version == NULL) {
909 dev_err(&client->dev, "Unsupported chip version 0x%04x\n",
910 version);
911 return -ENODEV;
912 }
913
914 dev_info(&client->dev, "%s detected at address 0x%02x\n",
915 mt9v032->version->name, client->addr);
916
917 mt9v032_configure_pixel_rate(mt9v032);
918
919 return ret;
920 }
921
922 static int mt9v032_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
923 {
924 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
925 struct v4l2_mbus_framefmt *format;
926 struct v4l2_rect *crop;
927
928 crop = v4l2_subdev_get_try_crop(subdev, fh->pad, 0);
929 crop->left = MT9V032_COLUMN_START_DEF;
930 crop->top = MT9V032_ROW_START_DEF;
931 crop->width = MT9V032_WINDOW_WIDTH_DEF;
932 crop->height = MT9V032_WINDOW_HEIGHT_DEF;
933
934 format = v4l2_subdev_get_try_format(subdev, fh->pad, 0);
935
936 if (mt9v032->model->color)
937 format->code = MEDIA_BUS_FMT_SGRBG10_1X10;
938 else
939 format->code = MEDIA_BUS_FMT_Y10_1X10;
940
941 format->width = MT9V032_WINDOW_WIDTH_DEF;
942 format->height = MT9V032_WINDOW_HEIGHT_DEF;
943 format->field = V4L2_FIELD_NONE;
944 format->colorspace = V4L2_COLORSPACE_SRGB;
945
946 return mt9v032_set_power(subdev, 1);
947 }
948
949 static int mt9v032_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
950 {
951 return mt9v032_set_power(subdev, 0);
952 }
953
954 static const struct v4l2_subdev_core_ops mt9v032_subdev_core_ops = {
955 .s_power = mt9v032_set_power,
956 };
957
958 static const struct v4l2_subdev_video_ops mt9v032_subdev_video_ops = {
959 .s_stream = mt9v032_s_stream,
960 };
961
962 static const struct v4l2_subdev_pad_ops mt9v032_subdev_pad_ops = {
963 .enum_mbus_code = mt9v032_enum_mbus_code,
964 .enum_frame_size = mt9v032_enum_frame_size,
965 .get_fmt = mt9v032_get_format,
966 .set_fmt = mt9v032_set_format,
967 .get_selection = mt9v032_get_selection,
968 .set_selection = mt9v032_set_selection,
969 };
970
971 static const struct v4l2_subdev_ops mt9v032_subdev_ops = {
972 .core = &mt9v032_subdev_core_ops,
973 .video = &mt9v032_subdev_video_ops,
974 .pad = &mt9v032_subdev_pad_ops,
975 };
976
977 static const struct v4l2_subdev_internal_ops mt9v032_subdev_internal_ops = {
978 .registered = mt9v032_registered,
979 .open = mt9v032_open,
980 .close = mt9v032_close,
981 };
982
983 static const struct regmap_config mt9v032_regmap_config = {
984 .reg_bits = 8,
985 .val_bits = 16,
986 .max_register = 0xff,
987 .cache_type = REGCACHE_RBTREE,
988 };
989
990 /* -----------------------------------------------------------------------------
991 * Driver initialization and probing
992 */
993
994 static struct mt9v032_platform_data *
995 mt9v032_get_pdata(struct i2c_client *client)
996 {
997 struct mt9v032_platform_data *pdata = NULL;
998 struct v4l2_fwnode_endpoint endpoint;
999 struct device_node *np;
1000 struct property *prop;
1001
1002 if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
1003 return client->dev.platform_data;
1004
1005 np = of_graph_get_next_endpoint(client->dev.of_node, NULL);
1006 if (!np)
1007 return NULL;
1008
1009 if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &endpoint) < 0)
1010 goto done;
1011
1012 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
1013 if (!pdata)
1014 goto done;
1015
1016 prop = of_find_property(np, "link-frequencies", NULL);
1017 if (prop) {
1018 u64 *link_freqs;
1019 size_t size = prop->length / sizeof(*link_freqs);
1020
1021 link_freqs = devm_kcalloc(&client->dev, size,
1022 sizeof(*link_freqs), GFP_KERNEL);
1023 if (!link_freqs)
1024 goto done;
1025
1026 if (of_property_read_u64_array(np, "link-frequencies",
1027 link_freqs, size) < 0)
1028 goto done;
1029
1030 pdata->link_freqs = link_freqs;
1031 pdata->link_def_freq = link_freqs[0];
1032 }
1033
1034 pdata->clk_pol = !!(endpoint.bus.parallel.flags &
1035 V4L2_MBUS_PCLK_SAMPLE_RISING);
1036
1037 done:
1038 of_node_put(np);
1039 return pdata;
1040 }
1041
1042 static int mt9v032_probe(struct i2c_client *client,
1043 const struct i2c_device_id *did)
1044 {
1045 struct mt9v032_platform_data *pdata = mt9v032_get_pdata(client);
1046 struct mt9v032 *mt9v032;
1047 unsigned int i;
1048 int ret;
1049
1050 mt9v032 = devm_kzalloc(&client->dev, sizeof(*mt9v032), GFP_KERNEL);
1051 if (!mt9v032)
1052 return -ENOMEM;
1053
1054 mt9v032->regmap = devm_regmap_init_i2c(client, &mt9v032_regmap_config);
1055 if (IS_ERR(mt9v032->regmap))
1056 return PTR_ERR(mt9v032->regmap);
1057
1058 mt9v032->clk = devm_clk_get(&client->dev, NULL);
1059 if (IS_ERR(mt9v032->clk))
1060 return PTR_ERR(mt9v032->clk);
1061
1062 mt9v032->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1063 GPIOD_OUT_HIGH);
1064 if (IS_ERR(mt9v032->reset_gpio))
1065 return PTR_ERR(mt9v032->reset_gpio);
1066
1067 mt9v032->standby_gpio = devm_gpiod_get_optional(&client->dev, "standby",
1068 GPIOD_OUT_LOW);
1069 if (IS_ERR(mt9v032->standby_gpio))
1070 return PTR_ERR(mt9v032->standby_gpio);
1071
1072 mutex_init(&mt9v032->power_lock);
1073 mt9v032->pdata = pdata;
1074 mt9v032->model = (const void *)did->driver_data;
1075
1076 v4l2_ctrl_handler_init(&mt9v032->ctrls, 11 +
1077 ARRAY_SIZE(mt9v032_aegc_controls));
1078
1079 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1080 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1081 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1082 V4L2_CID_GAIN, MT9V032_ANALOG_GAIN_MIN,
1083 MT9V032_ANALOG_GAIN_MAX, 1, MT9V032_ANALOG_GAIN_DEF);
1084 v4l2_ctrl_new_std_menu(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1085 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0,
1086 V4L2_EXPOSURE_AUTO);
1087 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1088 V4L2_CID_EXPOSURE, mt9v032->model->data->min_shutter,
1089 mt9v032->model->data->max_shutter, 1,
1090 MT9V032_TOTAL_SHUTTER_WIDTH_DEF);
1091 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1092 V4L2_CID_HBLANK, mt9v032->model->data->min_hblank,
1093 MT9V032_HORIZONTAL_BLANKING_MAX, 1,
1094 MT9V032_HORIZONTAL_BLANKING_DEF);
1095 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1096 V4L2_CID_VBLANK, mt9v032->model->data->min_vblank,
1097 mt9v032->model->data->max_vblank, 1,
1098 MT9V032_VERTICAL_BLANKING_DEF);
1099 mt9v032->test_pattern = v4l2_ctrl_new_std_menu_items(&mt9v032->ctrls,
1100 &mt9v032_ctrl_ops, V4L2_CID_TEST_PATTERN,
1101 ARRAY_SIZE(mt9v032_test_pattern_menu) - 1, 0, 0,
1102 mt9v032_test_pattern_menu);
1103 mt9v032->test_pattern_color = v4l2_ctrl_new_custom(&mt9v032->ctrls,
1104 &mt9v032_test_pattern_color, NULL);
1105
1106 v4l2_ctrl_new_custom(&mt9v032->ctrls,
1107 mt9v032->model->data->aec_max_shutter_v4l2_ctrl,
1108 NULL);
1109 for (i = 0; i < ARRAY_SIZE(mt9v032_aegc_controls); ++i)
1110 v4l2_ctrl_new_custom(&mt9v032->ctrls, &mt9v032_aegc_controls[i],
1111 NULL);
1112
1113 v4l2_ctrl_cluster(2, &mt9v032->test_pattern);
1114
1115 mt9v032->pixel_rate =
1116 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1117 V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1);
1118
1119 if (pdata && pdata->link_freqs) {
1120 unsigned int def = 0;
1121
1122 for (i = 0; pdata->link_freqs[i]; ++i) {
1123 if (pdata->link_freqs[i] == pdata->link_def_freq)
1124 def = i;
1125 }
1126
1127 mt9v032->link_freq =
1128 v4l2_ctrl_new_int_menu(&mt9v032->ctrls,
1129 &mt9v032_ctrl_ops,
1130 V4L2_CID_LINK_FREQ, i - 1, def,
1131 pdata->link_freqs);
1132 v4l2_ctrl_cluster(2, &mt9v032->link_freq);
1133 }
1134
1135
1136 mt9v032->subdev.ctrl_handler = &mt9v032->ctrls;
1137
1138 if (mt9v032->ctrls.error) {
1139 dev_err(&client->dev, "control initialization error %d\n",
1140 mt9v032->ctrls.error);
1141 ret = mt9v032->ctrls.error;
1142 goto err;
1143 }
1144
1145 mt9v032->crop.left = MT9V032_COLUMN_START_DEF;
1146 mt9v032->crop.top = MT9V032_ROW_START_DEF;
1147 mt9v032->crop.width = MT9V032_WINDOW_WIDTH_DEF;
1148 mt9v032->crop.height = MT9V032_WINDOW_HEIGHT_DEF;
1149
1150 if (mt9v032->model->color)
1151 mt9v032->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1152 else
1153 mt9v032->format.code = MEDIA_BUS_FMT_Y10_1X10;
1154
1155 mt9v032->format.width = MT9V032_WINDOW_WIDTH_DEF;
1156 mt9v032->format.height = MT9V032_WINDOW_HEIGHT_DEF;
1157 mt9v032->format.field = V4L2_FIELD_NONE;
1158 mt9v032->format.colorspace = V4L2_COLORSPACE_SRGB;
1159
1160 mt9v032->hratio = 1;
1161 mt9v032->vratio = 1;
1162
1163 mt9v032->aec_agc = MT9V032_AEC_ENABLE | MT9V032_AGC_ENABLE;
1164 mt9v032->hblank = MT9V032_HORIZONTAL_BLANKING_DEF;
1165 mt9v032->sysclk = MT9V032_SYSCLK_FREQ_DEF;
1166
1167 v4l2_i2c_subdev_init(&mt9v032->subdev, client, &mt9v032_subdev_ops);
1168 mt9v032->subdev.internal_ops = &mt9v032_subdev_internal_ops;
1169 mt9v032->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1170
1171 mt9v032->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1172 mt9v032->pad.flags = MEDIA_PAD_FL_SOURCE;
1173 ret = media_entity_pads_init(&mt9v032->subdev.entity, 1, &mt9v032->pad);
1174 if (ret < 0)
1175 goto err;
1176
1177 mt9v032->subdev.dev = &client->dev;
1178 ret = v4l2_async_register_subdev(&mt9v032->subdev);
1179 if (ret < 0)
1180 goto err;
1181
1182 return 0;
1183
1184 err:
1185 media_entity_cleanup(&mt9v032->subdev.entity);
1186 v4l2_ctrl_handler_free(&mt9v032->ctrls);
1187 return ret;
1188 }
1189
1190 static int mt9v032_remove(struct i2c_client *client)
1191 {
1192 struct v4l2_subdev *subdev = i2c_get_clientdata(client);
1193 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
1194
1195 v4l2_async_unregister_subdev(subdev);
1196 v4l2_ctrl_handler_free(&mt9v032->ctrls);
1197 media_entity_cleanup(&subdev->entity);
1198
1199 return 0;
1200 }
1201
1202 static const struct mt9v032_model_data mt9v032_model_data[] = {
1203 {
1204 /* MT9V022, MT9V032 revisions 1/2/3 */
1205 .min_row_time = 660,
1206 .min_hblank = MT9V032_HORIZONTAL_BLANKING_MIN,
1207 .min_vblank = MT9V032_VERTICAL_BLANKING_MIN,
1208 .max_vblank = MT9V032_VERTICAL_BLANKING_MAX,
1209 .min_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MIN,
1210 .max_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MAX,
1211 .pclk_reg = MT9V032_PIXEL_CLOCK,
1212 .aec_max_shutter_reg = MT9V032_AEC_MAX_SHUTTER_WIDTH,
1213 .aec_max_shutter_v4l2_ctrl = &mt9v032_aec_max_shutter_width,
1214 }, {
1215 /* MT9V024, MT9V034 */
1216 .min_row_time = 690,
1217 .min_hblank = MT9V034_HORIZONTAL_BLANKING_MIN,
1218 .min_vblank = MT9V034_VERTICAL_BLANKING_MIN,
1219 .max_vblank = MT9V034_VERTICAL_BLANKING_MAX,
1220 .min_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MIN,
1221 .max_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MAX,
1222 .pclk_reg = MT9V034_PIXEL_CLOCK,
1223 .aec_max_shutter_reg = MT9V034_AEC_MAX_SHUTTER_WIDTH,
1224 .aec_max_shutter_v4l2_ctrl = &mt9v034_aec_max_shutter_width,
1225 },
1226 };
1227
1228 static const struct mt9v032_model_info mt9v032_models[] = {
1229 [MT9V032_MODEL_V022_COLOR] = {
1230 .data = &mt9v032_model_data[0],
1231 .color = true,
1232 },
1233 [MT9V032_MODEL_V022_MONO] = {
1234 .data = &mt9v032_model_data[0],
1235 .color = false,
1236 },
1237 [MT9V032_MODEL_V024_COLOR] = {
1238 .data = &mt9v032_model_data[1],
1239 .color = true,
1240 },
1241 [MT9V032_MODEL_V024_MONO] = {
1242 .data = &mt9v032_model_data[1],
1243 .color = false,
1244 },
1245 [MT9V032_MODEL_V032_COLOR] = {
1246 .data = &mt9v032_model_data[0],
1247 .color = true,
1248 },
1249 [MT9V032_MODEL_V032_MONO] = {
1250 .data = &mt9v032_model_data[0],
1251 .color = false,
1252 },
1253 [MT9V032_MODEL_V034_COLOR] = {
1254 .data = &mt9v032_model_data[1],
1255 .color = true,
1256 },
1257 [MT9V032_MODEL_V034_MONO] = {
1258 .data = &mt9v032_model_data[1],
1259 .color = false,
1260 },
1261 };
1262
1263 static const struct i2c_device_id mt9v032_id[] = {
1264 { "mt9v022", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V022_COLOR] },
1265 { "mt9v022m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V022_MONO] },
1266 { "mt9v024", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V024_COLOR] },
1267 { "mt9v024m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V024_MONO] },
1268 { "mt9v032", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V032_COLOR] },
1269 { "mt9v032m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V032_MONO] },
1270 { "mt9v034", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V034_COLOR] },
1271 { "mt9v034m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V034_MONO] },
1272 { }
1273 };
1274 MODULE_DEVICE_TABLE(i2c, mt9v032_id);
1275
1276 #if IS_ENABLED(CONFIG_OF)
1277 static const struct of_device_id mt9v032_of_match[] = {
1278 { .compatible = "aptina,mt9v022" },
1279 { .compatible = "aptina,mt9v022m" },
1280 { .compatible = "aptina,mt9v024" },
1281 { .compatible = "aptina,mt9v024m" },
1282 { .compatible = "aptina,mt9v032" },
1283 { .compatible = "aptina,mt9v032m" },
1284 { .compatible = "aptina,mt9v034" },
1285 { .compatible = "aptina,mt9v034m" },
1286 { /* Sentinel */ }
1287 };
1288 MODULE_DEVICE_TABLE(of, mt9v032_of_match);
1289 #endif
1290
1291 static struct i2c_driver mt9v032_driver = {
1292 .driver = {
1293 .name = "mt9v032",
1294 .of_match_table = of_match_ptr(mt9v032_of_match),
1295 },
1296 .probe = mt9v032_probe,
1297 .remove = mt9v032_remove,
1298 .id_table = mt9v032_id,
1299 };
1300
1301 module_i2c_driver(mt9v032_driver);
1302
1303 MODULE_DESCRIPTION("Aptina MT9V032 Camera driver");
1304 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
1305 MODULE_LICENSE("GPL");
Linux with added FPC-III support