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vt: vt_ioctl: fix VT_DISALLOCATE freeing in-use virtual console
[linux/fpc-iii.git] / drivers / mmc / host / bcm2835.c
blob5301302fb53108641c16a5c7691f96efaa1b28f1
1 /*
2 * bcm2835 sdhost driver.
3 *
4 * The 2835 has two SD controllers: The Arasan sdhci controller
5 * (supported by the iproc driver) and a custom sdhost controller
6 * (supported by this driver).
7 *
8 * The sdhci controller supports both sdcard and sdio. The sdhost
9 * controller supports the sdcard only, but has better performance.
10 * Also note that the rpi3 has sdio wifi, so driving the sdcard with
11 * the sdhost controller allows to use the sdhci controller for wifi
12 * support.
13 *
14 * The configuration is done by devicetree via pin muxing. Both
15 * SD controller are available on the same pins (2 pin groups = pin 22
16 * to 27 + pin 48 to 53). So it's possible to use both SD controllers
17 * at the same time with different pin groups.
18 *
19 * Author: Phil Elwell <phil@raspberrypi.org>
20 * Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd.
21 *
22 * Based on
23 * mmc-bcm2835.c by Gellert Weisz
24 * which is, in turn, based on
25 * sdhci-bcm2708.c by Broadcom
26 * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
27 * sdhci.c and sdhci-pci.c by Pierre Ossman
28 *
29 * This program is free software; you can redistribute it and/or modify it
30 * under the terms and conditions of the GNU General Public License,
31 * version 2, as published by the Free Software Foundation.
32 *
33 * This program is distributed in the hope it will be useful, but WITHOUT
34 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
35 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
36 * more details.
37 *
38 * You should have received a copy of the GNU General Public License
39 * along with this program. If not, see <http://www.gnu.org/licenses/>.
40 */
41 #include <linux/clk.h>
42 #include <linux/delay.h>
43 #include <linux/device.h>
44 #include <linux/dmaengine.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/err.h>
47 #include <linux/highmem.h>
48 #include <linux/interrupt.h>
49 #include <linux/io.h>
50 #include <linux/iopoll.h>
51 #include <linux/module.h>
52 #include <linux/of_address.h>
53 #include <linux/of_irq.h>
54 #include <linux/platform_device.h>
55 #include <linux/scatterlist.h>
56 #include <linux/time.h>
57 #include <linux/workqueue.h>
58
59 #include <linux/mmc/host.h>
60 #include <linux/mmc/mmc.h>
61 #include <linux/mmc/sd.h>
62
63 #define SDCMD 0x00 /* Command to SD card - 16 R/W */
64 #define SDARG 0x04 /* Argument to SD card - 32 R/W */
65 #define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
66 #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */
67 #define SDRSP0 0x10 /* SD card response (31:0) - 32 R */
68 #define SDRSP1 0x14 /* SD card response (63:32) - 32 R */
69 #define SDRSP2 0x18 /* SD card response (95:64) - 32 R */
70 #define SDRSP3 0x1c /* SD card response (127:96) - 32 R */
71 #define SDHSTS 0x20 /* SD host status - 11 R/W */
72 #define SDVDD 0x30 /* SD card power control - 1 R/W */
73 #define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */
74 #define SDHCFG 0x38 /* Host configuration - 2 R/W */
75 #define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */
76 #define SDDATA 0x40 /* Data to/from SD card - 32 R/W */
77 #define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */
78
79 #define SDCMD_NEW_FLAG 0x8000
80 #define SDCMD_FAIL_FLAG 0x4000
81 #define SDCMD_BUSYWAIT 0x800
82 #define SDCMD_NO_RESPONSE 0x400
83 #define SDCMD_LONG_RESPONSE 0x200
84 #define SDCMD_WRITE_CMD 0x80
85 #define SDCMD_READ_CMD 0x40
86 #define SDCMD_CMD_MASK 0x3f
87
88 #define SDCDIV_MAX_CDIV 0x7ff
89
90 #define SDHSTS_BUSY_IRPT 0x400
91 #define SDHSTS_BLOCK_IRPT 0x200
92 #define SDHSTS_SDIO_IRPT 0x100
93 #define SDHSTS_REW_TIME_OUT 0x80
94 #define SDHSTS_CMD_TIME_OUT 0x40
95 #define SDHSTS_CRC16_ERROR 0x20
96 #define SDHSTS_CRC7_ERROR 0x10
97 #define SDHSTS_FIFO_ERROR 0x08
98 /* Reserved */
99 /* Reserved */
100 #define SDHSTS_DATA_FLAG 0x01
101
102 #define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \
103 SDHSTS_CRC16_ERROR | \
104 SDHSTS_REW_TIME_OUT | \
105 SDHSTS_FIFO_ERROR)
106
107 #define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \
108 SDHSTS_TRANSFER_ERROR_MASK)
109
110 #define SDHCFG_BUSY_IRPT_EN BIT(10)
111 #define SDHCFG_BLOCK_IRPT_EN BIT(8)
112 #define SDHCFG_SDIO_IRPT_EN BIT(5)
113 #define SDHCFG_DATA_IRPT_EN BIT(4)
114 #define SDHCFG_SLOW_CARD BIT(3)
115 #define SDHCFG_WIDE_EXT_BUS BIT(2)
116 #define SDHCFG_WIDE_INT_BUS BIT(1)
117 #define SDHCFG_REL_CMD_LINE BIT(0)
118
119 #define SDVDD_POWER_OFF 0
120 #define SDVDD_POWER_ON 1
121
122 #define SDEDM_FORCE_DATA_MODE BIT(19)
123 #define SDEDM_CLOCK_PULSE BIT(20)
124 #define SDEDM_BYPASS BIT(21)
125
126 #define SDEDM_WRITE_THRESHOLD_SHIFT 9
127 #define SDEDM_READ_THRESHOLD_SHIFT 14
128 #define SDEDM_THRESHOLD_MASK 0x1f
129
130 #define SDEDM_FSM_MASK 0xf
131 #define SDEDM_FSM_IDENTMODE 0x0
132 #define SDEDM_FSM_DATAMODE 0x1
133 #define SDEDM_FSM_READDATA 0x2
134 #define SDEDM_FSM_WRITEDATA 0x3
135 #define SDEDM_FSM_READWAIT 0x4
136 #define SDEDM_FSM_READCRC 0x5
137 #define SDEDM_FSM_WRITECRC 0x6
138 #define SDEDM_FSM_WRITEWAIT1 0x7
139 #define SDEDM_FSM_POWERDOWN 0x8
140 #define SDEDM_FSM_POWERUP 0x9
141 #define SDEDM_FSM_WRITESTART1 0xa
142 #define SDEDM_FSM_WRITESTART2 0xb
143 #define SDEDM_FSM_GENPULSES 0xc
144 #define SDEDM_FSM_WRITEWAIT2 0xd
145 #define SDEDM_FSM_STARTPOWDOWN 0xf
146
147 #define SDDATA_FIFO_WORDS 16
148
149 #define FIFO_READ_THRESHOLD 4
150 #define FIFO_WRITE_THRESHOLD 4
151 #define SDDATA_FIFO_PIO_BURST 8
152
153 #define PIO_THRESHOLD 1 /* Maximum block count for PIO (0 = always DMA) */
154
155 struct bcm2835_host {
156 spinlock_t lock;
157 struct mutex mutex;
158
159 void __iomem *ioaddr;
160 u32 phys_addr;
161
162 struct mmc_host *mmc;
163 struct platform_device *pdev;
164
165 int clock; /* Current clock speed */
166 unsigned int max_clk; /* Max possible freq */
167 struct work_struct dma_work;
168 struct delayed_work timeout_work; /* Timer for timeouts */
169 struct sg_mapping_iter sg_miter; /* SG state for PIO */
170 unsigned int blocks; /* remaining PIO blocks */
171 int irq; /* Device IRQ */
172
173 u32 ns_per_fifo_word;
174
175 /* cached registers */
176 u32 hcfg;
177 u32 cdiv;
178
179 struct mmc_request *mrq; /* Current request */
180 struct mmc_command *cmd; /* Current command */
181 struct mmc_data *data; /* Current data request */
182 bool data_complete:1;/* Data finished before cmd */
183 bool use_busy:1; /* Wait for busy interrupt */
184 bool use_sbc:1; /* Send CMD23 */
185
186 /* for threaded irq handler */
187 bool irq_block;
188 bool irq_busy;
189 bool irq_data;
190
191 /* DMA part */
192 struct dma_chan *dma_chan_rxtx;
193 struct dma_chan *dma_chan;
194 struct dma_slave_config dma_cfg_rx;
195 struct dma_slave_config dma_cfg_tx;
196 struct dma_async_tx_descriptor *dma_desc;
197 u32 dma_dir;
198 u32 drain_words;
199 struct page *drain_page;
200 u32 drain_offset;
201 bool use_dma;
202 };
203
204 static void bcm2835_dumpcmd(struct bcm2835_host *host, struct mmc_command *cmd,
205 const char *label)
206 {
207 struct device *dev = &host->pdev->dev;
208
209 if (!cmd)
210 return;
211
212 dev_dbg(dev, "%c%s op %d arg 0x%x flags 0x%x - resp %08x %08x %08x %08x, err %d\n",
213 (cmd == host->cmd) ? '>' : ' ',
214 label, cmd->opcode, cmd->arg, cmd->flags,
215 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3],
216 cmd->error);
217 }
218
219 static void bcm2835_dumpregs(struct bcm2835_host *host)
220 {
221 struct mmc_request *mrq = host->mrq;
222 struct device *dev = &host->pdev->dev;
223
224 if (mrq) {
225 bcm2835_dumpcmd(host, mrq->sbc, "sbc");
226 bcm2835_dumpcmd(host, mrq->cmd, "cmd");
227 if (mrq->data) {
228 dev_dbg(dev, "data blocks %x blksz %x - err %d\n",
229 mrq->data->blocks,
230 mrq->data->blksz,
231 mrq->data->error);
232 }
233 bcm2835_dumpcmd(host, mrq->stop, "stop");
234 }
235
236 dev_dbg(dev, "=========== REGISTER DUMP ===========\n");
237 dev_dbg(dev, "SDCMD 0x%08x\n", readl(host->ioaddr + SDCMD));
238 dev_dbg(dev, "SDARG 0x%08x\n", readl(host->ioaddr + SDARG));
239 dev_dbg(dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT));
240 dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV));
241 dev_dbg(dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0));
242 dev_dbg(dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1));
243 dev_dbg(dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2));
244 dev_dbg(dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3));
245 dev_dbg(dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS));
246 dev_dbg(dev, "SDVDD 0x%08x\n", readl(host->ioaddr + SDVDD));
247 dev_dbg(dev, "SDEDM 0x%08x\n", readl(host->ioaddr + SDEDM));
248 dev_dbg(dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG));
249 dev_dbg(dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT));
250 dev_dbg(dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC));
251 dev_dbg(dev, "===========================================\n");
252 }
253
254 static void bcm2835_reset_internal(struct bcm2835_host *host)
255 {
256 u32 temp;
257
258 writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD);
259 writel(0, host->ioaddr + SDCMD);
260 writel(0, host->ioaddr + SDARG);
261 writel(0xf00000, host->ioaddr + SDTOUT);
262 writel(0, host->ioaddr + SDCDIV);
263 writel(0x7f8, host->ioaddr + SDHSTS); /* Write 1s to clear */
264 writel(0, host->ioaddr + SDHCFG);
265 writel(0, host->ioaddr + SDHBCT);
266 writel(0, host->ioaddr + SDHBLC);
267
268 /* Limit fifo usage due to silicon bug */
269 temp = readl(host->ioaddr + SDEDM);
270 temp &= ~((SDEDM_THRESHOLD_MASK << SDEDM_READ_THRESHOLD_SHIFT) |
271 (SDEDM_THRESHOLD_MASK << SDEDM_WRITE_THRESHOLD_SHIFT));
272 temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) |
273 (FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT);
274 writel(temp, host->ioaddr + SDEDM);
275 msleep(20);
276 writel(SDVDD_POWER_ON, host->ioaddr + SDVDD);
277 msleep(20);
278 host->clock = 0;
279 writel(host->hcfg, host->ioaddr + SDHCFG);
280 writel(host->cdiv, host->ioaddr + SDCDIV);
281 }
282
283 static void bcm2835_reset(struct mmc_host *mmc)
284 {
285 struct bcm2835_host *host = mmc_priv(mmc);
286
287 if (host->dma_chan)
288 dmaengine_terminate_sync(host->dma_chan);
289 host->dma_chan = NULL;
290 bcm2835_reset_internal(host);
291 }
292
293 static void bcm2835_finish_command(struct bcm2835_host *host);
294
295 static void bcm2835_wait_transfer_complete(struct bcm2835_host *host)
296 {
297 int timediff;
298 u32 alternate_idle;
299
300 alternate_idle = (host->mrq->data->flags & MMC_DATA_READ) ?
301 SDEDM_FSM_READWAIT : SDEDM_FSM_WRITESTART1;
302
303 timediff = 0;
304
305 while (1) {
306 u32 edm, fsm;
307
308 edm = readl(host->ioaddr + SDEDM);
309 fsm = edm & SDEDM_FSM_MASK;
310
311 if ((fsm == SDEDM_FSM_IDENTMODE) ||
312 (fsm == SDEDM_FSM_DATAMODE))
313 break;
314 if (fsm == alternate_idle) {
315 writel(edm | SDEDM_FORCE_DATA_MODE,
316 host->ioaddr + SDEDM);
317 break;
318 }
319
320 timediff++;
321 if (timediff == 100000) {
322 dev_err(&host->pdev->dev,
323 "wait_transfer_complete - still waiting after %d retries\n",
324 timediff);
325 bcm2835_dumpregs(host);
326 host->mrq->data->error = -ETIMEDOUT;
327 return;
328 }
329 cpu_relax();
330 }
331 }
332
333 static void bcm2835_dma_complete(void *param)
334 {
335 struct bcm2835_host *host = param;
336
337 schedule_work(&host->dma_work);
338 }
339
340 static void bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read)
341 {
342 unsigned long flags;
343 size_t blksize;
344 unsigned long wait_max;
345
346 blksize = host->data->blksz;
347
348 wait_max = jiffies + msecs_to_jiffies(500);
349
350 local_irq_save(flags);
351
352 while (blksize) {
353 int copy_words;
354 u32 hsts = 0;
355 size_t len;
356 u32 *buf;
357
358 if (!sg_miter_next(&host->sg_miter)) {
359 host->data->error = -EINVAL;
360 break;
361 }
362
363 len = min(host->sg_miter.length, blksize);
364 if (len % 4) {
365 host->data->error = -EINVAL;
366 break;
367 }
368
369 blksize -= len;
370 host->sg_miter.consumed = len;
371
372 buf = (u32 *)host->sg_miter.addr;
373
374 copy_words = len / 4;
375
376 while (copy_words) {
377 int burst_words, words;
378 u32 edm;
379
380 burst_words = min(SDDATA_FIFO_PIO_BURST, copy_words);
381 edm = readl(host->ioaddr + SDEDM);
382 if (is_read)
383 words = ((edm >> 4) & 0x1f);
384 else
385 words = SDDATA_FIFO_WORDS - ((edm >> 4) & 0x1f);
386
387 if (words < burst_words) {
388 int fsm_state = (edm & SDEDM_FSM_MASK);
389 struct device *dev = &host->pdev->dev;
390
391 if ((is_read &&
392 (fsm_state != SDEDM_FSM_READDATA &&
393 fsm_state != SDEDM_FSM_READWAIT &&
394 fsm_state != SDEDM_FSM_READCRC)) ||
395 (!is_read &&
396 (fsm_state != SDEDM_FSM_WRITEDATA &&
397 fsm_state != SDEDM_FSM_WRITESTART1 &&
398 fsm_state != SDEDM_FSM_WRITESTART2))) {
399 hsts = readl(host->ioaddr + SDHSTS);
400 dev_err(dev, "fsm %x, hsts %08x\n",
401 fsm_state, hsts);
402 if (hsts & SDHSTS_ERROR_MASK)
403 break;
404 }
405
406 if (time_after(jiffies, wait_max)) {
407 dev_err(dev, "PIO %s timeout - EDM %08x\n",
408 is_read ? "read" : "write",
409 edm);
410 hsts = SDHSTS_REW_TIME_OUT;
411 break;
412 }
413 ndelay((burst_words - words) *
414 host->ns_per_fifo_word);
415 continue;
416 } else if (words > copy_words) {
417 words = copy_words;
418 }
419
420 copy_words -= words;
421
422 while (words) {
423 if (is_read)
424 *(buf++) = readl(host->ioaddr + SDDATA);
425 else
426 writel(*(buf++), host->ioaddr + SDDATA);
427 words--;
428 }
429 }
430
431 if (hsts & SDHSTS_ERROR_MASK)
432 break;
433 }
434
435 sg_miter_stop(&host->sg_miter);
436
437 local_irq_restore(flags);
438 }
439
440 static void bcm2835_transfer_pio(struct bcm2835_host *host)
441 {
442 struct device *dev = &host->pdev->dev;
443 u32 sdhsts;
444 bool is_read;
445
446 is_read = (host->data->flags & MMC_DATA_READ) != 0;
447 bcm2835_transfer_block_pio(host, is_read);
448
449 sdhsts = readl(host->ioaddr + SDHSTS);
450 if (sdhsts & (SDHSTS_CRC16_ERROR |
451 SDHSTS_CRC7_ERROR |
452 SDHSTS_FIFO_ERROR)) {
453 dev_err(dev, "%s transfer error - HSTS %08x\n",
454 is_read ? "read" : "write", sdhsts);
455 host->data->error = -EILSEQ;
456 } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT |
457 SDHSTS_REW_TIME_OUT))) {
458 dev_err(dev, "%s timeout error - HSTS %08x\n",
459 is_read ? "read" : "write", sdhsts);
460 host->data->error = -ETIMEDOUT;
461 }
462 }
463
464 static
465 void bcm2835_prepare_dma(struct bcm2835_host *host, struct mmc_data *data)
466 {
467 int len, dir_data, dir_slave;
468 struct dma_async_tx_descriptor *desc = NULL;
469 struct dma_chan *dma_chan;
470
471 dma_chan = host->dma_chan_rxtx;
472 if (data->flags & MMC_DATA_READ) {
473 dir_data = DMA_FROM_DEVICE;
474 dir_slave = DMA_DEV_TO_MEM;
475 } else {
476 dir_data = DMA_TO_DEVICE;
477 dir_slave = DMA_MEM_TO_DEV;
478 }
479
480 /* The block doesn't manage the FIFO DREQs properly for
481 * multi-block transfers, so don't attempt to DMA the final
482 * few words. Unfortunately this requires the final sg entry
483 * to be trimmed. N.B. This code demands that the overspill
484 * is contained in a single sg entry.
485 */
486
487 host->drain_words = 0;
488 if ((data->blocks > 1) && (dir_data == DMA_FROM_DEVICE)) {
489 struct scatterlist *sg;
490 u32 len;
491 int i;
492
493 len = min((u32)(FIFO_READ_THRESHOLD - 1) * 4,
494 (u32)data->blocks * data->blksz);
495
496 for_each_sg(data->sg, sg, data->sg_len, i) {
497 if (sg_is_last(sg)) {
498 WARN_ON(sg->length < len);
499 sg->length -= len;
500 host->drain_page = sg_page(sg);
501 host->drain_offset = sg->offset + sg->length;
502 }
503 }
504 host->drain_words = len / 4;
505 }
506
507 /* The parameters have already been validated, so this will not fail */
508 (void)dmaengine_slave_config(dma_chan,
509 (dir_data == DMA_FROM_DEVICE) ?
510 &host->dma_cfg_rx :
511 &host->dma_cfg_tx);
512
513 len = dma_map_sg(dma_chan->device->dev, data->sg, data->sg_len,
514 dir_data);
515
516 if (len > 0) {
517 desc = dmaengine_prep_slave_sg(dma_chan, data->sg,
518 len, dir_slave,
519 DMA_PREP_INTERRUPT |
520 DMA_CTRL_ACK);
521 }
522
523 if (desc) {
524 desc->callback = bcm2835_dma_complete;
525 desc->callback_param = host;
526 host->dma_desc = desc;
527 host->dma_chan = dma_chan;
528 host->dma_dir = dir_data;
529 }
530 }
531
532 static void bcm2835_start_dma(struct bcm2835_host *host)
533 {
534 dmaengine_submit(host->dma_desc);
535 dma_async_issue_pending(host->dma_chan);
536 }
537
538 static void bcm2835_set_transfer_irqs(struct bcm2835_host *host)
539 {
540 u32 all_irqs = SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN |
541 SDHCFG_BUSY_IRPT_EN;
542
543 if (host->dma_desc) {
544 host->hcfg = (host->hcfg & ~all_irqs) |
545 SDHCFG_BUSY_IRPT_EN;
546 } else {
547 host->hcfg = (host->hcfg & ~all_irqs) |
548 SDHCFG_DATA_IRPT_EN |
549 SDHCFG_BUSY_IRPT_EN;
550 }
551
552 writel(host->hcfg, host->ioaddr + SDHCFG);
553 }
554
555 static
556 void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd)
557 {
558 struct mmc_data *data = cmd->data;
559
560 WARN_ON(host->data);
561
562 host->data = data;
563 if (!data)
564 return;
565
566 host->data_complete = false;
567 host->data->bytes_xfered = 0;
568
569 if (!host->dma_desc) {
570 /* Use PIO */
571 int flags = SG_MITER_ATOMIC;
572
573 if (data->flags & MMC_DATA_READ)
574 flags |= SG_MITER_TO_SG;
575 else
576 flags |= SG_MITER_FROM_SG;
577 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
578 host->blocks = data->blocks;
579 }
580
581 bcm2835_set_transfer_irqs(host);
582
583 writel(data->blksz, host->ioaddr + SDHBCT);
584 writel(data->blocks, host->ioaddr + SDHBLC);
585 }
586
587 static u32 bcm2835_read_wait_sdcmd(struct bcm2835_host *host, u32 max_ms)
588 {
589 struct device *dev = &host->pdev->dev;
590 u32 value;
591 int ret;
592
593 ret = readl_poll_timeout(host->ioaddr + SDCMD, value,
594 !(value & SDCMD_NEW_FLAG), 1, 10);
595 if (ret == -ETIMEDOUT)
596 /* if it takes a while make poll interval bigger */
597 ret = readl_poll_timeout(host->ioaddr + SDCMD, value,
598 !(value & SDCMD_NEW_FLAG),
599 10, max_ms * 1000);
600 if (ret == -ETIMEDOUT)
601 dev_err(dev, "%s: timeout (%d ms)\n", __func__, max_ms);
602
603 return value;
604 }
605
606 static void bcm2835_finish_request(struct bcm2835_host *host)
607 {
608 struct dma_chan *terminate_chan = NULL;
609 struct mmc_request *mrq;
610
611 cancel_delayed_work(&host->timeout_work);
612
613 mrq = host->mrq;
614
615 host->mrq = NULL;
616 host->cmd = NULL;
617 host->data = NULL;
618
619 host->dma_desc = NULL;
620 terminate_chan = host->dma_chan;
621 host->dma_chan = NULL;
622
623 if (terminate_chan) {
624 int err = dmaengine_terminate_all(terminate_chan);
625
626 if (err)
627 dev_err(&host->pdev->dev,
628 "failed to terminate DMA (%d)\n", err);
629 }
630
631 mmc_request_done(host->mmc, mrq);
632 }
633
634 static
635 bool bcm2835_send_command(struct bcm2835_host *host, struct mmc_command *cmd)
636 {
637 struct device *dev = &host->pdev->dev;
638 u32 sdcmd, sdhsts;
639 unsigned long timeout;
640
641 WARN_ON(host->cmd);
642
643 sdcmd = bcm2835_read_wait_sdcmd(host, 100);
644 if (sdcmd & SDCMD_NEW_FLAG) {
645 dev_err(dev, "previous command never completed.\n");
646 bcm2835_dumpregs(host);
647 cmd->error = -EILSEQ;
648 bcm2835_finish_request(host);
649 return false;
650 }
651
652 if (!cmd->data && cmd->busy_timeout > 9000)
653 timeout = DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
654 else
655 timeout = 10 * HZ;
656 schedule_delayed_work(&host->timeout_work, timeout);
657
658 host->cmd = cmd;
659
660 /* Clear any error flags */
661 sdhsts = readl(host->ioaddr + SDHSTS);
662 if (sdhsts & SDHSTS_ERROR_MASK)
663 writel(sdhsts, host->ioaddr + SDHSTS);
664
665 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
666 dev_err(dev, "unsupported response type!\n");
667 cmd->error = -EINVAL;
668 bcm2835_finish_request(host);
669 return false;
670 }
671
672 bcm2835_prepare_data(host, cmd);
673
674 writel(cmd->arg, host->ioaddr + SDARG);
675
676 sdcmd = cmd->opcode & SDCMD_CMD_MASK;
677
678 host->use_busy = false;
679 if (!(cmd->flags & MMC_RSP_PRESENT)) {
680 sdcmd |= SDCMD_NO_RESPONSE;
681 } else {
682 if (cmd->flags & MMC_RSP_136)
683 sdcmd |= SDCMD_LONG_RESPONSE;
684 if (cmd->flags & MMC_RSP_BUSY) {
685 sdcmd |= SDCMD_BUSYWAIT;
686 host->use_busy = true;
687 }
688 }
689
690 if (cmd->data) {
691 if (cmd->data->flags & MMC_DATA_WRITE)
692 sdcmd |= SDCMD_WRITE_CMD;
693 if (cmd->data->flags & MMC_DATA_READ)
694 sdcmd |= SDCMD_READ_CMD;
695 }
696
697 writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD);
698
699 return true;
700 }
701
702 static void bcm2835_transfer_complete(struct bcm2835_host *host)
703 {
704 struct mmc_data *data;
705
706 WARN_ON(!host->data_complete);
707
708 data = host->data;
709 host->data = NULL;
710
711 /* Need to send CMD12 if -
712 * a) open-ended multiblock transfer (no CMD23)
713 * b) error in multiblock transfer
714 */
715 if (host->mrq->stop && (data->error || !host->use_sbc)) {
716 if (bcm2835_send_command(host, host->mrq->stop)) {
717 /* No busy, so poll for completion */
718 if (!host->use_busy)
719 bcm2835_finish_command(host);
720 }
721 } else {
722 bcm2835_wait_transfer_complete(host);
723 bcm2835_finish_request(host);
724 }
725 }
726
727 static void bcm2835_finish_data(struct bcm2835_host *host)
728 {
729 struct device *dev = &host->pdev->dev;
730 struct mmc_data *data;
731
732 data = host->data;
733
734 host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN);
735 writel(host->hcfg, host->ioaddr + SDHCFG);
736
737 data->bytes_xfered = data->error ? 0 : (data->blksz * data->blocks);
738
739 host->data_complete = true;
740
741 if (host->cmd) {
742 /* Data managed to finish before the
743 * command completed. Make sure we do
744 * things in the proper order.
745 */
746 dev_dbg(dev, "Finished early - HSTS %08x\n",
747 readl(host->ioaddr + SDHSTS));
748 } else {
749 bcm2835_transfer_complete(host);
750 }
751 }
752
753 static void bcm2835_finish_command(struct bcm2835_host *host)
754 {
755 struct device *dev = &host->pdev->dev;
756 struct mmc_command *cmd = host->cmd;
757 u32 sdcmd;
758
759 sdcmd = bcm2835_read_wait_sdcmd(host, 100);
760
761 /* Check for errors */
762 if (sdcmd & SDCMD_NEW_FLAG) {
763 dev_err(dev, "command never completed.\n");
764 bcm2835_dumpregs(host);
765 host->cmd->error = -EIO;
766 bcm2835_finish_request(host);
767 return;
768 } else if (sdcmd & SDCMD_FAIL_FLAG) {
769 u32 sdhsts = readl(host->ioaddr + SDHSTS);
770
771 /* Clear the errors */
772 writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS);
773
774 if (!(sdhsts & SDHSTS_CRC7_ERROR) ||
775 (host->cmd->opcode != MMC_SEND_OP_COND)) {
776 u32 edm, fsm;
777
778 if (sdhsts & SDHSTS_CMD_TIME_OUT) {
779 host->cmd->error = -ETIMEDOUT;
780 } else {
781 dev_err(dev, "unexpected command %d error\n",
782 host->cmd->opcode);
783 bcm2835_dumpregs(host);
784 host->cmd->error = -EILSEQ;
785 }
786 edm = readl(host->ioaddr + SDEDM);
787 fsm = edm & SDEDM_FSM_MASK;
788 if (fsm == SDEDM_FSM_READWAIT ||
789 fsm == SDEDM_FSM_WRITESTART1)
790 /* Kick the FSM out of its wait */
791 writel(edm | SDEDM_FORCE_DATA_MODE,
792 host->ioaddr + SDEDM);
793 bcm2835_finish_request(host);
794 return;
795 }
796 }
797
798 if (cmd->flags & MMC_RSP_PRESENT) {
799 if (cmd->flags & MMC_RSP_136) {
800 int i;
801
802 for (i = 0; i < 4; i++) {
803 cmd->resp[3 - i] =
804 readl(host->ioaddr + SDRSP0 + i * 4);
805 }
806 } else {
807 cmd->resp[0] = readl(host->ioaddr + SDRSP0);
808 }
809 }
810
811 if (cmd == host->mrq->sbc) {
812 /* Finished CMD23, now send actual command. */
813 host->cmd = NULL;
814 if (bcm2835_send_command(host, host->mrq->cmd)) {
815 if (host->data && host->dma_desc)
816 /* DMA transfer starts now, PIO starts
817 * after irq
818 */
819 bcm2835_start_dma(host);
820
821 if (!host->use_busy)
822 bcm2835_finish_command(host);
823 }
824 } else if (cmd == host->mrq->stop) {
825 /* Finished CMD12 */
826 bcm2835_finish_request(host);
827 } else {
828 /* Processed actual command. */
829 host->cmd = NULL;
830 if (!host->data)
831 bcm2835_finish_request(host);
832 else if (host->data_complete)
833 bcm2835_transfer_complete(host);
834 }
835 }
836
837 static void bcm2835_timeout(struct work_struct *work)
838 {
839 struct delayed_work *d = to_delayed_work(work);
840 struct bcm2835_host *host =
841 container_of(d, struct bcm2835_host, timeout_work);
842 struct device *dev = &host->pdev->dev;
843
844 mutex_lock(&host->mutex);
845
846 if (host->mrq) {
847 dev_err(dev, "timeout waiting for hardware interrupt.\n");
848 bcm2835_dumpregs(host);
849
850 bcm2835_reset(host->mmc);
851
852 if (host->data) {
853 host->data->error = -ETIMEDOUT;
854 bcm2835_finish_data(host);
855 } else {
856 if (host->cmd)
857 host->cmd->error = -ETIMEDOUT;
858 else
859 host->mrq->cmd->error = -ETIMEDOUT;
860
861 bcm2835_finish_request(host);
862 }
863 }
864
865 mutex_unlock(&host->mutex);
866 }
867
868 static bool bcm2835_check_cmd_error(struct bcm2835_host *host, u32 intmask)
869 {
870 struct device *dev = &host->pdev->dev;
871
872 if (!(intmask & SDHSTS_ERROR_MASK))
873 return false;
874
875 if (!host->cmd)
876 return true;
877
878 dev_err(dev, "sdhost_busy_irq: intmask %08x\n", intmask);
879 if (intmask & SDHSTS_CRC7_ERROR) {
880 host->cmd->error = -EILSEQ;
881 } else if (intmask & (SDHSTS_CRC16_ERROR |
882 SDHSTS_FIFO_ERROR)) {
883 if (host->mrq->data)
884 host->mrq->data->error = -EILSEQ;
885 else
886 host->cmd->error = -EILSEQ;
887 } else if (intmask & SDHSTS_REW_TIME_OUT) {
888 if (host->mrq->data)
889 host->mrq->data->error = -ETIMEDOUT;
890 else
891 host->cmd->error = -ETIMEDOUT;
892 } else if (intmask & SDHSTS_CMD_TIME_OUT) {
893 host->cmd->error = -ETIMEDOUT;
894 }
895 bcm2835_dumpregs(host);
896 return true;
897 }
898
899 static void bcm2835_check_data_error(struct bcm2835_host *host, u32 intmask)
900 {
901 if (!host->data)
902 return;
903 if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_FIFO_ERROR))
904 host->data->error = -EILSEQ;
905 if (intmask & SDHSTS_REW_TIME_OUT)
906 host->data->error = -ETIMEDOUT;
907 }
908
909 static void bcm2835_busy_irq(struct bcm2835_host *host)
910 {
911 if (WARN_ON(!host->cmd)) {
912 bcm2835_dumpregs(host);
913 return;
914 }
915
916 if (WARN_ON(!host->use_busy)) {
917 bcm2835_dumpregs(host);
918 return;
919 }
920 host->use_busy = false;
921
922 bcm2835_finish_command(host);
923 }
924
925 static void bcm2835_data_irq(struct bcm2835_host *host, u32 intmask)
926 {
927 /* There are no dedicated data/space available interrupt
928 * status bits, so it is necessary to use the single shared
929 * data/space available FIFO status bits. It is therefore not
930 * an error to get here when there is no data transfer in
931 * progress.
932 */
933 if (!host->data)
934 return;
935
936 bcm2835_check_data_error(host, intmask);
937 if (host->data->error)
938 goto finished;
939
940 if (host->data->flags & MMC_DATA_WRITE) {
941 /* Use the block interrupt for writes after the first block */
942 host->hcfg &= ~(SDHCFG_DATA_IRPT_EN);
943 host->hcfg |= SDHCFG_BLOCK_IRPT_EN;
944 writel(host->hcfg, host->ioaddr + SDHCFG);
945 bcm2835_transfer_pio(host);
946 } else {
947 bcm2835_transfer_pio(host);
948 host->blocks--;
949 if ((host->blocks == 0) || host->data->error)
950 goto finished;
951 }
952 return;
953
954 finished:
955 host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN);
956 writel(host->hcfg, host->ioaddr + SDHCFG);
957 }
958
959 static void bcm2835_data_threaded_irq(struct bcm2835_host *host)
960 {
961 if (!host->data)
962 return;
963 if ((host->blocks == 0) || host->data->error)
964 bcm2835_finish_data(host);
965 }
966
967 static void bcm2835_block_irq(struct bcm2835_host *host)
968 {
969 if (WARN_ON(!host->data)) {
970 bcm2835_dumpregs(host);
971 return;
972 }
973
974 if (!host->dma_desc) {
975 WARN_ON(!host->blocks);
976 if (host->data->error || (--host->blocks == 0))
977 bcm2835_finish_data(host);
978 else
979 bcm2835_transfer_pio(host);
980 } else if (host->data->flags & MMC_DATA_WRITE) {
981 bcm2835_finish_data(host);
982 }
983 }
984
985 static irqreturn_t bcm2835_irq(int irq, void *dev_id)
986 {
987 irqreturn_t result = IRQ_NONE;
988 struct bcm2835_host *host = dev_id;
989 u32 intmask;
990
991 spin_lock(&host->lock);
992
993 intmask = readl(host->ioaddr + SDHSTS);
994
995 writel(SDHSTS_BUSY_IRPT |
996 SDHSTS_BLOCK_IRPT |
997 SDHSTS_SDIO_IRPT |
998 SDHSTS_DATA_FLAG,
999 host->ioaddr + SDHSTS);
1000
1001 if (intmask & SDHSTS_BLOCK_IRPT) {
1002 bcm2835_check_data_error(host, intmask);
1003 host->irq_block = true;
1004 result = IRQ_WAKE_THREAD;
1005 }
1006
1007 if (intmask & SDHSTS_BUSY_IRPT) {
1008 if (!bcm2835_check_cmd_error(host, intmask)) {
1009 host->irq_busy = true;
1010 result = IRQ_WAKE_THREAD;
1011 } else {
1012 result = IRQ_HANDLED;
1013 }
1014 }
1015
1016 /* There is no true data interrupt status bit, so it is
1017 * necessary to qualify the data flag with the interrupt
1018 * enable bit.
1019 */
1020 if ((intmask & SDHSTS_DATA_FLAG) &&
1021 (host->hcfg & SDHCFG_DATA_IRPT_EN)) {
1022 bcm2835_data_irq(host, intmask);
1023 host->irq_data = true;
1024 result = IRQ_WAKE_THREAD;
1025 }
1026
1027 spin_unlock(&host->lock);
1028
1029 return result;
1030 }
1031
1032 static irqreturn_t bcm2835_threaded_irq(int irq, void *dev_id)
1033 {
1034 struct bcm2835_host *host = dev_id;
1035 unsigned long flags;
1036 bool block, busy, data;
1037
1038 spin_lock_irqsave(&host->lock, flags);
1039
1040 block = host->irq_block;
1041 busy = host->irq_busy;
1042 data = host->irq_data;
1043 host->irq_block = false;
1044 host->irq_busy = false;
1045 host->irq_data = false;
1046
1047 spin_unlock_irqrestore(&host->lock, flags);
1048
1049 mutex_lock(&host->mutex);
1050
1051 if (block)
1052 bcm2835_block_irq(host);
1053 if (busy)
1054 bcm2835_busy_irq(host);
1055 if (data)
1056 bcm2835_data_threaded_irq(host);
1057
1058 mutex_unlock(&host->mutex);
1059
1060 return IRQ_HANDLED;
1061 }
1062
1063 static void bcm2835_dma_complete_work(struct work_struct *work)
1064 {
1065 struct bcm2835_host *host =
1066 container_of(work, struct bcm2835_host, dma_work);
1067 struct mmc_data *data = host->data;
1068
1069 mutex_lock(&host->mutex);
1070
1071 if (host->dma_chan) {
1072 dma_unmap_sg(host->dma_chan->device->dev,
1073 data->sg, data->sg_len,
1074 host->dma_dir);
1075
1076 host->dma_chan = NULL;
1077 }
1078
1079 if (host->drain_words) {
1080 unsigned long flags;
1081 void *page;
1082 u32 *buf;
1083
1084 if (host->drain_offset & PAGE_MASK) {
1085 host->drain_page += host->drain_offset >> PAGE_SHIFT;
1086 host->drain_offset &= ~PAGE_MASK;
1087 }
1088 local_irq_save(flags);
1089 page = kmap_atomic(host->drain_page);
1090 buf = page + host->drain_offset;
1091
1092 while (host->drain_words) {
1093 u32 edm = readl(host->ioaddr + SDEDM);
1094
1095 if ((edm >> 4) & 0x1f)
1096 *(buf++) = readl(host->ioaddr + SDDATA);
1097 host->drain_words--;
1098 }
1099
1100 kunmap_atomic(page);
1101 local_irq_restore(flags);
1102 }
1103
1104 bcm2835_finish_data(host);
1105
1106 mutex_unlock(&host->mutex);
1107 }
1108
1109 static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock)
1110 {
1111 int div;
1112
1113 /* The SDCDIV register has 11 bits, and holds (div - 2). But
1114 * in data mode the max is 50MHz wihout a minimum, and only
1115 * the bottom 3 bits are used. Since the switch over is
1116 * automatic (unless we have marked the card as slow...),
1117 * chosen values have to make sense in both modes. Ident mode
1118 * must be 100-400KHz, so can range check the requested
1119 * clock. CMD15 must be used to return to data mode, so this
1120 * can be monitored.
1121 *
1122 * clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz
1123 * 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz
1124 *
1125 * 623->400KHz/27.8MHz
1126 * reset value (507)->491159/50MHz
1127 *
1128 * BUT, the 3-bit clock divisor in data mode is too small if
1129 * the core clock is higher than 250MHz, so instead use the
1130 * SLOW_CARD configuration bit to force the use of the ident
1131 * clock divisor at all times.
1132 */
1133
1134 if (clock < 100000) {
1135 /* Can't stop the clock, but make it as slow as possible
1136 * to show willing
1137 */
1138 host->cdiv = SDCDIV_MAX_CDIV;
1139 writel(host->cdiv, host->ioaddr + SDCDIV);
1140 return;
1141 }
1142
1143 div = host->max_clk / clock;
1144 if (div < 2)
1145 div = 2;
1146 if ((host->max_clk / div) > clock)
1147 div++;
1148 div -= 2;
1149
1150 if (div > SDCDIV_MAX_CDIV)
1151 div = SDCDIV_MAX_CDIV;
1152
1153 clock = host->max_clk / (div + 2);
1154 host->mmc->actual_clock = clock;
1155
1156 /* Calibrate some delays */
1157
1158 host->ns_per_fifo_word = (1000000000 / clock) *
1159 ((host->mmc->caps & MMC_CAP_4_BIT_DATA) ? 8 : 32);
1160
1161 host->cdiv = div;
1162 writel(host->cdiv, host->ioaddr + SDCDIV);
1163
1164 /* Set the timeout to 500ms */
1165 writel(host->mmc->actual_clock / 2, host->ioaddr + SDTOUT);
1166 }
1167
1168 static void bcm2835_request(struct mmc_host *mmc, struct mmc_request *mrq)
1169 {
1170 struct bcm2835_host *host = mmc_priv(mmc);
1171 struct device *dev = &host->pdev->dev;
1172 u32 edm, fsm;
1173
1174 /* Reset the error statuses in case this is a retry */
1175 if (mrq->sbc)
1176 mrq->sbc->error = 0;
1177 if (mrq->cmd)
1178 mrq->cmd->error = 0;
1179 if (mrq->data)
1180 mrq->data->error = 0;
1181 if (mrq->stop)
1182 mrq->stop->error = 0;
1183
1184 if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
1185 dev_err(dev, "unsupported block size (%d bytes)\n",
1186 mrq->data->blksz);
1187
1188 if (mrq->cmd)
1189 mrq->cmd->error = -EINVAL;
1190
1191 mmc_request_done(mmc, mrq);
1192 return;
1193 }
1194
1195 if (host->use_dma && mrq->data && (mrq->data->blocks > PIO_THRESHOLD))
1196 bcm2835_prepare_dma(host, mrq->data);
1197
1198 mutex_lock(&host->mutex);
1199
1200 WARN_ON(host->mrq);
1201 host->mrq = mrq;
1202
1203 edm = readl(host->ioaddr + SDEDM);
1204 fsm = edm & SDEDM_FSM_MASK;
1205
1206 if ((fsm != SDEDM_FSM_IDENTMODE) &&
1207 (fsm != SDEDM_FSM_DATAMODE)) {
1208 dev_err(dev, "previous command (%d) not complete (EDM %08x)\n",
1209 readl(host->ioaddr + SDCMD) & SDCMD_CMD_MASK,
1210 edm);
1211 bcm2835_dumpregs(host);
1212
1213 if (mrq->cmd)
1214 mrq->cmd->error = -EILSEQ;
1215
1216 bcm2835_finish_request(host);
1217 mutex_unlock(&host->mutex);
1218 return;
1219 }
1220
1221 host->use_sbc = !!mrq->sbc && host->mrq->data &&
1222 (host->mrq->data->flags & MMC_DATA_READ);
1223 if (host->use_sbc) {
1224 if (bcm2835_send_command(host, mrq->sbc)) {
1225 if (!host->use_busy)
1226 bcm2835_finish_command(host);
1227 }
1228 } else if (mrq->cmd && bcm2835_send_command(host, mrq->cmd)) {
1229 if (host->data && host->dma_desc) {
1230 /* DMA transfer starts now, PIO starts after irq */
1231 bcm2835_start_dma(host);
1232 }
1233
1234 if (!host->use_busy)
1235 bcm2835_finish_command(host);
1236 }
1237
1238 mutex_unlock(&host->mutex);
1239 }
1240
1241 static void bcm2835_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1242 {
1243 struct bcm2835_host *host = mmc_priv(mmc);
1244
1245 mutex_lock(&host->mutex);
1246
1247 if (!ios->clock || ios->clock != host->clock) {
1248 bcm2835_set_clock(host, ios->clock);
1249 host->clock = ios->clock;
1250 }
1251
1252 /* set bus width */
1253 host->hcfg &= ~SDHCFG_WIDE_EXT_BUS;
1254 if (ios->bus_width == MMC_BUS_WIDTH_4)
1255 host->hcfg |= SDHCFG_WIDE_EXT_BUS;
1256
1257 host->hcfg |= SDHCFG_WIDE_INT_BUS;
1258
1259 /* Disable clever clock switching, to cope with fast core clocks */
1260 host->hcfg |= SDHCFG_SLOW_CARD;
1261
1262 writel(host->hcfg, host->ioaddr + SDHCFG);
1263
1264 mutex_unlock(&host->mutex);
1265 }
1266
1267 static const struct mmc_host_ops bcm2835_ops = {
1268 .request = bcm2835_request,
1269 .set_ios = bcm2835_set_ios,
1270 .hw_reset = bcm2835_reset,
1271 };
1272
1273 static int bcm2835_add_host(struct bcm2835_host *host)
1274 {
1275 struct mmc_host *mmc = host->mmc;
1276 struct device *dev = &host->pdev->dev;
1277 char pio_limit_string[20];
1278 int ret;
1279
1280 if (!mmc->f_max || mmc->f_max > host->max_clk)
1281 mmc->f_max = host->max_clk;
1282 mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV;
1283
1284 mmc->max_busy_timeout = ~0 / (mmc->f_max / 1000);
1285
1286 dev_dbg(dev, "f_max %d, f_min %d, max_busy_timeout %d\n",
1287 mmc->f_max, mmc->f_min, mmc->max_busy_timeout);
1288
1289 /* host controller capabilities */
1290 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
1291 MMC_CAP_NEEDS_POLL | MMC_CAP_HW_RESET | MMC_CAP_ERASE |
1292 MMC_CAP_CMD23;
1293
1294 spin_lock_init(&host->lock);
1295 mutex_init(&host->mutex);
1296
1297 if (IS_ERR_OR_NULL(host->dma_chan_rxtx)) {
1298 dev_warn(dev, "unable to initialise DMA channel. Falling back to PIO\n");
1299 host->use_dma = false;
1300 } else {
1301 host->use_dma = true;
1302
1303 host->dma_cfg_tx.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1304 host->dma_cfg_tx.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1305 host->dma_cfg_tx.slave_id = 13; /* DREQ channel */
1306 host->dma_cfg_tx.direction = DMA_MEM_TO_DEV;
1307 host->dma_cfg_tx.src_addr = 0;
1308 host->dma_cfg_tx.dst_addr = host->phys_addr + SDDATA;
1309
1310 host->dma_cfg_rx.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1311 host->dma_cfg_rx.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1312 host->dma_cfg_rx.slave_id = 13; /* DREQ channel */
1313 host->dma_cfg_rx.direction = DMA_DEV_TO_MEM;
1314 host->dma_cfg_rx.src_addr = host->phys_addr + SDDATA;
1315 host->dma_cfg_rx.dst_addr = 0;
1316
1317 if (dmaengine_slave_config(host->dma_chan_rxtx,
1318 &host->dma_cfg_tx) != 0 ||
1319 dmaengine_slave_config(host->dma_chan_rxtx,
1320 &host->dma_cfg_rx) != 0)
1321 host->use_dma = false;
1322 }
1323
1324 mmc->max_segs = 128;
1325 mmc->max_req_size = 524288;
1326 mmc->max_seg_size = mmc->max_req_size;
1327 mmc->max_blk_size = 1024;
1328 mmc->max_blk_count = 65535;
1329
1330 /* report supported voltage ranges */
1331 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1332
1333 INIT_WORK(&host->dma_work, bcm2835_dma_complete_work);
1334 INIT_DELAYED_WORK(&host->timeout_work, bcm2835_timeout);
1335
1336 /* Set interrupt enables */
1337 host->hcfg = SDHCFG_BUSY_IRPT_EN;
1338
1339 bcm2835_reset_internal(host);
1340
1341 ret = request_threaded_irq(host->irq, bcm2835_irq,
1342 bcm2835_threaded_irq,
1343 0, mmc_hostname(mmc), host);
1344 if (ret) {
1345 dev_err(dev, "failed to request IRQ %d: %d\n", host->irq, ret);
1346 return ret;
1347 }
1348
1349 ret = mmc_add_host(mmc);
1350 if (ret) {
1351 free_irq(host->irq, host);
1352 return ret;
1353 }
1354
1355 pio_limit_string[0] = '\0';
1356 if (host->use_dma && (PIO_THRESHOLD > 0))
1357 sprintf(pio_limit_string, " (>%d)", PIO_THRESHOLD);
1358 dev_info(dev, "loaded - DMA %s%s\n",
1359 host->use_dma ? "enabled" : "disabled", pio_limit_string);
1360
1361 return 0;
1362 }
1363
1364 static int bcm2835_probe(struct platform_device *pdev)
1365 {
1366 struct device *dev = &pdev->dev;
1367 struct clk *clk;
1368 struct resource *iomem;
1369 struct bcm2835_host *host;
1370 struct mmc_host *mmc;
1371 const __be32 *regaddr_p;
1372 int ret;
1373
1374 dev_dbg(dev, "%s\n", __func__);
1375 mmc = mmc_alloc_host(sizeof(*host), dev);
1376 if (!mmc)
1377 return -ENOMEM;
1378
1379 mmc->ops = &bcm2835_ops;
1380 host = mmc_priv(mmc);
1381 host->mmc = mmc;
1382 host->pdev = pdev;
1383 spin_lock_init(&host->lock);
1384
1385 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1386 host->ioaddr = devm_ioremap_resource(dev, iomem);
1387 if (IS_ERR(host->ioaddr)) {
1388 ret = PTR_ERR(host->ioaddr);
1389 goto err;
1390 }
1391
1392 /* Parse OF address directly to get the physical address for
1393 * DMA to our registers.
1394 */
1395 regaddr_p = of_get_address(pdev->dev.of_node, 0, NULL, NULL);
1396 if (!regaddr_p) {
1397 dev_err(dev, "Can't get phys address\n");
1398 ret = -EINVAL;
1399 goto err;
1400 }
1401
1402 host->phys_addr = be32_to_cpup(regaddr_p);
1403
1404 host->dma_chan = NULL;
1405 host->dma_desc = NULL;
1406
1407 host->dma_chan_rxtx = dma_request_slave_channel(dev, "rx-tx");
1408
1409 clk = devm_clk_get(dev, NULL);
1410 if (IS_ERR(clk)) {
1411 ret = PTR_ERR(clk);
1412 if (ret != -EPROBE_DEFER)
1413 dev_err(dev, "could not get clk: %d\n", ret);
1414 goto err;
1415 }
1416
1417 host->max_clk = clk_get_rate(clk);
1418
1419 host->irq = platform_get_irq(pdev, 0);
1420 if (host->irq <= 0) {
1421 dev_err(dev, "get IRQ failed\n");
1422 ret = -EINVAL;
1423 goto err;
1424 }
1425
1426 ret = mmc_of_parse(mmc);
1427 if (ret)
1428 goto err;
1429
1430 ret = bcm2835_add_host(host);
1431 if (ret)
1432 goto err;
1433
1434 platform_set_drvdata(pdev, host);
1435
1436 dev_dbg(dev, "%s -> OK\n", __func__);
1437
1438 return 0;
1439
1440 err:
1441 dev_dbg(dev, "%s -> err %d\n", __func__, ret);
1442 if (host->dma_chan_rxtx)
1443 dma_release_channel(host->dma_chan_rxtx);
1444 mmc_free_host(mmc);
1445
1446 return ret;
1447 }
1448
1449 static int bcm2835_remove(struct platform_device *pdev)
1450 {
1451 struct bcm2835_host *host = platform_get_drvdata(pdev);
1452
1453 mmc_remove_host(host->mmc);
1454
1455 writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD);
1456
1457 free_irq(host->irq, host);
1458
1459 cancel_work_sync(&host->dma_work);
1460 cancel_delayed_work_sync(&host->timeout_work);
1461
1462 mmc_free_host(host->mmc);
1463 platform_set_drvdata(pdev, NULL);
1464
1465 return 0;
1466 }
1467
1468 static const struct of_device_id bcm2835_match[] = {
1469 { .compatible = "brcm,bcm2835-sdhost" },
1470 { }
1471 };
1472 MODULE_DEVICE_TABLE(of, bcm2835_match);
1473
1474 static struct platform_driver bcm2835_driver = {
1475 .probe = bcm2835_probe,
1476 .remove = bcm2835_remove,
1477 .driver = {
1478 .name = "sdhost-bcm2835",
1479 .of_match_table = bcm2835_match,
1480 },
1481 };
1482 module_platform_driver(bcm2835_driver);
1483
1484 MODULE_ALIAS("platform:sdhost-bcm2835");
1485 MODULE_DESCRIPTION("BCM2835 SDHost driver");
1486 MODULE_LICENSE("GPL v2");
1487 MODULE_AUTHOR("Phil Elwell");
Linux with added FPC-III support