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vt: vt_ioctl: fix VT_DISALLOCATE freeing in-use virtual console
[linux/fpc-iii.git] / drivers / mmc / host / meson-gx-mmc.c
blob72f34a58928ca6bd27fec902384d4a091e6b9ecf
1 /*
2 * Amlogic SD/eMMC driver for the GX/S905 family SoCs
3 *
4 * Copyright (c) 2016 BayLibre, SAS.
5 * Author: Kevin Hilman <khilman@baylibre.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution
19 * in the file called COPYING.
20 */
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/init.h>
24 #include <linux/delay.h>
25 #include <linux/device.h>
26 #include <linux/of_device.h>
27 #include <linux/platform_device.h>
28 #include <linux/ioport.h>
29 #include <linux/spinlock.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/sdio.h>
34 #include <linux/mmc/slot-gpio.h>
35 #include <linux/io.h>
36 #include <linux/clk.h>
37 #include <linux/clk-provider.h>
38 #include <linux/regulator/consumer.h>
39 #include <linux/reset.h>
40 #include <linux/interrupt.h>
41 #include <linux/bitfield.h>
42 #include <linux/pinctrl/consumer.h>
43
44 #define DRIVER_NAME "meson-gx-mmc"
45
46 #define SD_EMMC_CLOCK 0x0
47 #define CLK_DIV_MASK GENMASK(5, 0)
48 #define CLK_SRC_MASK GENMASK(7, 6)
49 #define CLK_CORE_PHASE_MASK GENMASK(9, 8)
50 #define CLK_TX_PHASE_MASK GENMASK(11, 10)
51 #define CLK_RX_PHASE_MASK GENMASK(13, 12)
52 #define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
53 #define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
54 #define CLK_V2_ALWAYS_ON BIT(24)
55
56 #define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
57 #define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
58 #define CLK_V3_ALWAYS_ON BIT(28)
59
60 #define CLK_DELAY_STEP_PS 200
61 #define CLK_PHASE_STEP 30
62 #define CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP)
63
64 #define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask)
65 #define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask)
66 #define CLK_ALWAYS_ON(h) (h->data->always_on)
67
68 #define SD_EMMC_DELAY 0x4
69 #define SD_EMMC_ADJUST 0x8
70
71 #define SD_EMMC_DELAY1 0x4
72 #define SD_EMMC_DELAY2 0x8
73 #define SD_EMMC_V3_ADJUST 0xc
74
75 #define SD_EMMC_CALOUT 0x10
76 #define SD_EMMC_START 0x40
77 #define START_DESC_INIT BIT(0)
78 #define START_DESC_BUSY BIT(1)
79 #define START_DESC_ADDR_MASK GENMASK(31, 2)
80
81 #define SD_EMMC_CFG 0x44
82 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
83 #define CFG_BUS_WIDTH_1 0x0
84 #define CFG_BUS_WIDTH_4 0x1
85 #define CFG_BUS_WIDTH_8 0x2
86 #define CFG_DDR BIT(2)
87 #define CFG_BLK_LEN_MASK GENMASK(7, 4)
88 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
89 #define CFG_RC_CC_MASK GENMASK(15, 12)
90 #define CFG_STOP_CLOCK BIT(22)
91 #define CFG_CLK_ALWAYS_ON BIT(18)
92 #define CFG_CHK_DS BIT(20)
93 #define CFG_AUTO_CLK BIT(23)
94 #define CFG_ERR_ABORT BIT(27)
95
96 #define SD_EMMC_STATUS 0x48
97 #define STATUS_BUSY BIT(31)
98 #define STATUS_DESC_BUSY BIT(30)
99 #define STATUS_DATI GENMASK(23, 16)
100
101 #define SD_EMMC_IRQ_EN 0x4c
102 #define IRQ_RXD_ERR_MASK GENMASK(7, 0)
103 #define IRQ_TXD_ERR BIT(8)
104 #define IRQ_DESC_ERR BIT(9)
105 #define IRQ_RESP_ERR BIT(10)
106 #define IRQ_CRC_ERR \
107 (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR)
108 #define IRQ_RESP_TIMEOUT BIT(11)
109 #define IRQ_DESC_TIMEOUT BIT(12)
110 #define IRQ_TIMEOUTS \
111 (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT)
112 #define IRQ_END_OF_CHAIN BIT(13)
113 #define IRQ_RESP_STATUS BIT(14)
114 #define IRQ_SDIO BIT(15)
115 #define IRQ_EN_MASK \
116 (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS |\
117 IRQ_SDIO)
118
119 #define SD_EMMC_CMD_CFG 0x50
120 #define SD_EMMC_CMD_ARG 0x54
121 #define SD_EMMC_CMD_DAT 0x58
122 #define SD_EMMC_CMD_RSP 0x5c
123 #define SD_EMMC_CMD_RSP1 0x60
124 #define SD_EMMC_CMD_RSP2 0x64
125 #define SD_EMMC_CMD_RSP3 0x68
126
127 #define SD_EMMC_RXD 0x94
128 #define SD_EMMC_TXD 0x94
129 #define SD_EMMC_LAST_REG SD_EMMC_TXD
130
131 #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */
132 #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */
133 #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */
134 #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */
135 #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */
136 #define SD_EMMC_DESC_BUF_LEN PAGE_SIZE
137
138 #define SD_EMMC_PRE_REQ_DONE BIT(0)
139 #define SD_EMMC_DESC_CHAIN_MODE BIT(1)
140
141 #define MUX_CLK_NUM_PARENTS 2
142
143 struct meson_mmc_data {
144 unsigned int tx_delay_mask;
145 unsigned int rx_delay_mask;
146 unsigned int always_on;
147 };
148
149 struct sd_emmc_desc {
150 u32 cmd_cfg;
151 u32 cmd_arg;
152 u32 cmd_data;
153 u32 cmd_resp;
154 };
155
156 struct meson_host {
157 struct device *dev;
158 struct meson_mmc_data *data;
159 struct mmc_host *mmc;
160 struct mmc_command *cmd;
161
162 spinlock_t lock;
163 void __iomem *regs;
164 struct clk *core_clk;
165 struct clk *mmc_clk;
166 struct clk *rx_clk;
167 struct clk *tx_clk;
168 unsigned long req_rate;
169
170 struct pinctrl *pinctrl;
171 struct pinctrl_state *pins_default;
172 struct pinctrl_state *pins_clk_gate;
173
174 unsigned int bounce_buf_size;
175 void *bounce_buf;
176 dma_addr_t bounce_dma_addr;
177 struct sd_emmc_desc *descs;
178 dma_addr_t descs_dma_addr;
179
180 int irq;
181
182 bool vqmmc_enabled;
183 };
184
185 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
186 #define CMD_CFG_BLOCK_MODE BIT(9)
187 #define CMD_CFG_R1B BIT(10)
188 #define CMD_CFG_END_OF_CHAIN BIT(11)
189 #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12)
190 #define CMD_CFG_NO_RESP BIT(16)
191 #define CMD_CFG_NO_CMD BIT(17)
192 #define CMD_CFG_DATA_IO BIT(18)
193 #define CMD_CFG_DATA_WR BIT(19)
194 #define CMD_CFG_RESP_NOCRC BIT(20)
195 #define CMD_CFG_RESP_128 BIT(21)
196 #define CMD_CFG_RESP_NUM BIT(22)
197 #define CMD_CFG_DATA_NUM BIT(23)
198 #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
199 #define CMD_CFG_ERROR BIT(30)
200 #define CMD_CFG_OWNER BIT(31)
201
202 #define CMD_DATA_MASK GENMASK(31, 2)
203 #define CMD_DATA_BIG_ENDIAN BIT(1)
204 #define CMD_DATA_SRAM BIT(0)
205 #define CMD_RESP_MASK GENMASK(31, 1)
206 #define CMD_RESP_SRAM BIT(0)
207
208 struct meson_mmc_phase {
209 struct clk_hw hw;
210 void __iomem *reg;
211 unsigned long phase_mask;
212 unsigned long delay_mask;
213 unsigned int delay_step_ps;
214 };
215
216 #define to_meson_mmc_phase(_hw) container_of(_hw, struct meson_mmc_phase, hw)
217
218 static int meson_mmc_clk_get_phase(struct clk_hw *hw)
219 {
220 struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw);
221 unsigned int phase_num = 1 << hweight_long(mmc->phase_mask);
222 unsigned long period_ps, p, d;
223 int degrees;
224 u32 val;
225
226 val = readl(mmc->reg);
227 p = (val & mmc->phase_mask) >> __ffs(mmc->phase_mask);
228 degrees = p * 360 / phase_num;
229
230 if (mmc->delay_mask) {
231 period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
232 clk_get_rate(hw->clk));
233 d = (val & mmc->delay_mask) >> __ffs(mmc->delay_mask);
234 degrees += d * mmc->delay_step_ps * 360 / period_ps;
235 degrees %= 360;
236 }
237
238 return degrees;
239 }
240
241 static void meson_mmc_apply_phase_delay(struct meson_mmc_phase *mmc,
242 unsigned int phase,
243 unsigned int delay)
244 {
245 u32 val;
246
247 val = readl(mmc->reg);
248 val &= ~mmc->phase_mask;
249 val |= phase << __ffs(mmc->phase_mask);
250
251 if (mmc->delay_mask) {
252 val &= ~mmc->delay_mask;
253 val |= delay << __ffs(mmc->delay_mask);
254 }
255
256 writel(val, mmc->reg);
257 }
258
259 static int meson_mmc_clk_set_phase(struct clk_hw *hw, int degrees)
260 {
261 struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw);
262 unsigned int phase_num = 1 << hweight_long(mmc->phase_mask);
263 unsigned long period_ps, d = 0, r;
264 uint64_t p;
265
266 p = degrees % 360;
267
268 if (!mmc->delay_mask) {
269 p = DIV_ROUND_CLOSEST_ULL(p, 360 / phase_num);
270 } else {
271 period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
272 clk_get_rate(hw->clk));
273
274 /* First compute the phase index (p), the remainder (r) is the
275 * part we'll try to acheive using the delays (d).
276 */
277 r = do_div(p, 360 / phase_num);
278 d = DIV_ROUND_CLOSEST(r * period_ps,
279 360 * mmc->delay_step_ps);
280 d = min(d, mmc->delay_mask >> __ffs(mmc->delay_mask));
281 }
282
283 meson_mmc_apply_phase_delay(mmc, p, d);
284 return 0;
285 }
286
287 static const struct clk_ops meson_mmc_clk_phase_ops = {
288 .get_phase = meson_mmc_clk_get_phase,
289 .set_phase = meson_mmc_clk_set_phase,
290 };
291
292 static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data)
293 {
294 unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC;
295
296 if (!timeout)
297 return SD_EMMC_CMD_TIMEOUT_DATA;
298
299 timeout = roundup_pow_of_two(timeout);
300
301 return min(timeout, 32768U); /* max. 2^15 ms */
302 }
303
304 static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd)
305 {
306 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error)
307 return cmd->mrq->cmd;
308 else if (mmc_op_multi(cmd->opcode) &&
309 (!cmd->mrq->sbc || cmd->error || cmd->data->error))
310 return cmd->mrq->stop;
311 else
312 return NULL;
313 }
314
315 static void meson_mmc_get_transfer_mode(struct mmc_host *mmc,
316 struct mmc_request *mrq)
317 {
318 struct mmc_data *data = mrq->data;
319 struct scatterlist *sg;
320 int i;
321 bool use_desc_chain_mode = true;
322
323 /*
324 * Broken SDIO with AP6255-based WiFi on Khadas VIM Pro has been
325 * reported. For some strange reason this occurs in descriptor
326 * chain mode only. So let's fall back to bounce buffer mode
327 * for command SD_IO_RW_EXTENDED.
328 */
329 if (mrq->cmd->opcode == SD_IO_RW_EXTENDED)
330 return;
331
332 for_each_sg(data->sg, sg, data->sg_len, i)
333 /* check for 8 byte alignment */
334 if (sg->offset & 7) {
335 WARN_ONCE(1, "unaligned scatterlist buffer\n");
336 use_desc_chain_mode = false;
337 break;
338 }
339
340 if (use_desc_chain_mode)
341 data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE;
342 }
343
344 static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data)
345 {
346 return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE;
347 }
348
349 static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data)
350 {
351 return data && data->flags & MMC_DATA_READ &&
352 !meson_mmc_desc_chain_mode(data);
353 }
354
355 static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
356 {
357 struct mmc_data *data = mrq->data;
358
359 if (!data)
360 return;
361
362 meson_mmc_get_transfer_mode(mmc, mrq);
363 data->host_cookie |= SD_EMMC_PRE_REQ_DONE;
364
365 if (!meson_mmc_desc_chain_mode(data))
366 return;
367
368 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len,
369 mmc_get_dma_dir(data));
370 if (!data->sg_count)
371 dev_err(mmc_dev(mmc), "dma_map_sg failed");
372 }
373
374 static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
375 int err)
376 {
377 struct mmc_data *data = mrq->data;
378
379 if (data && meson_mmc_desc_chain_mode(data) && data->sg_count)
380 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
381 mmc_get_dma_dir(data));
382 }
383
384 static bool meson_mmc_timing_is_ddr(struct mmc_ios *ios)
385 {
386 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
387 ios->timing == MMC_TIMING_UHS_DDR50 ||
388 ios->timing == MMC_TIMING_MMC_HS400)
389 return true;
390
391 return false;
392 }
393
394 /*
395 * Gating the clock on this controller is tricky. It seems the mmc clock
396 * is also used by the controller. It may crash during some operation if the
397 * clock is stopped. The safest thing to do, whenever possible, is to keep
398 * clock running at stop it at the pad using the pinmux.
399 */
400 static void meson_mmc_clk_gate(struct meson_host *host)
401 {
402 u32 cfg;
403
404 if (host->pins_clk_gate) {
405 pinctrl_select_state(host->pinctrl, host->pins_clk_gate);
406 } else {
407 /*
408 * If the pinmux is not provided - default to the classic and
409 * unsafe method
410 */
411 cfg = readl(host->regs + SD_EMMC_CFG);
412 cfg |= CFG_STOP_CLOCK;
413 writel(cfg, host->regs + SD_EMMC_CFG);
414 }
415 }
416
417 static void meson_mmc_clk_ungate(struct meson_host *host)
418 {
419 u32 cfg;
420
421 if (host->pins_clk_gate)
422 pinctrl_select_state(host->pinctrl, host->pins_default);
423
424 /* Make sure the clock is not stopped in the controller */
425 cfg = readl(host->regs + SD_EMMC_CFG);
426 cfg &= ~CFG_STOP_CLOCK;
427 writel(cfg, host->regs + SD_EMMC_CFG);
428 }
429
430 static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios)
431 {
432 struct mmc_host *mmc = host->mmc;
433 unsigned long rate = ios->clock;
434 int ret;
435 u32 cfg;
436
437 /* DDR modes require higher module clock */
438 if (meson_mmc_timing_is_ddr(ios))
439 rate <<= 1;
440
441 /* Same request - bail-out */
442 if (host->req_rate == rate)
443 return 0;
444
445 /* stop clock */
446 meson_mmc_clk_gate(host);
447 host->req_rate = 0;
448
449 if (!rate) {
450 mmc->actual_clock = 0;
451 /* return with clock being stopped */
452 return 0;
453 }
454
455 /* Stop the clock during rate change to avoid glitches */
456 cfg = readl(host->regs + SD_EMMC_CFG);
457 cfg |= CFG_STOP_CLOCK;
458 writel(cfg, host->regs + SD_EMMC_CFG);
459
460 ret = clk_set_rate(host->mmc_clk, rate);
461 if (ret) {
462 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n",
463 rate, ret);
464 return ret;
465 }
466
467 host->req_rate = rate;
468 mmc->actual_clock = clk_get_rate(host->mmc_clk);
469
470 /* We should report the real output frequency of the controller */
471 if (meson_mmc_timing_is_ddr(ios))
472 mmc->actual_clock >>= 1;
473
474 dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock);
475 if (ios->clock != mmc->actual_clock)
476 dev_dbg(host->dev, "requested rate was %u\n", ios->clock);
477
478 /* (re)start clock */
479 meson_mmc_clk_ungate(host);
480
481 return 0;
482 }
483
484 /*
485 * The SD/eMMC IP block has an internal mux and divider used for
486 * generating the MMC clock. Use the clock framework to create and
487 * manage these clocks.
488 */
489 static int meson_mmc_clk_init(struct meson_host *host)
490 {
491 struct clk_init_data init;
492 struct clk_mux *mux;
493 struct clk_divider *div;
494 struct meson_mmc_phase *core, *tx, *rx;
495 struct clk *clk;
496 char clk_name[32];
497 int i, ret = 0;
498 const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
499 const char *clk_parent[1];
500 u32 clk_reg;
501
502 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
503 clk_reg = 0;
504 clk_reg |= CLK_ALWAYS_ON(host);
505 clk_reg |= CLK_DIV_MASK;
506 writel(clk_reg, host->regs + SD_EMMC_CLOCK);
507
508 /* get the mux parents */
509 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
510 struct clk *clk;
511 char name[16];
512
513 snprintf(name, sizeof(name), "clkin%d", i);
514 clk = devm_clk_get(host->dev, name);
515 if (IS_ERR(clk)) {
516 if (clk != ERR_PTR(-EPROBE_DEFER))
517 dev_err(host->dev, "Missing clock %s\n", name);
518 return PTR_ERR(clk);
519 }
520
521 mux_parent_names[i] = __clk_get_name(clk);
522 }
523
524 /* create the mux */
525 mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL);
526 if (!mux)
527 return -ENOMEM;
528
529 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev));
530 init.name = clk_name;
531 init.ops = &clk_mux_ops;
532 init.flags = 0;
533 init.parent_names = mux_parent_names;
534 init.num_parents = MUX_CLK_NUM_PARENTS;
535
536 mux->reg = host->regs + SD_EMMC_CLOCK;
537 mux->shift = __ffs(CLK_SRC_MASK);
538 mux->mask = CLK_SRC_MASK >> mux->shift;
539 mux->hw.init = &init;
540
541 clk = devm_clk_register(host->dev, &mux->hw);
542 if (WARN_ON(IS_ERR(clk)))
543 return PTR_ERR(clk);
544
545 /* create the divider */
546 div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL);
547 if (!div)
548 return -ENOMEM;
549
550 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev));
551 init.name = clk_name;
552 init.ops = &clk_divider_ops;
553 init.flags = CLK_SET_RATE_PARENT;
554 clk_parent[0] = __clk_get_name(clk);
555 init.parent_names = clk_parent;
556 init.num_parents = 1;
557
558 div->reg = host->regs + SD_EMMC_CLOCK;
559 div->shift = __ffs(CLK_DIV_MASK);
560 div->width = __builtin_popcountl(CLK_DIV_MASK);
561 div->hw.init = &init;
562 div->flags = CLK_DIVIDER_ONE_BASED;
563
564 clk = devm_clk_register(host->dev, &div->hw);
565 if (WARN_ON(IS_ERR(clk)))
566 return PTR_ERR(clk);
567
568 /* create the mmc core clock */
569 core = devm_kzalloc(host->dev, sizeof(*core), GFP_KERNEL);
570 if (!core)
571 return -ENOMEM;
572
573 snprintf(clk_name, sizeof(clk_name), "%s#core", dev_name(host->dev));
574 init.name = clk_name;
575 init.ops = &meson_mmc_clk_phase_ops;
576 init.flags = CLK_SET_RATE_PARENT;
577 clk_parent[0] = __clk_get_name(clk);
578 init.parent_names = clk_parent;
579 init.num_parents = 1;
580
581 core->reg = host->regs + SD_EMMC_CLOCK;
582 core->phase_mask = CLK_CORE_PHASE_MASK;
583 core->hw.init = &init;
584
585 host->mmc_clk = devm_clk_register(host->dev, &core->hw);
586 if (WARN_ON(PTR_ERR_OR_ZERO(host->mmc_clk)))
587 return PTR_ERR(host->mmc_clk);
588
589 /* create the mmc tx clock */
590 tx = devm_kzalloc(host->dev, sizeof(*tx), GFP_KERNEL);
591 if (!tx)
592 return -ENOMEM;
593
594 snprintf(clk_name, sizeof(clk_name), "%s#tx", dev_name(host->dev));
595 init.name = clk_name;
596 init.ops = &meson_mmc_clk_phase_ops;
597 init.flags = 0;
598 clk_parent[0] = __clk_get_name(host->mmc_clk);
599 init.parent_names = clk_parent;
600 init.num_parents = 1;
601
602 tx->reg = host->regs + SD_EMMC_CLOCK;
603 tx->phase_mask = CLK_TX_PHASE_MASK;
604 tx->delay_mask = CLK_TX_DELAY_MASK(host);
605 tx->delay_step_ps = CLK_DELAY_STEP_PS;
606 tx->hw.init = &init;
607
608 host->tx_clk = devm_clk_register(host->dev, &tx->hw);
609 if (WARN_ON(PTR_ERR_OR_ZERO(host->tx_clk)))
610 return PTR_ERR(host->tx_clk);
611
612 /* create the mmc rx clock */
613 rx = devm_kzalloc(host->dev, sizeof(*rx), GFP_KERNEL);
614 if (!rx)
615 return -ENOMEM;
616
617 snprintf(clk_name, sizeof(clk_name), "%s#rx", dev_name(host->dev));
618 init.name = clk_name;
619 init.ops = &meson_mmc_clk_phase_ops;
620 init.flags = 0;
621 clk_parent[0] = __clk_get_name(host->mmc_clk);
622 init.parent_names = clk_parent;
623 init.num_parents = 1;
624
625 rx->reg = host->regs + SD_EMMC_CLOCK;
626 rx->phase_mask = CLK_RX_PHASE_MASK;
627 rx->delay_mask = CLK_RX_DELAY_MASK(host);
628 rx->delay_step_ps = CLK_DELAY_STEP_PS;
629 rx->hw.init = &init;
630
631 host->rx_clk = devm_clk_register(host->dev, &rx->hw);
632 if (WARN_ON(PTR_ERR_OR_ZERO(host->rx_clk)))
633 return PTR_ERR(host->rx_clk);
634
635 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
636 host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000);
637 ret = clk_set_rate(host->mmc_clk, host->mmc->f_min);
638 if (ret)
639 return ret;
640
641 /*
642 * Set phases : These values are mostly the datasheet recommended ones
643 * except for the Tx phase. Datasheet recommends 180 but some cards
644 * fail at initialisation with it. 270 works just fine, it fixes these
645 * initialisation issues and enable eMMC DDR52 mode.
646 */
647 clk_set_phase(host->mmc_clk, 180);
648 clk_set_phase(host->tx_clk, 270);
649 clk_set_phase(host->rx_clk, 0);
650
651 return clk_prepare_enable(host->mmc_clk);
652 }
653
654 static void meson_mmc_shift_map(unsigned long *map, unsigned long shift)
655 {
656 DECLARE_BITMAP(left, CLK_PHASE_POINT_NUM);
657 DECLARE_BITMAP(right, CLK_PHASE_POINT_NUM);
658
659 /*
660 * shift the bitmap right and reintroduce the dropped bits on the left
661 * of the bitmap
662 */
663 bitmap_shift_right(right, map, shift, CLK_PHASE_POINT_NUM);
664 bitmap_shift_left(left, map, CLK_PHASE_POINT_NUM - shift,
665 CLK_PHASE_POINT_NUM);
666 bitmap_or(map, left, right, CLK_PHASE_POINT_NUM);
667 }
668
669 static void meson_mmc_find_next_region(unsigned long *map,
670 unsigned long *start,
671 unsigned long *stop)
672 {
673 *start = find_next_bit(map, CLK_PHASE_POINT_NUM, *start);
674 *stop = find_next_zero_bit(map, CLK_PHASE_POINT_NUM, *start);
675 }
676
677 static int meson_mmc_find_tuning_point(unsigned long *test)
678 {
679 unsigned long shift, stop, offset = 0, start = 0, size = 0;
680
681 /* Get the all good/all bad situation out the way */
682 if (bitmap_full(test, CLK_PHASE_POINT_NUM))
683 return 0; /* All points are good so point 0 will do */
684 else if (bitmap_empty(test, CLK_PHASE_POINT_NUM))
685 return -EIO; /* No successful tuning point */
686
687 /*
688 * Now we know there is a least one region find. Make sure it does
689 * not wrap by the shifting the bitmap if necessary
690 */
691 shift = find_first_zero_bit(test, CLK_PHASE_POINT_NUM);
692 if (shift != 0)
693 meson_mmc_shift_map(test, shift);
694
695 while (start < CLK_PHASE_POINT_NUM) {
696 meson_mmc_find_next_region(test, &start, &stop);
697
698 if ((stop - start) > size) {
699 offset = start;
700 size = stop - start;
701 }
702
703 start = stop;
704 }
705
706 /* Get the center point of the region */
707 offset += (size / 2);
708
709 /* Shift the result back */
710 offset = (offset + shift) % CLK_PHASE_POINT_NUM;
711
712 return offset;
713 }
714
715 static int meson_mmc_clk_phase_tuning(struct mmc_host *mmc, u32 opcode,
716 struct clk *clk)
717 {
718 int point, ret;
719 DECLARE_BITMAP(test, CLK_PHASE_POINT_NUM);
720
721 dev_dbg(mmc_dev(mmc), "%s phase/delay tunning...\n",
722 __clk_get_name(clk));
723 bitmap_zero(test, CLK_PHASE_POINT_NUM);
724
725 /* Explore tuning points */
726 for (point = 0; point < CLK_PHASE_POINT_NUM; point++) {
727 clk_set_phase(clk, point * CLK_PHASE_STEP);
728 ret = mmc_send_tuning(mmc, opcode, NULL);
729 if (!ret)
730 set_bit(point, test);
731 }
732
733 /* Find the optimal tuning point and apply it */
734 point = meson_mmc_find_tuning_point(test);
735 if (point < 0)
736 return point; /* tuning failed */
737
738 clk_set_phase(clk, point * CLK_PHASE_STEP);
739 dev_dbg(mmc_dev(mmc), "success with phase: %d\n",
740 clk_get_phase(clk));
741 return 0;
742 }
743
744 static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
745 {
746 struct meson_host *host = mmc_priv(mmc);
747
748 return meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk);
749 }
750
751 static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
752 {
753 struct meson_host *host = mmc_priv(mmc);
754 u32 bus_width, val;
755 int err;
756
757 /*
758 * GPIO regulator, only controls switching between 1v8 and
759 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON.
760 */
761 switch (ios->power_mode) {
762 case MMC_POWER_OFF:
763 if (!IS_ERR(mmc->supply.vmmc))
764 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
765
766 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
767 regulator_disable(mmc->supply.vqmmc);
768 host->vqmmc_enabled = false;
769 }
770
771 break;
772
773 case MMC_POWER_UP:
774 if (!IS_ERR(mmc->supply.vmmc))
775 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
776
777 /* Reset rx phase */
778 clk_set_phase(host->rx_clk, 0);
779
780 break;
781
782 case MMC_POWER_ON:
783 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
784 int ret = regulator_enable(mmc->supply.vqmmc);
785
786 if (ret < 0)
787 dev_err(host->dev,
788 "failed to enable vqmmc regulator\n");
789 else
790 host->vqmmc_enabled = true;
791 }
792
793 break;
794 }
795
796 /* Bus width */
797 switch (ios->bus_width) {
798 case MMC_BUS_WIDTH_1:
799 bus_width = CFG_BUS_WIDTH_1;
800 break;
801 case MMC_BUS_WIDTH_4:
802 bus_width = CFG_BUS_WIDTH_4;
803 break;
804 case MMC_BUS_WIDTH_8:
805 bus_width = CFG_BUS_WIDTH_8;
806 break;
807 default:
808 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n",
809 ios->bus_width);
810 bus_width = CFG_BUS_WIDTH_4;
811 }
812
813 val = readl(host->regs + SD_EMMC_CFG);
814 val &= ~CFG_BUS_WIDTH_MASK;
815 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width);
816
817 val &= ~CFG_DDR;
818 if (meson_mmc_timing_is_ddr(ios))
819 val |= CFG_DDR;
820
821 val &= ~CFG_CHK_DS;
822 if (ios->timing == MMC_TIMING_MMC_HS400)
823 val |= CFG_CHK_DS;
824
825 err = meson_mmc_clk_set(host, ios);
826 if (err)
827 dev_err(host->dev, "Failed to set clock: %d\n,", err);
828
829 writel(val, host->regs + SD_EMMC_CFG);
830 dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val);
831 }
832
833 static void meson_mmc_request_done(struct mmc_host *mmc,
834 struct mmc_request *mrq)
835 {
836 struct meson_host *host = mmc_priv(mmc);
837
838 host->cmd = NULL;
839 mmc_request_done(host->mmc, mrq);
840 }
841
842 static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz)
843 {
844 struct meson_host *host = mmc_priv(mmc);
845 u32 cfg, blksz_old;
846
847 cfg = readl(host->regs + SD_EMMC_CFG);
848 blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg);
849
850 if (!is_power_of_2(blksz))
851 dev_err(host->dev, "blksz %u is not a power of 2\n", blksz);
852
853 blksz = ilog2(blksz);
854
855 /* check if block-size matches, if not update */
856 if (blksz == blksz_old)
857 return;
858
859 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__,
860 blksz_old, blksz);
861
862 cfg &= ~CFG_BLK_LEN_MASK;
863 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz);
864 writel(cfg, host->regs + SD_EMMC_CFG);
865 }
866
867 static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg)
868 {
869 if (cmd->flags & MMC_RSP_PRESENT) {
870 if (cmd->flags & MMC_RSP_136)
871 *cmd_cfg |= CMD_CFG_RESP_128;
872 *cmd_cfg |= CMD_CFG_RESP_NUM;
873
874 if (!(cmd->flags & MMC_RSP_CRC))
875 *cmd_cfg |= CMD_CFG_RESP_NOCRC;
876
877 if (cmd->flags & MMC_RSP_BUSY)
878 *cmd_cfg |= CMD_CFG_R1B;
879 } else {
880 *cmd_cfg |= CMD_CFG_NO_RESP;
881 }
882 }
883
884 static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg)
885 {
886 struct meson_host *host = mmc_priv(mmc);
887 struct sd_emmc_desc *desc = host->descs;
888 struct mmc_data *data = host->cmd->data;
889 struct scatterlist *sg;
890 u32 start;
891 int i;
892
893 if (data->flags & MMC_DATA_WRITE)
894 cmd_cfg |= CMD_CFG_DATA_WR;
895
896 if (data->blocks > 1) {
897 cmd_cfg |= CMD_CFG_BLOCK_MODE;
898 meson_mmc_set_blksz(mmc, data->blksz);
899 }
900
901 for_each_sg(data->sg, sg, data->sg_count, i) {
902 unsigned int len = sg_dma_len(sg);
903
904 if (data->blocks > 1)
905 len /= data->blksz;
906
907 desc[i].cmd_cfg = cmd_cfg;
908 desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len);
909 if (i > 0)
910 desc[i].cmd_cfg |= CMD_CFG_NO_CMD;
911 desc[i].cmd_arg = host->cmd->arg;
912 desc[i].cmd_resp = 0;
913 desc[i].cmd_data = sg_dma_address(sg);
914 }
915 desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN;
916
917 dma_wmb(); /* ensure descriptor is written before kicked */
918 start = host->descs_dma_addr | START_DESC_BUSY;
919 writel(start, host->regs + SD_EMMC_START);
920 }
921
922 static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd)
923 {
924 struct meson_host *host = mmc_priv(mmc);
925 struct mmc_data *data = cmd->data;
926 u32 cmd_cfg = 0, cmd_data = 0;
927 unsigned int xfer_bytes = 0;
928
929 /* Setup descriptors */
930 dma_rmb();
931
932 host->cmd = cmd;
933
934 cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode);
935 cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */
936 cmd_cfg |= CMD_CFG_ERROR; /* stop in case of error */
937
938 meson_mmc_set_response_bits(cmd, &cmd_cfg);
939
940 /* data? */
941 if (data) {
942 data->bytes_xfered = 0;
943 cmd_cfg |= CMD_CFG_DATA_IO;
944 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
945 ilog2(meson_mmc_get_timeout_msecs(data)));
946
947 if (meson_mmc_desc_chain_mode(data)) {
948 meson_mmc_desc_chain_transfer(mmc, cmd_cfg);
949 return;
950 }
951
952 if (data->blocks > 1) {
953 cmd_cfg |= CMD_CFG_BLOCK_MODE;
954 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK,
955 data->blocks);
956 meson_mmc_set_blksz(mmc, data->blksz);
957 } else {
958 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz);
959 }
960
961 xfer_bytes = data->blksz * data->blocks;
962 if (data->flags & MMC_DATA_WRITE) {
963 cmd_cfg |= CMD_CFG_DATA_WR;
964 WARN_ON(xfer_bytes > host->bounce_buf_size);
965 sg_copy_to_buffer(data->sg, data->sg_len,
966 host->bounce_buf, xfer_bytes);
967 dma_wmb();
968 }
969
970 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK;
971 } else {
972 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
973 ilog2(SD_EMMC_CMD_TIMEOUT));
974 }
975
976 /* Last descriptor */
977 cmd_cfg |= CMD_CFG_END_OF_CHAIN;
978 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG);
979 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT);
980 writel(0, host->regs + SD_EMMC_CMD_RSP);
981 wmb(); /* ensure descriptor is written before kicked */
982 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG);
983 }
984
985 static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
986 {
987 struct meson_host *host = mmc_priv(mmc);
988 bool needs_pre_post_req = mrq->data &&
989 !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE);
990
991 if (needs_pre_post_req) {
992 meson_mmc_get_transfer_mode(mmc, mrq);
993 if (!meson_mmc_desc_chain_mode(mrq->data))
994 needs_pre_post_req = false;
995 }
996
997 if (needs_pre_post_req)
998 meson_mmc_pre_req(mmc, mrq);
999
1000 /* Stop execution */
1001 writel(0, host->regs + SD_EMMC_START);
1002
1003 meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd);
1004
1005 if (needs_pre_post_req)
1006 meson_mmc_post_req(mmc, mrq, 0);
1007 }
1008
1009 static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd)
1010 {
1011 struct meson_host *host = mmc_priv(mmc);
1012
1013 if (cmd->flags & MMC_RSP_136) {
1014 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3);
1015 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2);
1016 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1);
1017 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP);
1018 } else if (cmd->flags & MMC_RSP_PRESENT) {
1019 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP);
1020 }
1021 }
1022
1023 static irqreturn_t meson_mmc_irq(int irq, void *dev_id)
1024 {
1025 struct meson_host *host = dev_id;
1026 struct mmc_command *cmd;
1027 struct mmc_data *data;
1028 u32 irq_en, status, raw_status;
1029 irqreturn_t ret = IRQ_NONE;
1030
1031 irq_en = readl(host->regs + SD_EMMC_IRQ_EN);
1032 raw_status = readl(host->regs + SD_EMMC_STATUS);
1033 status = raw_status & irq_en;
1034
1035 if (!status) {
1036 dev_dbg(host->dev,
1037 "Unexpected IRQ! irq_en 0x%08x - status 0x%08x\n",
1038 irq_en, raw_status);
1039 return IRQ_NONE;
1040 }
1041
1042 if (WARN_ON(!host) || WARN_ON(!host->cmd))
1043 return IRQ_NONE;
1044
1045 spin_lock(&host->lock);
1046
1047 cmd = host->cmd;
1048 data = cmd->data;
1049 cmd->error = 0;
1050 if (status & IRQ_CRC_ERR) {
1051 dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status);
1052 cmd->error = -EILSEQ;
1053 ret = IRQ_WAKE_THREAD;
1054 goto out;
1055 }
1056
1057 if (status & IRQ_TIMEOUTS) {
1058 dev_dbg(host->dev, "Timeout - status 0x%08x\n", status);
1059 cmd->error = -ETIMEDOUT;
1060 ret = IRQ_WAKE_THREAD;
1061 goto out;
1062 }
1063
1064 meson_mmc_read_resp(host->mmc, cmd);
1065
1066 if (status & IRQ_SDIO) {
1067 dev_dbg(host->dev, "IRQ: SDIO TODO.\n");
1068 ret = IRQ_HANDLED;
1069 }
1070
1071 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) {
1072 if (data && !cmd->error)
1073 data->bytes_xfered = data->blksz * data->blocks;
1074 if (meson_mmc_bounce_buf_read(data) ||
1075 meson_mmc_get_next_command(cmd))
1076 ret = IRQ_WAKE_THREAD;
1077 else
1078 ret = IRQ_HANDLED;
1079 }
1080
1081 out:
1082 /* ack all enabled interrupts */
1083 writel(irq_en, host->regs + SD_EMMC_STATUS);
1084
1085 if (cmd->error) {
1086 /* Stop desc in case of errors */
1087 u32 start = readl(host->regs + SD_EMMC_START);
1088
1089 start &= ~START_DESC_BUSY;
1090 writel(start, host->regs + SD_EMMC_START);
1091 }
1092
1093 if (ret == IRQ_HANDLED)
1094 meson_mmc_request_done(host->mmc, cmd->mrq);
1095
1096 spin_unlock(&host->lock);
1097 return ret;
1098 }
1099
1100 static int meson_mmc_wait_desc_stop(struct meson_host *host)
1101 {
1102 int loop;
1103 u32 status;
1104
1105 /*
1106 * It may sometimes take a while for it to actually halt. Here, we
1107 * are giving it 5ms to comply
1108 *
1109 * If we don't confirm the descriptor is stopped, it might raise new
1110 * IRQs after we have called mmc_request_done() which is bad.
1111 */
1112 for (loop = 50; loop; loop--) {
1113 status = readl(host->regs + SD_EMMC_STATUS);
1114 if (status & (STATUS_BUSY | STATUS_DESC_BUSY))
1115 udelay(100);
1116 else
1117 break;
1118 }
1119
1120 if (status & (STATUS_BUSY | STATUS_DESC_BUSY)) {
1121 dev_err(host->dev, "Timed out waiting for host to stop\n");
1122 return -ETIMEDOUT;
1123 }
1124
1125 return 0;
1126 }
1127
1128 static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id)
1129 {
1130 struct meson_host *host = dev_id;
1131 struct mmc_command *next_cmd, *cmd = host->cmd;
1132 struct mmc_data *data;
1133 unsigned int xfer_bytes;
1134
1135 if (WARN_ON(!cmd))
1136 return IRQ_NONE;
1137
1138 if (cmd->error) {
1139 meson_mmc_wait_desc_stop(host);
1140 meson_mmc_request_done(host->mmc, cmd->mrq);
1141
1142 return IRQ_HANDLED;
1143 }
1144
1145 data = cmd->data;
1146 if (meson_mmc_bounce_buf_read(data)) {
1147 xfer_bytes = data->blksz * data->blocks;
1148 WARN_ON(xfer_bytes > host->bounce_buf_size);
1149 sg_copy_from_buffer(data->sg, data->sg_len,
1150 host->bounce_buf, xfer_bytes);
1151 }
1152
1153 next_cmd = meson_mmc_get_next_command(cmd);
1154 if (next_cmd)
1155 meson_mmc_start_cmd(host->mmc, next_cmd);
1156 else
1157 meson_mmc_request_done(host->mmc, cmd->mrq);
1158
1159 return IRQ_HANDLED;
1160 }
1161
1162 /*
1163 * NOTE: we only need this until the GPIO/pinctrl driver can handle
1164 * interrupts. For now, the MMC core will use this for polling.
1165 */
1166 static int meson_mmc_get_cd(struct mmc_host *mmc)
1167 {
1168 int status = mmc_gpio_get_cd(mmc);
1169
1170 if (status == -ENOSYS)
1171 return 1; /* assume present */
1172
1173 return status;
1174 }
1175
1176 static void meson_mmc_cfg_init(struct meson_host *host)
1177 {
1178 u32 cfg = 0;
1179
1180 cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK,
1181 ilog2(SD_EMMC_CFG_RESP_TIMEOUT));
1182 cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP));
1183 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE));
1184
1185 /* abort chain on R/W errors */
1186 cfg |= CFG_ERR_ABORT;
1187
1188 writel(cfg, host->regs + SD_EMMC_CFG);
1189 }
1190
1191 static int meson_mmc_card_busy(struct mmc_host *mmc)
1192 {
1193 struct meson_host *host = mmc_priv(mmc);
1194 u32 regval;
1195
1196 regval = readl(host->regs + SD_EMMC_STATUS);
1197
1198 /* We are only interrested in lines 0 to 3, so mask the other ones */
1199 return !(FIELD_GET(STATUS_DATI, regval) & 0xf);
1200 }
1201
1202 static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1203 {
1204 /* vqmmc regulator is available */
1205 if (!IS_ERR(mmc->supply.vqmmc)) {
1206 /*
1207 * The usual amlogic setup uses a GPIO to switch from one
1208 * regulator to the other. While the voltage ramp up is
1209 * pretty fast, care must be taken when switching from 3.3v
1210 * to 1.8v. Please make sure the regulator framework is aware
1211 * of your own regulator constraints
1212 */
1213 return mmc_regulator_set_vqmmc(mmc, ios);
1214 }
1215
1216 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
1217 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1218 return 0;
1219
1220 return -EINVAL;
1221 }
1222
1223 static const struct mmc_host_ops meson_mmc_ops = {
1224 .request = meson_mmc_request,
1225 .set_ios = meson_mmc_set_ios,
1226 .get_cd = meson_mmc_get_cd,
1227 .pre_req = meson_mmc_pre_req,
1228 .post_req = meson_mmc_post_req,
1229 .execute_tuning = meson_mmc_execute_tuning,
1230 .card_busy = meson_mmc_card_busy,
1231 .start_signal_voltage_switch = meson_mmc_voltage_switch,
1232 };
1233
1234 static int meson_mmc_probe(struct platform_device *pdev)
1235 {
1236 struct resource *res;
1237 struct meson_host *host;
1238 struct mmc_host *mmc;
1239 int ret;
1240
1241 mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev);
1242 if (!mmc)
1243 return -ENOMEM;
1244 host = mmc_priv(mmc);
1245 host->mmc = mmc;
1246 host->dev = &pdev->dev;
1247 dev_set_drvdata(&pdev->dev, host);
1248
1249 spin_lock_init(&host->lock);
1250
1251 /* Get regulators and the supported OCR mask */
1252 host->vqmmc_enabled = false;
1253 ret = mmc_regulator_get_supply(mmc);
1254 if (ret)
1255 goto free_host;
1256
1257 ret = mmc_of_parse(mmc);
1258 if (ret) {
1259 if (ret != -EPROBE_DEFER)
1260 dev_warn(&pdev->dev, "error parsing DT: %d\n", ret);
1261 goto free_host;
1262 }
1263
1264 host->data = (struct meson_mmc_data *)
1265 of_device_get_match_data(&pdev->dev);
1266 if (!host->data) {
1267 ret = -EINVAL;
1268 goto free_host;
1269 }
1270
1271 ret = device_reset_optional(&pdev->dev);
1272 if (ret) {
1273 if (ret != -EPROBE_DEFER)
1274 dev_err(&pdev->dev, "device reset failed: %d\n", ret);
1275
1276 return ret;
1277 }
1278
1279 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1280 host->regs = devm_ioremap_resource(&pdev->dev, res);
1281 if (IS_ERR(host->regs)) {
1282 ret = PTR_ERR(host->regs);
1283 goto free_host;
1284 }
1285
1286 host->irq = platform_get_irq(pdev, 0);
1287 if (host->irq <= 0) {
1288 dev_err(&pdev->dev, "failed to get interrupt resource.\n");
1289 ret = -EINVAL;
1290 goto free_host;
1291 }
1292
1293 host->pinctrl = devm_pinctrl_get(&pdev->dev);
1294 if (IS_ERR(host->pinctrl)) {
1295 ret = PTR_ERR(host->pinctrl);
1296 goto free_host;
1297 }
1298
1299 host->pins_default = pinctrl_lookup_state(host->pinctrl,
1300 PINCTRL_STATE_DEFAULT);
1301 if (IS_ERR(host->pins_default)) {
1302 ret = PTR_ERR(host->pins_default);
1303 goto free_host;
1304 }
1305
1306 host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl,
1307 "clk-gate");
1308 if (IS_ERR(host->pins_clk_gate)) {
1309 dev_warn(&pdev->dev,
1310 "can't get clk-gate pinctrl, using clk_stop bit\n");
1311 host->pins_clk_gate = NULL;
1312 }
1313
1314 host->core_clk = devm_clk_get(&pdev->dev, "core");
1315 if (IS_ERR(host->core_clk)) {
1316 ret = PTR_ERR(host->core_clk);
1317 goto free_host;
1318 }
1319
1320 ret = clk_prepare_enable(host->core_clk);
1321 if (ret)
1322 goto free_host;
1323
1324 ret = meson_mmc_clk_init(host);
1325 if (ret)
1326 goto err_core_clk;
1327
1328 /* set config to sane default */
1329 meson_mmc_cfg_init(host);
1330
1331 /* Stop execution */
1332 writel(0, host->regs + SD_EMMC_START);
1333
1334 /* clear, ack and enable interrupts */
1335 writel(0, host->regs + SD_EMMC_IRQ_EN);
1336 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN,
1337 host->regs + SD_EMMC_STATUS);
1338 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN,
1339 host->regs + SD_EMMC_IRQ_EN);
1340
1341 ret = request_threaded_irq(host->irq, meson_mmc_irq,
1342 meson_mmc_irq_thread, IRQF_SHARED,
1343 dev_name(&pdev->dev), host);
1344 if (ret)
1345 goto err_init_clk;
1346
1347 mmc->caps |= MMC_CAP_CMD23;
1348 mmc->max_blk_count = CMD_CFG_LENGTH_MASK;
1349 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size;
1350 mmc->max_segs = SD_EMMC_DESC_BUF_LEN / sizeof(struct sd_emmc_desc);
1351 mmc->max_seg_size = mmc->max_req_size;
1352
1353 /* data bounce buffer */
1354 host->bounce_buf_size = mmc->max_req_size;
1355 host->bounce_buf =
1356 dma_alloc_coherent(host->dev, host->bounce_buf_size,
1357 &host->bounce_dma_addr, GFP_KERNEL);
1358 if (host->bounce_buf == NULL) {
1359 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
1360 ret = -ENOMEM;
1361 goto err_free_irq;
1362 }
1363
1364 host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
1365 &host->descs_dma_addr, GFP_KERNEL);
1366 if (!host->descs) {
1367 dev_err(host->dev, "Allocating descriptor DMA buffer failed\n");
1368 ret = -ENOMEM;
1369 goto err_bounce_buf;
1370 }
1371
1372 mmc->ops = &meson_mmc_ops;
1373 mmc_add_host(mmc);
1374
1375 return 0;
1376
1377 err_bounce_buf:
1378 dma_free_coherent(host->dev, host->bounce_buf_size,
1379 host->bounce_buf, host->bounce_dma_addr);
1380 err_free_irq:
1381 free_irq(host->irq, host);
1382 err_init_clk:
1383 clk_disable_unprepare(host->mmc_clk);
1384 err_core_clk:
1385 clk_disable_unprepare(host->core_clk);
1386 free_host:
1387 mmc_free_host(mmc);
1388 return ret;
1389 }
1390
1391 static int meson_mmc_remove(struct platform_device *pdev)
1392 {
1393 struct meson_host *host = dev_get_drvdata(&pdev->dev);
1394
1395 mmc_remove_host(host->mmc);
1396
1397 /* disable interrupts */
1398 writel(0, host->regs + SD_EMMC_IRQ_EN);
1399 free_irq(host->irq, host);
1400
1401 dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
1402 host->descs, host->descs_dma_addr);
1403 dma_free_coherent(host->dev, host->bounce_buf_size,
1404 host->bounce_buf, host->bounce_dma_addr);
1405
1406 clk_disable_unprepare(host->mmc_clk);
1407 clk_disable_unprepare(host->core_clk);
1408
1409 mmc_free_host(host->mmc);
1410 return 0;
1411 }
1412
1413 static const struct meson_mmc_data meson_gx_data = {
1414 .tx_delay_mask = CLK_V2_TX_DELAY_MASK,
1415 .rx_delay_mask = CLK_V2_RX_DELAY_MASK,
1416 .always_on = CLK_V2_ALWAYS_ON,
1417 };
1418
1419 static const struct meson_mmc_data meson_axg_data = {
1420 .tx_delay_mask = CLK_V3_TX_DELAY_MASK,
1421 .rx_delay_mask = CLK_V3_RX_DELAY_MASK,
1422 .always_on = CLK_V3_ALWAYS_ON,
1423 };
1424
1425 static const struct of_device_id meson_mmc_of_match[] = {
1426 { .compatible = "amlogic,meson-gx-mmc", .data = &meson_gx_data },
1427 { .compatible = "amlogic,meson-gxbb-mmc", .data = &meson_gx_data },
1428 { .compatible = "amlogic,meson-gxl-mmc", .data = &meson_gx_data },
1429 { .compatible = "amlogic,meson-gxm-mmc", .data = &meson_gx_data },
1430 { .compatible = "amlogic,meson-axg-mmc", .data = &meson_axg_data },
1431 {}
1432 };
1433 MODULE_DEVICE_TABLE(of, meson_mmc_of_match);
1434
1435 static struct platform_driver meson_mmc_driver = {
1436 .probe = meson_mmc_probe,
1437 .remove = meson_mmc_remove,
1438 .driver = {
1439 .name = DRIVER_NAME,
1440 .of_match_table = of_match_ptr(meson_mmc_of_match),
1441 },
1442 };
1443
1444 module_platform_driver(meson_mmc_driver);
1445
1446 MODULE_DESCRIPTION("Amlogic S905*/GX*/AXG SD/eMMC driver");
1447 MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>");
1448 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support