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vt: vt_ioctl: fix VT_DISALLOCATE freeing in-use virtual console
[linux/fpc-iii.git] / drivers / mmc / host / mtk-sd.c
blob9ecf86ba4bb0b60d24c72116c0e9eafa18c554f2
1 /*
2 * Copyright (c) 2014-2015 MediaTek Inc.
3 * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <linux/module.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/ioport.h>
20 #include <linux/irq.h>
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_gpio.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/slab.h>
31 #include <linux/spinlock.h>
32 #include <linux/interrupt.h>
33
34 #include <linux/mmc/card.h>
35 #include <linux/mmc/core.h>
36 #include <linux/mmc/host.h>
37 #include <linux/mmc/mmc.h>
38 #include <linux/mmc/sd.h>
39 #include <linux/mmc/sdio.h>
40 #include <linux/mmc/slot-gpio.h>
41
42 #define MAX_BD_NUM 1024
43
44 /*--------------------------------------------------------------------------*/
45 /* Common Definition */
46 /*--------------------------------------------------------------------------*/
47 #define MSDC_BUS_1BITS 0x0
48 #define MSDC_BUS_4BITS 0x1
49 #define MSDC_BUS_8BITS 0x2
50
51 #define MSDC_BURST_64B 0x6
52
53 /*--------------------------------------------------------------------------*/
54 /* Register Offset */
55 /*--------------------------------------------------------------------------*/
56 #define MSDC_CFG 0x0
57 #define MSDC_IOCON 0x04
58 #define MSDC_PS 0x08
59 #define MSDC_INT 0x0c
60 #define MSDC_INTEN 0x10
61 #define MSDC_FIFOCS 0x14
62 #define SDC_CFG 0x30
63 #define SDC_CMD 0x34
64 #define SDC_ARG 0x38
65 #define SDC_STS 0x3c
66 #define SDC_RESP0 0x40
67 #define SDC_RESP1 0x44
68 #define SDC_RESP2 0x48
69 #define SDC_RESP3 0x4c
70 #define SDC_BLK_NUM 0x50
71 #define SDC_ADV_CFG0 0x64
72 #define EMMC_IOCON 0x7c
73 #define SDC_ACMD_RESP 0x80
74 #define DMA_SA_H4BIT 0x8c
75 #define MSDC_DMA_SA 0x90
76 #define MSDC_DMA_CTRL 0x98
77 #define MSDC_DMA_CFG 0x9c
78 #define MSDC_PATCH_BIT 0xb0
79 #define MSDC_PATCH_BIT1 0xb4
80 #define MSDC_PATCH_BIT2 0xb8
81 #define MSDC_PAD_TUNE 0xec
82 #define MSDC_PAD_TUNE0 0xf0
83 #define PAD_DS_TUNE 0x188
84 #define PAD_CMD_TUNE 0x18c
85 #define EMMC50_CFG0 0x208
86 #define EMMC50_CFG3 0x220
87 #define SDC_FIFO_CFG 0x228
88
89 /*--------------------------------------------------------------------------*/
90 /* Register Mask */
91 /*--------------------------------------------------------------------------*/
92
93 /* MSDC_CFG mask */
94 #define MSDC_CFG_MODE (0x1 << 0) /* RW */
95 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
96 #define MSDC_CFG_RST (0x1 << 2) /* RW */
97 #define MSDC_CFG_PIO (0x1 << 3) /* RW */
98 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
99 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
100 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
101 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */
102 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */
103 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
104 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */
105 #define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */
106 #define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */
107 #define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */
108
109 /* MSDC_IOCON mask */
110 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
111 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
112 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
113 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
114 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
115 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
116 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */
117 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
118 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
119 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
120 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
121 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
122 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
123 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
124 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
125 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
126
127 /* MSDC_PS mask */
128 #define MSDC_PS_CDEN (0x1 << 0) /* RW */
129 #define MSDC_PS_CDSTS (0x1 << 1) /* R */
130 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
131 #define MSDC_PS_DAT (0xff << 16) /* R */
132 #define MSDC_PS_CMD (0x1 << 24) /* R */
133 #define MSDC_PS_WP (0x1 << 31) /* R */
134
135 /* MSDC_INT mask */
136 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
137 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */
138 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
139 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
140 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
141 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
142 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
143 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
144 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
145 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
146 #define MSDC_INT_CSTA (0x1 << 11) /* R */
147 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
148 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
149 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
150 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
151 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
152 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */
153 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */
154 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */
155
156 /* MSDC_INTEN mask */
157 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
158 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
159 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
160 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
161 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
162 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
163 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
164 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
165 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
166 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
167 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
168 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
169 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
170 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
171 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
172 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
173 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */
174 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */
175 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */
176
177 /* MSDC_FIFOCS mask */
178 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
179 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
180 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */
181
182 /* SDC_CFG mask */
183 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
184 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
185 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
186 #define SDC_CFG_SDIO (0x1 << 19) /* RW */
187 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
188 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
189 #define SDC_CFG_DTOC (0xff << 24) /* RW */
190
191 /* SDC_STS mask */
192 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
193 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
194 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
195
196 /* SDC_ADV_CFG0 mask */
197 #define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */
198
199 /* DMA_SA_H4BIT mask */
200 #define DMA_ADDR_HIGH_4BIT (0xf << 0) /* RW */
201
202 /* MSDC_DMA_CTRL mask */
203 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
204 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
205 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
206 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
207 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
208 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
209
210 /* MSDC_DMA_CFG mask */
211 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
212 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
213 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */
214 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */
215 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */
216
217 /* MSDC_PATCH_BIT mask */
218 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
219 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7)
220 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10)
221 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
222 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
223 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
224 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
225 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
226 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
227 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
228 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
229 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
230
231 #define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */
232 #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */
233
234 #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */
235 #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */
236 #define MSDC_PB2_SUPPORT_64G (0x1 << 1) /* RW */
237 #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */
238 #define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */
239 #define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */
240
241 #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */
242 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */
243 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */
244 #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */
245 #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */
246 #define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */
247 #define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */
248 #define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */
249
250 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */
251 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */
252 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */
253
254 #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */
255
256 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */
257 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */
258 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */
259
260 #define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */
261
262 #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */
263 #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */
264
265 #define REQ_CMD_EIO (0x1 << 0)
266 #define REQ_CMD_TMO (0x1 << 1)
267 #define REQ_DAT_ERR (0x1 << 2)
268 #define REQ_STOP_EIO (0x1 << 3)
269 #define REQ_STOP_TMO (0x1 << 4)
270 #define REQ_CMD_BUSY (0x1 << 5)
271
272 #define MSDC_PREPARE_FLAG (0x1 << 0)
273 #define MSDC_ASYNC_FLAG (0x1 << 1)
274 #define MSDC_MMAP_FLAG (0x1 << 2)
275
276 #define MTK_MMC_AUTOSUSPEND_DELAY 50
277 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */
278 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */
279
280 #define PAD_DELAY_MAX 32 /* PAD delay cells */
281 /*--------------------------------------------------------------------------*/
282 /* Descriptor Structure */
283 /*--------------------------------------------------------------------------*/
284 struct mt_gpdma_desc {
285 u32 gpd_info;
286 #define GPDMA_DESC_HWO (0x1 << 0)
287 #define GPDMA_DESC_BDP (0x1 << 1)
288 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
289 #define GPDMA_DESC_INT (0x1 << 16)
290 #define GPDMA_DESC_NEXT_H4 (0xf << 24)
291 #define GPDMA_DESC_PTR_H4 (0xf << 28)
292 u32 next;
293 u32 ptr;
294 u32 gpd_data_len;
295 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
296 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */
297 u32 arg;
298 u32 blknum;
299 u32 cmd;
300 };
301
302 struct mt_bdma_desc {
303 u32 bd_info;
304 #define BDMA_DESC_EOL (0x1 << 0)
305 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
306 #define BDMA_DESC_BLKPAD (0x1 << 17)
307 #define BDMA_DESC_DWPAD (0x1 << 18)
308 #define BDMA_DESC_NEXT_H4 (0xf << 24)
309 #define BDMA_DESC_PTR_H4 (0xf << 28)
310 u32 next;
311 u32 ptr;
312 u32 bd_data_len;
313 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
314 };
315
316 struct msdc_dma {
317 struct scatterlist *sg; /* I/O scatter list */
318 struct mt_gpdma_desc *gpd; /* pointer to gpd array */
319 struct mt_bdma_desc *bd; /* pointer to bd array */
320 dma_addr_t gpd_addr; /* the physical address of gpd array */
321 dma_addr_t bd_addr; /* the physical address of bd array */
322 };
323
324 struct msdc_save_para {
325 u32 msdc_cfg;
326 u32 iocon;
327 u32 sdc_cfg;
328 u32 pad_tune;
329 u32 patch_bit0;
330 u32 patch_bit1;
331 u32 patch_bit2;
332 u32 pad_ds_tune;
333 u32 pad_cmd_tune;
334 u32 emmc50_cfg0;
335 u32 emmc50_cfg3;
336 u32 sdc_fifo_cfg;
337 };
338
339 struct mtk_mmc_compatible {
340 u8 clk_div_bits;
341 bool hs400_tune; /* only used for MT8173 */
342 u32 pad_tune_reg;
343 bool async_fifo;
344 bool data_tune;
345 bool busy_check;
346 bool stop_clk_fix;
347 bool enhance_rx;
348 bool support_64g;
349 };
350
351 struct msdc_tune_para {
352 u32 iocon;
353 u32 pad_tune;
354 u32 pad_cmd_tune;
355 };
356
357 struct msdc_delay_phase {
358 u8 maxlen;
359 u8 start;
360 u8 final_phase;
361 };
362
363 struct msdc_host {
364 struct device *dev;
365 const struct mtk_mmc_compatible *dev_comp;
366 struct mmc_host *mmc; /* mmc structure */
367 int cmd_rsp;
368
369 spinlock_t lock;
370 struct mmc_request *mrq;
371 struct mmc_command *cmd;
372 struct mmc_data *data;
373 int error;
374
375 void __iomem *base; /* host base address */
376
377 struct msdc_dma dma; /* dma channel */
378 u64 dma_mask;
379
380 u32 timeout_ns; /* data timeout ns */
381 u32 timeout_clks; /* data timeout clks */
382
383 struct pinctrl *pinctrl;
384 struct pinctrl_state *pins_default;
385 struct pinctrl_state *pins_uhs;
386 struct delayed_work req_timeout;
387 int irq; /* host interrupt */
388
389 struct clk *src_clk; /* msdc source clock */
390 struct clk *h_clk; /* msdc h_clk */
391 struct clk *src_clk_cg; /* msdc source clock control gate */
392 u32 mclk; /* mmc subsystem clock frequency */
393 u32 src_clk_freq; /* source clock frequency */
394 unsigned char timing;
395 bool vqmmc_enabled;
396 u32 latch_ck;
397 u32 hs400_ds_delay;
398 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
399 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
400 bool hs400_cmd_resp_sel_rising;
401 /* cmd response sample selection for HS400 */
402 bool hs400_mode; /* current eMMC will run at hs400 mode */
403 struct msdc_save_para save_para; /* used when gate HCLK */
404 struct msdc_tune_para def_tune_para; /* default tune setting */
405 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
406 };
407
408 static const struct mtk_mmc_compatible mt8135_compat = {
409 .clk_div_bits = 8,
410 .hs400_tune = false,
411 .pad_tune_reg = MSDC_PAD_TUNE,
412 .async_fifo = false,
413 .data_tune = false,
414 .busy_check = false,
415 .stop_clk_fix = false,
416 .enhance_rx = false,
417 .support_64g = false,
418 };
419
420 static const struct mtk_mmc_compatible mt8173_compat = {
421 .clk_div_bits = 8,
422 .hs400_tune = true,
423 .pad_tune_reg = MSDC_PAD_TUNE,
424 .async_fifo = false,
425 .data_tune = false,
426 .busy_check = false,
427 .stop_clk_fix = false,
428 .enhance_rx = false,
429 .support_64g = false,
430 };
431
432 static const struct mtk_mmc_compatible mt2701_compat = {
433 .clk_div_bits = 12,
434 .hs400_tune = false,
435 .pad_tune_reg = MSDC_PAD_TUNE0,
436 .async_fifo = true,
437 .data_tune = true,
438 .busy_check = false,
439 .stop_clk_fix = false,
440 .enhance_rx = false,
441 .support_64g = false,
442 };
443
444 static const struct mtk_mmc_compatible mt2712_compat = {
445 .clk_div_bits = 12,
446 .hs400_tune = false,
447 .pad_tune_reg = MSDC_PAD_TUNE0,
448 .async_fifo = true,
449 .data_tune = true,
450 .busy_check = true,
451 .stop_clk_fix = true,
452 .enhance_rx = true,
453 .support_64g = true,
454 };
455
456 static const struct mtk_mmc_compatible mt7622_compat = {
457 .clk_div_bits = 12,
458 .hs400_tune = false,
459 .pad_tune_reg = MSDC_PAD_TUNE0,
460 .async_fifo = true,
461 .data_tune = true,
462 .busy_check = true,
463 .stop_clk_fix = true,
464 .enhance_rx = true,
465 .support_64g = false,
466 };
467
468 static const struct of_device_id msdc_of_ids[] = {
469 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
470 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
471 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
472 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
473 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
474 {}
475 };
476 MODULE_DEVICE_TABLE(of, msdc_of_ids);
477
478 static void sdr_set_bits(void __iomem *reg, u32 bs)
479 {
480 u32 val = readl(reg);
481
482 val |= bs;
483 writel(val, reg);
484 }
485
486 static void sdr_clr_bits(void __iomem *reg, u32 bs)
487 {
488 u32 val = readl(reg);
489
490 val &= ~bs;
491 writel(val, reg);
492 }
493
494 static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
495 {
496 unsigned int tv = readl(reg);
497
498 tv &= ~field;
499 tv |= ((val) << (ffs((unsigned int)field) - 1));
500 writel(tv, reg);
501 }
502
503 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
504 {
505 unsigned int tv = readl(reg);
506
507 *val = ((tv & field) >> (ffs((unsigned int)field) - 1));
508 }
509
510 static void msdc_reset_hw(struct msdc_host *host)
511 {
512 u32 val;
513
514 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
515 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST)
516 cpu_relax();
517
518 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
519 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR)
520 cpu_relax();
521
522 val = readl(host->base + MSDC_INT);
523 writel(val, host->base + MSDC_INT);
524 }
525
526 static void msdc_cmd_next(struct msdc_host *host,
527 struct mmc_request *mrq, struct mmc_command *cmd);
528
529 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
530 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
531 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
532 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
533 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
534 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
535
536 static u8 msdc_dma_calcs(u8 *buf, u32 len)
537 {
538 u32 i, sum = 0;
539
540 for (i = 0; i < len; i++)
541 sum += buf[i];
542 return 0xff - (u8) sum;
543 }
544
545 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
546 struct mmc_data *data)
547 {
548 unsigned int j, dma_len;
549 dma_addr_t dma_address;
550 u32 dma_ctrl;
551 struct scatterlist *sg;
552 struct mt_gpdma_desc *gpd;
553 struct mt_bdma_desc *bd;
554
555 sg = data->sg;
556
557 gpd = dma->gpd;
558 bd = dma->bd;
559
560 /* modify gpd */
561 gpd->gpd_info |= GPDMA_DESC_HWO;
562 gpd->gpd_info |= GPDMA_DESC_BDP;
563 /* need to clear first. use these bits to calc checksum */
564 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
565 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
566
567 /* modify bd */
568 for_each_sg(data->sg, sg, data->sg_count, j) {
569 dma_address = sg_dma_address(sg);
570 dma_len = sg_dma_len(sg);
571
572 /* init bd */
573 bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
574 bd[j].bd_info &= ~BDMA_DESC_DWPAD;
575 bd[j].ptr = lower_32_bits(dma_address);
576 if (host->dev_comp->support_64g) {
577 bd[j].bd_info &= ~BDMA_DESC_PTR_H4;
578 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf)
579 << 28;
580 }
581 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
582 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
583
584 if (j == data->sg_count - 1) /* the last bd */
585 bd[j].bd_info |= BDMA_DESC_EOL;
586 else
587 bd[j].bd_info &= ~BDMA_DESC_EOL;
588
589 /* checksume need to clear first */
590 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
591 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
592 }
593
594 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
595 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
596 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
597 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8);
598 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
599 if (host->dev_comp->support_64g)
600 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
601 upper_32_bits(dma->gpd_addr) & 0xf);
602 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
603 }
604
605 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq)
606 {
607 struct mmc_data *data = mrq->data;
608
609 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
610 data->host_cookie |= MSDC_PREPARE_FLAG;
611 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
612 mmc_get_dma_dir(data));
613 }
614 }
615
616 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq)
617 {
618 struct mmc_data *data = mrq->data;
619
620 if (data->host_cookie & MSDC_ASYNC_FLAG)
621 return;
622
623 if (data->host_cookie & MSDC_PREPARE_FLAG) {
624 dma_unmap_sg(host->dev, data->sg, data->sg_len,
625 mmc_get_dma_dir(data));
626 data->host_cookie &= ~MSDC_PREPARE_FLAG;
627 }
628 }
629
630 /* clock control primitives */
631 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
632 {
633 u32 timeout, clk_ns;
634 u32 mode = 0;
635
636 host->timeout_ns = ns;
637 host->timeout_clks = clks;
638 if (host->mmc->actual_clock == 0) {
639 timeout = 0;
640 } else {
641 clk_ns = 1000000000UL / host->mmc->actual_clock;
642 timeout = (ns + clk_ns - 1) / clk_ns + clks;
643 /* in 1048576 sclk cycle unit */
644 timeout = (timeout + (0x1 << 20) - 1) >> 20;
645 if (host->dev_comp->clk_div_bits == 8)
646 sdr_get_field(host->base + MSDC_CFG,
647 MSDC_CFG_CKMOD, &mode);
648 else
649 sdr_get_field(host->base + MSDC_CFG,
650 MSDC_CFG_CKMOD_EXTRA, &mode);
651 /*DDR mode will double the clk cycles for data timeout */
652 timeout = mode >= 2 ? timeout * 2 : timeout;
653 timeout = timeout > 1 ? timeout - 1 : 0;
654 timeout = timeout > 255 ? 255 : timeout;
655 }
656 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout);
657 }
658
659 static void msdc_gate_clock(struct msdc_host *host)
660 {
661 clk_disable_unprepare(host->src_clk_cg);
662 clk_disable_unprepare(host->src_clk);
663 clk_disable_unprepare(host->h_clk);
664 }
665
666 static void msdc_ungate_clock(struct msdc_host *host)
667 {
668 clk_prepare_enable(host->h_clk);
669 clk_prepare_enable(host->src_clk);
670 clk_prepare_enable(host->src_clk_cg);
671 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
672 cpu_relax();
673 }
674
675 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
676 {
677 u32 mode;
678 u32 flags;
679 u32 div;
680 u32 sclk;
681 u32 tune_reg = host->dev_comp->pad_tune_reg;
682
683 if (!hz) {
684 dev_dbg(host->dev, "set mclk to 0\n");
685 host->mclk = 0;
686 host->mmc->actual_clock = 0;
687 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
688 return;
689 }
690
691 flags = readl(host->base + MSDC_INTEN);
692 sdr_clr_bits(host->base + MSDC_INTEN, flags);
693 if (host->dev_comp->clk_div_bits == 8)
694 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
695 else
696 sdr_clr_bits(host->base + MSDC_CFG,
697 MSDC_CFG_HS400_CK_MODE_EXTRA);
698 if (timing == MMC_TIMING_UHS_DDR50 ||
699 timing == MMC_TIMING_MMC_DDR52 ||
700 timing == MMC_TIMING_MMC_HS400) {
701 if (timing == MMC_TIMING_MMC_HS400)
702 mode = 0x3;
703 else
704 mode = 0x2; /* ddr mode and use divisor */
705
706 if (hz >= (host->src_clk_freq >> 2)) {
707 div = 0; /* mean div = 1/4 */
708 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
709 } else {
710 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
711 sclk = (host->src_clk_freq >> 2) / div;
712 div = (div >> 1);
713 }
714
715 if (timing == MMC_TIMING_MMC_HS400 &&
716 hz >= (host->src_clk_freq >> 1)) {
717 if (host->dev_comp->clk_div_bits == 8)
718 sdr_set_bits(host->base + MSDC_CFG,
719 MSDC_CFG_HS400_CK_MODE);
720 else
721 sdr_set_bits(host->base + MSDC_CFG,
722 MSDC_CFG_HS400_CK_MODE_EXTRA);
723 sclk = host->src_clk_freq >> 1;
724 div = 0; /* div is ignore when bit18 is set */
725 }
726 } else if (hz >= host->src_clk_freq) {
727 mode = 0x1; /* no divisor */
728 div = 0;
729 sclk = host->src_clk_freq;
730 } else {
731 mode = 0x0; /* use divisor */
732 if (hz >= (host->src_clk_freq >> 1)) {
733 div = 0; /* mean div = 1/2 */
734 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
735 } else {
736 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
737 sclk = (host->src_clk_freq >> 2) / div;
738 }
739 }
740 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
741 /*
742 * As src_clk/HCLK use the same bit to gate/ungate,
743 * So if want to only gate src_clk, need gate its parent(mux).
744 */
745 if (host->src_clk_cg)
746 clk_disable_unprepare(host->src_clk_cg);
747 else
748 clk_disable_unprepare(clk_get_parent(host->src_clk));
749 if (host->dev_comp->clk_div_bits == 8)
750 sdr_set_field(host->base + MSDC_CFG,
751 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
752 (mode << 8) | div);
753 else
754 sdr_set_field(host->base + MSDC_CFG,
755 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
756 (mode << 12) | div);
757 if (host->src_clk_cg)
758 clk_prepare_enable(host->src_clk_cg);
759 else
760 clk_prepare_enable(clk_get_parent(host->src_clk));
761
762 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
763 cpu_relax();
764 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
765 host->mmc->actual_clock = sclk;
766 host->mclk = hz;
767 host->timing = timing;
768 /* need because clk changed. */
769 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
770 sdr_set_bits(host->base + MSDC_INTEN, flags);
771
772 /*
773 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
774 * tune result of hs200/200Mhz is not suitable for 50Mhz
775 */
776 if (host->mmc->actual_clock <= 52000000) {
777 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
778 writel(host->def_tune_para.pad_tune, host->base + tune_reg);
779 } else {
780 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
781 writel(host->saved_tune_para.pad_tune, host->base + tune_reg);
782 writel(host->saved_tune_para.pad_cmd_tune,
783 host->base + PAD_CMD_TUNE);
784 }
785
786 if (timing == MMC_TIMING_MMC_HS400 &&
787 host->dev_comp->hs400_tune)
788 sdr_set_field(host->base + tune_reg,
789 MSDC_PAD_TUNE_CMDRRDLY,
790 host->hs400_cmd_int_delay);
791 dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->mmc->actual_clock,
792 timing);
793 }
794
795 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
796 struct mmc_request *mrq, struct mmc_command *cmd)
797 {
798 u32 resp;
799
800 switch (mmc_resp_type(cmd)) {
801 /* Actually, R1, R5, R6, R7 are the same */
802 case MMC_RSP_R1:
803 resp = 0x1;
804 break;
805 case MMC_RSP_R1B:
806 resp = 0x7;
807 break;
808 case MMC_RSP_R2:
809 resp = 0x2;
810 break;
811 case MMC_RSP_R3:
812 resp = 0x3;
813 break;
814 case MMC_RSP_NONE:
815 default:
816 resp = 0x0;
817 break;
818 }
819
820 return resp;
821 }
822
823 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
824 struct mmc_request *mrq, struct mmc_command *cmd)
825 {
826 /* rawcmd :
827 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
828 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
829 */
830 u32 opcode = cmd->opcode;
831 u32 resp = msdc_cmd_find_resp(host, mrq, cmd);
832 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
833
834 host->cmd_rsp = resp;
835
836 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
837 opcode == MMC_STOP_TRANSMISSION)
838 rawcmd |= (0x1 << 14);
839 else if (opcode == SD_SWITCH_VOLTAGE)
840 rawcmd |= (0x1 << 30);
841 else if (opcode == SD_APP_SEND_SCR ||
842 opcode == SD_APP_SEND_NUM_WR_BLKS ||
843 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
844 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
845 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
846 rawcmd |= (0x1 << 11);
847
848 if (cmd->data) {
849 struct mmc_data *data = cmd->data;
850
851 if (mmc_op_multi(opcode)) {
852 if (mmc_card_mmc(host->mmc->card) && mrq->sbc &&
853 !(mrq->sbc->arg & 0xFFFF0000))
854 rawcmd |= 0x2 << 28; /* AutoCMD23 */
855 }
856
857 rawcmd |= ((data->blksz & 0xFFF) << 16);
858 if (data->flags & MMC_DATA_WRITE)
859 rawcmd |= (0x1 << 13);
860 if (data->blocks > 1)
861 rawcmd |= (0x2 << 11);
862 else
863 rawcmd |= (0x1 << 11);
864 /* Always use dma mode */
865 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
866
867 if (host->timeout_ns != data->timeout_ns ||
868 host->timeout_clks != data->timeout_clks)
869 msdc_set_timeout(host, data->timeout_ns,
870 data->timeout_clks);
871
872 writel(data->blocks, host->base + SDC_BLK_NUM);
873 }
874 return rawcmd;
875 }
876
877 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq,
878 struct mmc_command *cmd, struct mmc_data *data)
879 {
880 bool read;
881
882 WARN_ON(host->data);
883 host->data = data;
884 read = data->flags & MMC_DATA_READ;
885
886 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
887 msdc_dma_setup(host, &host->dma, data);
888 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
889 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
890 dev_dbg(host->dev, "DMA start\n");
891 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
892 __func__, cmd->opcode, data->blocks, read);
893 }
894
895 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
896 struct mmc_command *cmd)
897 {
898 u32 *rsp = cmd->resp;
899
900 rsp[0] = readl(host->base + SDC_ACMD_RESP);
901
902 if (events & MSDC_INT_ACMDRDY) {
903 cmd->error = 0;
904 } else {
905 msdc_reset_hw(host);
906 if (events & MSDC_INT_ACMDCRCERR) {
907 cmd->error = -EILSEQ;
908 host->error |= REQ_STOP_EIO;
909 } else if (events & MSDC_INT_ACMDTMO) {
910 cmd->error = -ETIMEDOUT;
911 host->error |= REQ_STOP_TMO;
912 }
913 dev_err(host->dev,
914 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
915 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
916 }
917 return cmd->error;
918 }
919
920 static void msdc_track_cmd_data(struct msdc_host *host,
921 struct mmc_command *cmd, struct mmc_data *data)
922 {
923 if (host->error)
924 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
925 __func__, cmd->opcode, cmd->arg, host->error);
926 }
927
928 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
929 {
930 unsigned long flags;
931 bool ret;
932
933 ret = cancel_delayed_work(&host->req_timeout);
934 if (!ret) {
935 /* delay work already running */
936 return;
937 }
938 spin_lock_irqsave(&host->lock, flags);
939 host->mrq = NULL;
940 spin_unlock_irqrestore(&host->lock, flags);
941
942 msdc_track_cmd_data(host, mrq->cmd, mrq->data);
943 if (mrq->data)
944 msdc_unprepare_data(host, mrq);
945 mmc_request_done(host->mmc, mrq);
946 }
947
948 /* returns true if command is fully handled; returns false otherwise */
949 static bool msdc_cmd_done(struct msdc_host *host, int events,
950 struct mmc_request *mrq, struct mmc_command *cmd)
951 {
952 bool done = false;
953 bool sbc_error;
954 unsigned long flags;
955 u32 *rsp = cmd->resp;
956
957 if (mrq->sbc && cmd == mrq->cmd &&
958 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
959 | MSDC_INT_ACMDTMO)))
960 msdc_auto_cmd_done(host, events, mrq->sbc);
961
962 sbc_error = mrq->sbc && mrq->sbc->error;
963
964 if (!sbc_error && !(events & (MSDC_INT_CMDRDY
965 | MSDC_INT_RSPCRCERR
966 | MSDC_INT_CMDTMO)))
967 return done;
968
969 spin_lock_irqsave(&host->lock, flags);
970 done = !host->cmd;
971 host->cmd = NULL;
972 spin_unlock_irqrestore(&host->lock, flags);
973
974 if (done)
975 return true;
976
977 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
978
979 if (cmd->flags & MMC_RSP_PRESENT) {
980 if (cmd->flags & MMC_RSP_136) {
981 rsp[0] = readl(host->base + SDC_RESP3);
982 rsp[1] = readl(host->base + SDC_RESP2);
983 rsp[2] = readl(host->base + SDC_RESP1);
984 rsp[3] = readl(host->base + SDC_RESP0);
985 } else {
986 rsp[0] = readl(host->base + SDC_RESP0);
987 }
988 }
989
990 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
991 if (cmd->opcode != MMC_SEND_TUNING_BLOCK &&
992 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)
993 /*
994 * should not clear fifo/interrupt as the tune data
995 * may have alreay come.
996 */
997 msdc_reset_hw(host);
998 if (events & MSDC_INT_RSPCRCERR) {
999 cmd->error = -EILSEQ;
1000 host->error |= REQ_CMD_EIO;
1001 } else if (events & MSDC_INT_CMDTMO) {
1002 cmd->error = -ETIMEDOUT;
1003 host->error |= REQ_CMD_TMO;
1004 }
1005 }
1006 if (cmd->error)
1007 dev_dbg(host->dev,
1008 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
1009 __func__, cmd->opcode, cmd->arg, rsp[0],
1010 cmd->error);
1011
1012 msdc_cmd_next(host, mrq, cmd);
1013 return true;
1014 }
1015
1016 /* It is the core layer's responsibility to ensure card status
1017 * is correct before issue a request. but host design do below
1018 * checks recommended.
1019 */
1020 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
1021 struct mmc_request *mrq, struct mmc_command *cmd)
1022 {
1023 /* The max busy time we can endure is 20ms */
1024 unsigned long tmo = jiffies + msecs_to_jiffies(20);
1025
1026 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) &&
1027 time_before(jiffies, tmo))
1028 cpu_relax();
1029 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) {
1030 dev_err(host->dev, "CMD bus busy detected\n");
1031 host->error |= REQ_CMD_BUSY;
1032 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1033 return false;
1034 }
1035
1036 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
1037 tmo = jiffies + msecs_to_jiffies(20);
1038 /* R1B or with data, should check SDCBUSY */
1039 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) &&
1040 time_before(jiffies, tmo))
1041 cpu_relax();
1042 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) {
1043 dev_err(host->dev, "Controller busy detected\n");
1044 host->error |= REQ_CMD_BUSY;
1045 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1046 return false;
1047 }
1048 }
1049 return true;
1050 }
1051
1052 static void msdc_start_command(struct msdc_host *host,
1053 struct mmc_request *mrq, struct mmc_command *cmd)
1054 {
1055 u32 rawcmd;
1056
1057 WARN_ON(host->cmd);
1058 host->cmd = cmd;
1059
1060 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1061 if (!msdc_cmd_is_ready(host, mrq, cmd))
1062 return;
1063
1064 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
1065 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
1066 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
1067 msdc_reset_hw(host);
1068 }
1069
1070 cmd->error = 0;
1071 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
1072
1073 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1074 writel(cmd->arg, host->base + SDC_ARG);
1075 writel(rawcmd, host->base + SDC_CMD);
1076 }
1077
1078 static void msdc_cmd_next(struct msdc_host *host,
1079 struct mmc_request *mrq, struct mmc_command *cmd)
1080 {
1081 if ((cmd->error &&
1082 !(cmd->error == -EILSEQ &&
1083 (cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1084 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) ||
1085 (mrq->sbc && mrq->sbc->error))
1086 msdc_request_done(host, mrq);
1087 else if (cmd == mrq->sbc)
1088 msdc_start_command(host, mrq, mrq->cmd);
1089 else if (!cmd->data)
1090 msdc_request_done(host, mrq);
1091 else
1092 msdc_start_data(host, mrq, cmd, cmd->data);
1093 }
1094
1095 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
1096 {
1097 struct msdc_host *host = mmc_priv(mmc);
1098
1099 host->error = 0;
1100 WARN_ON(host->mrq);
1101 host->mrq = mrq;
1102
1103 if (mrq->data)
1104 msdc_prepare_data(host, mrq);
1105
1106 /* if SBC is required, we have HW option and SW option.
1107 * if HW option is enabled, and SBC does not have "special" flags,
1108 * use HW option, otherwise use SW option
1109 */
1110 if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
1111 (mrq->sbc->arg & 0xFFFF0000)))
1112 msdc_start_command(host, mrq, mrq->sbc);
1113 else
1114 msdc_start_command(host, mrq, mrq->cmd);
1115 }
1116
1117 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1118 {
1119 struct msdc_host *host = mmc_priv(mmc);
1120 struct mmc_data *data = mrq->data;
1121
1122 if (!data)
1123 return;
1124
1125 msdc_prepare_data(host, mrq);
1126 data->host_cookie |= MSDC_ASYNC_FLAG;
1127 }
1128
1129 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1130 int err)
1131 {
1132 struct msdc_host *host = mmc_priv(mmc);
1133 struct mmc_data *data;
1134
1135 data = mrq->data;
1136 if (!data)
1137 return;
1138 if (data->host_cookie) {
1139 data->host_cookie &= ~MSDC_ASYNC_FLAG;
1140 msdc_unprepare_data(host, mrq);
1141 }
1142 }
1143
1144 static void msdc_data_xfer_next(struct msdc_host *host,
1145 struct mmc_request *mrq, struct mmc_data *data)
1146 {
1147 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
1148 !mrq->sbc)
1149 msdc_start_command(host, mrq, mrq->stop);
1150 else
1151 msdc_request_done(host, mrq);
1152 }
1153
1154 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events,
1155 struct mmc_request *mrq, struct mmc_data *data)
1156 {
1157 struct mmc_command *stop = data->stop;
1158 unsigned long flags;
1159 bool done;
1160 unsigned int check_data = events &
1161 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
1162 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
1163 | MSDC_INT_DMA_PROTECT);
1164
1165 spin_lock_irqsave(&host->lock, flags);
1166 done = !host->data;
1167 if (check_data)
1168 host->data = NULL;
1169 spin_unlock_irqrestore(&host->lock, flags);
1170
1171 if (done)
1172 return true;
1173
1174 if (check_data || (stop && stop->error)) {
1175 dev_dbg(host->dev, "DMA status: 0x%8X\n",
1176 readl(host->base + MSDC_DMA_CFG));
1177 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1178 1);
1179 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS)
1180 cpu_relax();
1181 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1182 dev_dbg(host->dev, "DMA stop\n");
1183
1184 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
1185 data->bytes_xfered = data->blocks * data->blksz;
1186 } else {
1187 dev_dbg(host->dev, "interrupt events: %x\n", events);
1188 msdc_reset_hw(host);
1189 host->error |= REQ_DAT_ERR;
1190 data->bytes_xfered = 0;
1191
1192 if (events & MSDC_INT_DATTMO)
1193 data->error = -ETIMEDOUT;
1194 else if (events & MSDC_INT_DATCRCERR)
1195 data->error = -EILSEQ;
1196
1197 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1198 __func__, mrq->cmd->opcode, data->blocks);
1199 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1200 (int)data->error, data->bytes_xfered);
1201 }
1202
1203 msdc_data_xfer_next(host, mrq, data);
1204 done = true;
1205 }
1206 return done;
1207 }
1208
1209 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1210 {
1211 u32 val = readl(host->base + SDC_CFG);
1212
1213 val &= ~SDC_CFG_BUSWIDTH;
1214
1215 switch (width) {
1216 default:
1217 case MMC_BUS_WIDTH_1:
1218 val |= (MSDC_BUS_1BITS << 16);
1219 break;
1220 case MMC_BUS_WIDTH_4:
1221 val |= (MSDC_BUS_4BITS << 16);
1222 break;
1223 case MMC_BUS_WIDTH_8:
1224 val |= (MSDC_BUS_8BITS << 16);
1225 break;
1226 }
1227
1228 writel(val, host->base + SDC_CFG);
1229 dev_dbg(host->dev, "Bus Width = %d", width);
1230 }
1231
1232 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1233 {
1234 struct msdc_host *host = mmc_priv(mmc);
1235 int ret = 0;
1236
1237 if (!IS_ERR(mmc->supply.vqmmc)) {
1238 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 &&
1239 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) {
1240 dev_err(host->dev, "Unsupported signal voltage!\n");
1241 return -EINVAL;
1242 }
1243
1244 ret = mmc_regulator_set_vqmmc(mmc, ios);
1245 if (ret) {
1246 dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1247 ret, ios->signal_voltage);
1248 } else {
1249 /* Apply different pinctrl settings for different signal voltage */
1250 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1251 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1252 else
1253 pinctrl_select_state(host->pinctrl, host->pins_default);
1254 }
1255 }
1256 return ret;
1257 }
1258
1259 static int msdc_card_busy(struct mmc_host *mmc)
1260 {
1261 struct msdc_host *host = mmc_priv(mmc);
1262 u32 status = readl(host->base + MSDC_PS);
1263
1264 /* only check if data0 is low */
1265 return !(status & BIT(16));
1266 }
1267
1268 static void msdc_request_timeout(struct work_struct *work)
1269 {
1270 struct msdc_host *host = container_of(work, struct msdc_host,
1271 req_timeout.work);
1272
1273 /* simulate HW timeout status */
1274 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1275 if (host->mrq) {
1276 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1277 host->mrq, host->mrq->cmd->opcode);
1278 if (host->cmd) {
1279 dev_err(host->dev, "%s: aborting cmd=%d\n",
1280 __func__, host->cmd->opcode);
1281 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1282 host->cmd);
1283 } else if (host->data) {
1284 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1285 __func__, host->mrq->cmd->opcode,
1286 host->data->blocks);
1287 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1288 host->data);
1289 }
1290 }
1291 }
1292
1293 static irqreturn_t msdc_irq(int irq, void *dev_id)
1294 {
1295 struct msdc_host *host = (struct msdc_host *) dev_id;
1296
1297 while (true) {
1298 unsigned long flags;
1299 struct mmc_request *mrq;
1300 struct mmc_command *cmd;
1301 struct mmc_data *data;
1302 u32 events, event_mask;
1303
1304 spin_lock_irqsave(&host->lock, flags);
1305 events = readl(host->base + MSDC_INT);
1306 event_mask = readl(host->base + MSDC_INTEN);
1307 /* clear interrupts */
1308 writel(events & event_mask, host->base + MSDC_INT);
1309
1310 mrq = host->mrq;
1311 cmd = host->cmd;
1312 data = host->data;
1313 spin_unlock_irqrestore(&host->lock, flags);
1314
1315 if (!(events & event_mask))
1316 break;
1317
1318 if (!mrq) {
1319 dev_err(host->dev,
1320 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1321 __func__, events, event_mask);
1322 WARN_ON(1);
1323 break;
1324 }
1325
1326 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1327
1328 if (cmd)
1329 msdc_cmd_done(host, events, mrq, cmd);
1330 else if (data)
1331 msdc_data_xfer_done(host, events, mrq, data);
1332 }
1333
1334 return IRQ_HANDLED;
1335 }
1336
1337 static void msdc_init_hw(struct msdc_host *host)
1338 {
1339 u32 val;
1340 u32 tune_reg = host->dev_comp->pad_tune_reg;
1341
1342 /* Configure to MMC/SD mode, clock free running */
1343 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1344
1345 /* Reset */
1346 msdc_reset_hw(host);
1347
1348 /* Disable card detection */
1349 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1350
1351 /* Disable and clear all interrupts */
1352 writel(0, host->base + MSDC_INTEN);
1353 val = readl(host->base + MSDC_INT);
1354 writel(val, host->base + MSDC_INT);
1355
1356 writel(0, host->base + tune_reg);
1357 writel(0, host->base + MSDC_IOCON);
1358 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1359 writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1360 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1361 writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
1362 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1363
1364 if (host->dev_comp->stop_clk_fix) {
1365 sdr_set_field(host->base + MSDC_PATCH_BIT1,
1366 MSDC_PATCH_BIT1_STOP_DLY, 3);
1367 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1368 SDC_FIFO_CFG_WRVALIDSEL);
1369 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1370 SDC_FIFO_CFG_RDVALIDSEL);
1371 }
1372
1373 if (host->dev_comp->busy_check)
1374 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7));
1375
1376 if (host->dev_comp->async_fifo) {
1377 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1378 MSDC_PB2_RESPWAIT, 3);
1379 if (host->dev_comp->enhance_rx) {
1380 sdr_set_bits(host->base + SDC_ADV_CFG0,
1381 SDC_RX_ENHANCE_EN);
1382 } else {
1383 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1384 MSDC_PB2_RESPSTSENSEL, 2);
1385 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1386 MSDC_PB2_CRCSTSENSEL, 2);
1387 }
1388 /* use async fifo, then no need tune internal delay */
1389 sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
1390 MSDC_PATCH_BIT2_CFGRESP);
1391 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1392 MSDC_PATCH_BIT2_CFGCRCSTS);
1393 }
1394
1395 if (host->dev_comp->support_64g)
1396 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1397 MSDC_PB2_SUPPORT_64G);
1398 if (host->dev_comp->data_tune) {
1399 sdr_set_bits(host->base + tune_reg,
1400 MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
1401 } else {
1402 /* choose clock tune */
1403 sdr_set_bits(host->base + tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
1404 }
1405
1406 /* Configure to enable SDIO mode.
1407 * it's must otherwise sdio cmd5 failed
1408 */
1409 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1410
1411 /* disable detect SDIO device interrupt function */
1412 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1413
1414 /* Configure to default data timeout */
1415 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1416
1417 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1418 host->def_tune_para.pad_tune = readl(host->base + tune_reg);
1419 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1420 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
1421 dev_dbg(host->dev, "init hardware done!");
1422 }
1423
1424 static void msdc_deinit_hw(struct msdc_host *host)
1425 {
1426 u32 val;
1427 /* Disable and clear all interrupts */
1428 writel(0, host->base + MSDC_INTEN);
1429
1430 val = readl(host->base + MSDC_INT);
1431 writel(val, host->base + MSDC_INT);
1432 }
1433
1434 /* init gpd and bd list in msdc_drv_probe */
1435 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1436 {
1437 struct mt_gpdma_desc *gpd = dma->gpd;
1438 struct mt_bdma_desc *bd = dma->bd;
1439 dma_addr_t dma_addr;
1440 int i;
1441
1442 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
1443
1444 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc);
1445 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
1446 /* gpd->next is must set for desc DMA
1447 * That's why must alloc 2 gpd structure.
1448 */
1449 gpd->next = lower_32_bits(dma_addr);
1450 if (host->dev_comp->support_64g)
1451 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1452
1453 dma_addr = dma->bd_addr;
1454 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */
1455 if (host->dev_comp->support_64g)
1456 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28;
1457
1458 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
1459 for (i = 0; i < (MAX_BD_NUM - 1); i++) {
1460 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1);
1461 bd[i].next = lower_32_bits(dma_addr);
1462 if (host->dev_comp->support_64g)
1463 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1464 }
1465 }
1466
1467 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1468 {
1469 struct msdc_host *host = mmc_priv(mmc);
1470 int ret;
1471
1472 msdc_set_buswidth(host, ios->bus_width);
1473
1474 /* Suspend/Resume will do power off/on */
1475 switch (ios->power_mode) {
1476 case MMC_POWER_UP:
1477 if (!IS_ERR(mmc->supply.vmmc)) {
1478 msdc_init_hw(host);
1479 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1480 ios->vdd);
1481 if (ret) {
1482 dev_err(host->dev, "Failed to set vmmc power!\n");
1483 return;
1484 }
1485 }
1486 break;
1487 case MMC_POWER_ON:
1488 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1489 ret = regulator_enable(mmc->supply.vqmmc);
1490 if (ret)
1491 dev_err(host->dev, "Failed to set vqmmc power!\n");
1492 else
1493 host->vqmmc_enabled = true;
1494 }
1495 break;
1496 case MMC_POWER_OFF:
1497 if (!IS_ERR(mmc->supply.vmmc))
1498 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1499
1500 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1501 regulator_disable(mmc->supply.vqmmc);
1502 host->vqmmc_enabled = false;
1503 }
1504 break;
1505 default:
1506 break;
1507 }
1508
1509 if (host->mclk != ios->clock || host->timing != ios->timing)
1510 msdc_set_mclk(host, ios->timing, ios->clock);
1511 }
1512
1513 static u32 test_delay_bit(u32 delay, u32 bit)
1514 {
1515 bit %= PAD_DELAY_MAX;
1516 return delay & (1 << bit);
1517 }
1518
1519 static int get_delay_len(u32 delay, u32 start_bit)
1520 {
1521 int i;
1522
1523 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
1524 if (test_delay_bit(delay, start_bit + i) == 0)
1525 return i;
1526 }
1527 return PAD_DELAY_MAX - start_bit;
1528 }
1529
1530 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
1531 {
1532 int start = 0, len = 0;
1533 int start_final = 0, len_final = 0;
1534 u8 final_phase = 0xff;
1535 struct msdc_delay_phase delay_phase = { 0, };
1536
1537 if (delay == 0) {
1538 dev_err(host->dev, "phase error: [map:%x]\n", delay);
1539 delay_phase.final_phase = final_phase;
1540 return delay_phase;
1541 }
1542
1543 while (start < PAD_DELAY_MAX) {
1544 len = get_delay_len(delay, start);
1545 if (len_final < len) {
1546 start_final = start;
1547 len_final = len;
1548 }
1549 start += len ? len : 1;
1550 if (len >= 12 && start_final < 4)
1551 break;
1552 }
1553
1554 /* The rule is that to find the smallest delay cell */
1555 if (start_final == 0)
1556 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
1557 else
1558 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
1559 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
1560 delay, len_final, final_phase);
1561
1562 delay_phase.maxlen = len_final;
1563 delay_phase.start = start_final;
1564 delay_phase.final_phase = final_phase;
1565 return delay_phase;
1566 }
1567
1568 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
1569 {
1570 struct msdc_host *host = mmc_priv(mmc);
1571 u32 rise_delay = 0, fall_delay = 0;
1572 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1573 struct msdc_delay_phase internal_delay_phase;
1574 u8 final_delay, final_maxlen;
1575 u32 internal_delay = 0;
1576 u32 tune_reg = host->dev_comp->pad_tune_reg;
1577 int cmd_err;
1578 int i, j;
1579
1580 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
1581 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
1582 sdr_set_field(host->base + tune_reg,
1583 MSDC_PAD_TUNE_CMDRRDLY,
1584 host->hs200_cmd_int_delay);
1585
1586 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1587 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1588 sdr_set_field(host->base + tune_reg,
1589 MSDC_PAD_TUNE_CMDRDLY, i);
1590 /*
1591 * Using the same parameters, it may sometimes pass the test,
1592 * but sometimes it may fail. To make sure the parameters are
1593 * more stable, we test each set of parameters 3 times.
1594 */
1595 for (j = 0; j < 3; j++) {
1596 mmc_send_tuning(mmc, opcode, &cmd_err);
1597 if (!cmd_err) {
1598 rise_delay |= (1 << i);
1599 } else {
1600 rise_delay &= ~(1 << i);
1601 break;
1602 }
1603 }
1604 }
1605 final_rise_delay = get_best_delay(host, rise_delay);
1606 /* if rising edge has enough margin, then do not scan falling edge */
1607 if (final_rise_delay.maxlen >= 12 ||
1608 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1609 goto skip_fall;
1610
1611 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1612 for (i = 0; i < PAD_DELAY_MAX; i++) {
1613 sdr_set_field(host->base + tune_reg,
1614 MSDC_PAD_TUNE_CMDRDLY, i);
1615 /*
1616 * Using the same parameters, it may sometimes pass the test,
1617 * but sometimes it may fail. To make sure the parameters are
1618 * more stable, we test each set of parameters 3 times.
1619 */
1620 for (j = 0; j < 3; j++) {
1621 mmc_send_tuning(mmc, opcode, &cmd_err);
1622 if (!cmd_err) {
1623 fall_delay |= (1 << i);
1624 } else {
1625 fall_delay &= ~(1 << i);
1626 break;
1627 }
1628 }
1629 }
1630 final_fall_delay = get_best_delay(host, fall_delay);
1631
1632 skip_fall:
1633 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1634 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4)
1635 final_maxlen = final_fall_delay.maxlen;
1636 if (final_maxlen == final_rise_delay.maxlen) {
1637 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1638 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
1639 final_rise_delay.final_phase);
1640 final_delay = final_rise_delay.final_phase;
1641 } else {
1642 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1643 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
1644 final_fall_delay.final_phase);
1645 final_delay = final_fall_delay.final_phase;
1646 }
1647 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
1648 goto skip_internal;
1649
1650 for (i = 0; i < PAD_DELAY_MAX; i++) {
1651 sdr_set_field(host->base + tune_reg,
1652 MSDC_PAD_TUNE_CMDRRDLY, i);
1653 mmc_send_tuning(mmc, opcode, &cmd_err);
1654 if (!cmd_err)
1655 internal_delay |= (1 << i);
1656 }
1657 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
1658 internal_delay_phase = get_best_delay(host, internal_delay);
1659 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
1660 internal_delay_phase.final_phase);
1661 skip_internal:
1662 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
1663 return final_delay == 0xff ? -EIO : 0;
1664 }
1665
1666 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
1667 {
1668 struct msdc_host *host = mmc_priv(mmc);
1669 u32 cmd_delay = 0;
1670 struct msdc_delay_phase final_cmd_delay = { 0,};
1671 u8 final_delay;
1672 int cmd_err;
1673 int i, j;
1674
1675 /* select EMMC50 PAD CMD tune */
1676 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
1677 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
1678
1679 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
1680 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
1681 sdr_set_field(host->base + MSDC_PAD_TUNE,
1682 MSDC_PAD_TUNE_CMDRRDLY,
1683 host->hs200_cmd_int_delay);
1684
1685 if (host->hs400_cmd_resp_sel_rising)
1686 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1687 else
1688 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1689 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1690 sdr_set_field(host->base + PAD_CMD_TUNE,
1691 PAD_CMD_TUNE_RX_DLY3, i);
1692 /*
1693 * Using the same parameters, it may sometimes pass the test,
1694 * but sometimes it may fail. To make sure the parameters are
1695 * more stable, we test each set of parameters 3 times.
1696 */
1697 for (j = 0; j < 3; j++) {
1698 mmc_send_tuning(mmc, opcode, &cmd_err);
1699 if (!cmd_err) {
1700 cmd_delay |= (1 << i);
1701 } else {
1702 cmd_delay &= ~(1 << i);
1703 break;
1704 }
1705 }
1706 }
1707 final_cmd_delay = get_best_delay(host, cmd_delay);
1708 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
1709 final_cmd_delay.final_phase);
1710 final_delay = final_cmd_delay.final_phase;
1711
1712 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
1713 return final_delay == 0xff ? -EIO : 0;
1714 }
1715
1716 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
1717 {
1718 struct msdc_host *host = mmc_priv(mmc);
1719 u32 rise_delay = 0, fall_delay = 0;
1720 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1721 u8 final_delay, final_maxlen;
1722 u32 tune_reg = host->dev_comp->pad_tune_reg;
1723 int i, ret;
1724
1725 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
1726 host->latch_ck);
1727 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1728 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1729 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1730 sdr_set_field(host->base + tune_reg,
1731 MSDC_PAD_TUNE_DATRRDLY, i);
1732 ret = mmc_send_tuning(mmc, opcode, NULL);
1733 if (!ret)
1734 rise_delay |= (1 << i);
1735 }
1736 final_rise_delay = get_best_delay(host, rise_delay);
1737 /* if rising edge has enough margin, then do not scan falling edge */
1738 if (final_rise_delay.maxlen >= 12 ||
1739 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1740 goto skip_fall;
1741
1742 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1743 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1744 for (i = 0; i < PAD_DELAY_MAX; i++) {
1745 sdr_set_field(host->base + tune_reg,
1746 MSDC_PAD_TUNE_DATRRDLY, i);
1747 ret = mmc_send_tuning(mmc, opcode, NULL);
1748 if (!ret)
1749 fall_delay |= (1 << i);
1750 }
1751 final_fall_delay = get_best_delay(host, fall_delay);
1752
1753 skip_fall:
1754 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1755 if (final_maxlen == final_rise_delay.maxlen) {
1756 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1757 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1758 sdr_set_field(host->base + tune_reg,
1759 MSDC_PAD_TUNE_DATRRDLY,
1760 final_rise_delay.final_phase);
1761 final_delay = final_rise_delay.final_phase;
1762 } else {
1763 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1764 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1765 sdr_set_field(host->base + tune_reg,
1766 MSDC_PAD_TUNE_DATRRDLY,
1767 final_fall_delay.final_phase);
1768 final_delay = final_fall_delay.final_phase;
1769 }
1770
1771 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
1772 return final_delay == 0xff ? -EIO : 0;
1773 }
1774
1775 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1776 {
1777 struct msdc_host *host = mmc_priv(mmc);
1778 int ret;
1779 u32 tune_reg = host->dev_comp->pad_tune_reg;
1780
1781 if (host->hs400_mode &&
1782 host->dev_comp->hs400_tune)
1783 ret = hs400_tune_response(mmc, opcode);
1784 else
1785 ret = msdc_tune_response(mmc, opcode);
1786 if (ret == -EIO) {
1787 dev_err(host->dev, "Tune response fail!\n");
1788 return ret;
1789 }
1790 if (host->hs400_mode == false) {
1791 ret = msdc_tune_data(mmc, opcode);
1792 if (ret == -EIO)
1793 dev_err(host->dev, "Tune data fail!\n");
1794 }
1795
1796 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1797 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
1798 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
1799 return ret;
1800 }
1801
1802 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1803 {
1804 struct msdc_host *host = mmc_priv(mmc);
1805 host->hs400_mode = true;
1806
1807 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
1808 /* hs400 mode must set it to 0 */
1809 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
1810 /* to improve read performance, set outstanding to 2 */
1811 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
1812
1813 return 0;
1814 }
1815
1816 static void msdc_hw_reset(struct mmc_host *mmc)
1817 {
1818 struct msdc_host *host = mmc_priv(mmc);
1819
1820 sdr_set_bits(host->base + EMMC_IOCON, 1);
1821 udelay(10); /* 10us is enough */
1822 sdr_clr_bits(host->base + EMMC_IOCON, 1);
1823 }
1824
1825 static const struct mmc_host_ops mt_msdc_ops = {
1826 .post_req = msdc_post_req,
1827 .pre_req = msdc_pre_req,
1828 .request = msdc_ops_request,
1829 .set_ios = msdc_ops_set_ios,
1830 .get_ro = mmc_gpio_get_ro,
1831 .get_cd = mmc_gpio_get_cd,
1832 .start_signal_voltage_switch = msdc_ops_switch_volt,
1833 .card_busy = msdc_card_busy,
1834 .execute_tuning = msdc_execute_tuning,
1835 .prepare_hs400_tuning = msdc_prepare_hs400_tuning,
1836 .hw_reset = msdc_hw_reset,
1837 };
1838
1839 static void msdc_of_property_parse(struct platform_device *pdev,
1840 struct msdc_host *host)
1841 {
1842 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
1843 &host->latch_ck);
1844
1845 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
1846 &host->hs400_ds_delay);
1847
1848 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay",
1849 &host->hs200_cmd_int_delay);
1850
1851 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay",
1852 &host->hs400_cmd_int_delay);
1853
1854 if (of_property_read_bool(pdev->dev.of_node,
1855 "mediatek,hs400-cmd-resp-sel-rising"))
1856 host->hs400_cmd_resp_sel_rising = true;
1857 else
1858 host->hs400_cmd_resp_sel_rising = false;
1859 }
1860
1861 static int msdc_drv_probe(struct platform_device *pdev)
1862 {
1863 struct mmc_host *mmc;
1864 struct msdc_host *host;
1865 struct resource *res;
1866 int ret;
1867
1868 if (!pdev->dev.of_node) {
1869 dev_err(&pdev->dev, "No DT found\n");
1870 return -EINVAL;
1871 }
1872
1873 /* Allocate MMC host for this device */
1874 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
1875 if (!mmc)
1876 return -ENOMEM;
1877
1878 host = mmc_priv(mmc);
1879 ret = mmc_of_parse(mmc);
1880 if (ret)
1881 goto host_free;
1882
1883 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1884 host->base = devm_ioremap_resource(&pdev->dev, res);
1885 if (IS_ERR(host->base)) {
1886 ret = PTR_ERR(host->base);
1887 goto host_free;
1888 }
1889
1890 ret = mmc_regulator_get_supply(mmc);
1891 if (ret)
1892 goto host_free;
1893
1894 host->src_clk = devm_clk_get(&pdev->dev, "source");
1895 if (IS_ERR(host->src_clk)) {
1896 ret = PTR_ERR(host->src_clk);
1897 goto host_free;
1898 }
1899
1900 host->h_clk = devm_clk_get(&pdev->dev, "hclk");
1901 if (IS_ERR(host->h_clk)) {
1902 ret = PTR_ERR(host->h_clk);
1903 goto host_free;
1904 }
1905
1906 /*source clock control gate is optional clock*/
1907 host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg");
1908 if (IS_ERR(host->src_clk_cg))
1909 host->src_clk_cg = NULL;
1910
1911 host->irq = platform_get_irq(pdev, 0);
1912 if (host->irq < 0) {
1913 ret = -EINVAL;
1914 goto host_free;
1915 }
1916
1917 host->pinctrl = devm_pinctrl_get(&pdev->dev);
1918 if (IS_ERR(host->pinctrl)) {
1919 ret = PTR_ERR(host->pinctrl);
1920 dev_err(&pdev->dev, "Cannot find pinctrl!\n");
1921 goto host_free;
1922 }
1923
1924 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
1925 if (IS_ERR(host->pins_default)) {
1926 ret = PTR_ERR(host->pins_default);
1927 dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
1928 goto host_free;
1929 }
1930
1931 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
1932 if (IS_ERR(host->pins_uhs)) {
1933 ret = PTR_ERR(host->pins_uhs);
1934 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
1935 goto host_free;
1936 }
1937
1938 msdc_of_property_parse(pdev, host);
1939
1940 host->dev = &pdev->dev;
1941 host->dev_comp = of_device_get_match_data(&pdev->dev);
1942 host->mmc = mmc;
1943 host->src_clk_freq = clk_get_rate(host->src_clk);
1944 /* Set host parameters to mmc */
1945 mmc->ops = &mt_msdc_ops;
1946 if (host->dev_comp->clk_div_bits == 8)
1947 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
1948 else
1949 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
1950
1951 mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23;
1952 /* MMC core transfer sizes tunable parameters */
1953 mmc->max_segs = MAX_BD_NUM;
1954 mmc->max_seg_size = BDMA_DESC_BUFLEN;
1955 mmc->max_blk_size = 2048;
1956 mmc->max_req_size = 512 * 1024;
1957 mmc->max_blk_count = mmc->max_req_size / 512;
1958 if (host->dev_comp->support_64g)
1959 host->dma_mask = DMA_BIT_MASK(36);
1960 else
1961 host->dma_mask = DMA_BIT_MASK(32);
1962 mmc_dev(mmc)->dma_mask = &host->dma_mask;
1963
1964 host->timeout_clks = 3 * 1048576;
1965 host->dma.gpd = dma_alloc_coherent(&pdev->dev,
1966 2 * sizeof(struct mt_gpdma_desc),
1967 &host->dma.gpd_addr, GFP_KERNEL);
1968 host->dma.bd = dma_alloc_coherent(&pdev->dev,
1969 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1970 &host->dma.bd_addr, GFP_KERNEL);
1971 if (!host->dma.gpd || !host->dma.bd) {
1972 ret = -ENOMEM;
1973 goto release_mem;
1974 }
1975 msdc_init_gpd_bd(host, &host->dma);
1976 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
1977 spin_lock_init(&host->lock);
1978
1979 platform_set_drvdata(pdev, mmc);
1980 msdc_ungate_clock(host);
1981 msdc_init_hw(host);
1982
1983 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
1984 IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host);
1985 if (ret)
1986 goto release;
1987
1988 pm_runtime_set_active(host->dev);
1989 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
1990 pm_runtime_use_autosuspend(host->dev);
1991 pm_runtime_enable(host->dev);
1992 ret = mmc_add_host(mmc);
1993
1994 if (ret)
1995 goto end;
1996
1997 return 0;
1998 end:
1999 pm_runtime_disable(host->dev);
2000 release:
2001 platform_set_drvdata(pdev, NULL);
2002 msdc_deinit_hw(host);
2003 msdc_gate_clock(host);
2004 release_mem:
2005 if (host->dma.gpd)
2006 dma_free_coherent(&pdev->dev,
2007 2 * sizeof(struct mt_gpdma_desc),
2008 host->dma.gpd, host->dma.gpd_addr);
2009 if (host->dma.bd)
2010 dma_free_coherent(&pdev->dev,
2011 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2012 host->dma.bd, host->dma.bd_addr);
2013 host_free:
2014 mmc_free_host(mmc);
2015
2016 return ret;
2017 }
2018
2019 static int msdc_drv_remove(struct platform_device *pdev)
2020 {
2021 struct mmc_host *mmc;
2022 struct msdc_host *host;
2023
2024 mmc = platform_get_drvdata(pdev);
2025 host = mmc_priv(mmc);
2026
2027 pm_runtime_get_sync(host->dev);
2028
2029 platform_set_drvdata(pdev, NULL);
2030 mmc_remove_host(host->mmc);
2031 msdc_deinit_hw(host);
2032 msdc_gate_clock(host);
2033
2034 pm_runtime_disable(host->dev);
2035 pm_runtime_put_noidle(host->dev);
2036 dma_free_coherent(&pdev->dev,
2037 2 * sizeof(struct mt_gpdma_desc),
2038 host->dma.gpd, host->dma.gpd_addr);
2039 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2040 host->dma.bd, host->dma.bd_addr);
2041
2042 mmc_free_host(host->mmc);
2043
2044 return 0;
2045 }
2046
2047 #ifdef CONFIG_PM
2048 static void msdc_save_reg(struct msdc_host *host)
2049 {
2050 u32 tune_reg = host->dev_comp->pad_tune_reg;
2051
2052 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
2053 host->save_para.iocon = readl(host->base + MSDC_IOCON);
2054 host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
2055 host->save_para.pad_tune = readl(host->base + tune_reg);
2056 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
2057 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
2058 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
2059 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
2060 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2061 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
2062 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
2063 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
2064 }
2065
2066 static void msdc_restore_reg(struct msdc_host *host)
2067 {
2068 u32 tune_reg = host->dev_comp->pad_tune_reg;
2069
2070 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
2071 writel(host->save_para.iocon, host->base + MSDC_IOCON);
2072 writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
2073 writel(host->save_para.pad_tune, host->base + tune_reg);
2074 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
2075 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
2076 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
2077 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
2078 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
2079 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
2080 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
2081 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
2082 }
2083
2084 static int msdc_runtime_suspend(struct device *dev)
2085 {
2086 struct mmc_host *mmc = dev_get_drvdata(dev);
2087 struct msdc_host *host = mmc_priv(mmc);
2088
2089 msdc_save_reg(host);
2090 msdc_gate_clock(host);
2091 return 0;
2092 }
2093
2094 static int msdc_runtime_resume(struct device *dev)
2095 {
2096 struct mmc_host *mmc = dev_get_drvdata(dev);
2097 struct msdc_host *host = mmc_priv(mmc);
2098
2099 msdc_ungate_clock(host);
2100 msdc_restore_reg(host);
2101 return 0;
2102 }
2103 #endif
2104
2105 static const struct dev_pm_ops msdc_dev_pm_ops = {
2106 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2107 pm_runtime_force_resume)
2108 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
2109 };
2110
2111 static struct platform_driver mt_msdc_driver = {
2112 .probe = msdc_drv_probe,
2113 .remove = msdc_drv_remove,
2114 .driver = {
2115 .name = "mtk-msdc",
2116 .of_match_table = msdc_of_ids,
2117 .pm = &msdc_dev_pm_ops,
2118 },
2119 };
2120
2121 module_platform_driver(mt_msdc_driver);
2122 MODULE_LICENSE("GPL v2");
2123 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");
Linux with added FPC-III support