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vt: vt_ioctl: fix VT_DISALLOCATE freeing in-use virtual console
[linux/fpc-iii.git] / drivers / mmc / host / sdhci-esdhc-imx.c
blob629860f7327c9e465331a568e2556b0550d3f192
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Freescale eSDHC i.MX controller driver for the platform bus.
4 *
5 * derived from the OF-version.
6 *
7 * Copyright (c) 2010 Pengutronix e.K.
8 * Author: Wolfram Sang <kernel@pengutronix.de>
9 */
10
11 #include <linux/io.h>
12 #include <linux/delay.h>
13 #include <linux/err.h>
14 #include <linux/clk.h>
15 #include <linux/gpio.h>
16 #include <linux/module.h>
17 #include <linux/slab.h>
18 #include <linux/mmc/host.h>
19 #include <linux/mmc/mmc.h>
20 #include <linux/mmc/sdio.h>
21 #include <linux/mmc/slot-gpio.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/of_gpio.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <linux/platform_data/mmc-esdhc-imx.h>
27 #include <linux/pm_runtime.h>
28 #include "sdhci-pltfm.h"
29 #include "sdhci-esdhc.h"
30
31 #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f
32 #define ESDHC_CTRL_D3CD 0x08
33 #define ESDHC_BURST_LEN_EN_INCR (1 << 27)
34 /* VENDOR SPEC register */
35 #define ESDHC_VENDOR_SPEC 0xc0
36 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
37 #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
38 #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
39 #define ESDHC_WTMK_LVL 0x44
40 #define ESDHC_WTMK_DEFAULT_VAL 0x10401040
41 #define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF
42 #define ESDHC_WTMK_LVL_RD_WML_SHIFT 0
43 #define ESDHC_WTMK_LVL_WR_WML_MASK 0x00FF0000
44 #define ESDHC_WTMK_LVL_WR_WML_SHIFT 16
45 #define ESDHC_WTMK_LVL_WML_VAL_DEF 64
46 #define ESDHC_WTMK_LVL_WML_VAL_MAX 128
47 #define ESDHC_MIX_CTRL 0x48
48 #define ESDHC_MIX_CTRL_DDREN (1 << 3)
49 #define ESDHC_MIX_CTRL_AC23EN (1 << 7)
50 #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
51 #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
52 #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24)
53 #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
54 #define ESDHC_MIX_CTRL_HS400_EN (1 << 26)
55 /* Bits 3 and 6 are not SDHCI standard definitions */
56 #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
57 /* Tuning bits */
58 #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000
59
60 /* dll control register */
61 #define ESDHC_DLL_CTRL 0x60
62 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
63 #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
64
65 /* tune control register */
66 #define ESDHC_TUNE_CTRL_STATUS 0x68
67 #define ESDHC_TUNE_CTRL_STEP 1
68 #define ESDHC_TUNE_CTRL_MIN 0
69 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
70
71 /* strobe dll register */
72 #define ESDHC_STROBE_DLL_CTRL 0x70
73 #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0)
74 #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1)
75 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
76
77 #define ESDHC_STROBE_DLL_STATUS 0x74
78 #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1)
79 #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
80
81 #define ESDHC_TUNING_CTRL 0xcc
82 #define ESDHC_STD_TUNING_EN (1 << 24)
83 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
84 #define ESDHC_TUNING_START_TAP_DEFAULT 0x1
85 #define ESDHC_TUNING_START_TAP_MASK 0xff
86 #define ESDHC_TUNING_STEP_MASK 0x00070000
87 #define ESDHC_TUNING_STEP_SHIFT 16
88
89 /* pinctrl state */
90 #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
91 #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
92
93 /*
94 * Our interpretation of the SDHCI_HOST_CONTROL register
95 */
96 #define ESDHC_CTRL_4BITBUS (0x1 << 1)
97 #define ESDHC_CTRL_8BITBUS (0x2 << 1)
98 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
99
100 /*
101 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
102 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
103 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
104 * Define this macro DMA error INT for fsl eSDHC
105 */
106 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
107
108 /*
109 * The CMDTYPE of the CMD register (offset 0xE) should be set to
110 * "11" when the STOP CMD12 is issued on imx53 to abort one
111 * open ended multi-blk IO. Otherwise the TC INT wouldn't
112 * be generated.
113 * In exact block transfer, the controller doesn't complete the
114 * operations automatically as required at the end of the
115 * transfer and remains on hold if the abort command is not sent.
116 * As a result, the TC flag is not asserted and SW received timeout
117 * exception. Bit1 of Vendor Spec register is used to fix it.
118 */
119 #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
120 /*
121 * The flag tells that the ESDHC controller is an USDHC block that is
122 * integrated on the i.MX6 series.
123 */
124 #define ESDHC_FLAG_USDHC BIT(3)
125 /* The IP supports manual tuning process */
126 #define ESDHC_FLAG_MAN_TUNING BIT(4)
127 /* The IP supports standard tuning process */
128 #define ESDHC_FLAG_STD_TUNING BIT(5)
129 /* The IP has SDHCI_CAPABILITIES_1 register */
130 #define ESDHC_FLAG_HAVE_CAP1 BIT(6)
131 /*
132 * The IP has erratum ERR004536
133 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
134 * when reading data from the card
135 * This flag is also set for i.MX25 and i.MX35 in order to get
136 * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits).
137 */
138 #define ESDHC_FLAG_ERR004536 BIT(7)
139 /* The IP supports HS200 mode */
140 #define ESDHC_FLAG_HS200 BIT(8)
141 /* The IP supports HS400 mode */
142 #define ESDHC_FLAG_HS400 BIT(9)
143
144 /* A clock frequency higher than this rate requires strobe dll control */
145 #define ESDHC_STROBE_DLL_CLK_FREQ 100000000
146
147 struct esdhc_soc_data {
148 u32 flags;
149 };
150
151 static struct esdhc_soc_data esdhc_imx25_data = {
152 .flags = ESDHC_FLAG_ERR004536,
153 };
154
155 static struct esdhc_soc_data esdhc_imx35_data = {
156 .flags = ESDHC_FLAG_ERR004536,
157 };
158
159 static struct esdhc_soc_data esdhc_imx51_data = {
160 .flags = 0,
161 };
162
163 static struct esdhc_soc_data esdhc_imx53_data = {
164 .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
165 };
166
167 static struct esdhc_soc_data usdhc_imx6q_data = {
168 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
169 };
170
171 static struct esdhc_soc_data usdhc_imx6sl_data = {
172 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
173 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
174 | ESDHC_FLAG_HS200,
175 };
176
177 static struct esdhc_soc_data usdhc_imx6sx_data = {
178 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
179 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
180 };
181
182 static struct esdhc_soc_data usdhc_imx7d_data = {
183 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
184 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
185 | ESDHC_FLAG_HS400,
186 };
187
188 struct pltfm_imx_data {
189 u32 scratchpad;
190 struct pinctrl *pinctrl;
191 struct pinctrl_state *pins_default;
192 struct pinctrl_state *pins_100mhz;
193 struct pinctrl_state *pins_200mhz;
194 const struct esdhc_soc_data *socdata;
195 struct esdhc_platform_data boarddata;
196 struct clk *clk_ipg;
197 struct clk *clk_ahb;
198 struct clk *clk_per;
199 unsigned int actual_clock;
200 enum {
201 NO_CMD_PENDING, /* no multiblock command pending */
202 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
203 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
204 } multiblock_status;
205 u32 is_ddr;
206 };
207
208 static const struct platform_device_id imx_esdhc_devtype[] = {
209 {
210 .name = "sdhci-esdhc-imx25",
211 .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
212 }, {
213 .name = "sdhci-esdhc-imx35",
214 .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
215 }, {
216 .name = "sdhci-esdhc-imx51",
217 .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
218 }, {
219 /* sentinel */
220 }
221 };
222 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
223
224 static const struct of_device_id imx_esdhc_dt_ids[] = {
225 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
226 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
227 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
228 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
229 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
230 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
231 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
232 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
233 { /* sentinel */ }
234 };
235 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
236
237 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
238 {
239 return data->socdata == &esdhc_imx25_data;
240 }
241
242 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
243 {
244 return data->socdata == &esdhc_imx53_data;
245 }
246
247 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
248 {
249 return data->socdata == &usdhc_imx6q_data;
250 }
251
252 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
253 {
254 return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
255 }
256
257 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
258 {
259 void __iomem *base = host->ioaddr + (reg & ~0x3);
260 u32 shift = (reg & 0x3) * 8;
261
262 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
263 }
264
265 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
266 {
267 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
268 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
269 u32 val = readl(host->ioaddr + reg);
270
271 if (unlikely(reg == SDHCI_PRESENT_STATE)) {
272 u32 fsl_prss = val;
273 /* save the least 20 bits */
274 val = fsl_prss & 0x000FFFFF;
275 /* move dat[0-3] bits */
276 val |= (fsl_prss & 0x0F000000) >> 4;
277 /* move cmd line bit */
278 val |= (fsl_prss & 0x00800000) << 1;
279 }
280
281 if (unlikely(reg == SDHCI_CAPABILITIES)) {
282 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
283 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
284 val &= 0xffff0000;
285
286 /* In FSL esdhc IC module, only bit20 is used to indicate the
287 * ADMA2 capability of esdhc, but this bit is messed up on
288 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
289 * don't actually support ADMA2). So set the BROKEN_ADMA
290 * quirk on MX25/35 platforms.
291 */
292
293 if (val & SDHCI_CAN_DO_ADMA1) {
294 val &= ~SDHCI_CAN_DO_ADMA1;
295 val |= SDHCI_CAN_DO_ADMA2;
296 }
297 }
298
299 if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
300 if (esdhc_is_usdhc(imx_data)) {
301 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
302 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
303 else
304 /* imx6q/dl does not have cap_1 register, fake one */
305 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
306 | SDHCI_SUPPORT_SDR50
307 | SDHCI_USE_SDR50_TUNING
308 | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT);
309
310 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
311 val |= SDHCI_SUPPORT_HS400;
312
313 /*
314 * Do not advertise faster UHS modes if there are no
315 * pinctrl states for 100MHz/200MHz.
316 */
317 if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
318 IS_ERR_OR_NULL(imx_data->pins_200mhz))
319 val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
320 | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
321 }
322 }
323
324 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
325 val = 0;
326 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
327 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
328 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
329 }
330
331 if (unlikely(reg == SDHCI_INT_STATUS)) {
332 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
333 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
334 val |= SDHCI_INT_ADMA_ERROR;
335 }
336
337 /*
338 * mask off the interrupt we get in response to the manually
339 * sent CMD12
340 */
341 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
342 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
343 val &= ~SDHCI_INT_RESPONSE;
344 writel(SDHCI_INT_RESPONSE, host->ioaddr +
345 SDHCI_INT_STATUS);
346 imx_data->multiblock_status = NO_CMD_PENDING;
347 }
348 }
349
350 return val;
351 }
352
353 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
354 {
355 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
356 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
357 u32 data;
358
359 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
360 reg == SDHCI_INT_STATUS)) {
361 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
362 /*
363 * Clear and then set D3CD bit to avoid missing the
364 * card interrupt. This is an eSDHC controller problem
365 * so we need to apply the following workaround: clear
366 * and set D3CD bit will make eSDHC re-sample the card
367 * interrupt. In case a card interrupt was lost,
368 * re-sample it by the following steps.
369 */
370 data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
371 data &= ~ESDHC_CTRL_D3CD;
372 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
373 data |= ESDHC_CTRL_D3CD;
374 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
375 }
376
377 if (val & SDHCI_INT_ADMA_ERROR) {
378 val &= ~SDHCI_INT_ADMA_ERROR;
379 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
380 }
381 }
382
383 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
384 && (reg == SDHCI_INT_STATUS)
385 && (val & SDHCI_INT_DATA_END))) {
386 u32 v;
387 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
388 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
389 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
390
391 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
392 {
393 /* send a manual CMD12 with RESPTYP=none */
394 data = MMC_STOP_TRANSMISSION << 24 |
395 SDHCI_CMD_ABORTCMD << 16;
396 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
397 imx_data->multiblock_status = WAIT_FOR_INT;
398 }
399 }
400
401 writel(val, host->ioaddr + reg);
402 }
403
404 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
405 {
406 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
407 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
408 u16 ret = 0;
409 u32 val;
410
411 if (unlikely(reg == SDHCI_HOST_VERSION)) {
412 reg ^= 2;
413 if (esdhc_is_usdhc(imx_data)) {
414 /*
415 * The usdhc register returns a wrong host version.
416 * Correct it here.
417 */
418 return SDHCI_SPEC_300;
419 }
420 }
421
422 if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
423 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
424 if (val & ESDHC_VENDOR_SPEC_VSELECT)
425 ret |= SDHCI_CTRL_VDD_180;
426
427 if (esdhc_is_usdhc(imx_data)) {
428 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
429 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
430 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
431 /* the std tuning bits is in ACMD12_ERR for imx6sl */
432 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
433 }
434
435 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
436 ret |= SDHCI_CTRL_EXEC_TUNING;
437 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
438 ret |= SDHCI_CTRL_TUNED_CLK;
439
440 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
441
442 return ret;
443 }
444
445 if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
446 if (esdhc_is_usdhc(imx_data)) {
447 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
448 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
449 /* Swap AC23 bit */
450 if (m & ESDHC_MIX_CTRL_AC23EN) {
451 ret &= ~ESDHC_MIX_CTRL_AC23EN;
452 ret |= SDHCI_TRNS_AUTO_CMD23;
453 }
454 } else {
455 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
456 }
457
458 return ret;
459 }
460
461 return readw(host->ioaddr + reg);
462 }
463
464 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
465 {
466 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
467 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
468 u32 new_val = 0;
469
470 switch (reg) {
471 case SDHCI_CLOCK_CONTROL:
472 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
473 if (val & SDHCI_CLOCK_CARD_EN)
474 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
475 else
476 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
477 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
478 return;
479 case SDHCI_HOST_CONTROL2:
480 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
481 if (val & SDHCI_CTRL_VDD_180)
482 new_val |= ESDHC_VENDOR_SPEC_VSELECT;
483 else
484 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
485 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
486 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
487 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
488 if (val & SDHCI_CTRL_TUNED_CLK) {
489 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
490 new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
491 } else {
492 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
493 new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
494 }
495 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
496 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
497 u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
498 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
499 if (val & SDHCI_CTRL_TUNED_CLK) {
500 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
501 } else {
502 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
503 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
504 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
505 }
506
507 if (val & SDHCI_CTRL_EXEC_TUNING) {
508 v |= ESDHC_MIX_CTRL_EXE_TUNE;
509 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
510 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
511 } else {
512 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
513 }
514
515 writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
516 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
517 }
518 return;
519 case SDHCI_TRANSFER_MODE:
520 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
521 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
522 && (host->cmd->data->blocks > 1)
523 && (host->cmd->data->flags & MMC_DATA_READ)) {
524 u32 v;
525 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
526 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
527 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
528 }
529
530 if (esdhc_is_usdhc(imx_data)) {
531 u32 wml;
532 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
533 /* Swap AC23 bit */
534 if (val & SDHCI_TRNS_AUTO_CMD23) {
535 val &= ~SDHCI_TRNS_AUTO_CMD23;
536 val |= ESDHC_MIX_CTRL_AC23EN;
537 }
538 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
539 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
540
541 /* Set watermark levels for PIO access to maximum value
542 * (128 words) to accommodate full 512 bytes buffer.
543 * For DMA access restore the levels to default value.
544 */
545 m = readl(host->ioaddr + ESDHC_WTMK_LVL);
546 if (val & SDHCI_TRNS_DMA)
547 wml = ESDHC_WTMK_LVL_WML_VAL_DEF;
548 else
549 wml = ESDHC_WTMK_LVL_WML_VAL_MAX;
550 m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK |
551 ESDHC_WTMK_LVL_WR_WML_MASK);
552 m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) |
553 (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT);
554 writel(m, host->ioaddr + ESDHC_WTMK_LVL);
555 } else {
556 /*
557 * Postpone this write, we must do it together with a
558 * command write that is down below.
559 */
560 imx_data->scratchpad = val;
561 }
562 return;
563 case SDHCI_COMMAND:
564 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
565 val |= SDHCI_CMD_ABORTCMD;
566
567 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
568 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
569 imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
570
571 if (esdhc_is_usdhc(imx_data))
572 writel(val << 16,
573 host->ioaddr + SDHCI_TRANSFER_MODE);
574 else
575 writel(val << 16 | imx_data->scratchpad,
576 host->ioaddr + SDHCI_TRANSFER_MODE);
577 return;
578 case SDHCI_BLOCK_SIZE:
579 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
580 break;
581 }
582 esdhc_clrset_le(host, 0xffff, val, reg);
583 }
584
585 static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
586 {
587 u8 ret;
588 u32 val;
589
590 switch (reg) {
591 case SDHCI_HOST_CONTROL:
592 val = readl(host->ioaddr + reg);
593
594 ret = val & SDHCI_CTRL_LED;
595 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
596 ret |= (val & ESDHC_CTRL_4BITBUS);
597 ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
598 return ret;
599 }
600
601 return readb(host->ioaddr + reg);
602 }
603
604 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
605 {
606 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
607 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
608 u32 new_val = 0;
609 u32 mask;
610
611 switch (reg) {
612 case SDHCI_POWER_CONTROL:
613 /*
614 * FSL put some DMA bits here
615 * If your board has a regulator, code should be here
616 */
617 return;
618 case SDHCI_HOST_CONTROL:
619 /* FSL messed up here, so we need to manually compose it. */
620 new_val = val & SDHCI_CTRL_LED;
621 /* ensure the endianness */
622 new_val |= ESDHC_HOST_CONTROL_LE;
623 /* bits 8&9 are reserved on mx25 */
624 if (!is_imx25_esdhc(imx_data)) {
625 /* DMA mode bits are shifted */
626 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
627 }
628
629 /*
630 * Do not touch buswidth bits here. This is done in
631 * esdhc_pltfm_bus_width.
632 * Do not touch the D3CD bit either which is used for the
633 * SDIO interrupt erratum workaround.
634 */
635 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
636
637 esdhc_clrset_le(host, mask, new_val, reg);
638 return;
639 case SDHCI_SOFTWARE_RESET:
640 if (val & SDHCI_RESET_DATA)
641 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
642 break;
643 }
644 esdhc_clrset_le(host, 0xff, val, reg);
645
646 if (reg == SDHCI_SOFTWARE_RESET) {
647 if (val & SDHCI_RESET_ALL) {
648 /*
649 * The esdhc has a design violation to SDHC spec which
650 * tells that software reset should not affect card
651 * detection circuit. But esdhc clears its SYSCTL
652 * register bits [0..2] during the software reset. This
653 * will stop those clocks that card detection circuit
654 * relies on. To work around it, we turn the clocks on
655 * back to keep card detection circuit functional.
656 */
657 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
658 /*
659 * The reset on usdhc fails to clear MIX_CTRL register.
660 * Do it manually here.
661 */
662 if (esdhc_is_usdhc(imx_data)) {
663 /*
664 * the tuning bits should be kept during reset
665 */
666 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
667 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
668 host->ioaddr + ESDHC_MIX_CTRL);
669 imx_data->is_ddr = 0;
670 }
671 } else if (val & SDHCI_RESET_DATA) {
672 /*
673 * The eSDHC DAT line software reset clears at least the
674 * data transfer width on i.MX25, so make sure that the
675 * Host Control register is unaffected.
676 */
677 esdhc_clrset_le(host, 0xff, new_val,
678 SDHCI_HOST_CONTROL);
679 }
680 }
681 }
682
683 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
684 {
685 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
686
687 return pltfm_host->clock;
688 }
689
690 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
691 {
692 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
693
694 return pltfm_host->clock / 256 / 16;
695 }
696
697 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
698 unsigned int clock)
699 {
700 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
701 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
702 unsigned int host_clock = pltfm_host->clock;
703 int ddr_pre_div = imx_data->is_ddr ? 2 : 1;
704 int pre_div = 1;
705 int div = 1;
706 u32 temp, val;
707
708 if (esdhc_is_usdhc(imx_data)) {
709 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
710 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
711 host->ioaddr + ESDHC_VENDOR_SPEC);
712 }
713
714 if (clock == 0) {
715 host->mmc->actual_clock = 0;
716 return;
717 }
718
719 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
720 if (is_imx53_esdhc(imx_data)) {
721 /*
722 * According to the i.MX53 reference manual, if DLLCTRL[10] can
723 * be set, then the controller is eSDHCv3, else it is eSDHCv2.
724 */
725 val = readl(host->ioaddr + ESDHC_DLL_CTRL);
726 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
727 temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
728 writel(val, host->ioaddr + ESDHC_DLL_CTRL);
729 if (temp & BIT(10))
730 pre_div = 2;
731 }
732
733 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
734 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
735 | ESDHC_CLOCK_MASK);
736 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
737
738 while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
739 pre_div < 256)
740 pre_div *= 2;
741
742 while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16)
743 div++;
744
745 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
746 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
747 clock, host->mmc->actual_clock);
748
749 pre_div >>= 1;
750 div--;
751
752 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
753 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
754 | (div << ESDHC_DIVIDER_SHIFT)
755 | (pre_div << ESDHC_PREDIV_SHIFT));
756 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
757
758 if (esdhc_is_usdhc(imx_data)) {
759 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
760 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
761 host->ioaddr + ESDHC_VENDOR_SPEC);
762 }
763
764 mdelay(1);
765 }
766
767 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
768 {
769 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
770 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
771 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
772
773 switch (boarddata->wp_type) {
774 case ESDHC_WP_GPIO:
775 return mmc_gpio_get_ro(host->mmc);
776 case ESDHC_WP_CONTROLLER:
777 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
778 SDHCI_WRITE_PROTECT);
779 case ESDHC_WP_NONE:
780 break;
781 }
782
783 return -ENOSYS;
784 }
785
786 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
787 {
788 u32 ctrl;
789
790 switch (width) {
791 case MMC_BUS_WIDTH_8:
792 ctrl = ESDHC_CTRL_8BITBUS;
793 break;
794 case MMC_BUS_WIDTH_4:
795 ctrl = ESDHC_CTRL_4BITBUS;
796 break;
797 default:
798 ctrl = 0;
799 break;
800 }
801
802 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
803 SDHCI_HOST_CONTROL);
804 }
805
806 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
807 {
808 u32 reg;
809
810 /* FIXME: delay a bit for card to be ready for next tuning due to errors */
811 mdelay(1);
812
813 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
814 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
815 ESDHC_MIX_CTRL_FBCLK_SEL;
816 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
817 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
818 dev_dbg(mmc_dev(host->mmc),
819 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
820 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
821 }
822
823 static void esdhc_post_tuning(struct sdhci_host *host)
824 {
825 u32 reg;
826
827 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
828 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
829 reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
830 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
831 }
832
833 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
834 {
835 int min, max, avg, ret;
836
837 /* find the mininum delay first which can pass tuning */
838 min = ESDHC_TUNE_CTRL_MIN;
839 while (min < ESDHC_TUNE_CTRL_MAX) {
840 esdhc_prepare_tuning(host, min);
841 if (!mmc_send_tuning(host->mmc, opcode, NULL))
842 break;
843 min += ESDHC_TUNE_CTRL_STEP;
844 }
845
846 /* find the maxinum delay which can not pass tuning */
847 max = min + ESDHC_TUNE_CTRL_STEP;
848 while (max < ESDHC_TUNE_CTRL_MAX) {
849 esdhc_prepare_tuning(host, max);
850 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
851 max -= ESDHC_TUNE_CTRL_STEP;
852 break;
853 }
854 max += ESDHC_TUNE_CTRL_STEP;
855 }
856
857 /* use average delay to get the best timing */
858 avg = (min + max) / 2;
859 esdhc_prepare_tuning(host, avg);
860 ret = mmc_send_tuning(host->mmc, opcode, NULL);
861 esdhc_post_tuning(host);
862
863 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
864 ret ? "failed" : "passed", avg, ret);
865
866 return ret;
867 }
868
869 static int esdhc_change_pinstate(struct sdhci_host *host,
870 unsigned int uhs)
871 {
872 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
873 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
874 struct pinctrl_state *pinctrl;
875
876 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
877
878 if (IS_ERR(imx_data->pinctrl) ||
879 IS_ERR(imx_data->pins_default) ||
880 IS_ERR(imx_data->pins_100mhz) ||
881 IS_ERR(imx_data->pins_200mhz))
882 return -EINVAL;
883
884 switch (uhs) {
885 case MMC_TIMING_UHS_SDR50:
886 case MMC_TIMING_UHS_DDR50:
887 pinctrl = imx_data->pins_100mhz;
888 break;
889 case MMC_TIMING_UHS_SDR104:
890 case MMC_TIMING_MMC_HS200:
891 case MMC_TIMING_MMC_HS400:
892 pinctrl = imx_data->pins_200mhz;
893 break;
894 default:
895 /* back to default state for other legacy timing */
896 pinctrl = imx_data->pins_default;
897 }
898
899 return pinctrl_select_state(imx_data->pinctrl, pinctrl);
900 }
901
902 /*
903 * For HS400 eMMC, there is a data_strobe line. This signal is generated
904 * by the device and used for data output and CRC status response output
905 * in HS400 mode. The frequency of this signal follows the frequency of
906 * CLK generated by host. The host receives the data which is aligned to the
907 * edge of data_strobe line. Due to the time delay between CLK line and
908 * data_strobe line, if the delay time is larger than one clock cycle,
909 * then CLK and data_strobe line will be misaligned, read error shows up.
910 * So when the CLK is higher than 100MHz, each clock cycle is short enough,
911 * host should configure the delay target.
912 */
913 static void esdhc_set_strobe_dll(struct sdhci_host *host)
914 {
915 u32 v;
916
917 if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) {
918 /* disable clock before enabling strobe dll */
919 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
920 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
921 host->ioaddr + ESDHC_VENDOR_SPEC);
922
923 /* force a reset on strobe dll */
924 writel(ESDHC_STROBE_DLL_CTRL_RESET,
925 host->ioaddr + ESDHC_STROBE_DLL_CTRL);
926 /*
927 * enable strobe dll ctrl and adjust the delay target
928 * for the uSDHC loopback read clock
929 */
930 v = ESDHC_STROBE_DLL_CTRL_ENABLE |
931 (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
932 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
933 /* wait 1us to make sure strobe dll status register stable */
934 udelay(1);
935 v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS);
936 if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK))
937 dev_warn(mmc_dev(host->mmc),
938 "warning! HS400 strobe DLL status REF not lock!\n");
939 if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK))
940 dev_warn(mmc_dev(host->mmc),
941 "warning! HS400 strobe DLL status SLV not lock!\n");
942 }
943 }
944
945 static void esdhc_reset_tuning(struct sdhci_host *host)
946 {
947 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
948 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
949 u32 ctrl;
950
951 /* Reset the tuning circuit */
952 if (esdhc_is_usdhc(imx_data)) {
953 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
954 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
955 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
956 ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
957 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
958 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
959 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
960 ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
961 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
962 writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
963 }
964 }
965 }
966
967 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
968 {
969 u32 m;
970 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
971 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
972 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
973
974 /* disable ddr mode and disable HS400 mode */
975 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
976 m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
977 imx_data->is_ddr = 0;
978
979 switch (timing) {
980 case MMC_TIMING_UHS_SDR12:
981 case MMC_TIMING_UHS_SDR25:
982 case MMC_TIMING_UHS_SDR50:
983 case MMC_TIMING_UHS_SDR104:
984 case MMC_TIMING_MMC_HS:
985 case MMC_TIMING_MMC_HS200:
986 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
987 break;
988 case MMC_TIMING_UHS_DDR50:
989 case MMC_TIMING_MMC_DDR52:
990 m |= ESDHC_MIX_CTRL_DDREN;
991 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
992 imx_data->is_ddr = 1;
993 if (boarddata->delay_line) {
994 u32 v;
995 v = boarddata->delay_line <<
996 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
997 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
998 if (is_imx53_esdhc(imx_data))
999 v <<= 1;
1000 writel(v, host->ioaddr + ESDHC_DLL_CTRL);
1001 }
1002 break;
1003 case MMC_TIMING_MMC_HS400:
1004 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
1005 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1006 imx_data->is_ddr = 1;
1007 /* update clock after enable DDR for strobe DLL lock */
1008 host->ops->set_clock(host, host->clock);
1009 esdhc_set_strobe_dll(host);
1010 break;
1011 case MMC_TIMING_LEGACY:
1012 default:
1013 esdhc_reset_tuning(host);
1014 break;
1015 }
1016
1017 esdhc_change_pinstate(host, timing);
1018 }
1019
1020 static void esdhc_reset(struct sdhci_host *host, u8 mask)
1021 {
1022 sdhci_reset(host, mask);
1023
1024 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1025 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1026 }
1027
1028 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
1029 {
1030 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1031 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1032
1033 /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */
1034 return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
1035 }
1036
1037 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1038 {
1039 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1040 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1041
1042 /* use maximum timeout counter */
1043 esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
1044 esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
1045 SDHCI_TIMEOUT_CONTROL);
1046 }
1047
1048 static struct sdhci_ops sdhci_esdhc_ops = {
1049 .read_l = esdhc_readl_le,
1050 .read_w = esdhc_readw_le,
1051 .read_b = esdhc_readb_le,
1052 .write_l = esdhc_writel_le,
1053 .write_w = esdhc_writew_le,
1054 .write_b = esdhc_writeb_le,
1055 .set_clock = esdhc_pltfm_set_clock,
1056 .get_max_clock = esdhc_pltfm_get_max_clock,
1057 .get_min_clock = esdhc_pltfm_get_min_clock,
1058 .get_max_timeout_count = esdhc_get_max_timeout_count,
1059 .get_ro = esdhc_pltfm_get_ro,
1060 .set_timeout = esdhc_set_timeout,
1061 .set_bus_width = esdhc_pltfm_set_bus_width,
1062 .set_uhs_signaling = esdhc_set_uhs_signaling,
1063 .reset = esdhc_reset,
1064 };
1065
1066 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
1067 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
1068 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
1069 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
1070 | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
1071 .ops = &sdhci_esdhc_ops,
1072 };
1073
1074 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
1075 {
1076 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1077 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1078 int tmp;
1079
1080 if (esdhc_is_usdhc(imx_data)) {
1081 /*
1082 * The imx6q ROM code will change the default watermark
1083 * level setting to something insane. Change it back here.
1084 */
1085 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
1086
1087 /*
1088 * ROM code will change the bit burst_length_enable setting
1089 * to zero if this usdhc is chosen to boot system. Change
1090 * it back here, otherwise it will impact the performance a
1091 * lot. This bit is used to enable/disable the burst length
1092 * for the external AHB2AXI bridge. It's useful especially
1093 * for INCR transfer because without burst length indicator,
1094 * the AHB2AXI bridge does not know the burst length in
1095 * advance. And without burst length indicator, AHB INCR
1096 * transfer can only be converted to singles on the AXI side.
1097 */
1098 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1099 | ESDHC_BURST_LEN_EN_INCR,
1100 host->ioaddr + SDHCI_HOST_CONTROL);
1101
1102 /*
1103 * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1104 * TO1.1, it's harmless for MX6SL
1105 */
1106 writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
1107 host->ioaddr + 0x6c);
1108
1109 /* disable DLL_CTRL delay line settings */
1110 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1111
1112 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1113 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1114 tmp |= ESDHC_STD_TUNING_EN |
1115 ESDHC_TUNING_START_TAP_DEFAULT;
1116 if (imx_data->boarddata.tuning_start_tap) {
1117 tmp &= ~ESDHC_TUNING_START_TAP_MASK;
1118 tmp |= imx_data->boarddata.tuning_start_tap;
1119 }
1120
1121 if (imx_data->boarddata.tuning_step) {
1122 tmp &= ~ESDHC_TUNING_STEP_MASK;
1123 tmp |= imx_data->boarddata.tuning_step
1124 << ESDHC_TUNING_STEP_SHIFT;
1125 }
1126 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1127 }
1128 }
1129 }
1130
1131 #ifdef CONFIG_OF
1132 static int
1133 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1134 struct sdhci_host *host,
1135 struct pltfm_imx_data *imx_data)
1136 {
1137 struct device_node *np = pdev->dev.of_node;
1138 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1139 int ret;
1140
1141 if (of_get_property(np, "fsl,wp-controller", NULL))
1142 boarddata->wp_type = ESDHC_WP_CONTROLLER;
1143
1144 boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
1145 if (gpio_is_valid(boarddata->wp_gpio))
1146 boarddata->wp_type = ESDHC_WP_GPIO;
1147
1148 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
1149 of_property_read_u32(np, "fsl,tuning-start-tap",
1150 &boarddata->tuning_start_tap);
1151
1152 if (of_find_property(np, "no-1-8-v", NULL))
1153 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1154
1155 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
1156 boarddata->delay_line = 0;
1157
1158 mmc_of_parse_voltage(np, &host->ocr_mask);
1159
1160 if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pins_default)) {
1161 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1162 ESDHC_PINCTRL_STATE_100MHZ);
1163 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1164 ESDHC_PINCTRL_STATE_200MHZ);
1165 }
1166
1167 /* call to generic mmc_of_parse to support additional capabilities */
1168 ret = mmc_of_parse(host->mmc);
1169 if (ret)
1170 return ret;
1171
1172 if (mmc_gpio_get_cd(host->mmc) >= 0)
1173 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1174
1175 return 0;
1176 }
1177 #else
1178 static inline int
1179 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1180 struct sdhci_host *host,
1181 struct pltfm_imx_data *imx_data)
1182 {
1183 return -ENODEV;
1184 }
1185 #endif
1186
1187 static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev,
1188 struct sdhci_host *host,
1189 struct pltfm_imx_data *imx_data)
1190 {
1191 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1192 int err;
1193
1194 if (!host->mmc->parent->platform_data) {
1195 dev_err(mmc_dev(host->mmc), "no board data!\n");
1196 return -EINVAL;
1197 }
1198
1199 imx_data->boarddata = *((struct esdhc_platform_data *)
1200 host->mmc->parent->platform_data);
1201 /* write_protect */
1202 if (boarddata->wp_type == ESDHC_WP_GPIO) {
1203 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
1204 if (err) {
1205 dev_err(mmc_dev(host->mmc),
1206 "failed to request write-protect gpio!\n");
1207 return err;
1208 }
1209 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1210 }
1211
1212 /* card_detect */
1213 switch (boarddata->cd_type) {
1214 case ESDHC_CD_GPIO:
1215 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
1216 if (err) {
1217 dev_err(mmc_dev(host->mmc),
1218 "failed to request card-detect gpio!\n");
1219 return err;
1220 }
1221 /* fall through */
1222
1223 case ESDHC_CD_CONTROLLER:
1224 /* we have a working card_detect back */
1225 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1226 break;
1227
1228 case ESDHC_CD_PERMANENT:
1229 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
1230 break;
1231
1232 case ESDHC_CD_NONE:
1233 break;
1234 }
1235
1236 switch (boarddata->max_bus_width) {
1237 case 8:
1238 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
1239 break;
1240 case 4:
1241 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
1242 break;
1243 case 1:
1244 default:
1245 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1246 break;
1247 }
1248
1249 return 0;
1250 }
1251
1252 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1253 {
1254 const struct of_device_id *of_id =
1255 of_match_device(imx_esdhc_dt_ids, &pdev->dev);
1256 struct sdhci_pltfm_host *pltfm_host;
1257 struct sdhci_host *host;
1258 int err;
1259 struct pltfm_imx_data *imx_data;
1260
1261 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1262 sizeof(*imx_data));
1263 if (IS_ERR(host))
1264 return PTR_ERR(host);
1265
1266 pltfm_host = sdhci_priv(host);
1267
1268 imx_data = sdhci_pltfm_priv(pltfm_host);
1269
1270 imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
1271 pdev->id_entry->driver_data;
1272
1273 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1274 if (IS_ERR(imx_data->clk_ipg)) {
1275 err = PTR_ERR(imx_data->clk_ipg);
1276 goto free_sdhci;
1277 }
1278
1279 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1280 if (IS_ERR(imx_data->clk_ahb)) {
1281 err = PTR_ERR(imx_data->clk_ahb);
1282 goto free_sdhci;
1283 }
1284
1285 imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1286 if (IS_ERR(imx_data->clk_per)) {
1287 err = PTR_ERR(imx_data->clk_per);
1288 goto free_sdhci;
1289 }
1290
1291 pltfm_host->clk = imx_data->clk_per;
1292 pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1293 err = clk_prepare_enable(imx_data->clk_per);
1294 if (err)
1295 goto free_sdhci;
1296 err = clk_prepare_enable(imx_data->clk_ipg);
1297 if (err)
1298 goto disable_per_clk;
1299 err = clk_prepare_enable(imx_data->clk_ahb);
1300 if (err)
1301 goto disable_ipg_clk;
1302
1303 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1304 if (IS_ERR(imx_data->pinctrl)) {
1305 err = PTR_ERR(imx_data->pinctrl);
1306 goto disable_ahb_clk;
1307 }
1308
1309 imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
1310 PINCTRL_STATE_DEFAULT);
1311 if (IS_ERR(imx_data->pins_default))
1312 dev_warn(mmc_dev(host->mmc), "could not get default state\n");
1313
1314 if (esdhc_is_usdhc(imx_data)) {
1315 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1316 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
1317 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1318 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1319
1320 /* clear tuning bits in case ROM has set it already */
1321 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1322 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1323 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1324 }
1325
1326 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1327 sdhci_esdhc_ops.platform_execute_tuning =
1328 esdhc_executing_tuning;
1329
1330 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1331 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1332
1333 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
1334 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
1335
1336 if (of_id)
1337 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1338 else
1339 err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data);
1340 if (err)
1341 goto disable_ahb_clk;
1342
1343 sdhci_esdhc_imx_hwinit(host);
1344
1345 err = sdhci_add_host(host);
1346 if (err)
1347 goto disable_ahb_clk;
1348
1349 pm_runtime_set_active(&pdev->dev);
1350 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1351 pm_runtime_use_autosuspend(&pdev->dev);
1352 pm_suspend_ignore_children(&pdev->dev, 1);
1353 pm_runtime_enable(&pdev->dev);
1354
1355 return 0;
1356
1357 disable_ahb_clk:
1358 clk_disable_unprepare(imx_data->clk_ahb);
1359 disable_ipg_clk:
1360 clk_disable_unprepare(imx_data->clk_ipg);
1361 disable_per_clk:
1362 clk_disable_unprepare(imx_data->clk_per);
1363 free_sdhci:
1364 sdhci_pltfm_free(pdev);
1365 return err;
1366 }
1367
1368 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1369 {
1370 struct sdhci_host *host = platform_get_drvdata(pdev);
1371 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1372 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1373 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1374
1375 pm_runtime_get_sync(&pdev->dev);
1376 pm_runtime_disable(&pdev->dev);
1377 pm_runtime_put_noidle(&pdev->dev);
1378
1379 sdhci_remove_host(host, dead);
1380
1381 clk_disable_unprepare(imx_data->clk_per);
1382 clk_disable_unprepare(imx_data->clk_ipg);
1383 clk_disable_unprepare(imx_data->clk_ahb);
1384
1385 sdhci_pltfm_free(pdev);
1386
1387 return 0;
1388 }
1389
1390 #ifdef CONFIG_PM_SLEEP
1391 static int sdhci_esdhc_suspend(struct device *dev)
1392 {
1393 struct sdhci_host *host = dev_get_drvdata(dev);
1394
1395 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1396 mmc_retune_needed(host->mmc);
1397
1398 return sdhci_suspend_host(host);
1399 }
1400
1401 static int sdhci_esdhc_resume(struct device *dev)
1402 {
1403 struct sdhci_host *host = dev_get_drvdata(dev);
1404
1405 /* re-initialize hw state in case it's lost in low power mode */
1406 sdhci_esdhc_imx_hwinit(host);
1407
1408 return sdhci_resume_host(host);
1409 }
1410 #endif
1411
1412 #ifdef CONFIG_PM
1413 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1414 {
1415 struct sdhci_host *host = dev_get_drvdata(dev);
1416 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1417 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1418 int ret;
1419
1420 ret = sdhci_runtime_suspend_host(host);
1421 if (ret)
1422 return ret;
1423
1424 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1425 mmc_retune_needed(host->mmc);
1426
1427 if (!sdhci_sdio_irq_enabled(host)) {
1428 imx_data->actual_clock = host->mmc->actual_clock;
1429 esdhc_pltfm_set_clock(host, 0);
1430 clk_disable_unprepare(imx_data->clk_per);
1431 clk_disable_unprepare(imx_data->clk_ipg);
1432 }
1433 clk_disable_unprepare(imx_data->clk_ahb);
1434
1435 return ret;
1436 }
1437
1438 static int sdhci_esdhc_runtime_resume(struct device *dev)
1439 {
1440 struct sdhci_host *host = dev_get_drvdata(dev);
1441 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1442 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1443 int err;
1444
1445 err = clk_prepare_enable(imx_data->clk_ahb);
1446 if (err)
1447 return err;
1448
1449 if (!sdhci_sdio_irq_enabled(host)) {
1450 err = clk_prepare_enable(imx_data->clk_per);
1451 if (err)
1452 goto disable_ahb_clk;
1453 err = clk_prepare_enable(imx_data->clk_ipg);
1454 if (err)
1455 goto disable_per_clk;
1456 esdhc_pltfm_set_clock(host, imx_data->actual_clock);
1457 }
1458
1459 err = sdhci_runtime_resume_host(host);
1460 if (err)
1461 goto disable_ipg_clk;
1462
1463 return 0;
1464
1465 disable_ipg_clk:
1466 if (!sdhci_sdio_irq_enabled(host))
1467 clk_disable_unprepare(imx_data->clk_ipg);
1468 disable_per_clk:
1469 if (!sdhci_sdio_irq_enabled(host))
1470 clk_disable_unprepare(imx_data->clk_per);
1471 disable_ahb_clk:
1472 clk_disable_unprepare(imx_data->clk_ahb);
1473 return err;
1474 }
1475 #endif
1476
1477 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1478 SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
1479 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1480 sdhci_esdhc_runtime_resume, NULL)
1481 };
1482
1483 static struct platform_driver sdhci_esdhc_imx_driver = {
1484 .driver = {
1485 .name = "sdhci-esdhc-imx",
1486 .of_match_table = imx_esdhc_dt_ids,
1487 .pm = &sdhci_esdhc_pmops,
1488 },
1489 .id_table = imx_esdhc_devtype,
1490 .probe = sdhci_esdhc_imx_probe,
1491 .remove = sdhci_esdhc_imx_remove,
1492 };
1493
1494 module_platform_driver(sdhci_esdhc_imx_driver);
1495
1496 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1497 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1498 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support