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vt: vt_ioctl: fix VT_DISALLOCATE freeing in-use virtual console
[linux/fpc-iii.git] / drivers / mmc / host / sdhci-pci-core.c
blob65985dc3e1a74a588e4ab758e080a5dde6e84cd2
1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15 #include <linux/bitfield.h>
16 #include <linux/string.h>
17 #include <linux/delay.h>
18 #include <linux/highmem.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/slab.h>
23 #include <linux/device.h>
24 #include <linux/mmc/host.h>
25 #include <linux/mmc/mmc.h>
26 #include <linux/scatterlist.h>
27 #include <linux/io.h>
28 #include <linux/gpio.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/mmc/slot-gpio.h>
31 #include <linux/mmc/sdhci-pci-data.h>
32 #include <linux/acpi.h>
33 #include <linux/dmi.h>
34
35 #include "cqhci.h"
36
37 #include "sdhci.h"
38 #include "sdhci-pci.h"
39
40 static void sdhci_pci_hw_reset(struct sdhci_host *host);
41
42 #ifdef CONFIG_PM_SLEEP
43 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip)
44 {
45 mmc_pm_flag_t pm_flags = 0;
46 bool cap_cd_wake = false;
47 int i;
48
49 for (i = 0; i < chip->num_slots; i++) {
50 struct sdhci_pci_slot *slot = chip->slots[i];
51
52 if (slot) {
53 pm_flags |= slot->host->mmc->pm_flags;
54 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE)
55 cap_cd_wake = true;
56 }
57 }
58
59 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ))
60 return device_wakeup_enable(&chip->pdev->dev);
61 else if (!cap_cd_wake)
62 return device_wakeup_disable(&chip->pdev->dev);
63
64 return 0;
65 }
66
67 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
68 {
69 int i, ret;
70
71 sdhci_pci_init_wakeup(chip);
72
73 for (i = 0; i < chip->num_slots; i++) {
74 struct sdhci_pci_slot *slot = chip->slots[i];
75 struct sdhci_host *host;
76
77 if (!slot)
78 continue;
79
80 host = slot->host;
81
82 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
83 mmc_retune_needed(host->mmc);
84
85 ret = sdhci_suspend_host(host);
86 if (ret)
87 goto err_pci_suspend;
88
89 if (device_may_wakeup(&chip->pdev->dev))
90 mmc_gpio_set_cd_wake(host->mmc, true);
91 }
92
93 return 0;
94
95 err_pci_suspend:
96 while (--i >= 0)
97 sdhci_resume_host(chip->slots[i]->host);
98 return ret;
99 }
100
101 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip)
102 {
103 struct sdhci_pci_slot *slot;
104 int i, ret;
105
106 for (i = 0; i < chip->num_slots; i++) {
107 slot = chip->slots[i];
108 if (!slot)
109 continue;
110
111 ret = sdhci_resume_host(slot->host);
112 if (ret)
113 return ret;
114
115 mmc_gpio_set_cd_wake(slot->host->mmc, false);
116 }
117
118 return 0;
119 }
120
121 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip)
122 {
123 int ret;
124
125 ret = cqhci_suspend(chip->slots[0]->host->mmc);
126 if (ret)
127 return ret;
128
129 return sdhci_pci_suspend_host(chip);
130 }
131
132 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip)
133 {
134 int ret;
135
136 ret = sdhci_pci_resume_host(chip);
137 if (ret)
138 return ret;
139
140 return cqhci_resume(chip->slots[0]->host->mmc);
141 }
142 #endif
143
144 #ifdef CONFIG_PM
145 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip)
146 {
147 struct sdhci_pci_slot *slot;
148 struct sdhci_host *host;
149 int i, ret;
150
151 for (i = 0; i < chip->num_slots; i++) {
152 slot = chip->slots[i];
153 if (!slot)
154 continue;
155
156 host = slot->host;
157
158 ret = sdhci_runtime_suspend_host(host);
159 if (ret)
160 goto err_pci_runtime_suspend;
161
162 if (chip->rpm_retune &&
163 host->tuning_mode != SDHCI_TUNING_MODE_3)
164 mmc_retune_needed(host->mmc);
165 }
166
167 return 0;
168
169 err_pci_runtime_suspend:
170 while (--i >= 0)
171 sdhci_runtime_resume_host(chip->slots[i]->host);
172 return ret;
173 }
174
175 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip)
176 {
177 struct sdhci_pci_slot *slot;
178 int i, ret;
179
180 for (i = 0; i < chip->num_slots; i++) {
181 slot = chip->slots[i];
182 if (!slot)
183 continue;
184
185 ret = sdhci_runtime_resume_host(slot->host);
186 if (ret)
187 return ret;
188 }
189
190 return 0;
191 }
192
193 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip)
194 {
195 int ret;
196
197 ret = cqhci_suspend(chip->slots[0]->host->mmc);
198 if (ret)
199 return ret;
200
201 return sdhci_pci_runtime_suspend_host(chip);
202 }
203
204 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip)
205 {
206 int ret;
207
208 ret = sdhci_pci_runtime_resume_host(chip);
209 if (ret)
210 return ret;
211
212 return cqhci_resume(chip->slots[0]->host->mmc);
213 }
214 #endif
215
216 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask)
217 {
218 int cmd_error = 0;
219 int data_error = 0;
220
221 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
222 return intmask;
223
224 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
225
226 return 0;
227 }
228
229 static void sdhci_pci_dumpregs(struct mmc_host *mmc)
230 {
231 sdhci_dumpregs(mmc_priv(mmc));
232 }
233
234 /*****************************************************************************\
235 * *
236 * Hardware specific quirk handling *
237 * *
238 \*****************************************************************************/
239
240 static int ricoh_probe(struct sdhci_pci_chip *chip)
241 {
242 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
243 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
244 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
245 return 0;
246 }
247
248 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
249 {
250 slot->host->caps =
251 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
252 & SDHCI_TIMEOUT_CLK_MASK) |
253
254 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
255 & SDHCI_CLOCK_BASE_MASK) |
256
257 SDHCI_TIMEOUT_CLK_UNIT |
258 SDHCI_CAN_VDD_330 |
259 SDHCI_CAN_DO_HISPD |
260 SDHCI_CAN_DO_SDMA;
261 return 0;
262 }
263
264 #ifdef CONFIG_PM_SLEEP
265 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
266 {
267 /* Apply a delay to allow controller to settle */
268 /* Otherwise it becomes confused if card state changed
269 during suspend */
270 msleep(500);
271 return sdhci_pci_resume_host(chip);
272 }
273 #endif
274
275 static const struct sdhci_pci_fixes sdhci_ricoh = {
276 .probe = ricoh_probe,
277 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
278 SDHCI_QUIRK_FORCE_DMA |
279 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
280 };
281
282 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
283 .probe_slot = ricoh_mmc_probe_slot,
284 #ifdef CONFIG_PM_SLEEP
285 .resume = ricoh_mmc_resume,
286 #endif
287 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
288 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
289 SDHCI_QUIRK_NO_CARD_NO_RESET |
290 SDHCI_QUIRK_MISSING_CAPS
291 };
292
293 static const struct sdhci_pci_fixes sdhci_ene_712 = {
294 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
295 SDHCI_QUIRK_BROKEN_DMA,
296 };
297
298 static const struct sdhci_pci_fixes sdhci_ene_714 = {
299 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
300 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
301 SDHCI_QUIRK_BROKEN_DMA,
302 };
303
304 static const struct sdhci_pci_fixes sdhci_cafe = {
305 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
306 SDHCI_QUIRK_NO_BUSY_IRQ |
307 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
308 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
309 };
310
311 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
312 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
313 };
314
315 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
316 {
317 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
318 return 0;
319 }
320
321 /*
322 * ADMA operation is disabled for Moorestown platform due to
323 * hardware bugs.
324 */
325 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
326 {
327 /*
328 * slots number is fixed here for MRST as SDIO3/5 are never used and
329 * have hardware bugs.
330 */
331 chip->num_slots = 1;
332 return 0;
333 }
334
335 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
336 {
337 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
338 return 0;
339 }
340
341 #ifdef CONFIG_PM
342
343 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
344 {
345 struct sdhci_pci_slot *slot = dev_id;
346 struct sdhci_host *host = slot->host;
347
348 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
349 return IRQ_HANDLED;
350 }
351
352 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
353 {
354 int err, irq, gpio = slot->cd_gpio;
355
356 slot->cd_gpio = -EINVAL;
357 slot->cd_irq = -EINVAL;
358
359 if (!gpio_is_valid(gpio))
360 return;
361
362 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd");
363 if (err < 0)
364 goto out;
365
366 err = gpio_direction_input(gpio);
367 if (err < 0)
368 goto out_free;
369
370 irq = gpio_to_irq(gpio);
371 if (irq < 0)
372 goto out_free;
373
374 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
375 IRQF_TRIGGER_FALLING, "sd_cd", slot);
376 if (err)
377 goto out_free;
378
379 slot->cd_gpio = gpio;
380 slot->cd_irq = irq;
381
382 return;
383
384 out_free:
385 devm_gpio_free(&slot->chip->pdev->dev, gpio);
386 out:
387 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
388 }
389
390 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
391 {
392 if (slot->cd_irq >= 0)
393 free_irq(slot->cd_irq, slot);
394 }
395
396 #else
397
398 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
399 {
400 }
401
402 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
403 {
404 }
405
406 #endif
407
408 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
409 {
410 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
411 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
412 return 0;
413 }
414
415 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
416 {
417 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
418 return 0;
419 }
420
421 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
422 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
423 .probe_slot = mrst_hc_probe_slot,
424 };
425
426 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
427 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
428 .probe = mrst_hc_probe,
429 };
430
431 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
432 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
433 .allow_runtime_pm = true,
434 .own_cd_for_runtime_pm = true,
435 };
436
437 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
438 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
439 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
440 .allow_runtime_pm = true,
441 .probe_slot = mfd_sdio_probe_slot,
442 };
443
444 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
445 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
446 .allow_runtime_pm = true,
447 .probe_slot = mfd_emmc_probe_slot,
448 };
449
450 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
451 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
452 .probe_slot = pch_hc_probe_slot,
453 };
454
455 enum {
456 INTEL_DSM_FNS = 0,
457 INTEL_DSM_V18_SWITCH = 3,
458 INTEL_DSM_V33_SWITCH = 4,
459 INTEL_DSM_DRV_STRENGTH = 9,
460 INTEL_DSM_D3_RETUNE = 10,
461 };
462
463 struct intel_host {
464 u32 dsm_fns;
465 int drv_strength;
466 bool d3_retune;
467 bool rpm_retune_ok;
468 u32 glk_rx_ctrl1;
469 u32 glk_tun_val;
470 };
471
472 static const guid_t intel_dsm_guid =
473 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
474 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
475
476 static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
477 unsigned int fn, u32 *result)
478 {
479 union acpi_object *obj;
480 int err = 0;
481 size_t len;
482
483 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
484 if (!obj)
485 return -EOPNOTSUPP;
486
487 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
488 err = -EINVAL;
489 goto out;
490 }
491
492 len = min_t(size_t, obj->buffer.length, 4);
493
494 *result = 0;
495 memcpy(result, obj->buffer.pointer, len);
496 out:
497 ACPI_FREE(obj);
498
499 return err;
500 }
501
502 static int intel_dsm(struct intel_host *intel_host, struct device *dev,
503 unsigned int fn, u32 *result)
504 {
505 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
506 return -EOPNOTSUPP;
507
508 return __intel_dsm(intel_host, dev, fn, result);
509 }
510
511 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
512 struct mmc_host *mmc)
513 {
514 int err;
515 u32 val;
516
517 intel_host->d3_retune = true;
518
519 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
520 if (err) {
521 pr_debug("%s: DSM not supported, error %d\n",
522 mmc_hostname(mmc), err);
523 return;
524 }
525
526 pr_debug("%s: DSM function mask %#x\n",
527 mmc_hostname(mmc), intel_host->dsm_fns);
528
529 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val);
530 intel_host->drv_strength = err ? 0 : val;
531
532 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val);
533 intel_host->d3_retune = err ? true : !!val;
534 }
535
536 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
537 {
538 u8 reg;
539
540 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
541 reg |= 0x10;
542 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
543 /* For eMMC, minimum is 1us but give it 9us for good measure */
544 udelay(9);
545 reg &= ~0x10;
546 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
547 /* For eMMC, minimum is 200us but give it 300us for good measure */
548 usleep_range(300, 1000);
549 }
550
551 static int intel_select_drive_strength(struct mmc_card *card,
552 unsigned int max_dtr, int host_drv,
553 int card_drv, int *drv_type)
554 {
555 struct sdhci_host *host = mmc_priv(card->host);
556 struct sdhci_pci_slot *slot = sdhci_priv(host);
557 struct intel_host *intel_host = sdhci_pci_priv(slot);
558
559 return intel_host->drv_strength;
560 }
561
562 static int bxt_get_cd(struct mmc_host *mmc)
563 {
564 int gpio_cd = mmc_gpio_get_cd(mmc);
565 struct sdhci_host *host = mmc_priv(mmc);
566 unsigned long flags;
567 int ret = 0;
568
569 if (!gpio_cd)
570 return 0;
571
572 spin_lock_irqsave(&host->lock, flags);
573
574 if (host->flags & SDHCI_DEVICE_DEAD)
575 goto out;
576
577 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
578 out:
579 spin_unlock_irqrestore(&host->lock, flags);
580
581 return ret;
582 }
583
584 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20
585 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100
586
587 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
588 unsigned short vdd)
589 {
590 int cntr;
591 u8 reg;
592
593 sdhci_set_power(host, mode, vdd);
594
595 if (mode == MMC_POWER_OFF)
596 return;
597
598 /*
599 * Bus power might not enable after D3 -> D0 transition due to the
600 * present state not yet having propagated. Retry for up to 2ms.
601 */
602 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
603 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
604 if (reg & SDHCI_POWER_ON)
605 break;
606 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
607 reg |= SDHCI_POWER_ON;
608 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
609 }
610 }
611
612 #define INTEL_HS400_ES_REG 0x78
613 #define INTEL_HS400_ES_BIT BIT(0)
614
615 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc,
616 struct mmc_ios *ios)
617 {
618 struct sdhci_host *host = mmc_priv(mmc);
619 u32 val;
620
621 val = sdhci_readl(host, INTEL_HS400_ES_REG);
622 if (ios->enhanced_strobe)
623 val |= INTEL_HS400_ES_BIT;
624 else
625 val &= ~INTEL_HS400_ES_BIT;
626 sdhci_writel(host, val, INTEL_HS400_ES_REG);
627 }
628
629 static int intel_start_signal_voltage_switch(struct mmc_host *mmc,
630 struct mmc_ios *ios)
631 {
632 struct device *dev = mmc_dev(mmc);
633 struct sdhci_host *host = mmc_priv(mmc);
634 struct sdhci_pci_slot *slot = sdhci_priv(host);
635 struct intel_host *intel_host = sdhci_pci_priv(slot);
636 unsigned int fn;
637 u32 result = 0;
638 int err;
639
640 err = sdhci_start_signal_voltage_switch(mmc, ios);
641 if (err)
642 return err;
643
644 switch (ios->signal_voltage) {
645 case MMC_SIGNAL_VOLTAGE_330:
646 fn = INTEL_DSM_V33_SWITCH;
647 break;
648 case MMC_SIGNAL_VOLTAGE_180:
649 fn = INTEL_DSM_V18_SWITCH;
650 break;
651 default:
652 return 0;
653 }
654
655 err = intel_dsm(intel_host, dev, fn, &result);
656 pr_debug("%s: %s DSM fn %u error %d result %u\n",
657 mmc_hostname(mmc), __func__, fn, err, result);
658
659 return 0;
660 }
661
662 static const struct sdhci_ops sdhci_intel_byt_ops = {
663 .set_clock = sdhci_set_clock,
664 .set_power = sdhci_intel_set_power,
665 .enable_dma = sdhci_pci_enable_dma,
666 .set_bus_width = sdhci_set_bus_width,
667 .reset = sdhci_reset,
668 .set_uhs_signaling = sdhci_set_uhs_signaling,
669 .hw_reset = sdhci_pci_hw_reset,
670 };
671
672 static const struct sdhci_ops sdhci_intel_glk_ops = {
673 .set_clock = sdhci_set_clock,
674 .set_power = sdhci_intel_set_power,
675 .enable_dma = sdhci_pci_enable_dma,
676 .set_bus_width = sdhci_set_bus_width,
677 .reset = sdhci_reset,
678 .set_uhs_signaling = sdhci_set_uhs_signaling,
679 .hw_reset = sdhci_pci_hw_reset,
680 .irq = sdhci_cqhci_irq,
681 };
682
683 static void byt_read_dsm(struct sdhci_pci_slot *slot)
684 {
685 struct intel_host *intel_host = sdhci_pci_priv(slot);
686 struct device *dev = &slot->chip->pdev->dev;
687 struct mmc_host *mmc = slot->host->mmc;
688
689 intel_dsm_init(intel_host, dev, mmc);
690 slot->chip->rpm_retune = intel_host->d3_retune;
691 }
692
693 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode)
694 {
695 int err = sdhci_execute_tuning(mmc, opcode);
696 struct sdhci_host *host = mmc_priv(mmc);
697
698 if (err)
699 return err;
700
701 /*
702 * Tuning can leave the IP in an active state (Buffer Read Enable bit
703 * set) which prevents the entry to low power states (i.e. S0i3). Data
704 * reset will clear it.
705 */
706 sdhci_reset(host, SDHCI_RESET_DATA);
707
708 return 0;
709 }
710
711 static void byt_probe_slot(struct sdhci_pci_slot *slot)
712 {
713 struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
714
715 byt_read_dsm(slot);
716
717 ops->execute_tuning = intel_execute_tuning;
718 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch;
719 }
720
721 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
722 {
723 byt_probe_slot(slot);
724 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
725 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
726 MMC_CAP_CMD_DURING_TFR |
727 MMC_CAP_WAIT_WHILE_BUSY;
728 slot->hw_reset = sdhci_pci_int_hw_reset;
729 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
730 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
731 slot->host->mmc_host_ops.select_drive_strength =
732 intel_select_drive_strength;
733 return 0;
734 }
735
736 static bool glk_broken_cqhci(struct sdhci_pci_slot *slot)
737 {
738 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC &&
739 dmi_match(DMI_BIOS_VENDOR, "LENOVO");
740 }
741
742 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
743 {
744 int ret = byt_emmc_probe_slot(slot);
745
746 if (!glk_broken_cqhci(slot))
747 slot->host->mmc->caps2 |= MMC_CAP2_CQE;
748
749 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
750 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES,
751 slot->host->mmc_host_ops.hs400_enhanced_strobe =
752 intel_hs400_enhanced_strobe;
753 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
754 }
755
756 return ret;
757 }
758
759 static const struct cqhci_host_ops glk_cqhci_ops = {
760 .enable = sdhci_cqe_enable,
761 .disable = sdhci_cqe_disable,
762 .dumpregs = sdhci_pci_dumpregs,
763 };
764
765 static int glk_emmc_add_host(struct sdhci_pci_slot *slot)
766 {
767 struct device *dev = &slot->chip->pdev->dev;
768 struct sdhci_host *host = slot->host;
769 struct cqhci_host *cq_host;
770 bool dma64;
771 int ret;
772
773 ret = sdhci_setup_host(host);
774 if (ret)
775 return ret;
776
777 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
778 if (!cq_host) {
779 ret = -ENOMEM;
780 goto cleanup;
781 }
782
783 cq_host->mmio = host->ioaddr + 0x200;
784 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
785 cq_host->ops = &glk_cqhci_ops;
786
787 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
788 if (dma64)
789 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
790
791 ret = cqhci_init(cq_host, host->mmc, dma64);
792 if (ret)
793 goto cleanup;
794
795 ret = __sdhci_add_host(host);
796 if (ret)
797 goto cleanup;
798
799 return 0;
800
801 cleanup:
802 sdhci_cleanup_host(host);
803 return ret;
804 }
805
806 #ifdef CONFIG_PM
807 #define GLK_RX_CTRL1 0x834
808 #define GLK_TUN_VAL 0x840
809 #define GLK_PATH_PLL GENMASK(13, 8)
810 #define GLK_DLY GENMASK(6, 0)
811 /* Workaround firmware failing to restore the tuning value */
812 static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp)
813 {
814 struct sdhci_pci_slot *slot = chip->slots[0];
815 struct intel_host *intel_host = sdhci_pci_priv(slot);
816 struct sdhci_host *host = slot->host;
817 u32 glk_rx_ctrl1;
818 u32 glk_tun_val;
819 u32 dly;
820
821 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc))
822 return;
823
824 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1);
825 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL);
826
827 if (susp) {
828 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1;
829 intel_host->glk_tun_val = glk_tun_val;
830 return;
831 }
832
833 if (!intel_host->glk_tun_val)
834 return;
835
836 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) {
837 intel_host->rpm_retune_ok = true;
838 return;
839 }
840
841 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) +
842 (intel_host->glk_tun_val << 1));
843 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1))
844 return;
845
846 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly;
847 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1);
848
849 intel_host->rpm_retune_ok = true;
850 chip->rpm_retune = true;
851 mmc_retune_needed(host->mmc);
852 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc));
853 }
854
855 static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp)
856 {
857 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC &&
858 !chip->rpm_retune)
859 glk_rpm_retune_wa(chip, susp);
860 }
861
862 static int glk_runtime_suspend(struct sdhci_pci_chip *chip)
863 {
864 glk_rpm_retune_chk(chip, true);
865
866 return sdhci_cqhci_runtime_suspend(chip);
867 }
868
869 static int glk_runtime_resume(struct sdhci_pci_chip *chip)
870 {
871 glk_rpm_retune_chk(chip, false);
872
873 return sdhci_cqhci_runtime_resume(chip);
874 }
875 #endif
876
877 #ifdef CONFIG_ACPI
878 static int ni_set_max_freq(struct sdhci_pci_slot *slot)
879 {
880 acpi_status status;
881 unsigned long long max_freq;
882
883 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
884 "MXFQ", NULL, &max_freq);
885 if (ACPI_FAILURE(status)) {
886 dev_err(&slot->chip->pdev->dev,
887 "MXFQ not found in acpi table\n");
888 return -EINVAL;
889 }
890
891 slot->host->mmc->f_max = max_freq * 1000000;
892
893 return 0;
894 }
895 #else
896 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
897 {
898 return 0;
899 }
900 #endif
901
902 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
903 {
904 int err;
905
906 byt_probe_slot(slot);
907
908 err = ni_set_max_freq(slot);
909 if (err)
910 return err;
911
912 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
913 MMC_CAP_WAIT_WHILE_BUSY;
914 return 0;
915 }
916
917 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
918 {
919 byt_probe_slot(slot);
920 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
921 MMC_CAP_WAIT_WHILE_BUSY;
922 return 0;
923 }
924
925 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
926 {
927 byt_probe_slot(slot);
928 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
929 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE;
930 slot->cd_idx = 0;
931 slot->cd_override_level = true;
932 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
933 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
934 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
935 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
936 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
937
938 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI &&
939 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3)
940 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V;
941
942 return 0;
943 }
944
945 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
946 .allow_runtime_pm = true,
947 .probe_slot = byt_emmc_probe_slot,
948 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
949 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
950 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
951 SDHCI_QUIRK2_STOP_WITH_TC,
952 .ops = &sdhci_intel_byt_ops,
953 .priv_size = sizeof(struct intel_host),
954 };
955
956 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = {
957 .allow_runtime_pm = true,
958 .probe_slot = glk_emmc_probe_slot,
959 .add_host = glk_emmc_add_host,
960 #ifdef CONFIG_PM_SLEEP
961 .suspend = sdhci_cqhci_suspend,
962 .resume = sdhci_cqhci_resume,
963 #endif
964 #ifdef CONFIG_PM
965 .runtime_suspend = glk_runtime_suspend,
966 .runtime_resume = glk_runtime_resume,
967 #endif
968 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
969 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
970 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
971 SDHCI_QUIRK2_STOP_WITH_TC,
972 .ops = &sdhci_intel_glk_ops,
973 .priv_size = sizeof(struct intel_host),
974 };
975
976 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
977 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
978 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
979 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
980 .allow_runtime_pm = true,
981 .probe_slot = ni_byt_sdio_probe_slot,
982 .ops = &sdhci_intel_byt_ops,
983 .priv_size = sizeof(struct intel_host),
984 };
985
986 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
987 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
988 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
989 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
990 .allow_runtime_pm = true,
991 .probe_slot = byt_sdio_probe_slot,
992 .ops = &sdhci_intel_byt_ops,
993 .priv_size = sizeof(struct intel_host),
994 };
995
996 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
997 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
998 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
999 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1000 SDHCI_QUIRK2_STOP_WITH_TC,
1001 .allow_runtime_pm = true,
1002 .own_cd_for_runtime_pm = true,
1003 .probe_slot = byt_sd_probe_slot,
1004 .ops = &sdhci_intel_byt_ops,
1005 .priv_size = sizeof(struct intel_host),
1006 };
1007
1008 /* Define Host controllers for Intel Merrifield platform */
1009 #define INTEL_MRFLD_EMMC_0 0
1010 #define INTEL_MRFLD_EMMC_1 1
1011 #define INTEL_MRFLD_SD 2
1012 #define INTEL_MRFLD_SDIO 3
1013
1014 #ifdef CONFIG_ACPI
1015 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot)
1016 {
1017 struct acpi_device *device, *child;
1018
1019 device = ACPI_COMPANION(&slot->chip->pdev->dev);
1020 if (!device)
1021 return;
1022
1023 acpi_device_fix_up_power(device);
1024 list_for_each_entry(child, &device->children, node)
1025 if (child->status.present && child->status.enabled)
1026 acpi_device_fix_up_power(child);
1027 }
1028 #else
1029 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {}
1030 #endif
1031
1032 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
1033 {
1034 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
1035
1036 switch (func) {
1037 case INTEL_MRFLD_EMMC_0:
1038 case INTEL_MRFLD_EMMC_1:
1039 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
1040 MMC_CAP_8_BIT_DATA |
1041 MMC_CAP_1_8V_DDR;
1042 break;
1043 case INTEL_MRFLD_SD:
1044 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1045 break;
1046 case INTEL_MRFLD_SDIO:
1047 /* Advertise 2.0v for compatibility with the SDIO card's OCR */
1048 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195;
1049 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
1050 MMC_CAP_POWER_OFF_CARD;
1051 break;
1052 default:
1053 return -ENODEV;
1054 }
1055
1056 intel_mrfld_mmc_fix_up_power_slot(slot);
1057 return 0;
1058 }
1059
1060 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
1061 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1062 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
1063 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1064 .allow_runtime_pm = true,
1065 .probe_slot = intel_mrfld_mmc_probe_slot,
1066 };
1067
1068 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
1069 {
1070 u8 scratch;
1071 int ret;
1072
1073 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
1074 if (ret)
1075 return ret;
1076
1077 /*
1078 * Turn PMOS on [bit 0], set over current detection to 2.4 V
1079 * [bit 1:2] and enable over current debouncing [bit 6].
1080 */
1081 if (on)
1082 scratch |= 0x47;
1083 else
1084 scratch &= ~0x47;
1085
1086 return pci_write_config_byte(chip->pdev, 0xAE, scratch);
1087 }
1088
1089 static int jmicron_probe(struct sdhci_pci_chip *chip)
1090 {
1091 int ret;
1092 u16 mmcdev = 0;
1093
1094 if (chip->pdev->revision == 0) {
1095 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
1096 SDHCI_QUIRK_32BIT_DMA_SIZE |
1097 SDHCI_QUIRK_32BIT_ADMA_SIZE |
1098 SDHCI_QUIRK_RESET_AFTER_REQUEST |
1099 SDHCI_QUIRK_BROKEN_SMALL_PIO;
1100 }
1101
1102 /*
1103 * JMicron chips can have two interfaces to the same hardware
1104 * in order to work around limitations in Microsoft's driver.
1105 * We need to make sure we only bind to one of them.
1106 *
1107 * This code assumes two things:
1108 *
1109 * 1. The PCI code adds subfunctions in order.
1110 *
1111 * 2. The MMC interface has a lower subfunction number
1112 * than the SD interface.
1113 */
1114 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
1115 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
1116 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
1117 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
1118
1119 if (mmcdev) {
1120 struct pci_dev *sd_dev;
1121
1122 sd_dev = NULL;
1123 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
1124 mmcdev, sd_dev)) != NULL) {
1125 if ((PCI_SLOT(chip->pdev->devfn) ==
1126 PCI_SLOT(sd_dev->devfn)) &&
1127 (chip->pdev->bus == sd_dev->bus))
1128 break;
1129 }
1130
1131 if (sd_dev) {
1132 pci_dev_put(sd_dev);
1133 dev_info(&chip->pdev->dev, "Refusing to bind to "
1134 "secondary interface.\n");
1135 return -ENODEV;
1136 }
1137 }
1138
1139 /*
1140 * JMicron chips need a bit of a nudge to enable the power
1141 * output pins.
1142 */
1143 ret = jmicron_pmos(chip, 1);
1144 if (ret) {
1145 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1146 return ret;
1147 }
1148
1149 /* quirk for unsable RO-detection on JM388 chips */
1150 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
1151 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1152 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
1153
1154 return 0;
1155 }
1156
1157 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
1158 {
1159 u8 scratch;
1160
1161 scratch = readb(host->ioaddr + 0xC0);
1162
1163 if (on)
1164 scratch |= 0x01;
1165 else
1166 scratch &= ~0x01;
1167
1168 writeb(scratch, host->ioaddr + 0xC0);
1169 }
1170
1171 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
1172 {
1173 if (slot->chip->pdev->revision == 0) {
1174 u16 version;
1175
1176 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
1177 version = (version & SDHCI_VENDOR_VER_MASK) >>
1178 SDHCI_VENDOR_VER_SHIFT;
1179
1180 /*
1181 * Older versions of the chip have lots of nasty glitches
1182 * in the ADMA engine. It's best just to avoid it
1183 * completely.
1184 */
1185 if (version < 0xAC)
1186 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1187 }
1188
1189 /* JM388 MMC doesn't support 1.8V while SD supports it */
1190 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1191 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
1192 MMC_VDD_29_30 | MMC_VDD_30_31 |
1193 MMC_VDD_165_195; /* allow 1.8V */
1194 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
1195 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
1196 }
1197
1198 /*
1199 * The secondary interface requires a bit set to get the
1200 * interrupts.
1201 */
1202 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1203 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1204 jmicron_enable_mmc(slot->host, 1);
1205
1206 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
1207
1208 return 0;
1209 }
1210
1211 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
1212 {
1213 if (dead)
1214 return;
1215
1216 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1217 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1218 jmicron_enable_mmc(slot->host, 0);
1219 }
1220
1221 #ifdef CONFIG_PM_SLEEP
1222 static int jmicron_suspend(struct sdhci_pci_chip *chip)
1223 {
1224 int i, ret;
1225
1226 ret = sdhci_pci_suspend_host(chip);
1227 if (ret)
1228 return ret;
1229
1230 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1231 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1232 for (i = 0; i < chip->num_slots; i++)
1233 jmicron_enable_mmc(chip->slots[i]->host, 0);
1234 }
1235
1236 return 0;
1237 }
1238
1239 static int jmicron_resume(struct sdhci_pci_chip *chip)
1240 {
1241 int ret, i;
1242
1243 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1244 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1245 for (i = 0; i < chip->num_slots; i++)
1246 jmicron_enable_mmc(chip->slots[i]->host, 1);
1247 }
1248
1249 ret = jmicron_pmos(chip, 1);
1250 if (ret) {
1251 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1252 return ret;
1253 }
1254
1255 return sdhci_pci_resume_host(chip);
1256 }
1257 #endif
1258
1259 static const struct sdhci_pci_fixes sdhci_o2 = {
1260 .probe = sdhci_pci_o2_probe,
1261 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1262 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
1263 .probe_slot = sdhci_pci_o2_probe_slot,
1264 #ifdef CONFIG_PM_SLEEP
1265 .resume = sdhci_pci_o2_resume,
1266 #endif
1267 };
1268
1269 static const struct sdhci_pci_fixes sdhci_jmicron = {
1270 .probe = jmicron_probe,
1271
1272 .probe_slot = jmicron_probe_slot,
1273 .remove_slot = jmicron_remove_slot,
1274
1275 #ifdef CONFIG_PM_SLEEP
1276 .suspend = jmicron_suspend,
1277 .resume = jmicron_resume,
1278 #endif
1279 };
1280
1281 /* SysKonnect CardBus2SDIO extra registers */
1282 #define SYSKT_CTRL 0x200
1283 #define SYSKT_RDFIFO_STAT 0x204
1284 #define SYSKT_WRFIFO_STAT 0x208
1285 #define SYSKT_POWER_DATA 0x20c
1286 #define SYSKT_POWER_330 0xef
1287 #define SYSKT_POWER_300 0xf8
1288 #define SYSKT_POWER_184 0xcc
1289 #define SYSKT_POWER_CMD 0x20d
1290 #define SYSKT_POWER_START (1 << 7)
1291 #define SYSKT_POWER_STATUS 0x20e
1292 #define SYSKT_POWER_STATUS_OK (1 << 0)
1293 #define SYSKT_BOARD_REV 0x210
1294 #define SYSKT_CHIP_REV 0x211
1295 #define SYSKT_CONF_DATA 0x212
1296 #define SYSKT_CONF_DATA_1V8 (1 << 2)
1297 #define SYSKT_CONF_DATA_2V5 (1 << 1)
1298 #define SYSKT_CONF_DATA_3V3 (1 << 0)
1299
1300 static int syskt_probe(struct sdhci_pci_chip *chip)
1301 {
1302 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1303 chip->pdev->class &= ~0x0000FF;
1304 chip->pdev->class |= PCI_SDHCI_IFDMA;
1305 }
1306 return 0;
1307 }
1308
1309 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
1310 {
1311 int tm, ps;
1312
1313 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
1314 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
1315 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
1316 "board rev %d.%d, chip rev %d.%d\n",
1317 board_rev >> 4, board_rev & 0xf,
1318 chip_rev >> 4, chip_rev & 0xf);
1319 if (chip_rev >= 0x20)
1320 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
1321
1322 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
1323 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
1324 udelay(50);
1325 tm = 10; /* Wait max 1 ms */
1326 do {
1327 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
1328 if (ps & SYSKT_POWER_STATUS_OK)
1329 break;
1330 udelay(100);
1331 } while (--tm);
1332 if (!tm) {
1333 dev_err(&slot->chip->pdev->dev,
1334 "power regulator never stabilized");
1335 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
1336 return -ENODEV;
1337 }
1338
1339 return 0;
1340 }
1341
1342 static const struct sdhci_pci_fixes sdhci_syskt = {
1343 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
1344 .probe = syskt_probe,
1345 .probe_slot = syskt_probe_slot,
1346 };
1347
1348 static int via_probe(struct sdhci_pci_chip *chip)
1349 {
1350 if (chip->pdev->revision == 0x10)
1351 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
1352
1353 return 0;
1354 }
1355
1356 static const struct sdhci_pci_fixes sdhci_via = {
1357 .probe = via_probe,
1358 };
1359
1360 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
1361 {
1362 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
1363 return 0;
1364 }
1365
1366 static const struct sdhci_pci_fixes sdhci_rtsx = {
1367 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1368 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
1369 SDHCI_QUIRK2_BROKEN_DDR50,
1370 .probe_slot = rtsx_probe_slot,
1371 };
1372
1373 /*AMD chipset generation*/
1374 enum amd_chipset_gen {
1375 AMD_CHIPSET_BEFORE_ML,
1376 AMD_CHIPSET_CZ,
1377 AMD_CHIPSET_NL,
1378 AMD_CHIPSET_UNKNOWN,
1379 };
1380
1381 /* AMD registers */
1382 #define AMD_SD_AUTO_PATTERN 0xB8
1383 #define AMD_MSLEEP_DURATION 4
1384 #define AMD_SD_MISC_CONTROL 0xD0
1385 #define AMD_MAX_TUNE_VALUE 0x0B
1386 #define AMD_AUTO_TUNE_SEL 0x10800
1387 #define AMD_FIFO_PTR 0x30
1388 #define AMD_BIT_MASK 0x1F
1389
1390 static void amd_tuning_reset(struct sdhci_host *host)
1391 {
1392 unsigned int val;
1393
1394 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1395 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
1396 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1397
1398 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1399 val &= ~SDHCI_CTRL_EXEC_TUNING;
1400 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1401 }
1402
1403 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
1404 {
1405 unsigned int val;
1406
1407 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val);
1408 val &= ~AMD_BIT_MASK;
1409 val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
1410 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val);
1411 }
1412
1413 static void amd_enable_manual_tuning(struct pci_dev *pdev)
1414 {
1415 unsigned int val;
1416
1417 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val);
1418 val |= AMD_FIFO_PTR;
1419 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val);
1420 }
1421
1422 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode)
1423 {
1424 struct sdhci_pci_slot *slot = sdhci_priv(host);
1425 struct pci_dev *pdev = slot->chip->pdev;
1426 u8 valid_win = 0;
1427 u8 valid_win_max = 0;
1428 u8 valid_win_end = 0;
1429 u8 ctrl, tune_around;
1430
1431 amd_tuning_reset(host);
1432
1433 for (tune_around = 0; tune_around < 12; tune_around++) {
1434 amd_config_tuning_phase(pdev, tune_around);
1435
1436 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1437 valid_win = 0;
1438 msleep(AMD_MSLEEP_DURATION);
1439 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
1440 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET);
1441 } else if (++valid_win > valid_win_max) {
1442 valid_win_max = valid_win;
1443 valid_win_end = tune_around;
1444 }
1445 }
1446
1447 if (!valid_win_max) {
1448 dev_err(&pdev->dev, "no tuning point found\n");
1449 return -EIO;
1450 }
1451
1452 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2);
1453
1454 amd_enable_manual_tuning(pdev);
1455
1456 host->mmc->retune_period = 0;
1457
1458 return 0;
1459 }
1460
1461 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode)
1462 {
1463 struct sdhci_host *host = mmc_priv(mmc);
1464
1465 /* AMD requires custom HS200 tuning */
1466 if (host->timing == MMC_TIMING_MMC_HS200)
1467 return amd_execute_tuning_hs200(host, opcode);
1468
1469 /* Otherwise perform standard SDHCI tuning */
1470 return sdhci_execute_tuning(mmc, opcode);
1471 }
1472
1473 static int amd_probe_slot(struct sdhci_pci_slot *slot)
1474 {
1475 struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
1476
1477 ops->execute_tuning = amd_execute_tuning;
1478
1479 return 0;
1480 }
1481
1482 static int amd_probe(struct sdhci_pci_chip *chip)
1483 {
1484 struct pci_dev *smbus_dev;
1485 enum amd_chipset_gen gen;
1486
1487 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1488 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
1489 if (smbus_dev) {
1490 gen = AMD_CHIPSET_BEFORE_ML;
1491 } else {
1492 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1493 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
1494 if (smbus_dev) {
1495 if (smbus_dev->revision < 0x51)
1496 gen = AMD_CHIPSET_CZ;
1497 else
1498 gen = AMD_CHIPSET_NL;
1499 } else {
1500 gen = AMD_CHIPSET_UNKNOWN;
1501 }
1502 }
1503
1504 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
1505 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
1506
1507 return 0;
1508 }
1509
1510 static const struct sdhci_ops amd_sdhci_pci_ops = {
1511 .set_clock = sdhci_set_clock,
1512 .enable_dma = sdhci_pci_enable_dma,
1513 .set_bus_width = sdhci_set_bus_width,
1514 .reset = sdhci_reset,
1515 .set_uhs_signaling = sdhci_set_uhs_signaling,
1516 };
1517
1518 static const struct sdhci_pci_fixes sdhci_amd = {
1519 .probe = amd_probe,
1520 .ops = &amd_sdhci_pci_ops,
1521 .probe_slot = amd_probe_slot,
1522 };
1523
1524 static const struct pci_device_id pci_ids[] = {
1525 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh),
1526 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc),
1527 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc),
1528 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc),
1529 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712),
1530 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712),
1531 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714),
1532 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714),
1533 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe),
1534 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron),
1535 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron),
1536 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron),
1537 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron),
1538 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt),
1539 SDHCI_PCI_DEVICE(VIA, 95D0, via),
1540 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx),
1541 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk),
1542 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0),
1543 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2),
1544 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2),
1545 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd),
1546 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio),
1547 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio),
1548 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc),
1549 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc),
1550 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio),
1551 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio),
1552 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc),
1553 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio),
1554 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio),
1555 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd),
1556 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc),
1557 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc),
1558 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio),
1559 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd),
1560 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd),
1561 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio),
1562 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio),
1563 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc),
1564 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc),
1565 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc),
1566 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc),
1567 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio),
1568 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd),
1569 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc),
1570 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc),
1571 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc),
1572 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio),
1573 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd),
1574 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc),
1575 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio),
1576 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd),
1577 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc),
1578 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio),
1579 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd),
1580 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc),
1581 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio),
1582 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd),
1583 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc),
1584 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd),
1585 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd),
1586 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc),
1587 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd),
1588 SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc),
1589 SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd),
1590 SDHCI_PCI_DEVICE(O2, 8120, o2),
1591 SDHCI_PCI_DEVICE(O2, 8220, o2),
1592 SDHCI_PCI_DEVICE(O2, 8221, o2),
1593 SDHCI_PCI_DEVICE(O2, 8320, o2),
1594 SDHCI_PCI_DEVICE(O2, 8321, o2),
1595 SDHCI_PCI_DEVICE(O2, FUJIN2, o2),
1596 SDHCI_PCI_DEVICE(O2, SDS0, o2),
1597 SDHCI_PCI_DEVICE(O2, SDS1, o2),
1598 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2),
1599 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
1600 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan),
1601 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps),
1602 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
1603 /* Generic SD host controller */
1604 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
1605 { /* end: all zeroes */ },
1606 };
1607
1608 MODULE_DEVICE_TABLE(pci, pci_ids);
1609
1610 /*****************************************************************************\
1611 * *
1612 * SDHCI core callbacks *
1613 * *
1614 \*****************************************************************************/
1615
1616 int sdhci_pci_enable_dma(struct sdhci_host *host)
1617 {
1618 struct sdhci_pci_slot *slot;
1619 struct pci_dev *pdev;
1620
1621 slot = sdhci_priv(host);
1622 pdev = slot->chip->pdev;
1623
1624 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1625 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1626 (host->flags & SDHCI_USE_SDMA)) {
1627 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1628 "doesn't fully claim to support it.\n");
1629 }
1630
1631 pci_set_master(pdev);
1632
1633 return 0;
1634 }
1635
1636 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1637 {
1638 struct sdhci_pci_slot *slot = sdhci_priv(host);
1639 int rst_n_gpio = slot->rst_n_gpio;
1640
1641 if (!gpio_is_valid(rst_n_gpio))
1642 return;
1643 gpio_set_value_cansleep(rst_n_gpio, 0);
1644 /* For eMMC, minimum is 1us but give it 10us for good measure */
1645 udelay(10);
1646 gpio_set_value_cansleep(rst_n_gpio, 1);
1647 /* For eMMC, minimum is 200us but give it 300us for good measure */
1648 usleep_range(300, 1000);
1649 }
1650
1651 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1652 {
1653 struct sdhci_pci_slot *slot = sdhci_priv(host);
1654
1655 if (slot->hw_reset)
1656 slot->hw_reset(host);
1657 }
1658
1659 static const struct sdhci_ops sdhci_pci_ops = {
1660 .set_clock = sdhci_set_clock,
1661 .enable_dma = sdhci_pci_enable_dma,
1662 .set_bus_width = sdhci_set_bus_width,
1663 .reset = sdhci_reset,
1664 .set_uhs_signaling = sdhci_set_uhs_signaling,
1665 .hw_reset = sdhci_pci_hw_reset,
1666 };
1667
1668 /*****************************************************************************\
1669 * *
1670 * Suspend/resume *
1671 * *
1672 \*****************************************************************************/
1673
1674 #ifdef CONFIG_PM_SLEEP
1675 static int sdhci_pci_suspend(struct device *dev)
1676 {
1677 struct pci_dev *pdev = to_pci_dev(dev);
1678 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1679
1680 if (!chip)
1681 return 0;
1682
1683 if (chip->fixes && chip->fixes->suspend)
1684 return chip->fixes->suspend(chip);
1685
1686 return sdhci_pci_suspend_host(chip);
1687 }
1688
1689 static int sdhci_pci_resume(struct device *dev)
1690 {
1691 struct pci_dev *pdev = to_pci_dev(dev);
1692 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1693
1694 if (!chip)
1695 return 0;
1696
1697 if (chip->fixes && chip->fixes->resume)
1698 return chip->fixes->resume(chip);
1699
1700 return sdhci_pci_resume_host(chip);
1701 }
1702 #endif
1703
1704 #ifdef CONFIG_PM
1705 static int sdhci_pci_runtime_suspend(struct device *dev)
1706 {
1707 struct pci_dev *pdev = to_pci_dev(dev);
1708 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1709
1710 if (!chip)
1711 return 0;
1712
1713 if (chip->fixes && chip->fixes->runtime_suspend)
1714 return chip->fixes->runtime_suspend(chip);
1715
1716 return sdhci_pci_runtime_suspend_host(chip);
1717 }
1718
1719 static int sdhci_pci_runtime_resume(struct device *dev)
1720 {
1721 struct pci_dev *pdev = to_pci_dev(dev);
1722 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1723
1724 if (!chip)
1725 return 0;
1726
1727 if (chip->fixes && chip->fixes->runtime_resume)
1728 return chip->fixes->runtime_resume(chip);
1729
1730 return sdhci_pci_runtime_resume_host(chip);
1731 }
1732 #endif
1733
1734 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1735 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
1736 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1737 sdhci_pci_runtime_resume, NULL)
1738 };
1739
1740 /*****************************************************************************\
1741 * *
1742 * Device probing/removal *
1743 * *
1744 \*****************************************************************************/
1745
1746 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1747 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1748 int slotno)
1749 {
1750 struct sdhci_pci_slot *slot;
1751 struct sdhci_host *host;
1752 int ret, bar = first_bar + slotno;
1753 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0;
1754
1755 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1756 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1757 return ERR_PTR(-ENODEV);
1758 }
1759
1760 if (pci_resource_len(pdev, bar) < 0x100) {
1761 dev_err(&pdev->dev, "Invalid iomem size. You may "
1762 "experience problems.\n");
1763 }
1764
1765 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1766 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1767 return ERR_PTR(-ENODEV);
1768 }
1769
1770 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1771 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1772 return ERR_PTR(-ENODEV);
1773 }
1774
1775 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size);
1776 if (IS_ERR(host)) {
1777 dev_err(&pdev->dev, "cannot allocate host\n");
1778 return ERR_CAST(host);
1779 }
1780
1781 slot = sdhci_priv(host);
1782
1783 slot->chip = chip;
1784 slot->host = host;
1785 slot->rst_n_gpio = -EINVAL;
1786 slot->cd_gpio = -EINVAL;
1787 slot->cd_idx = -1;
1788
1789 /* Retrieve platform data if there is any */
1790 if (*sdhci_pci_get_data)
1791 slot->data = sdhci_pci_get_data(pdev, slotno);
1792
1793 if (slot->data) {
1794 if (slot->data->setup) {
1795 ret = slot->data->setup(slot->data);
1796 if (ret) {
1797 dev_err(&pdev->dev, "platform setup failed\n");
1798 goto free;
1799 }
1800 }
1801 slot->rst_n_gpio = slot->data->rst_n_gpio;
1802 slot->cd_gpio = slot->data->cd_gpio;
1803 }
1804
1805 host->hw_name = "PCI";
1806 host->ops = chip->fixes && chip->fixes->ops ?
1807 chip->fixes->ops :
1808 &sdhci_pci_ops;
1809 host->quirks = chip->quirks;
1810 host->quirks2 = chip->quirks2;
1811
1812 host->irq = pdev->irq;
1813
1814 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
1815 if (ret) {
1816 dev_err(&pdev->dev, "cannot request region\n");
1817 goto cleanup;
1818 }
1819
1820 host->ioaddr = pcim_iomap_table(pdev)[bar];
1821
1822 if (chip->fixes && chip->fixes->probe_slot) {
1823 ret = chip->fixes->probe_slot(slot);
1824 if (ret)
1825 goto cleanup;
1826 }
1827
1828 if (gpio_is_valid(slot->rst_n_gpio)) {
1829 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) {
1830 gpio_direction_output(slot->rst_n_gpio, 1);
1831 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1832 slot->hw_reset = sdhci_pci_gpio_hw_reset;
1833 } else {
1834 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1835 slot->rst_n_gpio = -EINVAL;
1836 }
1837 }
1838
1839 host->mmc->pm_caps = MMC_PM_KEEP_POWER;
1840 host->mmc->slotno = slotno;
1841 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1842
1843 if (device_can_wakeup(&pdev->dev))
1844 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
1845
1846 if (host->mmc->caps & MMC_CAP_CD_WAKE)
1847 device_init_wakeup(&pdev->dev, true);
1848
1849 if (slot->cd_idx >= 0) {
1850 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx,
1851 slot->cd_override_level, 0, NULL);
1852 if (ret && ret != -EPROBE_DEFER)
1853 ret = mmc_gpiod_request_cd(host->mmc, NULL,
1854 slot->cd_idx,
1855 slot->cd_override_level,
1856 0, NULL);
1857 if (ret == -EPROBE_DEFER)
1858 goto remove;
1859
1860 if (ret) {
1861 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1862 slot->cd_idx = -1;
1863 }
1864 }
1865
1866 if (chip->fixes && chip->fixes->add_host)
1867 ret = chip->fixes->add_host(slot);
1868 else
1869 ret = sdhci_add_host(host);
1870 if (ret)
1871 goto remove;
1872
1873 sdhci_pci_add_own_cd(slot);
1874
1875 /*
1876 * Check if the chip needs a separate GPIO for card detect to wake up
1877 * from runtime suspend. If it is not there, don't allow runtime PM.
1878 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1879 */
1880 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1881 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
1882 chip->allow_runtime_pm = false;
1883
1884 return slot;
1885
1886 remove:
1887 if (chip->fixes && chip->fixes->remove_slot)
1888 chip->fixes->remove_slot(slot, 0);
1889
1890 cleanup:
1891 if (slot->data && slot->data->cleanup)
1892 slot->data->cleanup(slot->data);
1893
1894 free:
1895 sdhci_free_host(host);
1896
1897 return ERR_PTR(ret);
1898 }
1899
1900 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1901 {
1902 int dead;
1903 u32 scratch;
1904
1905 sdhci_pci_remove_own_cd(slot);
1906
1907 dead = 0;
1908 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1909 if (scratch == (u32)-1)
1910 dead = 1;
1911
1912 sdhci_remove_host(slot->host, dead);
1913
1914 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1915 slot->chip->fixes->remove_slot(slot, dead);
1916
1917 if (slot->data && slot->data->cleanup)
1918 slot->data->cleanup(slot->data);
1919
1920 sdhci_free_host(slot->host);
1921 }
1922
1923 static void sdhci_pci_runtime_pm_allow(struct device *dev)
1924 {
1925 pm_suspend_ignore_children(dev, 1);
1926 pm_runtime_set_autosuspend_delay(dev, 50);
1927 pm_runtime_use_autosuspend(dev);
1928 pm_runtime_allow(dev);
1929 /* Stay active until mmc core scans for a card */
1930 pm_runtime_put_noidle(dev);
1931 }
1932
1933 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1934 {
1935 pm_runtime_forbid(dev);
1936 pm_runtime_get_noresume(dev);
1937 }
1938
1939 static int sdhci_pci_probe(struct pci_dev *pdev,
1940 const struct pci_device_id *ent)
1941 {
1942 struct sdhci_pci_chip *chip;
1943 struct sdhci_pci_slot *slot;
1944
1945 u8 slots, first_bar;
1946 int ret, i;
1947
1948 BUG_ON(pdev == NULL);
1949 BUG_ON(ent == NULL);
1950
1951 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1952 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1953
1954 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1955 if (ret)
1956 return ret;
1957
1958 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1959 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1960 if (slots == 0)
1961 return -ENODEV;
1962
1963 BUG_ON(slots > MAX_SLOTS);
1964
1965 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1966 if (ret)
1967 return ret;
1968
1969 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1970
1971 if (first_bar > 5) {
1972 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1973 return -ENODEV;
1974 }
1975
1976 ret = pcim_enable_device(pdev);
1977 if (ret)
1978 return ret;
1979
1980 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
1981 if (!chip)
1982 return -ENOMEM;
1983
1984 chip->pdev = pdev;
1985 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1986 if (chip->fixes) {
1987 chip->quirks = chip->fixes->quirks;
1988 chip->quirks2 = chip->fixes->quirks2;
1989 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1990 }
1991 chip->num_slots = slots;
1992 chip->pm_retune = true;
1993 chip->rpm_retune = true;
1994
1995 pci_set_drvdata(pdev, chip);
1996
1997 if (chip->fixes && chip->fixes->probe) {
1998 ret = chip->fixes->probe(chip);
1999 if (ret)
2000 return ret;
2001 }
2002
2003 slots = chip->num_slots; /* Quirk may have changed this */
2004
2005 for (i = 0; i < slots; i++) {
2006 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
2007 if (IS_ERR(slot)) {
2008 for (i--; i >= 0; i--)
2009 sdhci_pci_remove_slot(chip->slots[i]);
2010 return PTR_ERR(slot);
2011 }
2012
2013 chip->slots[i] = slot;
2014 }
2015
2016 if (chip->allow_runtime_pm)
2017 sdhci_pci_runtime_pm_allow(&pdev->dev);
2018
2019 return 0;
2020 }
2021
2022 static void sdhci_pci_remove(struct pci_dev *pdev)
2023 {
2024 int i;
2025 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
2026
2027 if (chip->allow_runtime_pm)
2028 sdhci_pci_runtime_pm_forbid(&pdev->dev);
2029
2030 for (i = 0; i < chip->num_slots; i++)
2031 sdhci_pci_remove_slot(chip->slots[i]);
2032 }
2033
2034 static struct pci_driver sdhci_driver = {
2035 .name = "sdhci-pci",
2036 .id_table = pci_ids,
2037 .probe = sdhci_pci_probe,
2038 .remove = sdhci_pci_remove,
2039 .driver = {
2040 .pm = &sdhci_pci_pm_ops
2041 },
2042 };
2043
2044 module_pci_driver(sdhci_driver);
2045
2046 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2047 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
2048 MODULE_LICENSE("GPL");
Linux with added FPC-III support