| blob | 662c6dd98072e72beabcb1e894cc05999324da81 |
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
11 *
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 */
21 #include <linux/errno.h>
22 #include <asm/unistd.h>
23 #include <asm/processor.h>
24 #include <asm/page.h>
25 #include <asm/mmu.h>
26 #include <asm/thread_info.h>
27 #include <asm/ppc_asm.h>
28 #include <asm/asm-offsets.h>
29 #include <asm/cputable.h>
30 #include <asm/firmware.h>
31 #include <asm/bug.h>
32 #include <asm/ptrace.h>
33 #include <asm/irqflags.h>
34 #include <asm/ftrace.h>
35 #include <asm/hw_irq.h>
36 #include <asm/context_tracking.h>
38 /*
39 * System calls.
40 */
41 .section ".toc","aw"
42 .SYS_CALL_TABLE:
43 .tc .sys_call_table[TC],.sys_call_table
45 /* This value is used to mark exception frames on the stack. */
46 exception_marker:
47 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
49 .section ".text"
50 .align 7
52 #undef SHOW_SYSCALLS
54 .globl system_call_common
55 system_call_common:
56 andi. r10,r12,MSR_PR
57 mr r10,r1
58 addi r1,r1,-INT_FRAME_SIZE
59 beq- 1f
60 ld r1,PACAKSAVE(r13)
61 1: std r10,0(r1)
62 std r11,_NIP(r1)
63 std r12,_MSR(r1)
64 std r0,GPR0(r1)
65 std r10,GPR1(r1)
66 beq 2f /* if from kernel mode */
67 ACCOUNT_CPU_USER_ENTRY(r10, r11)
68 2: std r2,GPR2(r1)
69 std r3,GPR3(r1)
70 mfcr r2
71 std r4,GPR4(r1)
72 std r5,GPR5(r1)
73 std r6,GPR6(r1)
74 std r7,GPR7(r1)
75 std r8,GPR8(r1)
76 li r11,0
77 std r11,GPR9(r1)
78 std r11,GPR10(r1)
79 std r11,GPR11(r1)
80 std r11,GPR12(r1)
81 std r11,_XER(r1)
82 std r11,_CTR(r1)
83 std r9,GPR13(r1)
84 mflr r10
85 /*
86 * This clears CR0.SO (bit 28), which is the error indication on
87 * return from this system call.
88 */
89 rldimi r2,r11,28,(63-28)
90 li r11,0xc01
91 std r10,_LINK(r1)
92 std r11,_TRAP(r1)
93 std r3,ORIG_GPR3(r1)
94 std r2,_CCR(r1)
95 ld r2,PACATOC(r13)
96 addi r9,r1,STACK_FRAME_OVERHEAD
97 ld r11,exception_marker@toc(r2)
98 std r11,-16(r9) /* "regshere" marker */
99 #if defined(CONFIG_VIRT_CPU_ACCOUNTING_NATIVE) && defined(CONFIG_PPC_SPLPAR)
100 BEGIN_FW_FTR_SECTION
101 beq 33f
102 /* if from user, see if there are any DTL entries to process */
103 ld r10,PACALPPACAPTR(r13) /* get ptr to VPA */
104 ld r11,PACA_DTL_RIDX(r13) /* get log read index */
105 addi r10,r10,LPPACA_DTLIDX
106 LDX_BE r10,0,r10 /* get log write index */
107 cmpd cr1,r11,r10
108 beq+ cr1,33f
109 bl .accumulate_stolen_time
110 REST_GPR(0,r1)
111 REST_4GPRS(3,r1)
112 REST_2GPRS(7,r1)
113 addi r9,r1,STACK_FRAME_OVERHEAD
114 33:
115 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
116 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE && CONFIG_PPC_SPLPAR */
118 /*
119 * A syscall should always be called with interrupts enabled
120 * so we just unconditionally hard-enable here. When some kind
121 * of irq tracing is used, we additionally check that condition
122 * is correct
123 */
124 #if defined(CONFIG_TRACE_IRQFLAGS) && defined(CONFIG_BUG)
125 lbz r10,PACASOFTIRQEN(r13)
126 xori r10,r10,1
127 1: tdnei r10,0
128 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
129 #endif
131 #ifdef CONFIG_PPC_BOOK3E
132 wrteei 1
133 #else
134 ld r11,PACAKMSR(r13)
135 ori r11,r11,MSR_EE
136 mtmsrd r11,1
137 #endif /* CONFIG_PPC_BOOK3E */
139 /* We do need to set SOFTE in the stack frame or the return
140 * from interrupt will be painful
141 */
142 li r10,1
143 std r10,SOFTE(r1)
145 #ifdef SHOW_SYSCALLS
146 bl .do_show_syscall
147 REST_GPR(0,r1)
148 REST_4GPRS(3,r1)
149 REST_2GPRS(7,r1)
150 addi r9,r1,STACK_FRAME_OVERHEAD
151 #endif
152 CURRENT_THREAD_INFO(r11, r1)
153 ld r10,TI_FLAGS(r11)
154 andi. r11,r10,_TIF_SYSCALL_T_OR_A
155 bne syscall_dotrace
156 .Lsyscall_dotrace_cont:
157 cmpldi 0,r0,NR_syscalls
158 bge- syscall_enosys
160 system_call: /* label this so stack traces look sane */
161 /*
162 * Need to vector to 32 Bit or default sys_call_table here,
163 * based on caller's run-mode / personality.
164 */
165 ld r11,.SYS_CALL_TABLE@toc(2)
166 andi. r10,r10,_TIF_32BIT
167 beq 15f
168 addi r11,r11,8 /* use 32-bit syscall entries */
169 clrldi r3,r3,32
170 clrldi r4,r4,32
171 clrldi r5,r5,32
172 clrldi r6,r6,32
173 clrldi r7,r7,32
174 clrldi r8,r8,32
175 15:
176 slwi r0,r0,4
177 ldx r10,r11,r0 /* Fetch system call handler [ptr] */
178 mtctr r10
179 bctrl /* Call handler */
181 syscall_exit:
182 std r3,RESULT(r1)
183 #ifdef SHOW_SYSCALLS
184 bl .do_show_syscall_exit
185 ld r3,RESULT(r1)
186 #endif
187 CURRENT_THREAD_INFO(r12, r1)
189 ld r8,_MSR(r1)
190 #ifdef CONFIG_PPC_BOOK3S
191 /* No MSR:RI on BookE */
192 andi. r10,r8,MSR_RI
193 beq- unrecov_restore
194 #endif
195 /*
196 * Disable interrupts so current_thread_info()->flags can't change,
197 * and so that we don't get interrupted after loading SRR0/1.
198 */
199 #ifdef CONFIG_PPC_BOOK3E
200 wrteei 0
201 #else
202 ld r10,PACAKMSR(r13)
203 /*
204 * For performance reasons we clear RI the same time that we
205 * clear EE. We only need to clear RI just before we restore r13
206 * below, but batching it with EE saves us one expensive mtmsrd call.
207 * We have to be careful to restore RI if we branch anywhere from
208 * here (eg syscall_exit_work).
209 */
210 li r9,MSR_RI
211 andc r11,r10,r9
212 mtmsrd r11,1
213 #endif /* CONFIG_PPC_BOOK3E */
215 ld r9,TI_FLAGS(r12)
216 li r11,-_LAST_ERRNO
217 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
218 bne- syscall_exit_work
219 cmpld r3,r11
220 ld r5,_CCR(r1)
221 bge- syscall_error
222 .Lsyscall_error_cont:
223 ld r7,_NIP(r1)
224 BEGIN_FTR_SECTION
225 stdcx. r0,0,r1 /* to clear the reservation */
226 END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
227 andi. r6,r8,MSR_PR
228 ld r4,_LINK(r1)
230 beq- 1f
231 ACCOUNT_CPU_USER_EXIT(r11, r12)
232 HMT_MEDIUM_LOW_HAS_PPR
233 ld r13,GPR13(r1) /* only restore r13 if returning to usermode */
234 1: ld r2,GPR2(r1)
235 ld r1,GPR1(r1)
236 mtlr r4
237 mtcr r5
238 mtspr SPRN_SRR0,r7
239 mtspr SPRN_SRR1,r8
240 RFI
241 b . /* prevent speculative execution */
243 syscall_error:
244 oris r5,r5,0x1000 /* Set SO bit in CR */
245 neg r3,r3
246 std r5,_CCR(r1)
247 b .Lsyscall_error_cont
249 /* Traced system call support */
250 syscall_dotrace:
251 bl .save_nvgprs
252 addi r3,r1,STACK_FRAME_OVERHEAD
253 bl .do_syscall_trace_enter
254 /*
255 * Restore argument registers possibly just changed.
256 * We use the return value of do_syscall_trace_enter
257 * for the call number to look up in the table (r0).
258 */
259 mr r0,r3
260 ld r3,GPR3(r1)
261 ld r4,GPR4(r1)
262 ld r5,GPR5(r1)
263 ld r6,GPR6(r1)
264 ld r7,GPR7(r1)
265 ld r8,GPR8(r1)
266 addi r9,r1,STACK_FRAME_OVERHEAD
267 CURRENT_THREAD_INFO(r10, r1)
268 ld r10,TI_FLAGS(r10)
269 b .Lsyscall_dotrace_cont
271 syscall_enosys:
272 li r3,-ENOSYS
273 b syscall_exit
275 syscall_exit_work:
276 #ifdef CONFIG_PPC_BOOK3S
277 mtmsrd r10,1 /* Restore RI */
278 #endif
279 /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
280 If TIF_NOERROR is set, just save r3 as it is. */
282 andi. r0,r9,_TIF_RESTOREALL
283 beq+ 0f
284 REST_NVGPRS(r1)
285 b 2f
286 0: cmpld r3,r11 /* r10 is -LAST_ERRNO */
287 blt+ 1f
288 andi. r0,r9,_TIF_NOERROR
289 bne- 1f
290 ld r5,_CCR(r1)
291 neg r3,r3
292 oris r5,r5,0x1000 /* Set SO bit in CR */
293 std r5,_CCR(r1)
294 1: std r3,GPR3(r1)
295 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
296 beq 4f
298 /* Clear per-syscall TIF flags if any are set. */
300 li r11,_TIF_PERSYSCALL_MASK
301 addi r12,r12,TI_FLAGS
302 3: ldarx r10,0,r12
303 andc r10,r10,r11
304 stdcx. r10,0,r12
305 bne- 3b
306 subi r12,r12,TI_FLAGS
308 4: /* Anything else left to do? */
309 SET_DEFAULT_THREAD_PPR(r3, r10) /* Set thread.ppr = 3 */
310 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
311 beq .ret_from_except_lite
313 /* Re-enable interrupts */
314 #ifdef CONFIG_PPC_BOOK3E
315 wrteei 1
316 #else
317 ld r10,PACAKMSR(r13)
318 ori r10,r10,MSR_EE
319 mtmsrd r10,1
320 #endif /* CONFIG_PPC_BOOK3E */
322 bl .save_nvgprs
323 addi r3,r1,STACK_FRAME_OVERHEAD
324 bl .do_syscall_trace_leave
325 b .ret_from_except
327 /* Save non-volatile GPRs, if not already saved. */
328 _GLOBAL(save_nvgprs)
329 ld r11,_TRAP(r1)
330 andi. r0,r11,1
331 beqlr-
332 SAVE_NVGPRS(r1)
333 clrrdi r0,r11,1
334 std r0,_TRAP(r1)
335 blr
338 /*
339 * The sigsuspend and rt_sigsuspend system calls can call do_signal
340 * and thus put the process into the stopped state where we might
341 * want to examine its user state with ptrace. Therefore we need
342 * to save all the nonvolatile registers (r14 - r31) before calling
343 * the C code. Similarly, fork, vfork and clone need the full
344 * register state on the stack so that it can be copied to the child.
345 */
347 _GLOBAL(ppc_fork)
348 bl .save_nvgprs
349 bl .sys_fork
350 b syscall_exit
352 _GLOBAL(ppc_vfork)
353 bl .save_nvgprs
354 bl .sys_vfork
355 b syscall_exit
357 _GLOBAL(ppc_clone)
358 bl .save_nvgprs
359 bl .sys_clone
360 b syscall_exit
362 _GLOBAL(ppc32_swapcontext)
363 bl .save_nvgprs
364 bl .compat_sys_swapcontext
365 b syscall_exit
367 _GLOBAL(ppc64_swapcontext)
368 bl .save_nvgprs
369 bl .sys_swapcontext
370 b syscall_exit
372 _GLOBAL(ret_from_fork)
373 bl .schedule_tail
374 REST_NVGPRS(r1)
375 li r3,0
376 b syscall_exit
378 _GLOBAL(ret_from_kernel_thread)
379 bl .schedule_tail
380 REST_NVGPRS(r1)
381 ld r14, 0(r14)
382 mtlr r14
383 mr r3,r15
384 blrl
385 li r3,0
386 b syscall_exit
388 .section ".toc","aw"
389 DSCR_DEFAULT:
390 .tc dscr_default[TC],dscr_default
392 .section ".text"
394 /*
395 * This routine switches between two different tasks. The process
396 * state of one is saved on its kernel stack. Then the state
397 * of the other is restored from its kernel stack. The memory
398 * management hardware is updated to the second process's state.
399 * Finally, we can return to the second process, via ret_from_except.
400 * On entry, r3 points to the THREAD for the current task, r4
401 * points to the THREAD for the new task.
402 *
403 * Note: there are two ways to get to the "going out" portion
404 * of this code; either by coming in via the entry (_switch)
405 * or via "fork" which must set up an environment equivalent
406 * to the "_switch" path. If you change this you'll have to change
407 * the fork code also.
408 *
409 * The code which creates the new task context is in 'copy_thread'
410 * in arch/powerpc/kernel/process.c
411 */
412 .align 7
413 _GLOBAL(_switch)
414 mflr r0
415 std r0,16(r1)
416 stdu r1,-SWITCH_FRAME_SIZE(r1)
417 /* r3-r13 are caller saved -- Cort */
418 SAVE_8GPRS(14, r1)
419 SAVE_10GPRS(22, r1)
420 mflr r20 /* Return to switch caller */
421 mfmsr r22
422 li r0, MSR_FP
423 #ifdef CONFIG_VSX
424 BEGIN_FTR_SECTION
425 oris r0,r0,MSR_VSX@h /* Disable VSX */
426 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
427 #endif /* CONFIG_VSX */
428 #ifdef CONFIG_ALTIVEC
429 BEGIN_FTR_SECTION
430 oris r0,r0,MSR_VEC@h /* Disable altivec */
431 mfspr r24,SPRN_VRSAVE /* save vrsave register value */
432 std r24,THREAD_VRSAVE(r3)
433 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
434 #endif /* CONFIG_ALTIVEC */
435 #ifdef CONFIG_PPC64
436 BEGIN_FTR_SECTION
437 mfspr r25,SPRN_DSCR
438 std r25,THREAD_DSCR(r3)
439 END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
440 #endif
441 and. r0,r0,r22
442 beq+ 1f
443 andc r22,r22,r0
444 MTMSRD(r22)
445 isync
446 1: std r20,_NIP(r1)
447 mfcr r23
448 std r23,_CCR(r1)
449 std r1,KSP(r3) /* Set old stack pointer */
451 #ifdef CONFIG_PPC_BOOK3S_64
452 BEGIN_FTR_SECTION
453 /* Event based branch registers */
454 mfspr r0, SPRN_BESCR
455 std r0, THREAD_BESCR(r3)
456 mfspr r0, SPRN_EBBHR
457 std r0, THREAD_EBBHR(r3)
458 mfspr r0, SPRN_EBBRR
459 std r0, THREAD_EBBRR(r3)
460 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
461 #endif
463 #ifdef CONFIG_SMP
464 /* We need a sync somewhere here to make sure that if the
465 * previous task gets rescheduled on another CPU, it sees all
466 * stores it has performed on this one.
467 */
468 sync
469 #endif /* CONFIG_SMP */
471 /*
472 * If we optimise away the clear of the reservation in system
473 * calls because we know the CPU tracks the address of the
474 * reservation, then we need to clear it here to cover the
475 * case that the kernel context switch path has no larx
476 * instructions.
477 */
478 BEGIN_FTR_SECTION
479 ldarx r6,0,r1
480 END_FTR_SECTION_IFSET(CPU_FTR_STCX_CHECKS_ADDRESS)
482 #ifdef CONFIG_PPC_BOOK3S
483 /* Cancel all explict user streams as they will have no use after context
484 * switch and will stop the HW from creating streams itself
485 */
486 DCBT_STOP_ALL_STREAM_IDS(r6)
487 #endif
489 addi r6,r4,-THREAD /* Convert THREAD to 'current' */
490 std r6,PACACURRENT(r13) /* Set new 'current' */
492 ld r8,KSP(r4) /* new stack pointer */
493 #ifdef CONFIG_PPC_BOOK3S
494 BEGIN_FTR_SECTION
495 BEGIN_FTR_SECTION_NESTED(95)
496 clrrdi r6,r8,28 /* get its ESID */
497 clrrdi r9,r1,28 /* get current sp ESID */
498 FTR_SECTION_ELSE_NESTED(95)
499 clrrdi r6,r8,40 /* get its 1T ESID */
500 clrrdi r9,r1,40 /* get current sp 1T ESID */
501 ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_1T_SEGMENT, 95)
502 FTR_SECTION_ELSE
503 b 2f
504 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_SLB)
505 clrldi. r0,r6,2 /* is new ESID c00000000? */
506 cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
507 cror eq,4*cr1+eq,eq
508 beq 2f /* if yes, don't slbie it */
510 /* Bolt in the new stack SLB entry */
511 ld r7,KSP_VSID(r4) /* Get new stack's VSID */
512 oris r0,r6,(SLB_ESID_V)@h
513 ori r0,r0,(SLB_NUM_BOLTED-1)@l
514 BEGIN_FTR_SECTION
515 li r9,MMU_SEGSIZE_1T /* insert B field */
516 oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
517 rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
518 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
520 /* Update the last bolted SLB. No write barriers are needed
521 * here, provided we only update the current CPU's SLB shadow
522 * buffer.
523 */
524 ld r9,PACA_SLBSHADOWPTR(r13)
525 li r12,0
526 std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
527 li r12,SLBSHADOW_STACKVSID
528 STDX_BE r7,r12,r9 /* Save VSID */
529 li r12,SLBSHADOW_STACKESID
530 STDX_BE r0,r12,r9 /* Save ESID */
532 /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
533 * we have 1TB segments, the only CPUs known to have the errata
534 * only support less than 1TB of system memory and we'll never
535 * actually hit this code path.
536 */
538 slbie r6
539 slbie r6 /* Workaround POWER5 < DD2.1 issue */
540 slbmte r7,r0
541 isync
542 2:
543 #endif /* !CONFIG_PPC_BOOK3S */
545 CURRENT_THREAD_INFO(r7, r8) /* base of new stack */
546 /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
547 because we don't need to leave the 288-byte ABI gap at the
548 top of the kernel stack. */
549 addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
551 mr r1,r8 /* start using new stack pointer */
552 std r7,PACAKSAVE(r13)
554 #ifdef CONFIG_PPC_BOOK3S_64
555 BEGIN_FTR_SECTION
556 /* Event based branch registers */
557 ld r0, THREAD_BESCR(r4)
558 mtspr SPRN_BESCR, r0
559 ld r0, THREAD_EBBHR(r4)
560 mtspr SPRN_EBBHR, r0
561 ld r0, THREAD_EBBRR(r4)
562 mtspr SPRN_EBBRR, r0
564 ld r0,THREAD_TAR(r4)
565 mtspr SPRN_TAR,r0
566 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
567 #endif
569 #ifdef CONFIG_ALTIVEC
570 BEGIN_FTR_SECTION
571 ld r0,THREAD_VRSAVE(r4)
572 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
573 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
574 #endif /* CONFIG_ALTIVEC */
575 #ifdef CONFIG_PPC64
576 BEGIN_FTR_SECTION
577 lwz r6,THREAD_DSCR_INHERIT(r4)
578 ld r7,DSCR_DEFAULT@toc(2)
579 ld r0,THREAD_DSCR(r4)
580 cmpwi r6,0
581 bne 1f
582 ld r0,0(r7)
583 1:
584 BEGIN_FTR_SECTION_NESTED(70)
585 mfspr r8, SPRN_FSCR
586 rldimi r8, r6, FSCR_DSCR_LG, (63 - FSCR_DSCR_LG)
587 mtspr SPRN_FSCR, r8
588 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_207S, CPU_FTR_ARCH_207S, 70)
589 cmpd r0,r25
590 beq 2f
591 mtspr SPRN_DSCR,r0
592 2:
593 END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
594 #endif
596 ld r6,_CCR(r1)
597 mtcrf 0xFF,r6
599 /* r3-r13 are destroyed -- Cort */
600 REST_8GPRS(14, r1)
601 REST_10GPRS(22, r1)
603 /* convert old thread to its task_struct for return value */
604 addi r3,r3,-THREAD
605 ld r7,_NIP(r1) /* Return to _switch caller in new task */
606 mtlr r7
607 addi r1,r1,SWITCH_FRAME_SIZE
608 blr
610 .align 7
611 _GLOBAL(ret_from_except)
612 ld r11,_TRAP(r1)
613 andi. r0,r11,1
614 bne .ret_from_except_lite
615 REST_NVGPRS(r1)
617 _GLOBAL(ret_from_except_lite)
618 /*
619 * Disable interrupts so that current_thread_info()->flags
620 * can't change between when we test it and when we return
621 * from the interrupt.
622 */
623 #ifdef CONFIG_PPC_BOOK3E
624 wrteei 0
625 #else
626 ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */
627 mtmsrd r10,1 /* Update machine state */
628 #endif /* CONFIG_PPC_BOOK3E */
630 CURRENT_THREAD_INFO(r9, r1)
631 ld r3,_MSR(r1)
632 #ifdef CONFIG_PPC_BOOK3E
633 ld r10,PACACURRENT(r13)
634 #endif /* CONFIG_PPC_BOOK3E */
635 ld r4,TI_FLAGS(r9)
636 andi. r3,r3,MSR_PR
637 beq resume_kernel
638 #ifdef CONFIG_PPC_BOOK3E
639 lwz r3,(THREAD+THREAD_DBCR0)(r10)
640 #endif /* CONFIG_PPC_BOOK3E */
642 /* Check current_thread_info()->flags */
643 andi. r0,r4,_TIF_USER_WORK_MASK
644 #ifdef CONFIG_PPC_BOOK3E
645 bne 1f
646 /*
647 * Check to see if the dbcr0 register is set up to debug.
648 * Use the internal debug mode bit to do this.
649 */
650 andis. r0,r3,DBCR0_IDM@h
651 beq restore
652 mfmsr r0
653 rlwinm r0,r0,0,~MSR_DE /* Clear MSR.DE */
654 mtmsr r0
655 mtspr SPRN_DBCR0,r3
656 li r10, -1
657 mtspr SPRN_DBSR,r10
658 b restore
659 #else
660 beq restore
661 #endif
662 1: andi. r0,r4,_TIF_NEED_RESCHED
663 beq 2f
664 bl .restore_interrupts
665 SCHEDULE_USER
666 b .ret_from_except_lite
667 2:
668 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
669 andi. r0,r4,_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM
670 bne 3f /* only restore TM if nothing else to do */
671 addi r3,r1,STACK_FRAME_OVERHEAD
672 bl .restore_tm_state
673 b restore
674 3:
675 #endif
676 bl .save_nvgprs
677 bl .restore_interrupts
678 addi r3,r1,STACK_FRAME_OVERHEAD
679 bl .do_notify_resume
680 b .ret_from_except
682 resume_kernel:
683 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
684 andis. r8,r4,_TIF_EMULATE_STACK_STORE@h
685 beq+ 1f
687 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
689 lwz r3,GPR1(r1)
690 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
691 mr r4,r1 /* src: current exception frame */
692 mr r1,r3 /* Reroute the trampoline frame to r1 */
694 /* Copy from the original to the trampoline. */
695 li r5,INT_FRAME_SIZE/8 /* size: INT_FRAME_SIZE */
696 li r6,0 /* start offset: 0 */
697 mtctr r5
698 2: ldx r0,r6,r4
699 stdx r0,r6,r3
700 addi r6,r6,8
701 bdnz 2b
703 /* Do real store operation to complete stwu */
704 lwz r5,GPR1(r1)
705 std r8,0(r5)
707 /* Clear _TIF_EMULATE_STACK_STORE flag */
708 lis r11,_TIF_EMULATE_STACK_STORE@h
709 addi r5,r9,TI_FLAGS
710 0: ldarx r4,0,r5
711 andc r4,r4,r11
712 stdcx. r4,0,r5
713 bne- 0b
714 1:
716 #ifdef CONFIG_PREEMPT
717 /* Check if we need to preempt */
718 andi. r0,r4,_TIF_NEED_RESCHED
719 beq+ restore
720 /* Check that preempt_count() == 0 and interrupts are enabled */
721 lwz r8,TI_PREEMPT(r9)
722 cmpwi cr1,r8,0
723 ld r0,SOFTE(r1)
724 cmpdi r0,0
725 crandc eq,cr1*4+eq,eq
726 bne restore
728 /*
729 * Here we are preempting the current task. We want to make
730 * sure we are soft-disabled first and reconcile irq state.
731 */
732 RECONCILE_IRQ_STATE(r3,r4)
733 1: bl .preempt_schedule_irq
735 /* Re-test flags and eventually loop */
736 CURRENT_THREAD_INFO(r9, r1)
737 ld r4,TI_FLAGS(r9)
738 andi. r0,r4,_TIF_NEED_RESCHED
739 bne 1b
741 /*
742 * arch_local_irq_restore() from preempt_schedule_irq above may
743 * enable hard interrupt but we really should disable interrupts
744 * when we return from the interrupt, and so that we don't get
745 * interrupted after loading SRR0/1.
746 */
747 #ifdef CONFIG_PPC_BOOK3E
748 wrteei 0
749 #else
750 ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */
751 mtmsrd r10,1 /* Update machine state */
752 #endif /* CONFIG_PPC_BOOK3E */
753 #endif /* CONFIG_PREEMPT */
755 .globl fast_exc_return_irq
756 fast_exc_return_irq:
757 restore:
758 /*
759 * This is the main kernel exit path. First we check if we
760 * are about to re-enable interrupts
761 */
762 ld r5,SOFTE(r1)
763 lbz r6,PACASOFTIRQEN(r13)
764 cmpwi cr0,r5,0
765 beq restore_irq_off
767 /* We are enabling, were we already enabled ? Yes, just return */
768 cmpwi cr0,r6,1
769 beq cr0,do_restore
771 /*
772 * We are about to soft-enable interrupts (we are hard disabled
773 * at this point). We check if there's anything that needs to
774 * be replayed first.
775 */
776 lbz r0,PACAIRQHAPPENED(r13)
777 cmpwi cr0,r0,0
778 bne- restore_check_irq_replay
780 /*
781 * Get here when nothing happened while soft-disabled, just
782 * soft-enable and move-on. We will hard-enable as a side
783 * effect of rfi
784 */
785 restore_no_replay:
786 TRACE_ENABLE_INTS
787 li r0,1
788 stb r0,PACASOFTIRQEN(r13);
790 /*
791 * Final return path. BookE is handled in a different file
792 */
793 do_restore:
794 #ifdef CONFIG_PPC_BOOK3E
795 b .exception_return_book3e
796 #else
797 /*
798 * Clear the reservation. If we know the CPU tracks the address of
799 * the reservation then we can potentially save some cycles and use
800 * a larx. On POWER6 and POWER7 this is significantly faster.
801 */
802 BEGIN_FTR_SECTION
803 stdcx. r0,0,r1 /* to clear the reservation */
804 FTR_SECTION_ELSE
805 ldarx r4,0,r1
806 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
808 /*
809 * Some code path such as load_up_fpu or altivec return directly
810 * here. They run entirely hard disabled and do not alter the
811 * interrupt state. They also don't use lwarx/stwcx. and thus
812 * are known not to leave dangling reservations.
813 */
814 .globl fast_exception_return
815 fast_exception_return:
816 ld r3,_MSR(r1)
817 ld r4,_CTR(r1)
818 ld r0,_LINK(r1)
819 mtctr r4
820 mtlr r0
821 ld r4,_XER(r1)
822 mtspr SPRN_XER,r4
824 REST_8GPRS(5, r1)
826 andi. r0,r3,MSR_RI
827 beq- unrecov_restore
829 /* Load PPR from thread struct before we clear MSR:RI */
830 BEGIN_FTR_SECTION
831 ld r2,PACACURRENT(r13)
832 ld r2,TASKTHREADPPR(r2)
833 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
835 /*
836 * Clear RI before restoring r13. If we are returning to
837 * userspace and we take an exception after restoring r13,
838 * we end up corrupting the userspace r13 value.
839 */
840 ld r4,PACAKMSR(r13) /* Get kernel MSR without EE */
841 andc r4,r4,r0 /* r0 contains MSR_RI here */
842 mtmsrd r4,1
844 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
845 /* TM debug */
846 std r3, PACATMSCRATCH(r13) /* Stash returned-to MSR */
847 #endif
848 /*
849 * r13 is our per cpu area, only restore it if we are returning to
850 * userspace the value stored in the stack frame may belong to
851 * another CPU.
852 */
853 andi. r0,r3,MSR_PR
854 beq 1f
855 BEGIN_FTR_SECTION
856 mtspr SPRN_PPR,r2 /* Restore PPR */
857 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
858 ACCOUNT_CPU_USER_EXIT(r2, r4)
859 REST_GPR(13, r1)
860 1:
861 mtspr SPRN_SRR1,r3
863 ld r2,_CCR(r1)
864 mtcrf 0xFF,r2
865 ld r2,_NIP(r1)
866 mtspr SPRN_SRR0,r2
868 ld r0,GPR0(r1)
869 ld r2,GPR2(r1)
870 ld r3,GPR3(r1)
871 ld r4,GPR4(r1)
872 ld r1,GPR1(r1)
874 rfid
875 b . /* prevent speculative execution */
877 #endif /* CONFIG_PPC_BOOK3E */
879 /*
880 * We are returning to a context with interrupts soft disabled.
881 *
882 * However, we may also about to hard enable, so we need to
883 * make sure that in this case, we also clear PACA_IRQ_HARD_DIS
884 * or that bit can get out of sync and bad things will happen
885 */
886 restore_irq_off:
887 ld r3,_MSR(r1)
888 lbz r7,PACAIRQHAPPENED(r13)
889 andi. r0,r3,MSR_EE
890 beq 1f
891 rlwinm r7,r7,0,~PACA_IRQ_HARD_DIS
892 stb r7,PACAIRQHAPPENED(r13)
893 1: li r0,0
894 stb r0,PACASOFTIRQEN(r13);
895 TRACE_DISABLE_INTS
896 b do_restore
898 /*
899 * Something did happen, check if a re-emit is needed
900 * (this also clears paca->irq_happened)
901 */
902 restore_check_irq_replay:
903 /* XXX: We could implement a fast path here where we check
904 * for irq_happened being just 0x01, in which case we can
905 * clear it and return. That means that we would potentially
906 * miss a decrementer having wrapped all the way around.
907 *
908 * Still, this might be useful for things like hash_page
909 */
910 bl .__check_irq_replay
911 cmpwi cr0,r3,0
912 beq restore_no_replay
914 /*
915 * We need to re-emit an interrupt. We do so by re-using our
916 * existing exception frame. We first change the trap value,
917 * but we need to ensure we preserve the low nibble of it
918 */
919 ld r4,_TRAP(r1)
920 clrldi r4,r4,60
921 or r4,r4,r3
922 std r4,_TRAP(r1)
924 /*
925 * Then find the right handler and call it. Interrupts are
926 * still soft-disabled and we keep them that way.
927 */
928 cmpwi cr0,r3,0x500
929 bne 1f
930 addi r3,r1,STACK_FRAME_OVERHEAD;
931 bl .do_IRQ
932 b .ret_from_except
933 1: cmpwi cr0,r3,0x900
934 bne 1f
935 addi r3,r1,STACK_FRAME_OVERHEAD;
936 bl .timer_interrupt
937 b .ret_from_except
938 #ifdef CONFIG_PPC_DOORBELL
939 1:
940 #ifdef CONFIG_PPC_BOOK3E
941 cmpwi cr0,r3,0x280
942 #else
943 BEGIN_FTR_SECTION
944 cmpwi cr0,r3,0xe80
945 FTR_SECTION_ELSE
946 cmpwi cr0,r3,0xa00
947 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
948 #endif /* CONFIG_PPC_BOOK3E */
949 bne 1f
950 addi r3,r1,STACK_FRAME_OVERHEAD;
951 bl .doorbell_exception
952 b .ret_from_except
953 #endif /* CONFIG_PPC_DOORBELL */
954 1: b .ret_from_except /* What else to do here ? */
956 unrecov_restore:
957 addi r3,r1,STACK_FRAME_OVERHEAD
958 bl .unrecoverable_exception
959 b unrecov_restore
961 #ifdef CONFIG_PPC_RTAS
962 /*
963 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
964 * called with the MMU off.
965 *
966 * In addition, we need to be in 32b mode, at least for now.
967 *
968 * Note: r3 is an input parameter to rtas, so don't trash it...
969 */
970 _GLOBAL(enter_rtas)
971 mflr r0
972 std r0,16(r1)
973 stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */
975 /* Because RTAS is running in 32b mode, it clobbers the high order half
976 * of all registers that it saves. We therefore save those registers
977 * RTAS might touch to the stack. (r0, r3-r13 are caller saved)
978 */
979 SAVE_GPR(2, r1) /* Save the TOC */
980 SAVE_GPR(13, r1) /* Save paca */
981 SAVE_8GPRS(14, r1) /* Save the non-volatiles */
982 SAVE_10GPRS(22, r1) /* ditto */
984 mfcr r4
985 std r4,_CCR(r1)
986 mfctr r5
987 std r5,_CTR(r1)
988 mfspr r6,SPRN_XER
989 std r6,_XER(r1)
990 mfdar r7
991 std r7,_DAR(r1)
992 mfdsisr r8
993 std r8,_DSISR(r1)
995 /* Temporary workaround to clear CR until RTAS can be modified to
996 * ignore all bits.
997 */
998 li r0,0
999 mtcr r0
1001 #ifdef CONFIG_BUG
1002 /* There is no way it is acceptable to get here with interrupts enabled,
1003 * check it with the asm equivalent of WARN_ON
1004 */
1005 lbz r0,PACASOFTIRQEN(r13)
1006 1: tdnei r0,0
1007 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
1008 #endif
1010 /* Hard-disable interrupts */
1011 mfmsr r6
1012 rldicl r7,r6,48,1
1013 rotldi r7,r7,16
1014 mtmsrd r7,1
1016 /* Unfortunately, the stack pointer and the MSR are also clobbered,
1017 * so they are saved in the PACA which allows us to restore
1018 * our original state after RTAS returns.
1019 */
1020 std r1,PACAR1(r13)
1021 std r6,PACASAVEDMSR(r13)
1023 /* Setup our real return addr */
1024 LOAD_REG_ADDR(r4,.rtas_return_loc)
1025 clrldi r4,r4,2 /* convert to realmode address */
1026 mtlr r4
1028 li r0,0
1029 ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
1030 andc r0,r6,r0
1032 li r9,1
1033 rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
1034 ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI|MSR_LE
1035 andc r6,r0,r9
1036 sync /* disable interrupts so SRR0/1 */
1037 mtmsrd r0 /* don't get trashed */
1039 LOAD_REG_ADDR(r4, rtas)
1040 ld r5,RTASENTRY(r4) /* get the rtas->entry value */
1041 ld r4,RTASBASE(r4) /* get the rtas->base value */
1043 mtspr SPRN_SRR0,r5
1044 mtspr SPRN_SRR1,r6
1045 rfid
1046 b . /* prevent speculative execution */
1048 _STATIC(rtas_return_loc)
1049 FIXUP_ENDIAN
1051 /* relocation is off at this point */
1052 GET_PACA(r4)
1053 clrldi r4,r4,2 /* convert to realmode address */
1055 bcl 20,31,$+4
1056 0: mflr r3
1057 ld r3,(1f-0b)(r3) /* get &.rtas_restore_regs */
1059 mfmsr r6
1060 li r0,MSR_RI
1061 andc r6,r6,r0
1062 sync
1063 mtmsrd r6
1065 ld r1,PACAR1(r4) /* Restore our SP */
1066 ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
1068 mtspr SPRN_SRR0,r3
1069 mtspr SPRN_SRR1,r4
1070 rfid
1071 b . /* prevent speculative execution */
1073 .align 3
1074 1: .llong .rtas_restore_regs
1076 _STATIC(rtas_restore_regs)
1077 /* relocation is on at this point */
1078 REST_GPR(2, r1) /* Restore the TOC */
1079 REST_GPR(13, r1) /* Restore paca */
1080 REST_8GPRS(14, r1) /* Restore the non-volatiles */
1081 REST_10GPRS(22, r1) /* ditto */
1083 GET_PACA(r13)
1085 ld r4,_CCR(r1)
1086 mtcr r4
1087 ld r5,_CTR(r1)
1088 mtctr r5
1089 ld r6,_XER(r1)
1090 mtspr SPRN_XER,r6
1091 ld r7,_DAR(r1)
1092 mtdar r7
1093 ld r8,_DSISR(r1)
1094 mtdsisr r8
1096 addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */
1097 ld r0,16(r1) /* get return address */
1099 mtlr r0
1100 blr /* return to caller */
1102 #endif /* CONFIG_PPC_RTAS */
1104 _GLOBAL(enter_prom)
1105 mflr r0
1106 std r0,16(r1)
1107 stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
1109 /* Because PROM is running in 32b mode, it clobbers the high order half
1110 * of all registers that it saves. We therefore save those registers
1111 * PROM might touch to the stack. (r0, r3-r13 are caller saved)
1112 */
1113 SAVE_GPR(2, r1)
1114 SAVE_GPR(13, r1)
1115 SAVE_8GPRS(14, r1)
1116 SAVE_10GPRS(22, r1)
1117 mfcr r10
1118 mfmsr r11
1119 std r10,_CCR(r1)
1120 std r11,_MSR(r1)
1122 /* Put PROM address in SRR0 */
1123 mtsrr0 r4
1125 /* Setup our trampoline return addr in LR */
1126 bcl 20,31,$+4
1127 0: mflr r4
1128 addi r4,r4,(1f - 0b)
1129 mtlr r4
1131 /* Prepare a 32-bit mode big endian MSR
1132 */
1133 #ifdef CONFIG_PPC_BOOK3E
1134 rlwinm r11,r11,0,1,31
1135 mtsrr1 r11
1136 rfi
1137 #else /* CONFIG_PPC_BOOK3E */
1138 LOAD_REG_IMMEDIATE(r12, MSR_SF | MSR_ISF | MSR_LE)
1139 andc r11,r11,r12
1140 mtsrr1 r11
1141 rfid
1142 #endif /* CONFIG_PPC_BOOK3E */
1144 1: /* Return from OF */
1145 FIXUP_ENDIAN
1147 /* Just make sure that r1 top 32 bits didn't get
1148 * corrupt by OF
1149 */
1150 rldicl r1,r1,0,32
1152 /* Restore the MSR (back to 64 bits) */
1153 ld r0,_MSR(r1)
1154 MTMSRD(r0)
1155 isync
1157 /* Restore other registers */
1158 REST_GPR(2, r1)
1159 REST_GPR(13, r1)
1160 REST_8GPRS(14, r1)
1161 REST_10GPRS(22, r1)
1162 ld r4,_CCR(r1)
1163 mtcr r4
1165 addi r1,r1,PROM_FRAME_SIZE
1166 ld r0,16(r1)
1167 mtlr r0
1168 blr
1170 #ifdef CONFIG_FUNCTION_TRACER
1171 #ifdef CONFIG_DYNAMIC_FTRACE
1172 _GLOBAL(mcount)
1173 _GLOBAL(_mcount)
1174 blr
1176 _GLOBAL(ftrace_caller)
1177 /* Taken from output of objdump from lib64/glibc */
1178 mflr r3
1179 ld r11, 0(r1)
1180 stdu r1, -112(r1)
1181 std r3, 128(r1)
1182 ld r4, 16(r11)
1183 subi r3, r3, MCOUNT_INSN_SIZE
1184 .globl ftrace_call
1185 ftrace_call:
1186 bl ftrace_stub
1187 nop
1188 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1189 .globl ftrace_graph_call
1190 ftrace_graph_call:
1191 b ftrace_graph_stub
1192 _GLOBAL(ftrace_graph_stub)
1193 #endif
1194 ld r0, 128(r1)
1195 mtlr r0
1196 addi r1, r1, 112
1197 _GLOBAL(ftrace_stub)
1198 blr
1199 #else
1200 _GLOBAL(mcount)
1201 blr
1203 _GLOBAL(_mcount)
1204 /* Taken from output of objdump from lib64/glibc */
1205 mflr r3
1206 ld r11, 0(r1)
1207 stdu r1, -112(r1)
1208 std r3, 128(r1)
1209 ld r4, 16(r11)
1211 subi r3, r3, MCOUNT_INSN_SIZE
1212 LOAD_REG_ADDR(r5,ftrace_trace_function)
1213 ld r5,0(r5)
1214 ld r5,0(r5)
1215 mtctr r5
1216 bctrl
1217 nop
1220 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1221 b ftrace_graph_caller
1222 #endif
1223 ld r0, 128(r1)
1224 mtlr r0
1225 addi r1, r1, 112
1226 _GLOBAL(ftrace_stub)
1227 blr
1229 #endif /* CONFIG_DYNAMIC_FTRACE */
1231 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1232 _GLOBAL(ftrace_graph_caller)
1233 /* load r4 with local address */
1234 ld r4, 128(r1)
1235 subi r4, r4, MCOUNT_INSN_SIZE
1237 /* get the parent address */
1238 ld r11, 112(r1)
1239 addi r3, r11, 16
1241 bl .prepare_ftrace_return
1242 nop
1244 ld r0, 128(r1)
1245 mtlr r0
1246 addi r1, r1, 112
1247 blr
1249 _GLOBAL(return_to_handler)
1250 /* need to save return values */
1251 std r4, -24(r1)
1252 std r3, -16(r1)
1253 std r31, -8(r1)
1254 mr r31, r1
1255 stdu r1, -112(r1)
1257 bl .ftrace_return_to_handler
1258 nop
1260 /* return value has real return address */
1261 mtlr r3
1263 ld r1, 0(r1)
1264 ld r4, -24(r1)
1265 ld r3, -16(r1)
1266 ld r31, -8(r1)
1268 /* Jump back to real return address */
1269 blr
1271 _GLOBAL(mod_return_to_handler)
1272 /* need to save return values */
1273 std r4, -32(r1)
1274 std r3, -24(r1)
1275 /* save TOC */
1276 std r2, -16(r1)
1277 std r31, -8(r1)
1278 mr r31, r1
1279 stdu r1, -112(r1)
1281 /*
1282 * We are in a module using the module's TOC.
1283 * Switch to our TOC to run inside the core kernel.
1284 */
1285 ld r2, PACATOC(r13)
1287 bl .ftrace_return_to_handler
1288 nop
1290 /* return value has real return address */
1291 mtlr r3
1293 ld r1, 0(r1)
1294 ld r4, -32(r1)
1295 ld r3, -24(r1)
1296 ld r2, -16(r1)
1297 ld r31, -8(r1)
1299 /* Jump back to real return address */
1300 blr
1301 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
1302 #endif /* CONFIG_FUNCTION_TRACER */