| blob | b497188a94a1e2f67b71460189f9f225f7f5e1a3 |
1 /*
2 * Kernel execution entry point code.
3 *
4 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
5 * Initial PowerPC version.
6 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Rewritten for PReP
8 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
9 * Low-level exception handers, MMU support, and rewrite.
10 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
11 * PowerPC 8xx modifications.
12 * Copyright (c) 1998-1999 TiVo, Inc.
13 * PowerPC 403GCX modifications.
14 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
15 * PowerPC 403GCX/405GP modifications.
16 * Copyright 2000 MontaVista Software Inc.
17 * PPC405 modifications
18 * PowerPC 403GCX/405GP modifications.
19 * Author: MontaVista Software, Inc.
20 * frank_rowand@mvista.com or source@mvista.com
21 * debbie_chu@mvista.com
22 * Copyright 2002-2004 MontaVista Software, Inc.
23 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
24 * Copyright 2004 Freescale Semiconductor, Inc
25 * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
26 *
27 * This program is free software; you can redistribute it and/or modify it
28 * under the terms of the GNU General Public License as published by the
29 * Free Software Foundation; either version 2 of the License, or (at your
30 * option) any later version.
31 */
33 #include <linux/init.h>
34 #include <linux/threads.h>
35 #include <asm/processor.h>
36 #include <asm/page.h>
37 #include <asm/mmu.h>
38 #include <asm/pgtable.h>
39 #include <asm/cputable.h>
40 #include <asm/thread_info.h>
41 #include <asm/ppc_asm.h>
42 #include <asm/asm-offsets.h>
43 #include <asm/cache.h>
44 #include <asm/ptrace.h>
45 #include "head_booke.h"
47 /* As with the other PowerPC ports, it is expected that when code
48 * execution begins here, the following registers contain valid, yet
49 * optional, information:
50 *
51 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
52 * r4 - Starting address of the init RAM disk
53 * r5 - Ending address of the init RAM disk
54 * r6 - Start of kernel command line string (e.g. "mem=128")
55 * r7 - End of kernel command line string
56 *
57 */
58 __HEAD
59 _ENTRY(_stext);
60 _ENTRY(_start);
61 /*
62 * Reserve a word at a fixed location to store the address
63 * of abatron_pteptrs
64 */
65 nop
67 /* Translate device tree address to physical, save in r30/r31 */
68 bl get_phys_addr
69 mr r30,r3
70 mr r31,r4
72 li r25,0 /* phys kernel start (low) */
73 li r24,0 /* CPU number */
74 li r23,0 /* phys kernel start (high) */
76 #ifdef CONFIG_RELOCATABLE
77 LOAD_REG_ADDR_PIC(r3, _stext) /* Get our current runtime base */
79 /* Translate _stext address to physical, save in r23/r25 */
80 bl get_phys_addr
81 mr r23,r3
82 mr r25,r4
84 bl 0f
85 0: mflr r8
86 addis r3,r8,(is_second_reloc - 0b)@ha
87 lwz r19,(is_second_reloc - 0b)@l(r3)
89 /* Check if this is the second relocation. */
90 cmpwi r19,1
91 bne 1f
93 /*
94 * For the second relocation, we already get the real memstart_addr
95 * from device tree. So we will map PAGE_OFFSET to memstart_addr,
96 * then the virtual address of start kernel should be:
97 * PAGE_OFFSET + (kernstart_addr - memstart_addr)
98 * Since the offset between kernstart_addr and memstart_addr should
99 * never be beyond 1G, so we can just use the lower 32bit of them
100 * for the calculation.
101 */
102 lis r3,PAGE_OFFSET@h
104 addis r4,r8,(kernstart_addr - 0b)@ha
105 addi r4,r4,(kernstart_addr - 0b)@l
106 lwz r5,4(r4)
108 addis r6,r8,(memstart_addr - 0b)@ha
109 addi r6,r6,(memstart_addr - 0b)@l
110 lwz r7,4(r6)
112 subf r5,r7,r5
113 add r3,r3,r5
114 b 2f
116 1:
117 /*
118 * We have the runtime (virutal) address of our base.
119 * We calculate our shift of offset from a 64M page.
120 * We could map the 64M page we belong to at PAGE_OFFSET and
121 * get going from there.
122 */
123 lis r4,KERNELBASE@h
124 ori r4,r4,KERNELBASE@l
125 rlwinm r6,r25,0,0x3ffffff /* r6 = PHYS_START % 64M */
126 rlwinm r5,r4,0,0x3ffffff /* r5 = KERNELBASE % 64M */
127 subf r3,r5,r6 /* r3 = r6 - r5 */
128 add r3,r4,r3 /* Required Virtual Address */
130 2: bl relocate
132 /*
133 * For the second relocation, we already set the right tlb entries
134 * for the kernel space, so skip the code in fsl_booke_entry_mapping.S
135 */
136 cmpwi r19,1
137 beq set_ivor
138 #endif
140 /* We try to not make any assumptions about how the boot loader
141 * setup or used the TLBs. We invalidate all mappings from the
142 * boot loader and load a single entry in TLB1[0] to map the
143 * first 64M of kernel memory. Any boot info passed from the
144 * bootloader needs to live in this first 64M.
145 *
146 * Requirement on bootloader:
147 * - The page we're executing in needs to reside in TLB1 and
148 * have IPROT=1. If not an invalidate broadcast could
149 * evict the entry we're currently executing in.
150 *
151 * r3 = Index of TLB1 were executing in
152 * r4 = Current MSR[IS]
153 * r5 = Index of TLB1 temp mapping
154 *
155 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
156 * if needed
157 */
159 _ENTRY(__early_start)
161 #define ENTRY_MAPPING_BOOT_SETUP
162 #include "fsl_booke_entry_mapping.S"
163 #undef ENTRY_MAPPING_BOOT_SETUP
165 set_ivor:
166 /* Establish the interrupt vector offsets */
167 SET_IVOR(0, CriticalInput);
168 SET_IVOR(1, MachineCheck);
169 SET_IVOR(2, DataStorage);
170 SET_IVOR(3, InstructionStorage);
171 SET_IVOR(4, ExternalInput);
172 SET_IVOR(5, Alignment);
173 SET_IVOR(6, Program);
174 SET_IVOR(7, FloatingPointUnavailable);
175 SET_IVOR(8, SystemCall);
176 SET_IVOR(9, AuxillaryProcessorUnavailable);
177 SET_IVOR(10, Decrementer);
178 SET_IVOR(11, FixedIntervalTimer);
179 SET_IVOR(12, WatchdogTimer);
180 SET_IVOR(13, DataTLBError);
181 SET_IVOR(14, InstructionTLBError);
182 SET_IVOR(15, DebugCrit);
184 /* Establish the interrupt vector base */
185 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
186 mtspr SPRN_IVPR,r4
188 /* Setup the defaults for TLB entries */
189 li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
190 #ifdef CONFIG_E200
191 oris r2,r2,MAS4_TLBSELD(1)@h
192 #endif
193 mtspr SPRN_MAS4, r2
195 #if 0
196 /* Enable DOZE */
197 mfspr r2,SPRN_HID0
198 oris r2,r2,HID0_DOZE@h
199 mtspr SPRN_HID0, r2
200 #endif
202 #if !defined(CONFIG_BDI_SWITCH)
203 /*
204 * The Abatron BDI JTAG debugger does not tolerate others
205 * mucking with the debug registers.
206 */
207 lis r2,DBCR0_IDM@h
208 mtspr SPRN_DBCR0,r2
209 isync
210 /* clear any residual debug events */
211 li r2,-1
212 mtspr SPRN_DBSR,r2
213 #endif
215 #ifdef CONFIG_SMP
216 /* Check to see if we're the second processor, and jump
217 * to the secondary_start code if so
218 */
219 LOAD_REG_ADDR_PIC(r24, boot_cpuid)
220 lwz r24, 0(r24)
221 cmpwi r24, -1
222 mfspr r24,SPRN_PIR
223 bne __secondary_start
224 #endif
226 /*
227 * This is where the main kernel code starts.
228 */
230 /* ptr to current */
231 lis r2,init_task@h
232 ori r2,r2,init_task@l
234 /* ptr to current thread */
235 addi r4,r2,THREAD /* init task's THREAD */
236 mtspr SPRN_SPRG_THREAD,r4
238 /* stack */
239 lis r1,init_thread_union@h
240 ori r1,r1,init_thread_union@l
241 li r0,0
242 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
244 CURRENT_THREAD_INFO(r22, r1)
245 stw r24, TI_CPU(r22)
247 bl early_init
249 #ifdef CONFIG_RELOCATABLE
250 mr r3,r30
251 mr r4,r31
252 #ifdef CONFIG_PHYS_64BIT
253 mr r5,r23
254 mr r6,r25
255 #else
256 mr r5,r25
257 #endif
258 bl relocate_init
259 #endif
261 #ifdef CONFIG_DYNAMIC_MEMSTART
262 lis r3,kernstart_addr@ha
263 la r3,kernstart_addr@l(r3)
264 #ifdef CONFIG_PHYS_64BIT
265 stw r23,0(r3)
266 stw r25,4(r3)
267 #else
268 stw r25,0(r3)
269 #endif
270 #endif
272 /*
273 * Decide what sort of machine this is and initialize the MMU.
274 */
275 mr r3,r30
276 mr r4,r31
277 bl machine_init
278 bl MMU_init
280 /* Setup PTE pointers for the Abatron bdiGDB */
281 lis r6, swapper_pg_dir@h
282 ori r6, r6, swapper_pg_dir@l
283 lis r5, abatron_pteptrs@h
284 ori r5, r5, abatron_pteptrs@l
285 lis r4, KERNELBASE@h
286 ori r4, r4, KERNELBASE@l
287 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
288 stw r6, 0(r5)
290 /* Let's move on */
291 lis r4,start_kernel@h
292 ori r4,r4,start_kernel@l
293 lis r3,MSR_KERNEL@h
294 ori r3,r3,MSR_KERNEL@l
295 mtspr SPRN_SRR0,r4
296 mtspr SPRN_SRR1,r3
297 rfi /* change context and jump to start_kernel */
299 /* Macros to hide the PTE size differences
300 *
301 * FIND_PTE -- walks the page tables given EA & pgdir pointer
302 * r10 -- EA of fault
303 * r11 -- PGDIR pointer
304 * r12 -- free
305 * label 2: is the bailout case
306 *
307 * if we find the pte (fall through):
308 * r11 is low pte word
309 * r12 is pointer to the pte
310 * r10 is the pshift from the PGD, if we're a hugepage
311 */
312 #ifdef CONFIG_PTE_64BIT
313 #ifdef CONFIG_HUGETLB_PAGE
314 #define FIND_PTE \
315 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
316 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
317 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
318 blt 1000f; /* Normal non-huge page */ \
319 beq 2f; /* Bail if no table */ \
320 oris r11, r11, PD_HUGE@h; /* Put back address bit */ \
321 andi. r10, r11, HUGEPD_SHIFT_MASK@l; /* extract size field */ \
322 xor r12, r10, r11; /* drop size bits from pointer */ \
323 b 1001f; \
324 1000: rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
325 li r10, 0; /* clear r10 */ \
326 1001: lwz r11, 4(r12); /* Get pte entry */
327 #else
328 #define FIND_PTE \
329 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
330 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
331 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
332 beq 2f; /* Bail if no table */ \
333 rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
334 lwz r11, 4(r12); /* Get pte entry */
335 #endif /* HUGEPAGE */
336 #else /* !PTE_64BIT */
337 #define FIND_PTE \
338 rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
339 lwz r11, 0(r11); /* Get L1 entry */ \
340 rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
341 beq 2f; /* Bail if no table */ \
342 rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \
343 lwz r11, 0(r12); /* Get Linux PTE */
344 #endif
346 /*
347 * Interrupt vector entry code
348 *
349 * The Book E MMUs are always on so we don't need to handle
350 * interrupts in real mode as with previous PPC processors. In
351 * this case we handle interrupts in the kernel virtual address
352 * space.
353 *
354 * Interrupt vectors are dynamically placed relative to the
355 * interrupt prefix as determined by the address of interrupt_base.
356 * The interrupt vectors offsets are programmed using the labels
357 * for each interrupt vector entry.
358 *
359 * Interrupt vectors must be aligned on a 16 byte boundary.
360 * We align on a 32 byte cache line boundary for good measure.
361 */
363 interrupt_base:
364 /* Critical Input Interrupt */
365 CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception)
367 /* Machine Check Interrupt */
368 #ifdef CONFIG_E200
369 /* no RFMCI, MCSRRs on E200 */
370 CRITICAL_EXCEPTION(0x0200, MACHINE_CHECK, MachineCheck, \
371 machine_check_exception)
372 #else
373 MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
374 #endif
376 /* Data Storage Interrupt */
377 START_EXCEPTION(DataStorage)
378 NORMAL_EXCEPTION_PROLOG(DATA_STORAGE)
379 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
380 stw r5,_ESR(r11)
381 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
382 andis. r10,r5,(ESR_ILK|ESR_DLK)@h
383 bne 1f
384 EXC_XFER_LITE(0x0300, handle_page_fault)
385 1:
386 addi r3,r1,STACK_FRAME_OVERHEAD
387 EXC_XFER_EE_LITE(0x0300, CacheLockingException)
389 /* Instruction Storage Interrupt */
390 INSTRUCTION_STORAGE_EXCEPTION
392 /* External Input Interrupt */
393 EXCEPTION(0x0500, EXTERNAL, ExternalInput, do_IRQ, EXC_XFER_LITE)
395 /* Alignment Interrupt */
396 ALIGNMENT_EXCEPTION
398 /* Program Interrupt */
399 PROGRAM_EXCEPTION
401 /* Floating Point Unavailable Interrupt */
402 #ifdef CONFIG_PPC_FPU
403 FP_UNAVAILABLE_EXCEPTION
404 #else
405 #ifdef CONFIG_E200
406 /* E200 treats 'normal' floating point instructions as FP Unavail exception */
407 EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
408 program_check_exception, EXC_XFER_EE)
409 #else
410 EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
411 unknown_exception, EXC_XFER_EE)
412 #endif
413 #endif
415 /* System Call Interrupt */
416 START_EXCEPTION(SystemCall)
417 NORMAL_EXCEPTION_PROLOG(SYSCALL)
418 EXC_XFER_EE_LITE(0x0c00, DoSyscall)
420 /* Auxiliary Processor Unavailable Interrupt */
421 EXCEPTION(0x2900, AP_UNAVAIL, AuxillaryProcessorUnavailable, \
422 unknown_exception, EXC_XFER_EE)
424 /* Decrementer Interrupt */
425 DECREMENTER_EXCEPTION
427 /* Fixed Internal Timer Interrupt */
428 /* TODO: Add FIT support */
429 EXCEPTION(0x3100, FIT, FixedIntervalTimer, \
430 unknown_exception, EXC_XFER_EE)
432 /* Watchdog Timer Interrupt */
433 #ifdef CONFIG_BOOKE_WDT
434 CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, WatchdogException)
435 #else
436 CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, unknown_exception)
437 #endif
439 /* Data TLB Error Interrupt */
440 START_EXCEPTION(DataTLBError)
441 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
442 mfspr r10, SPRN_SPRG_THREAD
443 stw r11, THREAD_NORMSAVE(0)(r10)
444 #ifdef CONFIG_KVM_BOOKE_HV
445 BEGIN_FTR_SECTION
446 mfspr r11, SPRN_SRR1
447 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
448 #endif
449 stw r12, THREAD_NORMSAVE(1)(r10)
450 stw r13, THREAD_NORMSAVE(2)(r10)
451 mfcr r13
452 stw r13, THREAD_NORMSAVE(3)(r10)
453 DO_KVM BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1
454 mfspr r10, SPRN_DEAR /* Get faulting address */
456 /* If we are faulting a kernel address, we have to use the
457 * kernel page tables.
458 */
459 lis r11, PAGE_OFFSET@h
460 cmplw 5, r10, r11
461 blt 5, 3f
462 lis r11, swapper_pg_dir@h
463 ori r11, r11, swapper_pg_dir@l
465 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
466 rlwinm r12,r12,0,16,1
467 mtspr SPRN_MAS1,r12
469 b 4f
471 /* Get the PGD for the current thread */
472 3:
473 mfspr r11,SPRN_SPRG_THREAD
474 lwz r11,PGDIR(r11)
476 4:
477 /* Mask of required permission bits. Note that while we
478 * do copy ESR:ST to _PAGE_RW position as trying to write
479 * to an RO page is pretty common, we don't do it with
480 * _PAGE_DIRTY. We could do it, but it's a fairly rare
481 * event so I'd rather take the overhead when it happens
482 * rather than adding an instruction here. We should measure
483 * whether the whole thing is worth it in the first place
484 * as we could avoid loading SPRN_ESR completely in the first
485 * place...
486 *
487 * TODO: Is it worth doing that mfspr & rlwimi in the first
488 * place or can we save a couple of instructions here ?
489 */
490 mfspr r12,SPRN_ESR
491 #ifdef CONFIG_PTE_64BIT
492 li r13,_PAGE_PRESENT
493 oris r13,r13,_PAGE_ACCESSED@h
494 #else
495 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
496 #endif
497 rlwimi r13,r12,11,29,29
499 FIND_PTE
500 andc. r13,r13,r11 /* Check permission */
502 #ifdef CONFIG_PTE_64BIT
503 #ifdef CONFIG_SMP
504 subf r13,r11,r12 /* create false data dep */
505 lwzx r13,r11,r13 /* Get upper pte bits */
506 #else
507 lwz r13,0(r12) /* Get upper pte bits */
508 #endif
509 #endif
511 bne 2f /* Bail if permission/valid mismach */
513 /* Jump to common tlb load */
514 b finish_tlb_load
515 2:
516 /* The bailout. Restore registers to pre-exception conditions
517 * and call the heavyweights to help us out.
518 */
519 mfspr r10, SPRN_SPRG_THREAD
520 lwz r11, THREAD_NORMSAVE(3)(r10)
521 mtcr r11
522 lwz r13, THREAD_NORMSAVE(2)(r10)
523 lwz r12, THREAD_NORMSAVE(1)(r10)
524 lwz r11, THREAD_NORMSAVE(0)(r10)
525 mfspr r10, SPRN_SPRG_RSCRATCH0
526 b DataStorage
528 /* Instruction TLB Error Interrupt */
529 /*
530 * Nearly the same as above, except we get our
531 * information from different registers and bailout
532 * to a different point.
533 */
534 START_EXCEPTION(InstructionTLBError)
535 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
536 mfspr r10, SPRN_SPRG_THREAD
537 stw r11, THREAD_NORMSAVE(0)(r10)
538 #ifdef CONFIG_KVM_BOOKE_HV
539 BEGIN_FTR_SECTION
540 mfspr r11, SPRN_SRR1
541 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
542 #endif
543 stw r12, THREAD_NORMSAVE(1)(r10)
544 stw r13, THREAD_NORMSAVE(2)(r10)
545 mfcr r13
546 stw r13, THREAD_NORMSAVE(3)(r10)
547 DO_KVM BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1
548 mfspr r10, SPRN_SRR0 /* Get faulting address */
550 /* If we are faulting a kernel address, we have to use the
551 * kernel page tables.
552 */
553 lis r11, PAGE_OFFSET@h
554 cmplw 5, r10, r11
555 blt 5, 3f
556 lis r11, swapper_pg_dir@h
557 ori r11, r11, swapper_pg_dir@l
559 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
560 rlwinm r12,r12,0,16,1
561 mtspr SPRN_MAS1,r12
563 /* Make up the required permissions for kernel code */
564 #ifdef CONFIG_PTE_64BIT
565 li r13,_PAGE_PRESENT | _PAGE_BAP_SX
566 oris r13,r13,_PAGE_ACCESSED@h
567 #else
568 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
569 #endif
570 b 4f
572 /* Get the PGD for the current thread */
573 3:
574 mfspr r11,SPRN_SPRG_THREAD
575 lwz r11,PGDIR(r11)
577 /* Make up the required permissions for user code */
578 #ifdef CONFIG_PTE_64BIT
579 li r13,_PAGE_PRESENT | _PAGE_BAP_UX
580 oris r13,r13,_PAGE_ACCESSED@h
581 #else
582 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
583 #endif
585 4:
586 FIND_PTE
587 andc. r13,r13,r11 /* Check permission */
589 #ifdef CONFIG_PTE_64BIT
590 #ifdef CONFIG_SMP
591 subf r13,r11,r12 /* create false data dep */
592 lwzx r13,r11,r13 /* Get upper pte bits */
593 #else
594 lwz r13,0(r12) /* Get upper pte bits */
595 #endif
596 #endif
598 bne 2f /* Bail if permission mismach */
600 /* Jump to common TLB load point */
601 b finish_tlb_load
603 2:
604 /* The bailout. Restore registers to pre-exception conditions
605 * and call the heavyweights to help us out.
606 */
607 mfspr r10, SPRN_SPRG_THREAD
608 lwz r11, THREAD_NORMSAVE(3)(r10)
609 mtcr r11
610 lwz r13, THREAD_NORMSAVE(2)(r10)
611 lwz r12, THREAD_NORMSAVE(1)(r10)
612 lwz r11, THREAD_NORMSAVE(0)(r10)
613 mfspr r10, SPRN_SPRG_RSCRATCH0
614 b InstructionStorage
616 #ifdef CONFIG_SPE
617 /* SPE Unavailable */
618 START_EXCEPTION(SPEUnavailable)
619 NORMAL_EXCEPTION_PROLOG(SPE_ALTIVEC_UNAVAIL)
620 beq 1f
621 bl load_up_spe
622 b fast_exception_return
623 1: addi r3,r1,STACK_FRAME_OVERHEAD
624 EXC_XFER_EE_LITE(0x2010, KernelSPE)
625 #else
626 EXCEPTION(0x2020, SPE_ALTIVEC_UNAVAIL, SPEUnavailable, \
627 unknown_exception, EXC_XFER_EE)
628 #endif /* CONFIG_SPE */
630 /* SPE Floating Point Data */
631 #ifdef CONFIG_SPE
632 EXCEPTION(0x2030, SPE_FP_DATA_ALTIVEC_ASSIST, SPEFloatingPointData,
633 SPEFloatingPointException, EXC_XFER_EE)
635 /* SPE Floating Point Round */
636 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
637 SPEFloatingPointRoundException, EXC_XFER_EE)
638 #else
639 EXCEPTION(0x2040, SPE_FP_DATA_ALTIVEC_ASSIST, SPEFloatingPointData,
640 unknown_exception, EXC_XFER_EE)
641 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
642 unknown_exception, EXC_XFER_EE)
643 #endif /* CONFIG_SPE */
645 /* Performance Monitor */
646 EXCEPTION(0x2060, PERFORMANCE_MONITOR, PerformanceMonitor, \
647 performance_monitor_exception, EXC_XFER_STD)
649 EXCEPTION(0x2070, DOORBELL, Doorbell, doorbell_exception, EXC_XFER_STD)
651 CRITICAL_EXCEPTION(0x2080, DOORBELL_CRITICAL, \
652 CriticalDoorbell, unknown_exception)
654 /* Debug Interrupt */
655 DEBUG_DEBUG_EXCEPTION
656 DEBUG_CRIT_EXCEPTION
658 GUEST_DOORBELL_EXCEPTION
660 CRITICAL_EXCEPTION(0, GUEST_DBELL_CRIT, CriticalGuestDoorbell, \
661 unknown_exception)
663 /* Hypercall */
664 EXCEPTION(0, HV_SYSCALL, Hypercall, unknown_exception, EXC_XFER_EE)
666 /* Embedded Hypervisor Privilege */
667 EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception, EXC_XFER_EE)
669 interrupt_end:
671 /*
672 * Local functions
673 */
675 /*
676 * Both the instruction and data TLB miss get to this
677 * point to load the TLB.
678 * r10 - tsize encoding (if HUGETLB_PAGE) or available to use
679 * r11 - TLB (info from Linux PTE)
680 * r12 - available to use
681 * r13 - upper bits of PTE (if PTE_64BIT) or available to use
682 * CR5 - results of addr >= PAGE_OFFSET
683 * MAS0, MAS1 - loaded with proper value when we get here
684 * MAS2, MAS3 - will need additional info from Linux PTE
685 * Upon exit, we reload everything and RFI.
686 */
687 finish_tlb_load:
688 #ifdef CONFIG_HUGETLB_PAGE
689 cmpwi 6, r10, 0 /* check for huge page */
690 beq 6, finish_tlb_load_cont /* !huge */
692 /* Alas, we need more scratch registers for hugepages */
693 mfspr r12, SPRN_SPRG_THREAD
694 stw r14, THREAD_NORMSAVE(4)(r12)
695 stw r15, THREAD_NORMSAVE(5)(r12)
696 stw r16, THREAD_NORMSAVE(6)(r12)
697 stw r17, THREAD_NORMSAVE(7)(r12)
699 /* Get the next_tlbcam_idx percpu var */
700 #ifdef CONFIG_SMP
701 lwz r12, THREAD_INFO-THREAD(r12)
702 lwz r15, TI_CPU(r12)
703 lis r14, __per_cpu_offset@h
704 ori r14, r14, __per_cpu_offset@l
705 rlwinm r15, r15, 2, 0, 29
706 lwzx r16, r14, r15
707 #else
708 li r16, 0
709 #endif
710 lis r17, next_tlbcam_idx@h
711 ori r17, r17, next_tlbcam_idx@l
712 add r17, r17, r16 /* r17 = *next_tlbcam_idx */
713 lwz r15, 0(r17) /* r15 = next_tlbcam_idx */
715 lis r14, MAS0_TLBSEL(1)@h /* select TLB1 (TLBCAM) */
716 rlwimi r14, r15, 16, 4, 15 /* next_tlbcam_idx entry */
717 mtspr SPRN_MAS0, r14
719 /* Extract TLB1CFG(NENTRY) */
720 mfspr r16, SPRN_TLB1CFG
721 andi. r16, r16, 0xfff
723 /* Update next_tlbcam_idx, wrapping when necessary */
724 addi r15, r15, 1
725 cmpw r15, r16
726 blt 100f
727 lis r14, tlbcam_index@h
728 ori r14, r14, tlbcam_index@l
729 lwz r15, 0(r14)
730 100: stw r15, 0(r17)
732 /*
733 * Calc MAS1_TSIZE from r10 (which has pshift encoded)
734 * tlb_enc = (pshift - 10).
735 */
736 subi r15, r10, 10
737 mfspr r16, SPRN_MAS1
738 rlwimi r16, r15, 7, 20, 24
739 mtspr SPRN_MAS1, r16
741 /* copy the pshift for use later */
742 mr r14, r10
744 /* fall through */
746 #endif /* CONFIG_HUGETLB_PAGE */
748 /*
749 * We set execute, because we don't have the granularity to
750 * properly set this at the page level (Linux problem).
751 * Many of these bits are software only. Bits we don't set
752 * here we (properly should) assume have the appropriate value.
753 */
754 finish_tlb_load_cont:
755 #ifdef CONFIG_PTE_64BIT
756 rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */
757 andi. r10, r11, _PAGE_DIRTY
758 bne 1f
759 li r10, MAS3_SW | MAS3_UW
760 andc r12, r12, r10
761 1: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */
762 rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */
763 2: mtspr SPRN_MAS3, r12
764 BEGIN_MMU_FTR_SECTION
765 srwi r10, r13, 12 /* grab RPN[12:31] */
766 mtspr SPRN_MAS7, r10
767 END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
768 #else
769 li r10, (_PAGE_EXEC | _PAGE_PRESENT)
770 mr r13, r11
771 rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */
772 and r12, r11, r10
773 andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
774 slwi r10, r12, 1
775 or r10, r10, r12
776 iseleq r12, r12, r10
777 rlwimi r13, r12, 0, 20, 31 /* Get RPN from PTE, merge w/ perms */
778 mtspr SPRN_MAS3, r13
779 #endif
781 mfspr r12, SPRN_MAS2
782 #ifdef CONFIG_PTE_64BIT
783 rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */
784 #else
785 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
786 #endif
787 #ifdef CONFIG_HUGETLB_PAGE
788 beq 6, 3f /* don't mask if page isn't huge */
789 li r13, 1
790 slw r13, r13, r14
791 subi r13, r13, 1
792 rlwinm r13, r13, 0, 0, 19 /* bottom bits used for WIMGE/etc */
793 andc r12, r12, r13 /* mask off ea bits within the page */
794 #endif
795 3: mtspr SPRN_MAS2, r12
797 #ifdef CONFIG_E200
798 /* Round robin TLB1 entries assignment */
799 mfspr r12, SPRN_MAS0
801 /* Extract TLB1CFG(NENTRY) */
802 mfspr r11, SPRN_TLB1CFG
803 andi. r11, r11, 0xfff
805 /* Extract MAS0(NV) */
806 andi. r13, r12, 0xfff
807 addi r13, r13, 1
808 cmpw 0, r13, r11
809 addi r12, r12, 1
811 /* check if we need to wrap */
812 blt 7f
814 /* wrap back to first free tlbcam entry */
815 lis r13, tlbcam_index@ha
816 lwz r13, tlbcam_index@l(r13)
817 rlwimi r12, r13, 0, 20, 31
818 7:
819 mtspr SPRN_MAS0,r12
820 #endif /* CONFIG_E200 */
822 tlb_write_entry:
823 tlbwe
825 /* Done...restore registers and get out of here. */
826 mfspr r10, SPRN_SPRG_THREAD
827 #ifdef CONFIG_HUGETLB_PAGE
828 beq 6, 8f /* skip restore for 4k page faults */
829 lwz r14, THREAD_NORMSAVE(4)(r10)
830 lwz r15, THREAD_NORMSAVE(5)(r10)
831 lwz r16, THREAD_NORMSAVE(6)(r10)
832 lwz r17, THREAD_NORMSAVE(7)(r10)
833 #endif
834 8: lwz r11, THREAD_NORMSAVE(3)(r10)
835 mtcr r11
836 lwz r13, THREAD_NORMSAVE(2)(r10)
837 lwz r12, THREAD_NORMSAVE(1)(r10)
838 lwz r11, THREAD_NORMSAVE(0)(r10)
839 mfspr r10, SPRN_SPRG_RSCRATCH0
840 rfi /* Force context change */
842 #ifdef CONFIG_SPE
843 /* Note that the SPE support is closely modeled after the AltiVec
844 * support. Changes to one are likely to be applicable to the
845 * other! */
846 _GLOBAL(load_up_spe)
847 /*
848 * Disable SPE for the task which had SPE previously,
849 * and save its SPE registers in its thread_struct.
850 * Enables SPE for use in the kernel on return.
851 * On SMP we know the SPE units are free, since we give it up every
852 * switch. -- Kumar
853 */
854 mfmsr r5
855 oris r5,r5,MSR_SPE@h
856 mtmsr r5 /* enable use of SPE now */
857 isync
858 /*
859 * For SMP, we don't do lazy SPE switching because it just gets too
860 * horrendously complex, especially when a task switches from one CPU
861 * to another. Instead we call giveup_spe in switch_to.
862 */
863 #ifndef CONFIG_SMP
864 lis r3,last_task_used_spe@ha
865 lwz r4,last_task_used_spe@l(r3)
866 cmpi 0,r4,0
867 beq 1f
868 addi r4,r4,THREAD /* want THREAD of last_task_used_spe */
869 SAVE_32EVRS(0,r10,r4,THREAD_EVR0)
870 evxor evr10, evr10, evr10 /* clear out evr10 */
871 evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */
872 li r5,THREAD_ACC
873 evstddx evr10, r4, r5 /* save off accumulator */
874 lwz r5,PT_REGS(r4)
875 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
876 lis r10,MSR_SPE@h
877 andc r4,r4,r10 /* disable SPE for previous task */
878 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
879 1:
880 #endif /* !CONFIG_SMP */
881 /* enable use of SPE after return */
882 oris r9,r9,MSR_SPE@h
883 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
884 li r4,1
885 li r10,THREAD_ACC
886 stw r4,THREAD_USED_SPE(r5)
887 evlddx evr4,r10,r5
888 evmra evr4,evr4
889 REST_32EVRS(0,r10,r5,THREAD_EVR0)
890 #ifndef CONFIG_SMP
891 subi r4,r5,THREAD
892 stw r4,last_task_used_spe@l(r3)
893 #endif /* !CONFIG_SMP */
894 blr
896 /*
897 * SPE unavailable trap from kernel - print a message, but let
898 * the task use SPE in the kernel until it returns to user mode.
899 */
900 KernelSPE:
901 lwz r3,_MSR(r1)
902 oris r3,r3,MSR_SPE@h
903 stw r3,_MSR(r1) /* enable use of SPE after return */
904 #ifdef CONFIG_PRINTK
905 lis r3,87f@h
906 ori r3,r3,87f@l
907 mr r4,r2 /* current */
908 lwz r5,_NIP(r1)
909 bl printk
910 #endif
911 b ret_from_except
912 #ifdef CONFIG_PRINTK
913 87: .string "SPE used in kernel (task=%p, pc=%x) \n"
914 #endif
915 .align 4,0
917 #endif /* CONFIG_SPE */
919 /*
920 * Translate the effec addr in r3 to phys addr. The phys addr will be put
921 * into r3(higher 32bit) and r4(lower 32bit)
922 */
923 get_phys_addr:
924 mfmsr r8
925 mfspr r9,SPRN_PID
926 rlwinm r9,r9,16,0x3fff0000 /* turn PID into MAS6[SPID] */
927 rlwimi r9,r8,28,0x00000001 /* turn MSR[DS] into MAS6[SAS] */
928 mtspr SPRN_MAS6,r9
930 tlbsx 0,r3 /* must succeed */
932 mfspr r8,SPRN_MAS1
933 mfspr r12,SPRN_MAS3
934 rlwinm r9,r8,25,0x1f /* r9 = log2(page size) */
935 li r10,1024
936 slw r10,r10,r9 /* r10 = page size */
937 addi r10,r10,-1
938 and r11,r3,r10 /* r11 = page offset */
939 andc r4,r12,r10 /* r4 = page base */
940 or r4,r4,r11 /* r4 = devtree phys addr */
941 #ifdef CONFIG_PHYS_64BIT
942 mfspr r3,SPRN_MAS7
943 #endif
944 blr
946 /*
947 * Global functions
948 */
950 /* Adjust or setup IVORs for e200 */
951 _GLOBAL(__setup_e200_ivors)
952 li r3,DebugDebug@l
953 mtspr SPRN_IVOR15,r3
954 li r3,SPEUnavailable@l
955 mtspr SPRN_IVOR32,r3
956 li r3,SPEFloatingPointData@l
957 mtspr SPRN_IVOR33,r3
958 li r3,SPEFloatingPointRound@l
959 mtspr SPRN_IVOR34,r3
960 sync
961 blr
963 /* Adjust or setup IVORs for e500v1/v2 */
964 _GLOBAL(__setup_e500_ivors)
965 li r3,DebugCrit@l
966 mtspr SPRN_IVOR15,r3
967 li r3,SPEUnavailable@l
968 mtspr SPRN_IVOR32,r3
969 li r3,SPEFloatingPointData@l
970 mtspr SPRN_IVOR33,r3
971 li r3,SPEFloatingPointRound@l
972 mtspr SPRN_IVOR34,r3
973 li r3,PerformanceMonitor@l
974 mtspr SPRN_IVOR35,r3
975 sync
976 blr
978 /* Adjust or setup IVORs for e500mc */
979 _GLOBAL(__setup_e500mc_ivors)
980 li r3,DebugDebug@l
981 mtspr SPRN_IVOR15,r3
982 li r3,PerformanceMonitor@l
983 mtspr SPRN_IVOR35,r3
984 li r3,Doorbell@l
985 mtspr SPRN_IVOR36,r3
986 li r3,CriticalDoorbell@l
987 mtspr SPRN_IVOR37,r3
988 sync
989 blr
991 /* setup ehv ivors for */
992 _GLOBAL(__setup_ehv_ivors)
993 li r3,GuestDoorbell@l
994 mtspr SPRN_IVOR38,r3
995 li r3,CriticalGuestDoorbell@l
996 mtspr SPRN_IVOR39,r3
997 li r3,Hypercall@l
998 mtspr SPRN_IVOR40,r3
999 li r3,Ehvpriv@l
1000 mtspr SPRN_IVOR41,r3
1001 sync
1002 blr
1004 #ifdef CONFIG_SPE
1005 /*
1006 * extern void giveup_spe(struct task_struct *prev)
1007 *
1008 */
1009 _GLOBAL(giveup_spe)
1010 mfmsr r5
1011 oris r5,r5,MSR_SPE@h
1012 mtmsr r5 /* enable use of SPE now */
1013 isync
1014 cmpi 0,r3,0
1015 beqlr- /* if no previous owner, done */
1016 addi r3,r3,THREAD /* want THREAD of task */
1017 lwz r5,PT_REGS(r3)
1018 cmpi 0,r5,0
1019 SAVE_32EVRS(0, r4, r3, THREAD_EVR0)
1020 evxor evr6, evr6, evr6 /* clear out evr6 */
1021 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
1022 li r4,THREAD_ACC
1023 evstddx evr6, r4, r3 /* save off accumulator */
1024 beq 1f
1025 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1026 lis r3,MSR_SPE@h
1027 andc r4,r4,r3 /* disable SPE for previous task */
1028 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1029 1:
1030 #ifndef CONFIG_SMP
1031 li r5,0
1032 lis r4,last_task_used_spe@ha
1033 stw r5,last_task_used_spe@l(r4)
1034 #endif /* !CONFIG_SMP */
1035 blr
1036 #endif /* CONFIG_SPE */
1038 /*
1039 * extern void abort(void)
1040 *
1041 * At present, this routine just applies a system reset.
1042 */
1043 _GLOBAL(abort)
1044 li r13,0
1045 mtspr SPRN_DBCR0,r13 /* disable all debug events */
1046 isync
1047 mfmsr r13
1048 ori r13,r13,MSR_DE@l /* Enable Debug Events */
1049 mtmsr r13
1050 isync
1051 mfspr r13,SPRN_DBCR0
1052 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
1053 mtspr SPRN_DBCR0,r13
1054 isync
1056 _GLOBAL(set_context)
1058 #ifdef CONFIG_BDI_SWITCH
1059 /* Context switch the PTE pointer for the Abatron BDI2000.
1060 * The PGDIR is the second parameter.
1061 */
1062 lis r5, abatron_pteptrs@h
1063 ori r5, r5, abatron_pteptrs@l
1064 stw r4, 0x4(r5)
1065 #endif
1066 mtspr SPRN_PID,r3
1067 isync /* Force context change */
1068 blr
1070 _GLOBAL(flush_dcache_L1)
1071 mfspr r3,SPRN_L1CFG0
1073 rlwinm r5,r3,9,3 /* Extract cache block size */
1074 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1075 * are currently defined.
1076 */
1077 li r4,32
1078 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1079 * log2(number of ways)
1080 */
1081 slw r5,r4,r5 /* r5 = cache block size */
1083 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1084 mulli r7,r7,13 /* An 8-way cache will require 13
1085 * loads per set.
1086 */
1087 slw r7,r7,r6
1089 /* save off HID0 and set DCFA */
1090 mfspr r8,SPRN_HID0
1091 ori r9,r8,HID0_DCFA@l
1092 mtspr SPRN_HID0,r9
1093 isync
1095 lis r4,KERNELBASE@h
1096 mtctr r7
1098 1: lwz r3,0(r4) /* Load... */
1099 add r4,r4,r5
1100 bdnz 1b
1102 msync
1103 lis r4,KERNELBASE@h
1104 mtctr r7
1106 1: dcbf 0,r4 /* ...and flush. */
1107 add r4,r4,r5
1108 bdnz 1b
1110 /* restore HID0 */
1111 mtspr SPRN_HID0,r8
1112 isync
1114 blr
1116 /* Flush L1 d-cache, invalidate and disable d-cache and i-cache */
1117 _GLOBAL(__flush_disable_L1)
1118 mflr r10
1119 bl flush_dcache_L1 /* Flush L1 d-cache */
1120 mtlr r10
1122 mfspr r4, SPRN_L1CSR0 /* Invalidate and disable d-cache */
1123 li r5, 2
1124 rlwimi r4, r5, 0, 3
1126 msync
1127 isync
1128 mtspr SPRN_L1CSR0, r4
1129 isync
1131 1: mfspr r4, SPRN_L1CSR0 /* Wait for the invalidate to finish */
1132 andi. r4, r4, 2
1133 bne 1b
1135 mfspr r4, SPRN_L1CSR1 /* Invalidate and disable i-cache */
1136 li r5, 2
1137 rlwimi r4, r5, 0, 3
1139 mtspr SPRN_L1CSR1, r4
1140 isync
1142 blr
1144 #ifdef CONFIG_SMP
1145 /* When we get here, r24 needs to hold the CPU # */
1146 .globl __secondary_start
1147 __secondary_start:
1148 LOAD_REG_ADDR_PIC(r3, tlbcam_index)
1149 lwz r3,0(r3)
1150 mtctr r3
1151 li r26,0 /* r26 safe? */
1153 bl switch_to_as1
1154 mr r27,r3 /* tlb entry */
1155 /* Load each CAM entry */
1156 1: mr r3,r26
1157 bl loadcam_entry
1158 addi r26,r26,1
1159 bdnz 1b
1160 mr r3,r27 /* tlb entry */
1161 LOAD_REG_ADDR_PIC(r4, memstart_addr)
1162 lwz r4,0(r4)
1163 mr r5,r25 /* phys kernel start */
1164 rlwinm r5,r5,0,~0x3ffffff /* aligned 64M */
1165 subf r4,r5,r4 /* memstart_addr - phys kernel start */
1166 li r5,0 /* no device tree */
1167 li r6,0 /* not boot cpu */
1168 bl restore_to_as0
1171 lis r3,__secondary_hold_acknowledge@h
1172 ori r3,r3,__secondary_hold_acknowledge@l
1173 stw r24,0(r3)
1175 li r3,0
1176 mr r4,r24 /* Why? */
1177 bl call_setup_cpu
1179 /* get current_thread_info and current */
1180 lis r1,secondary_ti@ha
1181 lwz r1,secondary_ti@l(r1)
1182 lwz r2,TI_TASK(r1)
1184 /* stack */
1185 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1186 li r0,0
1187 stw r0,0(r1)
1189 /* ptr to current thread */
1190 addi r4,r2,THREAD /* address of our thread_struct */
1191 mtspr SPRN_SPRG_THREAD,r4
1193 /* Setup the defaults for TLB entries */
1194 li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
1195 mtspr SPRN_MAS4,r4
1197 /* Jump to start_secondary */
1198 lis r4,MSR_KERNEL@h
1199 ori r4,r4,MSR_KERNEL@l
1200 lis r3,start_secondary@h
1201 ori r3,r3,start_secondary@l
1202 mtspr SPRN_SRR0,r3
1203 mtspr SPRN_SRR1,r4
1204 sync
1205 rfi
1206 sync
1208 .globl __secondary_hold_acknowledge
1209 __secondary_hold_acknowledge:
1210 .long -1
1211 #endif
1213 /*
1214 * Create a tlb entry with the same effective and physical address as
1215 * the tlb entry used by the current running code. But set the TS to 1.
1216 * Then switch to the address space 1. It will return with the r3 set to
1217 * the ESEL of the new created tlb.
1218 */
1219 _GLOBAL(switch_to_as1)
1220 mflr r5
1222 /* Find a entry not used */
1223 mfspr r3,SPRN_TLB1CFG
1224 andi. r3,r3,0xfff
1225 mfspr r4,SPRN_PID
1226 rlwinm r4,r4,16,0x3fff0000 /* turn PID into MAS6[SPID] */
1227 mtspr SPRN_MAS6,r4
1228 1: lis r4,0x1000 /* Set MAS0(TLBSEL) = 1 */
1229 addi r3,r3,-1
1230 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1231 mtspr SPRN_MAS0,r4
1232 tlbre
1233 mfspr r4,SPRN_MAS1
1234 andis. r4,r4,MAS1_VALID@h
1235 bne 1b
1237 /* Get the tlb entry used by the current running code */
1238 bl 0f
1239 0: mflr r4
1240 tlbsx 0,r4
1242 mfspr r4,SPRN_MAS1
1243 ori r4,r4,MAS1_TS /* Set the TS = 1 */
1244 mtspr SPRN_MAS1,r4
1246 mfspr r4,SPRN_MAS0
1247 rlwinm r4,r4,0,~MAS0_ESEL_MASK
1248 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1249 mtspr SPRN_MAS0,r4
1250 tlbwe
1251 isync
1252 sync
1254 mfmsr r4
1255 ori r4,r4,MSR_IS | MSR_DS
1256 mtspr SPRN_SRR0,r5
1257 mtspr SPRN_SRR1,r4
1258 sync
1259 rfi
1261 /*
1262 * Restore to the address space 0 and also invalidate the tlb entry created
1263 * by switch_to_as1.
1264 * r3 - the tlb entry which should be invalidated
1265 * r4 - __pa(PAGE_OFFSET in AS1) - __pa(PAGE_OFFSET in AS0)
1266 * r5 - device tree virtual address. If r4 is 0, r5 is ignored.
1267 * r6 - boot cpu
1268 */
1269 _GLOBAL(restore_to_as0)
1270 mflr r0
1272 bl 0f
1273 0: mflr r9
1274 addi r9,r9,1f - 0b
1276 /*
1277 * We may map the PAGE_OFFSET in AS0 to a different physical address,
1278 * so we need calculate the right jump and device tree address based
1279 * on the offset passed by r4.
1280 */
1281 add r9,r9,r4
1282 add r5,r5,r4
1283 add r0,r0,r4
1285 2: mfmsr r7
1286 li r8,(MSR_IS | MSR_DS)
1287 andc r7,r7,r8
1289 mtspr SPRN_SRR0,r9
1290 mtspr SPRN_SRR1,r7
1291 sync
1292 rfi
1294 /* Invalidate the temporary tlb entry for AS1 */
1295 1: lis r9,0x1000 /* Set MAS0(TLBSEL) = 1 */
1296 rlwimi r9,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1297 mtspr SPRN_MAS0,r9
1298 tlbre
1299 mfspr r9,SPRN_MAS1
1300 rlwinm r9,r9,0,2,31 /* Clear MAS1 Valid and IPPROT */
1301 mtspr SPRN_MAS1,r9
1302 tlbwe
1303 isync
1305 cmpwi r4,0
1306 cmpwi cr1,r6,0
1307 cror eq,4*cr1+eq,eq
1308 bne 3f /* offset != 0 && is_boot_cpu */
1309 mtlr r0
1310 blr
1312 /*
1313 * The PAGE_OFFSET will map to a different physical address,
1314 * jump to _start to do another relocation again.
1315 */
1316 3: mr r3,r5
1317 bl _start
1319 /*
1320 * We put a few things here that have to be page-aligned. This stuff
1321 * goes at the beginning of the data segment, which is page-aligned.
1322 */
1323 .data
1324 .align 12
1325 .globl sdata
1326 sdata:
1327 .globl empty_zero_page
1328 empty_zero_page:
1329 .space 4096
1330 .globl swapper_pg_dir
1331 swapper_pg_dir:
1332 .space PGD_TABLE_SIZE
1334 /*
1335 * Room for two PTE pointers, usually the kernel and current user pointers
1336 * to their respective root page table.
1337 */
1338 abatron_pteptrs:
1339 .space 8