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efivars: Refactor sanity checking code into separate function
[linux/fpc-iii.git] / arch / powerpc / sysdev / fsl_rio.c
blobcf2b0840a672f893a3b2386154716ef54672dfd7
1 /*
2 * Freescale MPC85xx/MPC86xx RapidIO support
3 *
4 * Copyright 2009 Sysgo AG
5 * Thomas Moll <thomas.moll@sysgo.com>
6 * - fixed maintenance access routines, check for aligned access
7 *
8 * Copyright 2009 Integrated Device Technology, Inc.
9 * Alex Bounine <alexandre.bounine@idt.com>
10 * - Added Port-Write message handling
11 * - Added Machine Check exception handling
12 *
13 * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
14 * Zhang Wei <wei.zhang@freescale.com>
15 *
16 * Copyright 2005 MontaVista Software, Inc.
17 * Matt Porter <mporter@kernel.crashing.org>
18 *
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2 of the License, or (at your
22 * option) any later version.
23 */
24
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/types.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/interrupt.h>
30 #include <linux/device.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/of_platform.h>
34 #include <linux/delay.h>
35 #include <linux/slab.h>
36
37 #include <linux/io.h>
38 #include <linux/uaccess.h>
39 #include <asm/machdep.h>
40
41 #include "fsl_rio.h"
42
43 #undef DEBUG_PW /* Port-Write debugging */
44
45 #define RIO_PORT1_EDCSR 0x0640
46 #define RIO_PORT2_EDCSR 0x0680
47 #define RIO_PORT1_IECSR 0x10130
48 #define RIO_PORT2_IECSR 0x101B0
49
50 #define RIO_GCCSR 0x13c
51 #define RIO_ESCSR 0x158
52 #define ESCSR_CLEAR 0x07120204
53 #define RIO_PORT2_ESCSR 0x178
54 #define RIO_CCSR 0x15c
55 #define RIO_LTLEDCSR_IER 0x80000000
56 #define RIO_LTLEDCSR_PRT 0x01000000
57 #define IECSR_CLEAR 0x80000000
58 #define RIO_ISR_AACR 0x10120
59 #define RIO_ISR_AACR_AA 0x1 /* Accept All ID */
60
61 #define __fsl_read_rio_config(x, addr, err, op) \
62 __asm__ __volatile__( \
63 "1: "op" %1,0(%2)\n" \
64 " eieio\n" \
65 "2:\n" \
66 ".section .fixup,\"ax\"\n" \
67 "3: li %1,-1\n" \
68 " li %0,%3\n" \
69 " b 2b\n" \
70 ".section __ex_table,\"a\"\n" \
71 PPC_LONG_ALIGN "\n" \
72 PPC_LONG "1b,3b\n" \
73 ".text" \
74 : "=r" (err), "=r" (x) \
75 : "b" (addr), "i" (-EFAULT), "0" (err))
76
77 void __iomem *rio_regs_win;
78 void __iomem *rmu_regs_win;
79 resource_size_t rio_law_start;
80
81 struct fsl_rio_dbell *dbell;
82 struct fsl_rio_pw *pw;
83
84 #ifdef CONFIG_E500
85 int fsl_rio_mcheck_exception(struct pt_regs *regs)
86 {
87 const struct exception_table_entry *entry;
88 unsigned long reason;
89
90 if (!rio_regs_win)
91 return 0;
92
93 reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR));
94 if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) {
95 /* Check if we are prepared to handle this fault */
96 entry = search_exception_tables(regs->nip);
97 if (entry) {
98 pr_debug("RIO: %s - MC Exception handled\n",
99 __func__);
100 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR),
101 0);
102 regs->msr |= MSR_RI;
103 regs->nip = entry->fixup;
104 return 1;
105 }
106 }
107
108 return 0;
109 }
110 EXPORT_SYMBOL_GPL(fsl_rio_mcheck_exception);
111 #endif
112
113 /**
114 * fsl_local_config_read - Generate a MPC85xx local config space read
115 * @mport: RapidIO master port info
116 * @index: ID of RapdiIO interface
117 * @offset: Offset into configuration space
118 * @len: Length (in bytes) of the maintenance transaction
119 * @data: Value to be read into
120 *
121 * Generates a MPC85xx local configuration space read. Returns %0 on
122 * success or %-EINVAL on failure.
123 */
124 static int fsl_local_config_read(struct rio_mport *mport,
125 int index, u32 offset, int len, u32 *data)
126 {
127 struct rio_priv *priv = mport->priv;
128 pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
129 offset);
130 *data = in_be32(priv->regs_win + offset);
131
132 return 0;
133 }
134
135 /**
136 * fsl_local_config_write - Generate a MPC85xx local config space write
137 * @mport: RapidIO master port info
138 * @index: ID of RapdiIO interface
139 * @offset: Offset into configuration space
140 * @len: Length (in bytes) of the maintenance transaction
141 * @data: Value to be written
142 *
143 * Generates a MPC85xx local configuration space write. Returns %0 on
144 * success or %-EINVAL on failure.
145 */
146 static int fsl_local_config_write(struct rio_mport *mport,
147 int index, u32 offset, int len, u32 data)
148 {
149 struct rio_priv *priv = mport->priv;
150 pr_debug
151 ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
152 index, offset, data);
153 out_be32(priv->regs_win + offset, data);
154
155 return 0;
156 }
157
158 /**
159 * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
160 * @mport: RapidIO master port info
161 * @index: ID of RapdiIO interface
162 * @destid: Destination ID of transaction
163 * @hopcount: Number of hops to target device
164 * @offset: Offset into configuration space
165 * @len: Length (in bytes) of the maintenance transaction
166 * @val: Location to be read into
167 *
168 * Generates a MPC85xx read maintenance transaction. Returns %0 on
169 * success or %-EINVAL on failure.
170 */
171 static int
172 fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
173 u8 hopcount, u32 offset, int len, u32 *val)
174 {
175 struct rio_priv *priv = mport->priv;
176 u8 *data;
177 u32 rval, err = 0;
178
179 pr_debug
180 ("fsl_rio_config_read:"
181 " index %d destid %d hopcount %d offset %8.8x len %d\n",
182 index, destid, hopcount, offset, len);
183
184 /* 16MB maintenance window possible */
185 /* allow only aligned access to maintenance registers */
186 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
187 return -EINVAL;
188
189 out_be32(&priv->maint_atmu_regs->rowtar,
190 (destid << 22) | (hopcount << 12) | (offset >> 12));
191 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
192
193 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
194 switch (len) {
195 case 1:
196 __fsl_read_rio_config(rval, data, err, "lbz");
197 break;
198 case 2:
199 __fsl_read_rio_config(rval, data, err, "lhz");
200 break;
201 case 4:
202 __fsl_read_rio_config(rval, data, err, "lwz");
203 break;
204 default:
205 return -EINVAL;
206 }
207
208 if (err) {
209 pr_debug("RIO: cfg_read error %d for %x:%x:%x\n",
210 err, destid, hopcount, offset);
211 }
212
213 *val = rval;
214
215 return err;
216 }
217
218 /**
219 * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
220 * @mport: RapidIO master port info
221 * @index: ID of RapdiIO interface
222 * @destid: Destination ID of transaction
223 * @hopcount: Number of hops to target device
224 * @offset: Offset into configuration space
225 * @len: Length (in bytes) of the maintenance transaction
226 * @val: Value to be written
227 *
228 * Generates an MPC85xx write maintenance transaction. Returns %0 on
229 * success or %-EINVAL on failure.
230 */
231 static int
232 fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
233 u8 hopcount, u32 offset, int len, u32 val)
234 {
235 struct rio_priv *priv = mport->priv;
236 u8 *data;
237 pr_debug
238 ("fsl_rio_config_write:"
239 " index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
240 index, destid, hopcount, offset, len, val);
241
242 /* 16MB maintenance windows possible */
243 /* allow only aligned access to maintenance registers */
244 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
245 return -EINVAL;
246
247 out_be32(&priv->maint_atmu_regs->rowtar,
248 (destid << 22) | (hopcount << 12) | (offset >> 12));
249 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
250
251 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
252 switch (len) {
253 case 1:
254 out_8((u8 *) data, val);
255 break;
256 case 2:
257 out_be16((u16 *) data, val);
258 break;
259 case 4:
260 out_be32((u32 *) data, val);
261 break;
262 default:
263 return -EINVAL;
264 }
265
266 return 0;
267 }
268
269 void fsl_rio_port_error_handler(int offset)
270 {
271 /*XXX: Error recovery is not implemented, we just clear errors */
272 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
273
274 if (offset == 0) {
275 out_be32((u32 *)(rio_regs_win + RIO_PORT1_EDCSR), 0);
276 out_be32((u32 *)(rio_regs_win + RIO_PORT1_IECSR), IECSR_CLEAR);
277 out_be32((u32 *)(rio_regs_win + RIO_ESCSR), ESCSR_CLEAR);
278 } else {
279 out_be32((u32 *)(rio_regs_win + RIO_PORT2_EDCSR), 0);
280 out_be32((u32 *)(rio_regs_win + RIO_PORT2_IECSR), IECSR_CLEAR);
281 out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR);
282 }
283 }
284 static inline void fsl_rio_info(struct device *dev, u32 ccsr)
285 {
286 const char *str;
287 if (ccsr & 1) {
288 /* Serial phy */
289 switch (ccsr >> 30) {
290 case 0:
291 str = "1";
292 break;
293 case 1:
294 str = "4";
295 break;
296 default:
297 str = "Unknown";
298 break;
299 }
300 dev_info(dev, "Hardware port width: %s\n", str);
301
302 switch ((ccsr >> 27) & 7) {
303 case 0:
304 str = "Single-lane 0";
305 break;
306 case 1:
307 str = "Single-lane 2";
308 break;
309 case 2:
310 str = "Four-lane";
311 break;
312 default:
313 str = "Unknown";
314 break;
315 }
316 dev_info(dev, "Training connection status: %s\n", str);
317 } else {
318 /* Parallel phy */
319 if (!(ccsr & 0x80000000))
320 dev_info(dev, "Output port operating in 8-bit mode\n");
321 if (!(ccsr & 0x08000000))
322 dev_info(dev, "Input port operating in 8-bit mode\n");
323 }
324 }
325
326 /**
327 * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
328 * @dev: platform_device pointer
329 *
330 * Initializes MPC85xx RapidIO hardware interface, configures
331 * master port with system-specific info, and registers the
332 * master port with the RapidIO subsystem.
333 */
334 int fsl_rio_setup(struct platform_device *dev)
335 {
336 struct rio_ops *ops;
337 struct rio_mport *port;
338 struct rio_priv *priv;
339 int rc = 0;
340 const u32 *dt_range, *cell, *port_index;
341 u32 active_ports = 0;
342 struct resource regs, rmu_regs;
343 struct device_node *np, *rmu_node;
344 int rlen;
345 u32 ccsr;
346 u64 range_start, range_size;
347 int paw, aw, sw;
348 u32 i;
349 static int tmp;
350 struct device_node *rmu_np[MAX_MSG_UNIT_NUM] = {NULL};
351
352 if (!dev->dev.of_node) {
353 dev_err(&dev->dev, "Device OF-Node is NULL");
354 return -ENODEV;
355 }
356
357 rc = of_address_to_resource(dev->dev.of_node, 0, &regs);
358 if (rc) {
359 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
360 dev->dev.of_node->full_name);
361 return -EFAULT;
362 }
363 dev_info(&dev->dev, "Of-device full name %s\n",
364 dev->dev.of_node->full_name);
365 dev_info(&dev->dev, "Regs: %pR\n", &regs);
366
367 rio_regs_win = ioremap(regs.start, resource_size(&regs));
368 if (!rio_regs_win) {
369 dev_err(&dev->dev, "Unable to map rio register window\n");
370 rc = -ENOMEM;
371 goto err_rio_regs;
372 }
373
374 ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
375 if (!ops) {
376 rc = -ENOMEM;
377 goto err_ops;
378 }
379 ops->lcread = fsl_local_config_read;
380 ops->lcwrite = fsl_local_config_write;
381 ops->cread = fsl_rio_config_read;
382 ops->cwrite = fsl_rio_config_write;
383 ops->dsend = fsl_rio_doorbell_send;
384 ops->pwenable = fsl_rio_pw_enable;
385 ops->open_outb_mbox = fsl_open_outb_mbox;
386 ops->open_inb_mbox = fsl_open_inb_mbox;
387 ops->close_outb_mbox = fsl_close_outb_mbox;
388 ops->close_inb_mbox = fsl_close_inb_mbox;
389 ops->add_outb_message = fsl_add_outb_message;
390 ops->add_inb_buffer = fsl_add_inb_buffer;
391 ops->get_inb_message = fsl_get_inb_message;
392
393 rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0);
394 if (!rmu_node)
395 goto err_rmu;
396 rc = of_address_to_resource(rmu_node, 0, &rmu_regs);
397 if (rc) {
398 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
399 rmu_node->full_name);
400 goto err_rmu;
401 }
402 rmu_regs_win = ioremap(rmu_regs.start, resource_size(&rmu_regs));
403 if (!rmu_regs_win) {
404 dev_err(&dev->dev, "Unable to map rmu register window\n");
405 rc = -ENOMEM;
406 goto err_rmu;
407 }
408 for_each_compatible_node(np, NULL, "fsl,srio-msg-unit") {
409 rmu_np[tmp] = np;
410 tmp++;
411 }
412
413 /*set up doobell node*/
414 np = of_find_compatible_node(NULL, NULL, "fsl,srio-dbell-unit");
415 if (!np) {
416 rc = -ENODEV;
417 goto err_dbell;
418 }
419 dbell = kzalloc(sizeof(struct fsl_rio_dbell), GFP_KERNEL);
420 if (!(dbell)) {
421 dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_dbell'\n");
422 rc = -ENOMEM;
423 goto err_dbell;
424 }
425 dbell->dev = &dev->dev;
426 dbell->bellirq = irq_of_parse_and_map(np, 1);
427 dev_info(&dev->dev, "bellirq: %d\n", dbell->bellirq);
428
429 aw = of_n_addr_cells(np);
430 dt_range = of_get_property(np, "reg", &rlen);
431 if (!dt_range) {
432 pr_err("%s: unable to find 'reg' property\n",
433 np->full_name);
434 rc = -ENOMEM;
435 goto err_pw;
436 }
437 range_start = of_read_number(dt_range, aw);
438 dbell->dbell_regs = (struct rio_dbell_regs *)(rmu_regs_win +
439 (u32)range_start);
440
441 /*set up port write node*/
442 np = of_find_compatible_node(NULL, NULL, "fsl,srio-port-write-unit");
443 if (!np) {
444 rc = -ENODEV;
445 goto err_pw;
446 }
447 pw = kzalloc(sizeof(struct fsl_rio_pw), GFP_KERNEL);
448 if (!(pw)) {
449 dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_pw'\n");
450 rc = -ENOMEM;
451 goto err_pw;
452 }
453 pw->dev = &dev->dev;
454 pw->pwirq = irq_of_parse_and_map(np, 0);
455 dev_info(&dev->dev, "pwirq: %d\n", pw->pwirq);
456 aw = of_n_addr_cells(np);
457 dt_range = of_get_property(np, "reg", &rlen);
458 if (!dt_range) {
459 pr_err("%s: unable to find 'reg' property\n",
460 np->full_name);
461 rc = -ENOMEM;
462 goto err;
463 }
464 range_start = of_read_number(dt_range, aw);
465 pw->pw_regs = (struct rio_pw_regs *)(rmu_regs_win + (u32)range_start);
466
467 /*set up ports node*/
468 for_each_child_of_node(dev->dev.of_node, np) {
469 port_index = of_get_property(np, "cell-index", NULL);
470 if (!port_index) {
471 dev_err(&dev->dev, "Can't get %s property 'cell-index'\n",
472 np->full_name);
473 continue;
474 }
475
476 dt_range = of_get_property(np, "ranges", &rlen);
477 if (!dt_range) {
478 dev_err(&dev->dev, "Can't get %s property 'ranges'\n",
479 np->full_name);
480 continue;
481 }
482
483 /* Get node address wide */
484 cell = of_get_property(np, "#address-cells", NULL);
485 if (cell)
486 aw = *cell;
487 else
488 aw = of_n_addr_cells(np);
489 /* Get node size wide */
490 cell = of_get_property(np, "#size-cells", NULL);
491 if (cell)
492 sw = *cell;
493 else
494 sw = of_n_size_cells(np);
495 /* Get parent address wide wide */
496 paw = of_n_addr_cells(np);
497 range_start = of_read_number(dt_range + aw, paw);
498 range_size = of_read_number(dt_range + aw + paw, sw);
499
500 dev_info(&dev->dev, "%s: LAW start 0x%016llx, size 0x%016llx.\n",
501 np->full_name, range_start, range_size);
502
503 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
504 if (!port)
505 continue;
506
507 i = *port_index - 1;
508 port->index = (unsigned char)i;
509
510 priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
511 if (!priv) {
512 dev_err(&dev->dev, "Can't alloc memory for 'priv'\n");
513 kfree(port);
514 continue;
515 }
516
517 INIT_LIST_HEAD(&port->dbells);
518 port->iores.start = range_start;
519 port->iores.end = port->iores.start + range_size - 1;
520 port->iores.flags = IORESOURCE_MEM;
521 port->iores.name = "rio_io_win";
522
523 if (request_resource(&iomem_resource, &port->iores) < 0) {
524 dev_err(&dev->dev, "RIO: Error requesting master port region"
525 " 0x%016llx-0x%016llx\n",
526 (u64)port->iores.start, (u64)port->iores.end);
527 kfree(priv);
528 kfree(port);
529 continue;
530 }
531 sprintf(port->name, "RIO mport %d", i);
532
533 priv->dev = &dev->dev;
534 port->dev.parent = &dev->dev;
535 port->ops = ops;
536 port->priv = priv;
537 port->phys_efptr = 0x100;
538 priv->regs_win = rio_regs_win;
539
540 /* Probe the master port phy type */
541 ccsr = in_be32(priv->regs_win + RIO_CCSR + i*0x20);
542 port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL;
543 if (port->phy_type == RIO_PHY_PARALLEL) {
544 dev_err(&dev->dev, "RIO: Parallel PHY type, unsupported port type!\n");
545 release_resource(&port->iores);
546 kfree(priv);
547 kfree(port);
548 continue;
549 }
550 dev_info(&dev->dev, "RapidIO PHY type: Serial\n");
551 /* Checking the port training status */
552 if (in_be32((priv->regs_win + RIO_ESCSR + i*0x20)) & 1) {
553 dev_err(&dev->dev, "Port %d is not ready. "
554 "Try to restart connection...\n", i);
555 /* Disable ports */
556 out_be32(priv->regs_win
557 + RIO_CCSR + i*0x20, 0);
558 /* Set 1x lane */
559 setbits32(priv->regs_win
560 + RIO_CCSR + i*0x20, 0x02000000);
561 /* Enable ports */
562 setbits32(priv->regs_win
563 + RIO_CCSR + i*0x20, 0x00600000);
564 msleep(100);
565 if (in_be32((priv->regs_win
566 + RIO_ESCSR + i*0x20)) & 1) {
567 dev_err(&dev->dev,
568 "Port %d restart failed.\n", i);
569 release_resource(&port->iores);
570 kfree(priv);
571 kfree(port);
572 continue;
573 }
574 dev_info(&dev->dev, "Port %d restart success!\n", i);
575 }
576 fsl_rio_info(&dev->dev, ccsr);
577
578 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
579 & RIO_PEF_CTLS) >> 4;
580 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
581 port->sys_size ? 65536 : 256);
582
583 if (rio_register_mport(port)) {
584 release_resource(&port->iores);
585 kfree(priv);
586 kfree(port);
587 continue;
588 }
589 if (port->host_deviceid >= 0)
590 out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST |
591 RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED);
592 else
593 out_be32(priv->regs_win + RIO_GCCSR,
594 RIO_PORT_GEN_MASTER);
595
596 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
597 + ((i == 0) ? RIO_ATMU_REGS_PORT1_OFFSET :
598 RIO_ATMU_REGS_PORT2_OFFSET));
599
600 priv->maint_atmu_regs = priv->atmu_regs + 1;
601
602 /* Set to receive any dist ID for serial RapidIO controller. */
603 if (port->phy_type == RIO_PHY_SERIAL)
604 out_be32((priv->regs_win
605 + RIO_ISR_AACR + i*0x80), RIO_ISR_AACR_AA);
606
607 /* Configure maintenance transaction window */
608 out_be32(&priv->maint_atmu_regs->rowbar,
609 port->iores.start >> 12);
610 out_be32(&priv->maint_atmu_regs->rowar,
611 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
612
613 priv->maint_win = ioremap(port->iores.start,
614 RIO_MAINT_WIN_SIZE);
615
616 rio_law_start = range_start;
617
618 fsl_rio_setup_rmu(port, rmu_np[i]);
619
620 dbell->mport[i] = port;
621
622 active_ports++;
623 }
624
625 if (!active_ports) {
626 rc = -ENOLINK;
627 goto err;
628 }
629
630 fsl_rio_doorbell_init(dbell);
631 fsl_rio_port_write_init(pw);
632
633 return 0;
634 err:
635 kfree(pw);
636 err_pw:
637 kfree(dbell);
638 err_dbell:
639 iounmap(rmu_regs_win);
640 err_rmu:
641 kfree(ops);
642 err_ops:
643 iounmap(rio_regs_win);
644 err_rio_regs:
645 return rc;
646 }
647
648 /* The probe function for RapidIO peer-to-peer network.
649 */
650 static int fsl_of_rio_rpn_probe(struct platform_device *dev)
651 {
652 printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n",
653 dev->dev.of_node->full_name);
654
655 return fsl_rio_setup(dev);
656 };
657
658 static const struct of_device_id fsl_of_rio_rpn_ids[] = {
659 {
660 .compatible = "fsl,srio",
661 },
662 {},
663 };
664
665 static struct platform_driver fsl_of_rio_rpn_driver = {
666 .driver = {
667 .name = "fsl-of-rio",
668 .owner = THIS_MODULE,
669 .of_match_table = fsl_of_rio_rpn_ids,
670 },
671 .probe = fsl_of_rio_rpn_probe,
672 };
673
674 static __init int fsl_of_rio_rpn_init(void)
675 {
676 return platform_driver_register(&fsl_of_rio_rpn_driver);
677 }
678
679 subsys_initcall(fsl_of_rio_rpn_init);
Linux with added FPC-III support