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watchdog/core: Rename some softlockup_* functions
[linux/fpc-iii.git] / drivers / iommu / intel_irq_remapping.c
bloba5b89f6bcdbf08af9e4bfb75d1baf1e063735708
1
2 #define pr_fmt(fmt) "DMAR-IR: " fmt
3
4 #include <linux/interrupt.h>
5 #include <linux/dmar.h>
6 #include <linux/spinlock.h>
7 #include <linux/slab.h>
8 #include <linux/jiffies.h>
9 #include <linux/hpet.h>
10 #include <linux/pci.h>
11 #include <linux/irq.h>
12 #include <linux/intel-iommu.h>
13 #include <linux/acpi.h>
14 #include <linux/irqdomain.h>
15 #include <linux/crash_dump.h>
16 #include <asm/io_apic.h>
17 #include <asm/smp.h>
18 #include <asm/cpu.h>
19 #include <asm/irq_remapping.h>
20 #include <asm/pci-direct.h>
21 #include <asm/msidef.h>
22
23 #include "irq_remapping.h"
24
25 enum irq_mode {
26 IRQ_REMAPPING,
27 IRQ_POSTING,
28 };
29
30 struct ioapic_scope {
31 struct intel_iommu *iommu;
32 unsigned int id;
33 unsigned int bus; /* PCI bus number */
34 unsigned int devfn; /* PCI devfn number */
35 };
36
37 struct hpet_scope {
38 struct intel_iommu *iommu;
39 u8 id;
40 unsigned int bus;
41 unsigned int devfn;
42 };
43
44 struct irq_2_iommu {
45 struct intel_iommu *iommu;
46 u16 irte_index;
47 u16 sub_handle;
48 u8 irte_mask;
49 enum irq_mode mode;
50 };
51
52 struct intel_ir_data {
53 struct irq_2_iommu irq_2_iommu;
54 struct irte irte_entry;
55 union {
56 struct msi_msg msi_entry;
57 };
58 };
59
60 #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
61 #define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8)
62
63 static int __read_mostly eim_mode;
64 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
65 static struct hpet_scope ir_hpet[MAX_HPET_TBS];
66
67 /*
68 * Lock ordering:
69 * ->dmar_global_lock
70 * ->irq_2_ir_lock
71 * ->qi->q_lock
72 * ->iommu->register_lock
73 * Note:
74 * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called
75 * in single-threaded environment with interrupt disabled, so no need to tabke
76 * the dmar_global_lock.
77 */
78 static DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
79 static const struct irq_domain_ops intel_ir_domain_ops;
80
81 static void iommu_disable_irq_remapping(struct intel_iommu *iommu);
82 static int __init parse_ioapics_under_ir(void);
83
84 static bool ir_pre_enabled(struct intel_iommu *iommu)
85 {
86 return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED);
87 }
88
89 static void clear_ir_pre_enabled(struct intel_iommu *iommu)
90 {
91 iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
92 }
93
94 static void init_ir_status(struct intel_iommu *iommu)
95 {
96 u32 gsts;
97
98 gsts = readl(iommu->reg + DMAR_GSTS_REG);
99 if (gsts & DMA_GSTS_IRES)
100 iommu->flags |= VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
101 }
102
103 static int alloc_irte(struct intel_iommu *iommu, int irq,
104 struct irq_2_iommu *irq_iommu, u16 count)
105 {
106 struct ir_table *table = iommu->ir_table;
107 unsigned int mask = 0;
108 unsigned long flags;
109 int index;
110
111 if (!count || !irq_iommu)
112 return -1;
113
114 if (count > 1) {
115 count = __roundup_pow_of_two(count);
116 mask = ilog2(count);
117 }
118
119 if (mask > ecap_max_handle_mask(iommu->ecap)) {
120 pr_err("Requested mask %x exceeds the max invalidation handle"
121 " mask value %Lx\n", mask,
122 ecap_max_handle_mask(iommu->ecap));
123 return -1;
124 }
125
126 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
127 index = bitmap_find_free_region(table->bitmap,
128 INTR_REMAP_TABLE_ENTRIES, mask);
129 if (index < 0) {
130 pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id);
131 } else {
132 irq_iommu->iommu = iommu;
133 irq_iommu->irte_index = index;
134 irq_iommu->sub_handle = 0;
135 irq_iommu->irte_mask = mask;
136 irq_iommu->mode = IRQ_REMAPPING;
137 }
138 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
139
140 return index;
141 }
142
143 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
144 {
145 struct qi_desc desc;
146
147 desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
148 | QI_IEC_SELECTIVE;
149 desc.high = 0;
150
151 return qi_submit_sync(&desc, iommu);
152 }
153
154 static int modify_irte(struct irq_2_iommu *irq_iommu,
155 struct irte *irte_modified)
156 {
157 struct intel_iommu *iommu;
158 unsigned long flags;
159 struct irte *irte;
160 int rc, index;
161
162 if (!irq_iommu)
163 return -1;
164
165 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
166
167 iommu = irq_iommu->iommu;
168
169 index = irq_iommu->irte_index + irq_iommu->sub_handle;
170 irte = &iommu->ir_table->base[index];
171
172 #if defined(CONFIG_HAVE_CMPXCHG_DOUBLE)
173 if ((irte->pst == 1) || (irte_modified->pst == 1)) {
174 bool ret;
175
176 ret = cmpxchg_double(&irte->low, &irte->high,
177 irte->low, irte->high,
178 irte_modified->low, irte_modified->high);
179 /*
180 * We use cmpxchg16 to atomically update the 128-bit IRTE,
181 * and it cannot be updated by the hardware or other processors
182 * behind us, so the return value of cmpxchg16 should be the
183 * same as the old value.
184 */
185 WARN_ON(!ret);
186 } else
187 #endif
188 {
189 set_64bit(&irte->low, irte_modified->low);
190 set_64bit(&irte->high, irte_modified->high);
191 }
192 __iommu_flush_cache(iommu, irte, sizeof(*irte));
193
194 rc = qi_flush_iec(iommu, index, 0);
195
196 /* Update iommu mode according to the IRTE mode */
197 irq_iommu->mode = irte->pst ? IRQ_POSTING : IRQ_REMAPPING;
198 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
199
200 return rc;
201 }
202
203 static struct intel_iommu *map_hpet_to_ir(u8 hpet_id)
204 {
205 int i;
206
207 for (i = 0; i < MAX_HPET_TBS; i++)
208 if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu)
209 return ir_hpet[i].iommu;
210 return NULL;
211 }
212
213 static struct intel_iommu *map_ioapic_to_ir(int apic)
214 {
215 int i;
216
217 for (i = 0; i < MAX_IO_APICS; i++)
218 if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu)
219 return ir_ioapic[i].iommu;
220 return NULL;
221 }
222
223 static struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
224 {
225 struct dmar_drhd_unit *drhd;
226
227 drhd = dmar_find_matched_drhd_unit(dev);
228 if (!drhd)
229 return NULL;
230
231 return drhd->iommu;
232 }
233
234 static int clear_entries(struct irq_2_iommu *irq_iommu)
235 {
236 struct irte *start, *entry, *end;
237 struct intel_iommu *iommu;
238 int index;
239
240 if (irq_iommu->sub_handle)
241 return 0;
242
243 iommu = irq_iommu->iommu;
244 index = irq_iommu->irte_index;
245
246 start = iommu->ir_table->base + index;
247 end = start + (1 << irq_iommu->irte_mask);
248
249 for (entry = start; entry < end; entry++) {
250 set_64bit(&entry->low, 0);
251 set_64bit(&entry->high, 0);
252 }
253 bitmap_release_region(iommu->ir_table->bitmap, index,
254 irq_iommu->irte_mask);
255
256 return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
257 }
258
259 /*
260 * source validation type
261 */
262 #define SVT_NO_VERIFY 0x0 /* no verification is required */
263 #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */
264 #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
265
266 /*
267 * source-id qualifier
268 */
269 #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
270 #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
271 * the third least significant bit
272 */
273 #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
274 * the second and third least significant bits
275 */
276 #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
277 * the least three significant bits
278 */
279
280 /*
281 * set SVT, SQ and SID fields of irte to verify
282 * source ids of interrupt requests
283 */
284 static void set_irte_sid(struct irte *irte, unsigned int svt,
285 unsigned int sq, unsigned int sid)
286 {
287 if (disable_sourceid_checking)
288 svt = SVT_NO_VERIFY;
289 irte->svt = svt;
290 irte->sq = sq;
291 irte->sid = sid;
292 }
293
294 static int set_ioapic_sid(struct irte *irte, int apic)
295 {
296 int i;
297 u16 sid = 0;
298
299 if (!irte)
300 return -1;
301
302 down_read(&dmar_global_lock);
303 for (i = 0; i < MAX_IO_APICS; i++) {
304 if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) {
305 sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
306 break;
307 }
308 }
309 up_read(&dmar_global_lock);
310
311 if (sid == 0) {
312 pr_warn("Failed to set source-id of IOAPIC (%d)\n", apic);
313 return -1;
314 }
315
316 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid);
317
318 return 0;
319 }
320
321 static int set_hpet_sid(struct irte *irte, u8 id)
322 {
323 int i;
324 u16 sid = 0;
325
326 if (!irte)
327 return -1;
328
329 down_read(&dmar_global_lock);
330 for (i = 0; i < MAX_HPET_TBS; i++) {
331 if (ir_hpet[i].iommu && ir_hpet[i].id == id) {
332 sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
333 break;
334 }
335 }
336 up_read(&dmar_global_lock);
337
338 if (sid == 0) {
339 pr_warn("Failed to set source-id of HPET block (%d)\n", id);
340 return -1;
341 }
342
343 /*
344 * Should really use SQ_ALL_16. Some platforms are broken.
345 * While we figure out the right quirks for these broken platforms, use
346 * SQ_13_IGNORE_3 for now.
347 */
348 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
349
350 return 0;
351 }
352
353 struct set_msi_sid_data {
354 struct pci_dev *pdev;
355 u16 alias;
356 };
357
358 static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque)
359 {
360 struct set_msi_sid_data *data = opaque;
361
362 data->pdev = pdev;
363 data->alias = alias;
364
365 return 0;
366 }
367
368 static int set_msi_sid(struct irte *irte, struct pci_dev *dev)
369 {
370 struct set_msi_sid_data data;
371
372 if (!irte || !dev)
373 return -1;
374
375 pci_for_each_dma_alias(dev, set_msi_sid_cb, &data);
376
377 /*
378 * DMA alias provides us with a PCI device and alias. The only case
379 * where the it will return an alias on a different bus than the
380 * device is the case of a PCIe-to-PCI bridge, where the alias is for
381 * the subordinate bus. In this case we can only verify the bus.
382 *
383 * If the alias device is on a different bus than our source device
384 * then we have a topology based alias, use it.
385 *
386 * Otherwise, the alias is for a device DMA quirk and we cannot
387 * assume that MSI uses the same requester ID. Therefore use the
388 * original device.
389 */
390 if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number)
391 set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
392 PCI_DEVID(PCI_BUS_NUM(data.alias),
393 dev->bus->number));
394 else if (data.pdev->bus->number != dev->bus->number)
395 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias);
396 else
397 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
398 PCI_DEVID(dev->bus->number, dev->devfn));
399
400 return 0;
401 }
402
403 static int iommu_load_old_irte(struct intel_iommu *iommu)
404 {
405 struct irte *old_ir_table;
406 phys_addr_t irt_phys;
407 unsigned int i;
408 size_t size;
409 u64 irta;
410
411 /* Check whether the old ir-table has the same size as ours */
412 irta = dmar_readq(iommu->reg + DMAR_IRTA_REG);
413 if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK)
414 != INTR_REMAP_TABLE_REG_SIZE)
415 return -EINVAL;
416
417 irt_phys = irta & VTD_PAGE_MASK;
418 size = INTR_REMAP_TABLE_ENTRIES*sizeof(struct irte);
419
420 /* Map the old IR table */
421 old_ir_table = memremap(irt_phys, size, MEMREMAP_WB);
422 if (!old_ir_table)
423 return -ENOMEM;
424
425 /* Copy data over */
426 memcpy(iommu->ir_table->base, old_ir_table, size);
427
428 __iommu_flush_cache(iommu, iommu->ir_table->base, size);
429
430 /*
431 * Now check the table for used entries and mark those as
432 * allocated in the bitmap
433 */
434 for (i = 0; i < INTR_REMAP_TABLE_ENTRIES; i++) {
435 if (iommu->ir_table->base[i].present)
436 bitmap_set(iommu->ir_table->bitmap, i, 1);
437 }
438
439 memunmap(old_ir_table);
440
441 return 0;
442 }
443
444
445 static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
446 {
447 unsigned long flags;
448 u64 addr;
449 u32 sts;
450
451 addr = virt_to_phys((void *)iommu->ir_table->base);
452
453 raw_spin_lock_irqsave(&iommu->register_lock, flags);
454
455 dmar_writeq(iommu->reg + DMAR_IRTA_REG,
456 (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
457
458 /* Set interrupt-remapping table pointer */
459 writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG);
460
461 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
462 readl, (sts & DMA_GSTS_IRTPS), sts);
463 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
464
465 /*
466 * Global invalidation of interrupt entry cache to make sure the
467 * hardware uses the new irq remapping table.
468 */
469 qi_global_iec(iommu);
470 }
471
472 static void iommu_enable_irq_remapping(struct intel_iommu *iommu)
473 {
474 unsigned long flags;
475 u32 sts;
476
477 raw_spin_lock_irqsave(&iommu->register_lock, flags);
478
479 /* Enable interrupt-remapping */
480 iommu->gcmd |= DMA_GCMD_IRE;
481 iommu->gcmd &= ~DMA_GCMD_CFI; /* Block compatibility-format MSIs */
482 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
483
484 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
485 readl, (sts & DMA_GSTS_IRES), sts);
486
487 /*
488 * With CFI clear in the Global Command register, we should be
489 * protected from dangerous (i.e. compatibility) interrupts
490 * regardless of x2apic status. Check just to be sure.
491 */
492 if (sts & DMA_GSTS_CFIS)
493 WARN(1, KERN_WARNING
494 "Compatibility-format IRQs enabled despite intr remapping;\n"
495 "you are vulnerable to IRQ injection.\n");
496
497 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
498 }
499
500 static int intel_setup_irq_remapping(struct intel_iommu *iommu)
501 {
502 struct ir_table *ir_table;
503 struct fwnode_handle *fn;
504 unsigned long *bitmap;
505 struct page *pages;
506
507 if (iommu->ir_table)
508 return 0;
509
510 ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL);
511 if (!ir_table)
512 return -ENOMEM;
513
514 pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO,
515 INTR_REMAP_PAGE_ORDER);
516 if (!pages) {
517 pr_err("IR%d: failed to allocate pages of order %d\n",
518 iommu->seq_id, INTR_REMAP_PAGE_ORDER);
519 goto out_free_table;
520 }
521
522 bitmap = kcalloc(BITS_TO_LONGS(INTR_REMAP_TABLE_ENTRIES),
523 sizeof(long), GFP_ATOMIC);
524 if (bitmap == NULL) {
525 pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id);
526 goto out_free_pages;
527 }
528
529 fn = irq_domain_alloc_named_id_fwnode("INTEL-IR", iommu->seq_id);
530 if (!fn)
531 goto out_free_bitmap;
532
533 iommu->ir_domain =
534 irq_domain_create_hierarchy(arch_get_ir_parent_domain(),
535 0, INTR_REMAP_TABLE_ENTRIES,
536 fn, &intel_ir_domain_ops,
537 iommu);
538 irq_domain_free_fwnode(fn);
539 if (!iommu->ir_domain) {
540 pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id);
541 goto out_free_bitmap;
542 }
543 iommu->ir_msi_domain =
544 arch_create_remap_msi_irq_domain(iommu->ir_domain,
545 "INTEL-IR-MSI",
546 iommu->seq_id);
547
548 ir_table->base = page_address(pages);
549 ir_table->bitmap = bitmap;
550 iommu->ir_table = ir_table;
551
552 /*
553 * If the queued invalidation is already initialized,
554 * shouldn't disable it.
555 */
556 if (!iommu->qi) {
557 /*
558 * Clear previous faults.
559 */
560 dmar_fault(-1, iommu);
561 dmar_disable_qi(iommu);
562
563 if (dmar_enable_qi(iommu)) {
564 pr_err("Failed to enable queued invalidation\n");
565 goto out_free_bitmap;
566 }
567 }
568
569 init_ir_status(iommu);
570
571 if (ir_pre_enabled(iommu)) {
572 if (!is_kdump_kernel()) {
573 pr_warn("IRQ remapping was enabled on %s but we are not in kdump mode\n",
574 iommu->name);
575 clear_ir_pre_enabled(iommu);
576 iommu_disable_irq_remapping(iommu);
577 } else if (iommu_load_old_irte(iommu))
578 pr_err("Failed to copy IR table for %s from previous kernel\n",
579 iommu->name);
580 else
581 pr_info("Copied IR table for %s from previous kernel\n",
582 iommu->name);
583 }
584
585 iommu_set_irq_remapping(iommu, eim_mode);
586
587 return 0;
588
589 out_free_bitmap:
590 kfree(bitmap);
591 out_free_pages:
592 __free_pages(pages, INTR_REMAP_PAGE_ORDER);
593 out_free_table:
594 kfree(ir_table);
595
596 iommu->ir_table = NULL;
597
598 return -ENOMEM;
599 }
600
601 static void intel_teardown_irq_remapping(struct intel_iommu *iommu)
602 {
603 if (iommu && iommu->ir_table) {
604 if (iommu->ir_msi_domain) {
605 irq_domain_remove(iommu->ir_msi_domain);
606 iommu->ir_msi_domain = NULL;
607 }
608 if (iommu->ir_domain) {
609 irq_domain_remove(iommu->ir_domain);
610 iommu->ir_domain = NULL;
611 }
612 free_pages((unsigned long)iommu->ir_table->base,
613 INTR_REMAP_PAGE_ORDER);
614 kfree(iommu->ir_table->bitmap);
615 kfree(iommu->ir_table);
616 iommu->ir_table = NULL;
617 }
618 }
619
620 /*
621 * Disable Interrupt Remapping.
622 */
623 static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
624 {
625 unsigned long flags;
626 u32 sts;
627
628 if (!ecap_ir_support(iommu->ecap))
629 return;
630
631 /*
632 * global invalidation of interrupt entry cache before disabling
633 * interrupt-remapping.
634 */
635 qi_global_iec(iommu);
636
637 raw_spin_lock_irqsave(&iommu->register_lock, flags);
638
639 sts = readl(iommu->reg + DMAR_GSTS_REG);
640 if (!(sts & DMA_GSTS_IRES))
641 goto end;
642
643 iommu->gcmd &= ~DMA_GCMD_IRE;
644 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
645
646 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
647 readl, !(sts & DMA_GSTS_IRES), sts);
648
649 end:
650 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
651 }
652
653 static int __init dmar_x2apic_optout(void)
654 {
655 struct acpi_table_dmar *dmar;
656 dmar = (struct acpi_table_dmar *)dmar_tbl;
657 if (!dmar || no_x2apic_optout)
658 return 0;
659 return dmar->flags & DMAR_X2APIC_OPT_OUT;
660 }
661
662 static void __init intel_cleanup_irq_remapping(void)
663 {
664 struct dmar_drhd_unit *drhd;
665 struct intel_iommu *iommu;
666
667 for_each_iommu(iommu, drhd) {
668 if (ecap_ir_support(iommu->ecap)) {
669 iommu_disable_irq_remapping(iommu);
670 intel_teardown_irq_remapping(iommu);
671 }
672 }
673
674 if (x2apic_supported())
675 pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
676 }
677
678 static int __init intel_prepare_irq_remapping(void)
679 {
680 struct dmar_drhd_unit *drhd;
681 struct intel_iommu *iommu;
682 int eim = 0;
683
684 if (irq_remap_broken) {
685 pr_warn("This system BIOS has enabled interrupt remapping\n"
686 "on a chipset that contains an erratum making that\n"
687 "feature unstable. To maintain system stability\n"
688 "interrupt remapping is being disabled. Please\n"
689 "contact your BIOS vendor for an update\n");
690 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
691 return -ENODEV;
692 }
693
694 if (dmar_table_init() < 0)
695 return -ENODEV;
696
697 if (!dmar_ir_support())
698 return -ENODEV;
699
700 if (parse_ioapics_under_ir()) {
701 pr_info("Not enabling interrupt remapping\n");
702 goto error;
703 }
704
705 /* First make sure all IOMMUs support IRQ remapping */
706 for_each_iommu(iommu, drhd)
707 if (!ecap_ir_support(iommu->ecap))
708 goto error;
709
710 /* Detect remapping mode: lapic or x2apic */
711 if (x2apic_supported()) {
712 eim = !dmar_x2apic_optout();
713 if (!eim) {
714 pr_info("x2apic is disabled because BIOS sets x2apic opt out bit.");
715 pr_info("Use 'intremap=no_x2apic_optout' to override the BIOS setting.\n");
716 }
717 }
718
719 for_each_iommu(iommu, drhd) {
720 if (eim && !ecap_eim_support(iommu->ecap)) {
721 pr_info("%s does not support EIM\n", iommu->name);
722 eim = 0;
723 }
724 }
725
726 eim_mode = eim;
727 if (eim)
728 pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
729
730 /* Do the initializations early */
731 for_each_iommu(iommu, drhd) {
732 if (intel_setup_irq_remapping(iommu)) {
733 pr_err("Failed to setup irq remapping for %s\n",
734 iommu->name);
735 goto error;
736 }
737 }
738
739 return 0;
740
741 error:
742 intel_cleanup_irq_remapping();
743 return -ENODEV;
744 }
745
746 /*
747 * Set Posted-Interrupts capability.
748 */
749 static inline void set_irq_posting_cap(void)
750 {
751 struct dmar_drhd_unit *drhd;
752 struct intel_iommu *iommu;
753
754 if (!disable_irq_post) {
755 /*
756 * If IRTE is in posted format, the 'pda' field goes across the
757 * 64-bit boundary, we need use cmpxchg16b to atomically update
758 * it. We only expose posted-interrupt when X86_FEATURE_CX16
759 * is supported. Actually, hardware platforms supporting PI
760 * should have X86_FEATURE_CX16 support, this has been confirmed
761 * with Intel hardware guys.
762 */
763 if (boot_cpu_has(X86_FEATURE_CX16))
764 intel_irq_remap_ops.capability |= 1 << IRQ_POSTING_CAP;
765
766 for_each_iommu(iommu, drhd)
767 if (!cap_pi_support(iommu->cap)) {
768 intel_irq_remap_ops.capability &=
769 ~(1 << IRQ_POSTING_CAP);
770 break;
771 }
772 }
773 }
774
775 static int __init intel_enable_irq_remapping(void)
776 {
777 struct dmar_drhd_unit *drhd;
778 struct intel_iommu *iommu;
779 bool setup = false;
780
781 /*
782 * Setup Interrupt-remapping for all the DRHD's now.
783 */
784 for_each_iommu(iommu, drhd) {
785 if (!ir_pre_enabled(iommu))
786 iommu_enable_irq_remapping(iommu);
787 setup = true;
788 }
789
790 if (!setup)
791 goto error;
792
793 irq_remapping_enabled = 1;
794
795 set_irq_posting_cap();
796
797 pr_info("Enabled IRQ remapping in %s mode\n", eim_mode ? "x2apic" : "xapic");
798
799 return eim_mode ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE;
800
801 error:
802 intel_cleanup_irq_remapping();
803 return -1;
804 }
805
806 static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
807 struct intel_iommu *iommu,
808 struct acpi_dmar_hardware_unit *drhd)
809 {
810 struct acpi_dmar_pci_path *path;
811 u8 bus;
812 int count, free = -1;
813
814 bus = scope->bus;
815 path = (struct acpi_dmar_pci_path *)(scope + 1);
816 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
817 / sizeof(struct acpi_dmar_pci_path);
818
819 while (--count > 0) {
820 /*
821 * Access PCI directly due to the PCI
822 * subsystem isn't initialized yet.
823 */
824 bus = read_pci_config_byte(bus, path->device, path->function,
825 PCI_SECONDARY_BUS);
826 path++;
827 }
828
829 for (count = 0; count < MAX_HPET_TBS; count++) {
830 if (ir_hpet[count].iommu == iommu &&
831 ir_hpet[count].id == scope->enumeration_id)
832 return 0;
833 else if (ir_hpet[count].iommu == NULL && free == -1)
834 free = count;
835 }
836 if (free == -1) {
837 pr_warn("Exceeded Max HPET blocks\n");
838 return -ENOSPC;
839 }
840
841 ir_hpet[free].iommu = iommu;
842 ir_hpet[free].id = scope->enumeration_id;
843 ir_hpet[free].bus = bus;
844 ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function);
845 pr_info("HPET id %d under DRHD base 0x%Lx\n",
846 scope->enumeration_id, drhd->address);
847
848 return 0;
849 }
850
851 static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
852 struct intel_iommu *iommu,
853 struct acpi_dmar_hardware_unit *drhd)
854 {
855 struct acpi_dmar_pci_path *path;
856 u8 bus;
857 int count, free = -1;
858
859 bus = scope->bus;
860 path = (struct acpi_dmar_pci_path *)(scope + 1);
861 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
862 / sizeof(struct acpi_dmar_pci_path);
863
864 while (--count > 0) {
865 /*
866 * Access PCI directly due to the PCI
867 * subsystem isn't initialized yet.
868 */
869 bus = read_pci_config_byte(bus, path->device, path->function,
870 PCI_SECONDARY_BUS);
871 path++;
872 }
873
874 for (count = 0; count < MAX_IO_APICS; count++) {
875 if (ir_ioapic[count].iommu == iommu &&
876 ir_ioapic[count].id == scope->enumeration_id)
877 return 0;
878 else if (ir_ioapic[count].iommu == NULL && free == -1)
879 free = count;
880 }
881 if (free == -1) {
882 pr_warn("Exceeded Max IO APICS\n");
883 return -ENOSPC;
884 }
885
886 ir_ioapic[free].bus = bus;
887 ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function);
888 ir_ioapic[free].iommu = iommu;
889 ir_ioapic[free].id = scope->enumeration_id;
890 pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n",
891 scope->enumeration_id, drhd->address, iommu->seq_id);
892
893 return 0;
894 }
895
896 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
897 struct intel_iommu *iommu)
898 {
899 int ret = 0;
900 struct acpi_dmar_hardware_unit *drhd;
901 struct acpi_dmar_device_scope *scope;
902 void *start, *end;
903
904 drhd = (struct acpi_dmar_hardware_unit *)header;
905 start = (void *)(drhd + 1);
906 end = ((void *)drhd) + header->length;
907
908 while (start < end && ret == 0) {
909 scope = start;
910 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC)
911 ret = ir_parse_one_ioapic_scope(scope, iommu, drhd);
912 else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET)
913 ret = ir_parse_one_hpet_scope(scope, iommu, drhd);
914 start += scope->length;
915 }
916
917 return ret;
918 }
919
920 static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu)
921 {
922 int i;
923
924 for (i = 0; i < MAX_HPET_TBS; i++)
925 if (ir_hpet[i].iommu == iommu)
926 ir_hpet[i].iommu = NULL;
927
928 for (i = 0; i < MAX_IO_APICS; i++)
929 if (ir_ioapic[i].iommu == iommu)
930 ir_ioapic[i].iommu = NULL;
931 }
932
933 /*
934 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
935 * hardware unit.
936 */
937 static int __init parse_ioapics_under_ir(void)
938 {
939 struct dmar_drhd_unit *drhd;
940 struct intel_iommu *iommu;
941 bool ir_supported = false;
942 int ioapic_idx;
943
944 for_each_iommu(iommu, drhd) {
945 int ret;
946
947 if (!ecap_ir_support(iommu->ecap))
948 continue;
949
950 ret = ir_parse_ioapic_hpet_scope(drhd->hdr, iommu);
951 if (ret)
952 return ret;
953
954 ir_supported = true;
955 }
956
957 if (!ir_supported)
958 return -ENODEV;
959
960 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
961 int ioapic_id = mpc_ioapic_id(ioapic_idx);
962 if (!map_ioapic_to_ir(ioapic_id)) {
963 pr_err(FW_BUG "ioapic %d has no mapping iommu, "
964 "interrupt remapping will be disabled\n",
965 ioapic_id);
966 return -1;
967 }
968 }
969
970 return 0;
971 }
972
973 static int __init ir_dev_scope_init(void)
974 {
975 int ret;
976
977 if (!irq_remapping_enabled)
978 return 0;
979
980 down_write(&dmar_global_lock);
981 ret = dmar_dev_scope_init();
982 up_write(&dmar_global_lock);
983
984 return ret;
985 }
986 rootfs_initcall(ir_dev_scope_init);
987
988 static void disable_irq_remapping(void)
989 {
990 struct dmar_drhd_unit *drhd;
991 struct intel_iommu *iommu = NULL;
992
993 /*
994 * Disable Interrupt-remapping for all the DRHD's now.
995 */
996 for_each_iommu(iommu, drhd) {
997 if (!ecap_ir_support(iommu->ecap))
998 continue;
999
1000 iommu_disable_irq_remapping(iommu);
1001 }
1002
1003 /*
1004 * Clear Posted-Interrupts capability.
1005 */
1006 if (!disable_irq_post)
1007 intel_irq_remap_ops.capability &= ~(1 << IRQ_POSTING_CAP);
1008 }
1009
1010 static int reenable_irq_remapping(int eim)
1011 {
1012 struct dmar_drhd_unit *drhd;
1013 bool setup = false;
1014 struct intel_iommu *iommu = NULL;
1015
1016 for_each_iommu(iommu, drhd)
1017 if (iommu->qi)
1018 dmar_reenable_qi(iommu);
1019
1020 /*
1021 * Setup Interrupt-remapping for all the DRHD's now.
1022 */
1023 for_each_iommu(iommu, drhd) {
1024 if (!ecap_ir_support(iommu->ecap))
1025 continue;
1026
1027 /* Set up interrupt remapping for iommu.*/
1028 iommu_set_irq_remapping(iommu, eim);
1029 iommu_enable_irq_remapping(iommu);
1030 setup = true;
1031 }
1032
1033 if (!setup)
1034 goto error;
1035
1036 set_irq_posting_cap();
1037
1038 return 0;
1039
1040 error:
1041 /*
1042 * handle error condition gracefully here!
1043 */
1044 return -1;
1045 }
1046
1047 static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
1048 {
1049 memset(irte, 0, sizeof(*irte));
1050
1051 irte->present = 1;
1052 irte->dst_mode = apic->irq_dest_mode;
1053 /*
1054 * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
1055 * actual level or edge trigger will be setup in the IO-APIC
1056 * RTE. This will help simplify level triggered irq migration.
1057 * For more details, see the comments (in io_apic.c) explainig IO-APIC
1058 * irq migration in the presence of interrupt-remapping.
1059 */
1060 irte->trigger_mode = 0;
1061 irte->dlvry_mode = apic->irq_delivery_mode;
1062 irte->vector = vector;
1063 irte->dest_id = IRTE_DEST(dest);
1064 irte->redir_hint = 1;
1065 }
1066
1067 static struct irq_domain *intel_get_ir_irq_domain(struct irq_alloc_info *info)
1068 {
1069 struct intel_iommu *iommu = NULL;
1070
1071 if (!info)
1072 return NULL;
1073
1074 switch (info->type) {
1075 case X86_IRQ_ALLOC_TYPE_IOAPIC:
1076 iommu = map_ioapic_to_ir(info->ioapic_id);
1077 break;
1078 case X86_IRQ_ALLOC_TYPE_HPET:
1079 iommu = map_hpet_to_ir(info->hpet_id);
1080 break;
1081 case X86_IRQ_ALLOC_TYPE_MSI:
1082 case X86_IRQ_ALLOC_TYPE_MSIX:
1083 iommu = map_dev_to_ir(info->msi_dev);
1084 break;
1085 default:
1086 BUG_ON(1);
1087 break;
1088 }
1089
1090 return iommu ? iommu->ir_domain : NULL;
1091 }
1092
1093 static struct irq_domain *intel_get_irq_domain(struct irq_alloc_info *info)
1094 {
1095 struct intel_iommu *iommu;
1096
1097 if (!info)
1098 return NULL;
1099
1100 switch (info->type) {
1101 case X86_IRQ_ALLOC_TYPE_MSI:
1102 case X86_IRQ_ALLOC_TYPE_MSIX:
1103 iommu = map_dev_to_ir(info->msi_dev);
1104 if (iommu)
1105 return iommu->ir_msi_domain;
1106 break;
1107 default:
1108 break;
1109 }
1110
1111 return NULL;
1112 }
1113
1114 struct irq_remap_ops intel_irq_remap_ops = {
1115 .prepare = intel_prepare_irq_remapping,
1116 .enable = intel_enable_irq_remapping,
1117 .disable = disable_irq_remapping,
1118 .reenable = reenable_irq_remapping,
1119 .enable_faulting = enable_drhd_fault_handling,
1120 .get_ir_irq_domain = intel_get_ir_irq_domain,
1121 .get_irq_domain = intel_get_irq_domain,
1122 };
1123
1124 /*
1125 * Migrate the IO-APIC irq in the presence of intr-remapping.
1126 *
1127 * For both level and edge triggered, irq migration is a simple atomic
1128 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
1129 *
1130 * For level triggered, we eliminate the io-apic RTE modification (with the
1131 * updated vector information), by using a virtual vector (io-apic pin number).
1132 * Real vector that is used for interrupting cpu will be coming from
1133 * the interrupt-remapping table entry.
1134 *
1135 * As the migration is a simple atomic update of IRTE, the same mechanism
1136 * is used to migrate MSI irq's in the presence of interrupt-remapping.
1137 */
1138 static int
1139 intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask,
1140 bool force)
1141 {
1142 struct intel_ir_data *ir_data = data->chip_data;
1143 struct irte *irte = &ir_data->irte_entry;
1144 struct irq_cfg *cfg = irqd_cfg(data);
1145 struct irq_data *parent = data->parent_data;
1146 int ret;
1147
1148 ret = parent->chip->irq_set_affinity(parent, mask, force);
1149 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
1150 return ret;
1151
1152 /*
1153 * Atomically updates the IRTE with the new destination, vector
1154 * and flushes the interrupt entry cache.
1155 */
1156 irte->vector = cfg->vector;
1157 irte->dest_id = IRTE_DEST(cfg->dest_apicid);
1158
1159 /* Update the hardware only if the interrupt is in remapped mode. */
1160 if (ir_data->irq_2_iommu.mode == IRQ_REMAPPING)
1161 modify_irte(&ir_data->irq_2_iommu, irte);
1162
1163 /*
1164 * After this point, all the interrupts will start arriving
1165 * at the new destination. So, time to cleanup the previous
1166 * vector allocation.
1167 */
1168 send_cleanup_vector(cfg);
1169
1170 return IRQ_SET_MASK_OK_DONE;
1171 }
1172
1173 static void intel_ir_compose_msi_msg(struct irq_data *irq_data,
1174 struct msi_msg *msg)
1175 {
1176 struct intel_ir_data *ir_data = irq_data->chip_data;
1177
1178 *msg = ir_data->msi_entry;
1179 }
1180
1181 static int intel_ir_set_vcpu_affinity(struct irq_data *data, void *info)
1182 {
1183 struct intel_ir_data *ir_data = data->chip_data;
1184 struct vcpu_data *vcpu_pi_info = info;
1185
1186 /* stop posting interrupts, back to remapping mode */
1187 if (!vcpu_pi_info) {
1188 modify_irte(&ir_data->irq_2_iommu, &ir_data->irte_entry);
1189 } else {
1190 struct irte irte_pi;
1191
1192 /*
1193 * We are not caching the posted interrupt entry. We
1194 * copy the data from the remapped entry and modify
1195 * the fields which are relevant for posted mode. The
1196 * cached remapped entry is used for switching back to
1197 * remapped mode.
1198 */
1199 memset(&irte_pi, 0, sizeof(irte_pi));
1200 dmar_copy_shared_irte(&irte_pi, &ir_data->irte_entry);
1201
1202 /* Update the posted mode fields */
1203 irte_pi.p_pst = 1;
1204 irte_pi.p_urgent = 0;
1205 irte_pi.p_vector = vcpu_pi_info->vector;
1206 irte_pi.pda_l = (vcpu_pi_info->pi_desc_addr >>
1207 (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT);
1208 irte_pi.pda_h = (vcpu_pi_info->pi_desc_addr >> 32) &
1209 ~(-1UL << PDA_HIGH_BIT);
1210
1211 modify_irte(&ir_data->irq_2_iommu, &irte_pi);
1212 }
1213
1214 return 0;
1215 }
1216
1217 static struct irq_chip intel_ir_chip = {
1218 .name = "INTEL-IR",
1219 .irq_ack = ir_ack_apic_edge,
1220 .irq_set_affinity = intel_ir_set_affinity,
1221 .irq_compose_msi_msg = intel_ir_compose_msi_msg,
1222 .irq_set_vcpu_affinity = intel_ir_set_vcpu_affinity,
1223 };
1224
1225 static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
1226 struct irq_cfg *irq_cfg,
1227 struct irq_alloc_info *info,
1228 int index, int sub_handle)
1229 {
1230 struct IR_IO_APIC_route_entry *entry;
1231 struct irte *irte = &data->irte_entry;
1232 struct msi_msg *msg = &data->msi_entry;
1233
1234 prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid);
1235 switch (info->type) {
1236 case X86_IRQ_ALLOC_TYPE_IOAPIC:
1237 /* Set source-id of interrupt request */
1238 set_ioapic_sid(irte, info->ioapic_id);
1239 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n",
1240 info->ioapic_id, irte->present, irte->fpd,
1241 irte->dst_mode, irte->redir_hint,
1242 irte->trigger_mode, irte->dlvry_mode,
1243 irte->avail, irte->vector, irte->dest_id,
1244 irte->sid, irte->sq, irte->svt);
1245
1246 entry = (struct IR_IO_APIC_route_entry *)info->ioapic_entry;
1247 info->ioapic_entry = NULL;
1248 memset(entry, 0, sizeof(*entry));
1249 entry->index2 = (index >> 15) & 0x1;
1250 entry->zero = 0;
1251 entry->format = 1;
1252 entry->index = (index & 0x7fff);
1253 /*
1254 * IO-APIC RTE will be configured with virtual vector.
1255 * irq handler will do the explicit EOI to the io-apic.
1256 */
1257 entry->vector = info->ioapic_pin;
1258 entry->mask = 0; /* enable IRQ */
1259 entry->trigger = info->ioapic_trigger;
1260 entry->polarity = info->ioapic_polarity;
1261 if (info->ioapic_trigger)
1262 entry->mask = 1; /* Mask level triggered irqs. */
1263 break;
1264
1265 case X86_IRQ_ALLOC_TYPE_HPET:
1266 case X86_IRQ_ALLOC_TYPE_MSI:
1267 case X86_IRQ_ALLOC_TYPE_MSIX:
1268 if (info->type == X86_IRQ_ALLOC_TYPE_HPET)
1269 set_hpet_sid(irte, info->hpet_id);
1270 else
1271 set_msi_sid(irte, info->msi_dev);
1272
1273 msg->address_hi = MSI_ADDR_BASE_HI;
1274 msg->data = sub_handle;
1275 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
1276 MSI_ADDR_IR_SHV |
1277 MSI_ADDR_IR_INDEX1(index) |
1278 MSI_ADDR_IR_INDEX2(index);
1279 break;
1280
1281 default:
1282 BUG_ON(1);
1283 break;
1284 }
1285 }
1286
1287 static void intel_free_irq_resources(struct irq_domain *domain,
1288 unsigned int virq, unsigned int nr_irqs)
1289 {
1290 struct irq_data *irq_data;
1291 struct intel_ir_data *data;
1292 struct irq_2_iommu *irq_iommu;
1293 unsigned long flags;
1294 int i;
1295 for (i = 0; i < nr_irqs; i++) {
1296 irq_data = irq_domain_get_irq_data(domain, virq + i);
1297 if (irq_data && irq_data->chip_data) {
1298 data = irq_data->chip_data;
1299 irq_iommu = &data->irq_2_iommu;
1300 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
1301 clear_entries(irq_iommu);
1302 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
1303 irq_domain_reset_irq_data(irq_data);
1304 kfree(data);
1305 }
1306 }
1307 }
1308
1309 static int intel_irq_remapping_alloc(struct irq_domain *domain,
1310 unsigned int virq, unsigned int nr_irqs,
1311 void *arg)
1312 {
1313 struct intel_iommu *iommu = domain->host_data;
1314 struct irq_alloc_info *info = arg;
1315 struct intel_ir_data *data, *ird;
1316 struct irq_data *irq_data;
1317 struct irq_cfg *irq_cfg;
1318 int i, ret, index;
1319
1320 if (!info || !iommu)
1321 return -EINVAL;
1322 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
1323 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
1324 return -EINVAL;
1325
1326 /*
1327 * With IRQ remapping enabled, don't need contiguous CPU vectors
1328 * to support multiple MSI interrupts.
1329 */
1330 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
1331 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
1332
1333 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
1334 if (ret < 0)
1335 return ret;
1336
1337 ret = -ENOMEM;
1338 data = kzalloc(sizeof(*data), GFP_KERNEL);
1339 if (!data)
1340 goto out_free_parent;
1341
1342 down_read(&dmar_global_lock);
1343 index = alloc_irte(iommu, virq, &data->irq_2_iommu, nr_irqs);
1344 up_read(&dmar_global_lock);
1345 if (index < 0) {
1346 pr_warn("Failed to allocate IRTE\n");
1347 kfree(data);
1348 goto out_free_parent;
1349 }
1350
1351 for (i = 0; i < nr_irqs; i++) {
1352 irq_data = irq_domain_get_irq_data(domain, virq + i);
1353 irq_cfg = irqd_cfg(irq_data);
1354 if (!irq_data || !irq_cfg) {
1355 ret = -EINVAL;
1356 goto out_free_data;
1357 }
1358
1359 if (i > 0) {
1360 ird = kzalloc(sizeof(*ird), GFP_KERNEL);
1361 if (!ird)
1362 goto out_free_data;
1363 /* Initialize the common data */
1364 ird->irq_2_iommu = data->irq_2_iommu;
1365 ird->irq_2_iommu.sub_handle = i;
1366 } else {
1367 ird = data;
1368 }
1369
1370 irq_data->hwirq = (index << 16) + i;
1371 irq_data->chip_data = ird;
1372 irq_data->chip = &intel_ir_chip;
1373 intel_irq_remapping_prepare_irte(ird, irq_cfg, info, index, i);
1374 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
1375 }
1376 return 0;
1377
1378 out_free_data:
1379 intel_free_irq_resources(domain, virq, i);
1380 out_free_parent:
1381 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1382 return ret;
1383 }
1384
1385 static void intel_irq_remapping_free(struct irq_domain *domain,
1386 unsigned int virq, unsigned int nr_irqs)
1387 {
1388 intel_free_irq_resources(domain, virq, nr_irqs);
1389 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1390 }
1391
1392 static void intel_irq_remapping_activate(struct irq_domain *domain,
1393 struct irq_data *irq_data)
1394 {
1395 struct intel_ir_data *data = irq_data->chip_data;
1396
1397 modify_irte(&data->irq_2_iommu, &data->irte_entry);
1398 }
1399
1400 static void intel_irq_remapping_deactivate(struct irq_domain *domain,
1401 struct irq_data *irq_data)
1402 {
1403 struct intel_ir_data *data = irq_data->chip_data;
1404 struct irte entry;
1405
1406 memset(&entry, 0, sizeof(entry));
1407 modify_irte(&data->irq_2_iommu, &entry);
1408 }
1409
1410 static const struct irq_domain_ops intel_ir_domain_ops = {
1411 .alloc = intel_irq_remapping_alloc,
1412 .free = intel_irq_remapping_free,
1413 .activate = intel_irq_remapping_activate,
1414 .deactivate = intel_irq_remapping_deactivate,
1415 };
1416
1417 /*
1418 * Support of Interrupt Remapping Unit Hotplug
1419 */
1420 static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu)
1421 {
1422 int ret;
1423 int eim = x2apic_enabled();
1424
1425 if (eim && !ecap_eim_support(iommu->ecap)) {
1426 pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n",
1427 iommu->reg_phys, iommu->ecap);
1428 return -ENODEV;
1429 }
1430
1431 if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) {
1432 pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n",
1433 iommu->reg_phys);
1434 return -ENODEV;
1435 }
1436
1437 /* TODO: check all IOAPICs are covered by IOMMU */
1438
1439 /* Setup Interrupt-remapping now. */
1440 ret = intel_setup_irq_remapping(iommu);
1441 if (ret) {
1442 pr_err("Failed to setup irq remapping for %s\n",
1443 iommu->name);
1444 intel_teardown_irq_remapping(iommu);
1445 ir_remove_ioapic_hpet_scope(iommu);
1446 } else {
1447 iommu_enable_irq_remapping(iommu);
1448 }
1449
1450 return ret;
1451 }
1452
1453 int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
1454 {
1455 int ret = 0;
1456 struct intel_iommu *iommu = dmaru->iommu;
1457
1458 if (!irq_remapping_enabled)
1459 return 0;
1460 if (iommu == NULL)
1461 return -EINVAL;
1462 if (!ecap_ir_support(iommu->ecap))
1463 return 0;
1464 if (irq_remapping_cap(IRQ_POSTING_CAP) &&
1465 !cap_pi_support(iommu->cap))
1466 return -EBUSY;
1467
1468 if (insert) {
1469 if (!iommu->ir_table)
1470 ret = dmar_ir_add(dmaru, iommu);
1471 } else {
1472 if (iommu->ir_table) {
1473 if (!bitmap_empty(iommu->ir_table->bitmap,
1474 INTR_REMAP_TABLE_ENTRIES)) {
1475 ret = -EBUSY;
1476 } else {
1477 iommu_disable_irq_remapping(iommu);
1478 intel_teardown_irq_remapping(iommu);
1479 ir_remove_ioapic_hpet_scope(iommu);
1480 }
1481 }
1482 }
1483
1484 return ret;
1485 }
Linux with added FPC-III support