drivers/net/phy/marvell10g.c

   1 /*
   2  * Marvell 10G 88x3310 PHY driver
   3  *
   4  * Based upon the ID registers, this PHY appears to be a mixture of IPs
   5  * from two different companies.
   6  *
   7  * There appears to be several different data paths through the PHY which
   8  * are automatically managed by the PHY.  The following has been determined
   9  * via observation and experimentation:
  10  *
  11  *       SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
  12  *  10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
  13  *  10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
  14  *
  15  * If both the fiber and copper ports are connected, the first to gain
  16  * link takes priority and the other port is completely locked out.
  17  */
  18 #include <linux/phy.h>
  19
  20 enum {
  21         MV_PCS_BASE_T           = 0x0000,
  22         MV_PCS_BASE_R           = 0x1000,
  23         MV_PCS_1000BASEX        = 0x2000,
  24
  25         /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
  26          * registers appear to set themselves to the 0x800X when AN is
  27          * restarted, but status registers appear readable from either.
  28          */
  29         MV_AN_CTRL1000          = 0x8000, /* 1000base-T control register */
  30         MV_AN_STAT1000          = 0x8001, /* 1000base-T status register */
  31
  32         /* This register appears to reflect the copper status */
  33         MV_AN_RESULT            = 0xa016,
  34         MV_AN_RESULT_SPD_10     = BIT(12),
  35         MV_AN_RESULT_SPD_100    = BIT(13),
  36         MV_AN_RESULT_SPD_1000   = BIT(14),
  37         MV_AN_RESULT_SPD_10000  = BIT(15),
  38 };
  39
  40 static int mv3310_modify(struct phy_device *phydev, int devad, u16 reg,
  41                          u16 mask, u16 bits)
  42 {
  43         int old, val, ret;
  44
  45         old = phy_read_mmd(phydev, devad, reg);
  46         if (old < 0)
  47                 return old;
  48
  49         val = (old & ~mask) | (bits & mask);
  50         if (val == old)
  51                 return 0;
  52
  53         ret = phy_write_mmd(phydev, devad, reg, val);
  54
  55         return ret < 0 ? ret : 1;
  56 }
  57
  58 static int mv3310_probe(struct phy_device *phydev)
  59 {
  60         u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
  61
  62         if (!phydev->is_c45 ||
  63             (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
  64                 return -ENODEV;
  65
  66         return 0;
  67 }
  68
  69 /*
  70  * Resetting the MV88X3310 causes it to become non-responsive.  Avoid
  71  * setting the reset bit(s).
  72  */
  73 static int mv3310_soft_reset(struct phy_device *phydev)
  74 {
  75         return 0;
  76 }
  77
  78 static int mv3310_config_init(struct phy_device *phydev)
  79 {
  80         __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
  81         u32 mask;
  82         int val;
  83
  84         /* Check that the PHY interface type is compatible */
  85         if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
  86             phydev->interface != PHY_INTERFACE_MODE_XGMII &&
  87             phydev->interface != PHY_INTERFACE_MODE_XAUI &&
  88             phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
  89             phydev->interface != PHY_INTERFACE_MODE_10GKR)
  90                 return -ENODEV;
  91
  92         __set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
  93         __set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported);
  94
  95         if (phydev->c45_ids.devices_in_package & MDIO_DEVS_AN) {
  96                 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
  97                 if (val < 0)
  98                         return val;
  99
 100                 if (val & MDIO_AN_STAT1_ABLE)
 101                         __set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported);
 102         }
 103
 104         val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2);
 105         if (val < 0)
 106                 return val;
 107
 108         /* Ethtool does not support the WAN mode bits */
 109         if (val & (MDIO_PMA_STAT2_10GBSR | MDIO_PMA_STAT2_10GBLR |
 110                    MDIO_PMA_STAT2_10GBER | MDIO_PMA_STAT2_10GBLX4 |
 111                    MDIO_PMA_STAT2_10GBSW | MDIO_PMA_STAT2_10GBLW |
 112                    MDIO_PMA_STAT2_10GBEW))
 113                 __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
 114         if (val & MDIO_PMA_STAT2_10GBSR)
 115                 __set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, supported);
 116         if (val & MDIO_PMA_STAT2_10GBLR)
 117                 __set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, supported);
 118         if (val & MDIO_PMA_STAT2_10GBER)
 119                 __set_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, supported);
 120
 121         if (val & MDIO_PMA_STAT2_EXTABLE) {
 122                 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
 123                 if (val < 0)
 124                         return val;
 125
 126                 if (val & (MDIO_PMA_EXTABLE_10GBT | MDIO_PMA_EXTABLE_1000BT |
 127                            MDIO_PMA_EXTABLE_100BTX | MDIO_PMA_EXTABLE_10BT))
 128                         __set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported);
 129                 if (val & MDIO_PMA_EXTABLE_10GBLRM)
 130                         __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
 131                 if (val & (MDIO_PMA_EXTABLE_10GBKX4 | MDIO_PMA_EXTABLE_10GBKR |
 132                            MDIO_PMA_EXTABLE_1000BKX))
 133                         __set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, supported);
 134                 if (val & MDIO_PMA_EXTABLE_10GBLRM)
 135                         __set_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
 136                                   supported);
 137                 if (val & MDIO_PMA_EXTABLE_10GBT)
 138                         __set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
 139                                   supported);
 140                 if (val & MDIO_PMA_EXTABLE_10GBKX4)
 141                         __set_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
 142                                   supported);
 143                 if (val & MDIO_PMA_EXTABLE_10GBKR)
 144                         __set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
 145                                   supported);
 146                 if (val & MDIO_PMA_EXTABLE_1000BT)
 147                         __set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
 148                                   supported);
 149                 if (val & MDIO_PMA_EXTABLE_1000BKX)
 150                         __set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
 151                                   supported);
 152                 if (val & MDIO_PMA_EXTABLE_100BTX)
 153                         __set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
 154                                   supported);
 155                 if (val & MDIO_PMA_EXTABLE_10BT)
 156                         __set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
 157                                   supported);
 158         }
 159
 160         if (!ethtool_convert_link_mode_to_legacy_u32(&mask, supported))
 161                 dev_warn(&phydev->mdio.dev,
 162                          "PHY supports (%*pb) more modes than phylib supports, some modes not supported.\n",
 163                          __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
 164
 165         phydev->supported &= mask;
 166         phydev->advertising &= phydev->supported;
 167
 168         return 0;
 169 }
 170
 171 static int mv3310_config_aneg(struct phy_device *phydev)
 172 {
 173         bool changed = false;
 174         u32 advertising;
 175         int ret;
 176
 177         if (phydev->autoneg == AUTONEG_DISABLE) {
 178                 ret = genphy_c45_pma_setup_forced(phydev);
 179                 if (ret < 0)
 180                         return ret;
 181
 182                 return genphy_c45_an_disable_aneg(phydev);
 183         }
 184
 185         phydev->advertising &= phydev->supported;
 186         advertising = phydev->advertising;
 187
 188         ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
 189                             ADVERTISE_ALL | ADVERTISE_100BASE4 |
 190                             ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
 191                             ethtool_adv_to_mii_adv_t(advertising));
 192         if (ret < 0)
 193                 return ret;
 194         if (ret > 0)
 195                 changed = true;
 196
 197         ret = mv3310_modify(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
 198                             ADVERTISE_1000FULL | ADVERTISE_1000HALF,
 199                             ethtool_adv_to_mii_ctrl1000_t(advertising));
 200         if (ret < 0)
 201                 return ret;
 202         if (ret > 0)
 203                 changed = true;
 204
 205         /* 10G control register */
 206         ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
 207                             MDIO_AN_10GBT_CTRL_ADV10G,
 208                             advertising & ADVERTISED_10000baseT_Full ?
 209                                 MDIO_AN_10GBT_CTRL_ADV10G : 0);
 210         if (ret < 0)
 211                 return ret;
 212         if (ret > 0)
 213                 changed = true;
 214
 215         if (changed)
 216                 ret = genphy_c45_restart_aneg(phydev);
 217
 218         return ret;
 219 }
 220
 221 static int mv3310_aneg_done(struct phy_device *phydev)
 222 {
 223         int val;
 224
 225         val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
 226         if (val < 0)
 227                 return val;
 228
 229         if (val & MDIO_STAT1_LSTATUS)
 230                 return 1;
 231
 232         return genphy_c45_aneg_done(phydev);
 233 }
 234
 235 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
 236 static int mv3310_read_10gbr_status(struct phy_device *phydev)
 237 {
 238         phydev->link = 1;
 239         phydev->speed = SPEED_10000;
 240         phydev->duplex = DUPLEX_FULL;
 241
 242         if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
 243                 phydev->interface = PHY_INTERFACE_MODE_10GKR;
 244
 245         return 0;
 246 }
 247
 248 static int mv3310_read_status(struct phy_device *phydev)
 249 {
 250         u32 mmd_mask = phydev->c45_ids.devices_in_package;
 251         int val;
 252
 253         /* The vendor devads do not report link status.  Avoid the PHYXS
 254          * instance as there are three, and its status depends on the MAC
 255          * being appropriately configured for the negotiated speed.
 256          */
 257         mmd_mask &= ~(BIT(MDIO_MMD_VEND1) | BIT(MDIO_MMD_VEND2) |
 258                       BIT(MDIO_MMD_PHYXS));
 259
 260         phydev->speed = SPEED_UNKNOWN;
 261         phydev->duplex = DUPLEX_UNKNOWN;
 262         phydev->lp_advertising = 0;
 263         phydev->link = 0;
 264         phydev->pause = 0;
 265         phydev->asym_pause = 0;
 266
 267         val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
 268         if (val < 0)
 269                 return val;
 270
 271         if (val & MDIO_STAT1_LSTATUS)
 272                 return mv3310_read_10gbr_status(phydev);
 273
 274         val = genphy_c45_read_link(phydev, mmd_mask);
 275         if (val < 0)
 276                 return val;
 277
 278         phydev->link = val > 0 ? 1 : 0;
 279
 280         val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
 281         if (val < 0)
 282                 return val;
 283
 284         if (val & MDIO_AN_STAT1_COMPLETE) {
 285                 val = genphy_c45_read_lpa(phydev);
 286                 if (val < 0)
 287                         return val;
 288
 289                 /* Read the link partner's 1G advertisment */
 290                 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000);
 291                 if (val < 0)
 292                         return val;
 293
 294                 phydev->lp_advertising |= mii_stat1000_to_ethtool_lpa_t(val);
 295
 296                 if (phydev->autoneg == AUTONEG_ENABLE) {
 297                         val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_RESULT);
 298                         if (val < 0)
 299                                 return val;
 300
 301                         if (val & MV_AN_RESULT_SPD_10000)
 302                                 phydev->speed = SPEED_10000;
 303                         else if (val & MV_AN_RESULT_SPD_1000)
 304                                 phydev->speed = SPEED_1000;
 305                         else if (val & MV_AN_RESULT_SPD_100)
 306                                 phydev->speed = SPEED_100;
 307                         else if (val & MV_AN_RESULT_SPD_10)
 308                                 phydev->speed = SPEED_10;
 309
 310                         phydev->duplex = DUPLEX_FULL;
 311                 }
 312         }
 313
 314         if (phydev->autoneg != AUTONEG_ENABLE) {
 315                 val = genphy_c45_read_pma(phydev);
 316                 if (val < 0)
 317                         return val;
 318         }
 319
 320         if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
 321              phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) {
 322                 /* The PHY automatically switches its serdes interface (and
 323                  * active PHYXS instance) between Cisco SGMII and 10GBase-KR
 324                  * modes according to the speed.  Florian suggests setting
 325                  * phydev->interface to communicate this to the MAC. Only do
 326                  * this if we are already in either SGMII or 10GBase-KR mode.
 327                  */
 328                 if (phydev->speed == SPEED_10000)
 329                         phydev->interface = PHY_INTERFACE_MODE_10GKR;
 330                 else if (phydev->speed >= SPEED_10 &&
 331                          phydev->speed < SPEED_10000)
 332                         phydev->interface = PHY_INTERFACE_MODE_SGMII;
 333         }
 334
 335         return 0;
 336 }
 337
 338 static struct phy_driver mv3310_drivers[] = {
 339         {
 340                 .phy_id         = 0x002b09aa,
 341                 .phy_id_mask    = 0xffffffff,
 342                 .name           = "mv88x3310",
 343                 .features       = SUPPORTED_10baseT_Full |
 344                                   SUPPORTED_100baseT_Full |
 345                                   SUPPORTED_1000baseT_Full |
 346                                   SUPPORTED_Autoneg |
 347                                   SUPPORTED_TP |
 348                                   SUPPORTED_FIBRE |
 349                                   SUPPORTED_10000baseT_Full |
 350                                   SUPPORTED_Backplane,
 351                 .probe          = mv3310_probe,
 352                 .soft_reset     = mv3310_soft_reset,
 353                 .config_init    = mv3310_config_init,
 354                 .config_aneg    = mv3310_config_aneg,
 355                 .aneg_done      = mv3310_aneg_done,
 356                 .read_status    = mv3310_read_status,
 357         },
 358 };
 359
 360 module_phy_driver(mv3310_drivers);
 361
 362 static struct mdio_device_id __maybe_unused mv3310_tbl[] = {
 363         { 0x002b09aa, 0xffffffff },
 364         { },
 365 };
 366 MODULE_DEVICE_TABLE(mdio, mv3310_tbl);
 367 MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)");
 368 MODULE_LICENSE("GPL");