| blob | cf69aab648fbdf9e02dc9d61e78d05b708bfdc91 |
1 # SPDX-License-Identifier: GPL-2.0
2 config ARM
3 bool
4 default y
5 select ARCH_CLOCKSOURCE_DATA
6 select ARCH_HAS_DEBUG_VIRTUAL
7 select ARCH_HAS_DEVMEM_IS_ALLOWED
8 select ARCH_HAS_ELF_RANDOMIZE
9 select ARCH_HAS_SET_MEMORY
10 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
11 select ARCH_HAS_STRICT_MODULE_RWX if MMU
12 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
13 select ARCH_HAVE_CUSTOM_GPIO_H
14 select ARCH_HAS_GCOV_PROFILE_ALL
15 select ARCH_MIGHT_HAVE_PC_PARPORT
16 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
17 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
18 select ARCH_SUPPORTS_ATOMIC_RMW
19 select ARCH_USE_BUILTIN_BSWAP
20 select ARCH_USE_CMPXCHG_LOCKREF
21 select ARCH_WANT_IPC_PARSE_VERSION
22 select BUILDTIME_EXTABLE_SORT if MMU
23 select CLONE_BACKWARDS
24 select CPU_PM if (SUSPEND || CPU_IDLE)
25 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
26 select DMA_NOOP_OPS if !MMU
27 select EDAC_SUPPORT
28 select EDAC_ATOMIC_SCRUB
29 select GENERIC_ALLOCATOR
30 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
31 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
32 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
33 select GENERIC_CPU_AUTOPROBE
34 select GENERIC_EARLY_IOREMAP
35 select GENERIC_IDLE_POLL_SETUP
36 select GENERIC_IRQ_PROBE
37 select GENERIC_IRQ_SHOW
38 select GENERIC_IRQ_SHOW_LEVEL
39 select GENERIC_PCI_IOMAP
40 select GENERIC_SCHED_CLOCK
41 select GENERIC_SMP_IDLE_THREAD
42 select GENERIC_STRNCPY_FROM_USER
43 select GENERIC_STRNLEN_USER
44 select HANDLE_DOMAIN_IRQ
45 select HARDIRQS_SW_RESEND
46 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
47 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
48 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
49 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
50 select HAVE_ARCH_MMAP_RND_BITS if MMU
51 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
52 select HAVE_ARCH_TRACEHOOK
53 select HAVE_ARM_SMCCC if CPU_V7
54 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
55 select HAVE_CC_STACKPROTECTOR
56 select HAVE_CONTEXT_TRACKING
57 select HAVE_C_RECORDMCOUNT
58 select HAVE_DEBUG_KMEMLEAK
59 select HAVE_DMA_API_DEBUG
60 select HAVE_DMA_CONTIGUOUS if MMU
61 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
62 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
63 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
64 select HAVE_EXIT_THREAD
65 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
66 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
67 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
68 select HAVE_GCC_PLUGINS
69 select HAVE_GENERIC_DMA_COHERENT
70 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
71 select HAVE_IDE if PCI || ISA || PCMCIA
72 select HAVE_IRQ_TIME_ACCOUNTING
73 select HAVE_KERNEL_GZIP
74 select HAVE_KERNEL_LZ4
75 select HAVE_KERNEL_LZMA
76 select HAVE_KERNEL_LZO
77 select HAVE_KERNEL_XZ
78 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
79 select HAVE_KRETPROBES if (HAVE_KPROBES)
80 select HAVE_MEMBLOCK
81 select HAVE_MOD_ARCH_SPECIFIC
82 select HAVE_NMI
83 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
84 select HAVE_OPTPROBES if !THUMB2_KERNEL
85 select HAVE_PERF_EVENTS
86 select HAVE_PERF_REGS
87 select HAVE_PERF_USER_STACK_DUMP
88 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
89 select HAVE_REGS_AND_STACK_ACCESS_API
90 select HAVE_SYSCALL_TRACEPOINTS
91 select HAVE_UID16
92 select HAVE_VIRT_CPU_ACCOUNTING_GEN
93 select IRQ_FORCED_THREADING
94 select MODULES_USE_ELF_REL
95 select NO_BOOTMEM
96 select OF_EARLY_FLATTREE if OF
97 select OF_RESERVED_MEM if OF
98 select OLD_SIGACTION
99 select OLD_SIGSUSPEND3
100 select PERF_USE_VMALLOC
101 select RTC_LIB
102 select SYS_SUPPORTS_APM_EMULATION
103 # Above selects are sorted alphabetically; please add new ones
104 # according to that. Thanks.
105 help
106 The ARM series is a line of low-power-consumption RISC chip designs
107 licensed by ARM Ltd and targeted at embedded applications and
108 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
109 manufactured, but legacy ARM-based PC hardware remains popular in
110 Europe. There is an ARM Linux project with a web page at
111 <http://www.arm.linux.org.uk/>.
113 config ARM_HAS_SG_CHAIN
114 select ARCH_HAS_SG_CHAIN
115 bool
117 config NEED_SG_DMA_LENGTH
118 bool
120 config ARM_DMA_USE_IOMMU
121 bool
122 select ARM_HAS_SG_CHAIN
123 select NEED_SG_DMA_LENGTH
125 if ARM_DMA_USE_IOMMU
127 config ARM_DMA_IOMMU_ALIGNMENT
128 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
129 range 4 9
130 default 8
131 help
132 DMA mapping framework by default aligns all buffers to the smallest
133 PAGE_SIZE order which is greater than or equal to the requested buffer
134 size. This works well for buffers up to a few hundreds kilobytes, but
135 for larger buffers it just a waste of address space. Drivers which has
136 relatively small addressing window (like 64Mib) might run out of
137 virtual space with just a few allocations.
139 With this parameter you can specify the maximum PAGE_SIZE order for
140 DMA IOMMU buffers. Larger buffers will be aligned only to this
141 specified order. The order is expressed as a power of two multiplied
142 by the PAGE_SIZE.
144 endif
146 config MIGHT_HAVE_PCI
147 bool
149 config SYS_SUPPORTS_APM_EMULATION
150 bool
152 config HAVE_TCM
153 bool
154 select GENERIC_ALLOCATOR
156 config HAVE_PROC_CPU
157 bool
159 config NO_IOPORT_MAP
160 bool
162 config EISA
163 bool
164 ---help---
165 The Extended Industry Standard Architecture (EISA) bus was
166 developed as an open alternative to the IBM MicroChannel bus.
168 The EISA bus provided some of the features of the IBM MicroChannel
169 bus while maintaining backward compatibility with cards made for
170 the older ISA bus. The EISA bus saw limited use between 1988 and
171 1995 when it was made obsolete by the PCI bus.
173 Say Y here if you are building a kernel for an EISA-based machine.
175 Otherwise, say N.
177 config SBUS
178 bool
180 config STACKTRACE_SUPPORT
181 bool
182 default y
184 config LOCKDEP_SUPPORT
185 bool
186 default y
188 config TRACE_IRQFLAGS_SUPPORT
189 bool
190 default !CPU_V7M
192 config RWSEM_XCHGADD_ALGORITHM
193 bool
194 default y
196 config ARCH_HAS_ILOG2_U32
197 bool
199 config ARCH_HAS_ILOG2_U64
200 bool
202 config ARCH_HAS_BANDGAP
203 bool
205 config FIX_EARLYCON_MEM
206 def_bool y if MMU
208 config GENERIC_HWEIGHT
209 bool
210 default y
212 config GENERIC_CALIBRATE_DELAY
213 bool
214 default y
216 config ARCH_MAY_HAVE_PC_FDC
217 bool
219 config ZONE_DMA
220 bool
222 config NEED_DMA_MAP_STATE
223 def_bool y
225 config ARCH_SUPPORTS_UPROBES
226 def_bool y
228 config ARCH_HAS_DMA_SET_COHERENT_MASK
229 bool
231 config GENERIC_ISA_DMA
232 bool
234 config FIQ
235 bool
237 config NEED_RET_TO_USER
238 bool
240 config ARCH_MTD_XIP
241 bool
243 config VECTORS_BASE
244 hex
245 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
246 default DRAM_BASE if REMAP_VECTORS_TO_RAM
247 default 0x00000000
248 help
249 The base address of exception vectors. This must be two pages
250 in size.
252 config ARM_PATCH_PHYS_VIRT
253 bool "Patch physical to virtual translations at runtime" if EMBEDDED
254 default y
255 depends on !XIP_KERNEL && MMU
256 help
257 Patch phys-to-virt and virt-to-phys translation functions at
258 boot and module load time according to the position of the
259 kernel in system memory.
261 This can only be used with non-XIP MMU kernels where the base
262 of physical memory is at a 16MB boundary.
264 Only disable this option if you know that you do not require
265 this feature (eg, building a kernel for a single machine) and
266 you need to shrink the kernel to the minimal size.
268 config NEED_MACH_IO_H
269 bool
270 help
271 Select this when mach/io.h is required to provide special
272 definitions for this platform. The need for mach/io.h should
273 be avoided when possible.
275 config NEED_MACH_MEMORY_H
276 bool
277 help
278 Select this when mach/memory.h is required to provide special
279 definitions for this platform. The need for mach/memory.h should
280 be avoided when possible.
282 config PHYS_OFFSET
283 hex "Physical address of main memory" if MMU
284 depends on !ARM_PATCH_PHYS_VIRT
285 default DRAM_BASE if !MMU
286 default 0x00000000 if ARCH_EBSA110 || \
287 ARCH_FOOTBRIDGE || \
288 ARCH_INTEGRATOR || \
289 ARCH_IOP13XX || \
290 ARCH_KS8695 || \
291 ARCH_REALVIEW
292 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
293 default 0x20000000 if ARCH_S5PV210
294 default 0xc0000000 if ARCH_SA1100
295 help
296 Please provide the physical address corresponding to the
297 location of main memory in your system.
299 config GENERIC_BUG
300 def_bool y
301 depends on BUG
303 config PGTABLE_LEVELS
304 int
305 default 3 if ARM_LPAE
306 default 2
308 source "init/Kconfig"
310 source "kernel/Kconfig.freezer"
312 menu "System Type"
314 config MMU
315 bool "MMU-based Paged Memory Management Support"
316 default y
317 help
318 Select if you want MMU-based virtualised addressing space
319 support by paged memory management. If unsure, say 'Y'.
321 config ARCH_MMAP_RND_BITS_MIN
322 default 8
324 config ARCH_MMAP_RND_BITS_MAX
325 default 14 if PAGE_OFFSET=0x40000000
326 default 15 if PAGE_OFFSET=0x80000000
327 default 16
329 #
330 # The "ARM system type" choice list is ordered alphabetically by option
331 # text. Please add new entries in the option alphabetic order.
332 #
333 choice
334 prompt "ARM system type"
335 default ARM_SINGLE_ARMV7M if !MMU
336 default ARCH_MULTIPLATFORM if MMU
338 config ARCH_MULTIPLATFORM
339 bool "Allow multiple platforms to be selected"
340 depends on MMU
341 select ARM_HAS_SG_CHAIN
342 select ARM_PATCH_PHYS_VIRT
343 select AUTO_ZRELADDR
344 select TIMER_OF
345 select COMMON_CLK
346 select GENERIC_CLOCKEVENTS
347 select MIGHT_HAVE_PCI
348 select MULTI_IRQ_HANDLER
349 select PCI_DOMAINS if PCI
350 select SPARSE_IRQ
351 select USE_OF
353 config ARM_SINGLE_ARMV7M
354 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
355 depends on !MMU
356 select ARM_NVIC
357 select AUTO_ZRELADDR
358 select TIMER_OF
359 select COMMON_CLK
360 select CPU_V7M
361 select GENERIC_CLOCKEVENTS
362 select NO_IOPORT_MAP
363 select SPARSE_IRQ
364 select USE_OF
366 config ARCH_EBSA110
367 bool "EBSA-110"
368 select ARCH_USES_GETTIMEOFFSET
369 select CPU_SA110
370 select ISA
371 select NEED_MACH_IO_H
372 select NEED_MACH_MEMORY_H
373 select NO_IOPORT_MAP
374 help
375 This is an evaluation board for the StrongARM processor available
376 from Digital. It has limited hardware on-board, including an
377 Ethernet interface, two PCMCIA sockets, two serial ports and a
378 parallel port.
380 config ARCH_EP93XX
381 bool "EP93xx-based"
382 select ARCH_HAS_HOLES_MEMORYMODEL
383 select ARM_AMBA
384 imply ARM_PATCH_PHYS_VIRT
385 select ARM_VIC
386 select AUTO_ZRELADDR
387 select CLKDEV_LOOKUP
388 select CLKSRC_MMIO
389 select CPU_ARM920T
390 select GENERIC_CLOCKEVENTS
391 select GPIOLIB
392 help
393 This enables support for the Cirrus EP93xx series of CPUs.
395 config ARCH_FOOTBRIDGE
396 bool "FootBridge"
397 select CPU_SA110
398 select FOOTBRIDGE
399 select GENERIC_CLOCKEVENTS
400 select HAVE_IDE
401 select NEED_MACH_IO_H if !MMU
402 select NEED_MACH_MEMORY_H
403 help
404 Support for systems based on the DC21285 companion chip
405 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
407 config ARCH_NETX
408 bool "Hilscher NetX based"
409 select ARM_VIC
410 select CLKSRC_MMIO
411 select CPU_ARM926T
412 select GENERIC_CLOCKEVENTS
413 help
414 This enables support for systems based on the Hilscher NetX Soc
416 config ARCH_IOP13XX
417 bool "IOP13xx-based"
418 depends on MMU
419 select CPU_XSC3
420 select NEED_MACH_MEMORY_H
421 select NEED_RET_TO_USER
422 select PCI
423 select PLAT_IOP
424 select VMSPLIT_1G
425 select SPARSE_IRQ
426 help
427 Support for Intel's IOP13XX (XScale) family of processors.
429 config ARCH_IOP32X
430 bool "IOP32x-based"
431 depends on MMU
432 select CPU_XSCALE
433 select GPIO_IOP
434 select GPIOLIB
435 select NEED_RET_TO_USER
436 select PCI
437 select PLAT_IOP
438 help
439 Support for Intel's 80219 and IOP32X (XScale) family of
440 processors.
442 config ARCH_IOP33X
443 bool "IOP33x-based"
444 depends on MMU
445 select CPU_XSCALE
446 select GPIO_IOP
447 select GPIOLIB
448 select NEED_RET_TO_USER
449 select PCI
450 select PLAT_IOP
451 help
452 Support for Intel's IOP33X (XScale) family of processors.
454 config ARCH_IXP4XX
455 bool "IXP4xx-based"
456 depends on MMU
457 select ARCH_HAS_DMA_SET_COHERENT_MASK
458 select ARCH_SUPPORTS_BIG_ENDIAN
459 select CLKSRC_MMIO
460 select CPU_XSCALE
461 select DMABOUNCE if PCI
462 select GENERIC_CLOCKEVENTS
463 select GPIOLIB
464 select MIGHT_HAVE_PCI
465 select NEED_MACH_IO_H
466 select USB_EHCI_BIG_ENDIAN_DESC
467 select USB_EHCI_BIG_ENDIAN_MMIO
468 help
469 Support for Intel's IXP4XX (XScale) family of processors.
471 config ARCH_DOVE
472 bool "Marvell Dove"
473 select CPU_PJ4
474 select GENERIC_CLOCKEVENTS
475 select GPIOLIB
476 select MIGHT_HAVE_PCI
477 select MULTI_IRQ_HANDLER
478 select MVEBU_MBUS
479 select PINCTRL
480 select PINCTRL_DOVE
481 select PLAT_ORION_LEGACY
482 select SPARSE_IRQ
483 select PM_GENERIC_DOMAINS if PM
484 help
485 Support for the Marvell Dove SoC 88AP510
487 config ARCH_KS8695
488 bool "Micrel/Kendin KS8695"
489 select CLKSRC_MMIO
490 select CPU_ARM922T
491 select GENERIC_CLOCKEVENTS
492 select GPIOLIB
493 select NEED_MACH_MEMORY_H
494 help
495 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
496 System-on-Chip devices.
498 config ARCH_W90X900
499 bool "Nuvoton W90X900 CPU"
500 select CLKDEV_LOOKUP
501 select CLKSRC_MMIO
502 select CPU_ARM926T
503 select GENERIC_CLOCKEVENTS
504 select GPIOLIB
505 help
506 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
507 At present, the w90x900 has been renamed nuc900, regarding
508 the ARM series product line, you can login the following
509 link address to know more.
511 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
512 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
514 config ARCH_LPC32XX
515 bool "NXP LPC32XX"
516 select ARM_AMBA
517 select CLKDEV_LOOKUP
518 select CLKSRC_LPC32XX
519 select COMMON_CLK
520 select CPU_ARM926T
521 select GENERIC_CLOCKEVENTS
522 select GPIOLIB
523 select MULTI_IRQ_HANDLER
524 select SPARSE_IRQ
525 select USE_OF
526 help
527 Support for the NXP LPC32XX family of processors
529 config ARCH_PXA
530 bool "PXA2xx/PXA3xx-based"
531 depends on MMU
532 select ARCH_MTD_XIP
533 select ARM_CPU_SUSPEND if PM
534 select AUTO_ZRELADDR
535 select COMMON_CLK
536 select CLKDEV_LOOKUP
537 select CLKSRC_PXA
538 select CLKSRC_MMIO
539 select TIMER_OF
540 select CPU_XSCALE if !CPU_XSC3
541 select GENERIC_CLOCKEVENTS
542 select GPIO_PXA
543 select GPIOLIB
544 select HAVE_IDE
545 select IRQ_DOMAIN
546 select MULTI_IRQ_HANDLER
547 select PLAT_PXA
548 select SPARSE_IRQ
549 help
550 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
552 config ARCH_RPC
553 bool "RiscPC"
554 depends on MMU
555 select ARCH_ACORN
556 select ARCH_MAY_HAVE_PC_FDC
557 select ARCH_SPARSEMEM_ENABLE
558 select ARCH_USES_GETTIMEOFFSET
559 select CPU_SA110
560 select FIQ
561 select HAVE_IDE
562 select HAVE_PATA_PLATFORM
563 select ISA_DMA_API
564 select NEED_MACH_IO_H
565 select NEED_MACH_MEMORY_H
566 select NO_IOPORT_MAP
567 help
568 On the Acorn Risc-PC, Linux can support the internal IDE disk and
569 CD-ROM interface, serial and parallel port, and the floppy drive.
571 config ARCH_SA1100
572 bool "SA1100-based"
573 select ARCH_MTD_XIP
574 select ARCH_SPARSEMEM_ENABLE
575 select CLKDEV_LOOKUP
576 select CLKSRC_MMIO
577 select CLKSRC_PXA
578 select TIMER_OF if OF
579 select CPU_FREQ
580 select CPU_SA1100
581 select GENERIC_CLOCKEVENTS
582 select GPIOLIB
583 select HAVE_IDE
584 select IRQ_DOMAIN
585 select ISA
586 select MULTI_IRQ_HANDLER
587 select NEED_MACH_MEMORY_H
588 select SPARSE_IRQ
589 help
590 Support for StrongARM 11x0 based boards.
592 config ARCH_S3C24XX
593 bool "Samsung S3C24XX SoCs"
594 select ATAGS
595 select CLKDEV_LOOKUP
596 select CLKSRC_SAMSUNG_PWM
597 select GENERIC_CLOCKEVENTS
598 select GPIO_SAMSUNG
599 select GPIOLIB
600 select HAVE_S3C2410_I2C if I2C
601 select HAVE_S3C2410_WATCHDOG if WATCHDOG
602 select HAVE_S3C_RTC if RTC_CLASS
603 select MULTI_IRQ_HANDLER
604 select NEED_MACH_IO_H
605 select SAMSUNG_ATAGS
606 help
607 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
608 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
609 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
610 Samsung SMDK2410 development board (and derivatives).
612 config ARCH_DAVINCI
613 bool "TI DaVinci"
614 select ARCH_HAS_HOLES_MEMORYMODEL
615 select CLKDEV_LOOKUP
616 select CPU_ARM926T
617 select GENERIC_ALLOCATOR
618 select GENERIC_CLOCKEVENTS
619 select GENERIC_IRQ_CHIP
620 select GPIOLIB
621 select HAVE_IDE
622 select USE_OF
623 select ZONE_DMA
624 help
625 Support for TI's DaVinci platform.
627 config ARCH_OMAP1
628 bool "TI OMAP1"
629 depends on MMU
630 select ARCH_HAS_HOLES_MEMORYMODEL
631 select ARCH_OMAP
632 select CLKDEV_LOOKUP
633 select CLKSRC_MMIO
634 select GENERIC_CLOCKEVENTS
635 select GENERIC_IRQ_CHIP
636 select GPIOLIB
637 select HAVE_IDE
638 select IRQ_DOMAIN
639 select MULTI_IRQ_HANDLER
640 select NEED_MACH_IO_H if PCCARD
641 select NEED_MACH_MEMORY_H
642 select SPARSE_IRQ
643 help
644 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
646 endchoice
648 menu "Multiple platform selection"
649 depends on ARCH_MULTIPLATFORM
651 comment "CPU Core family selection"
653 config ARCH_MULTI_V4
654 bool "ARMv4 based platforms (FA526)"
655 depends on !ARCH_MULTI_V6_V7
656 select ARCH_MULTI_V4_V5
657 select CPU_FA526
659 config ARCH_MULTI_V4T
660 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
661 depends on !ARCH_MULTI_V6_V7
662 select ARCH_MULTI_V4_V5
663 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
664 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
665 CPU_ARM925T || CPU_ARM940T)
667 config ARCH_MULTI_V5
668 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
669 depends on !ARCH_MULTI_V6_V7
670 select ARCH_MULTI_V4_V5
671 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
672 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
673 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
675 config ARCH_MULTI_V4_V5
676 bool
678 config ARCH_MULTI_V6
679 bool "ARMv6 based platforms (ARM11)"
680 select ARCH_MULTI_V6_V7
681 select CPU_V6K
683 config ARCH_MULTI_V7
684 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
685 default y
686 select ARCH_MULTI_V6_V7
687 select CPU_V7
688 select HAVE_SMP
690 config ARCH_MULTI_V6_V7
691 bool
692 select MIGHT_HAVE_CACHE_L2X0
694 config ARCH_MULTI_CPU_AUTO
695 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
696 select ARCH_MULTI_V5
698 endmenu
700 config ARCH_VIRT
701 bool "Dummy Virtual Machine"
702 depends on ARCH_MULTI_V7
703 select ARM_AMBA
704 select ARM_GIC
705 select ARM_GIC_V2M if PCI
706 select ARM_GIC_V3
707 select ARM_GIC_V3_ITS if PCI
708 select ARM_PSCI
709 select HAVE_ARM_ARCH_TIMER
711 #
712 # This is sorted alphabetically by mach-* pathname. However, plat-*
713 # Kconfigs may be included either alphabetically (according to the
714 # plat- suffix) or along side the corresponding mach-* source.
715 #
716 source "arch/arm/mach-mvebu/Kconfig"
718 source "arch/arm/mach-actions/Kconfig"
720 source "arch/arm/mach-alpine/Kconfig"
722 source "arch/arm/mach-artpec/Kconfig"
724 source "arch/arm/mach-asm9260/Kconfig"
726 source "arch/arm/mach-at91/Kconfig"
728 source "arch/arm/mach-axxia/Kconfig"
730 source "arch/arm/mach-bcm/Kconfig"
732 source "arch/arm/mach-berlin/Kconfig"
734 source "arch/arm/mach-clps711x/Kconfig"
736 source "arch/arm/mach-cns3xxx/Kconfig"
738 source "arch/arm/mach-davinci/Kconfig"
740 source "arch/arm/mach-digicolor/Kconfig"
742 source "arch/arm/mach-dove/Kconfig"
744 source "arch/arm/mach-ep93xx/Kconfig"
746 source "arch/arm/mach-footbridge/Kconfig"
748 source "arch/arm/mach-gemini/Kconfig"
750 source "arch/arm/mach-highbank/Kconfig"
752 source "arch/arm/mach-hisi/Kconfig"
754 source "arch/arm/mach-integrator/Kconfig"
756 source "arch/arm/mach-iop32x/Kconfig"
758 source "arch/arm/mach-iop33x/Kconfig"
760 source "arch/arm/mach-iop13xx/Kconfig"
762 source "arch/arm/mach-ixp4xx/Kconfig"
764 source "arch/arm/mach-keystone/Kconfig"
766 source "arch/arm/mach-ks8695/Kconfig"
768 source "arch/arm/mach-meson/Kconfig"
770 source "arch/arm/mach-moxart/Kconfig"
772 source "arch/arm/mach-aspeed/Kconfig"
774 source "arch/arm/mach-mv78xx0/Kconfig"
776 source "arch/arm/mach-imx/Kconfig"
778 source "arch/arm/mach-mediatek/Kconfig"
780 source "arch/arm/mach-mxs/Kconfig"
782 source "arch/arm/mach-netx/Kconfig"
784 source "arch/arm/mach-nomadik/Kconfig"
786 source "arch/arm/mach-nspire/Kconfig"
788 source "arch/arm/plat-omap/Kconfig"
790 source "arch/arm/mach-omap1/Kconfig"
792 source "arch/arm/mach-omap2/Kconfig"
794 source "arch/arm/mach-orion5x/Kconfig"
796 source "arch/arm/mach-picoxcell/Kconfig"
798 source "arch/arm/mach-pxa/Kconfig"
799 source "arch/arm/plat-pxa/Kconfig"
801 source "arch/arm/mach-mmp/Kconfig"
803 source "arch/arm/mach-oxnas/Kconfig"
805 source "arch/arm/mach-qcom/Kconfig"
807 source "arch/arm/mach-realview/Kconfig"
809 source "arch/arm/mach-rockchip/Kconfig"
811 source "arch/arm/mach-sa1100/Kconfig"
813 source "arch/arm/mach-socfpga/Kconfig"
815 source "arch/arm/mach-spear/Kconfig"
817 source "arch/arm/mach-sti/Kconfig"
819 source "arch/arm/mach-stm32/Kconfig"
821 source "arch/arm/mach-s3c24xx/Kconfig"
823 source "arch/arm/mach-s3c64xx/Kconfig"
825 source "arch/arm/mach-s5pv210/Kconfig"
827 source "arch/arm/mach-exynos/Kconfig"
828 source "arch/arm/plat-samsung/Kconfig"
830 source "arch/arm/mach-shmobile/Kconfig"
832 source "arch/arm/mach-sunxi/Kconfig"
834 source "arch/arm/mach-prima2/Kconfig"
836 source "arch/arm/mach-tango/Kconfig"
838 source "arch/arm/mach-tegra/Kconfig"
840 source "arch/arm/mach-u300/Kconfig"
842 source "arch/arm/mach-uniphier/Kconfig"
844 source "arch/arm/mach-ux500/Kconfig"
846 source "arch/arm/mach-versatile/Kconfig"
848 source "arch/arm/mach-vexpress/Kconfig"
849 source "arch/arm/plat-versatile/Kconfig"
851 source "arch/arm/mach-vt8500/Kconfig"
853 source "arch/arm/mach-w90x900/Kconfig"
855 source "arch/arm/mach-zx/Kconfig"
857 source "arch/arm/mach-zynq/Kconfig"
859 # ARMv7-M architecture
860 config ARCH_EFM32
861 bool "Energy Micro efm32"
862 depends on ARM_SINGLE_ARMV7M
863 select GPIOLIB
864 help
865 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
866 processors.
868 config ARCH_LPC18XX
869 bool "NXP LPC18xx/LPC43xx"
870 depends on ARM_SINGLE_ARMV7M
871 select ARCH_HAS_RESET_CONTROLLER
872 select ARM_AMBA
873 select CLKSRC_LPC32XX
874 select PINCTRL
875 help
876 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
877 high performance microcontrollers.
879 config ARCH_MPS2
880 bool "ARM MPS2 platform"
881 depends on ARM_SINGLE_ARMV7M
882 select ARM_AMBA
883 select CLKSRC_MPS2
884 help
885 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
886 with a range of available cores like Cortex-M3/M4/M7.
888 Please, note that depends which Application Note is used memory map
889 for the platform may vary, so adjustment of RAM base might be needed.
891 # Definitions to make life easier
892 config ARCH_ACORN
893 bool
895 config PLAT_IOP
896 bool
897 select GENERIC_CLOCKEVENTS
899 config PLAT_ORION
900 bool
901 select CLKSRC_MMIO
902 select COMMON_CLK
903 select GENERIC_IRQ_CHIP
904 select IRQ_DOMAIN
906 config PLAT_ORION_LEGACY
907 bool
908 select PLAT_ORION
910 config PLAT_PXA
911 bool
913 config PLAT_VERSATILE
914 bool
916 source "arch/arm/firmware/Kconfig"
918 source arch/arm/mm/Kconfig
920 config IWMMXT
921 bool "Enable iWMMXt support"
922 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
923 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
924 help
925 Enable support for iWMMXt context switching at run time if
926 running on a CPU that supports it.
928 config MULTI_IRQ_HANDLER
929 bool
930 help
931 Allow each machine to specify it's own IRQ handler at run time.
933 if !MMU
934 source "arch/arm/Kconfig-nommu"
935 endif
937 config PJ4B_ERRATA_4742
938 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
939 depends on CPU_PJ4B && MACH_ARMADA_370
940 default y
941 help
942 When coming out of either a Wait for Interrupt (WFI) or a Wait for
943 Event (WFE) IDLE states, a specific timing sensitivity exists between
944 the retiring WFI/WFE instructions and the newly issued subsequent
945 instructions. This sensitivity can result in a CPU hang scenario.
946 Workaround:
947 The software must insert either a Data Synchronization Barrier (DSB)
948 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
949 instruction
951 config ARM_ERRATA_326103
952 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
953 depends on CPU_V6
954 help
955 Executing a SWP instruction to read-only memory does not set bit 11
956 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
957 treat the access as a read, preventing a COW from occurring and
958 causing the faulting task to livelock.
960 config ARM_ERRATA_411920
961 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
962 depends on CPU_V6 || CPU_V6K
963 help
964 Invalidation of the Instruction Cache operation can
965 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
966 It does not affect the MPCore. This option enables the ARM Ltd.
967 recommended workaround.
969 config ARM_ERRATA_430973
970 bool "ARM errata: Stale prediction on replaced interworking branch"
971 depends on CPU_V7
972 help
973 This option enables the workaround for the 430973 Cortex-A8
974 r1p* erratum. If a code sequence containing an ARM/Thumb
975 interworking branch is replaced with another code sequence at the
976 same virtual address, whether due to self-modifying code or virtual
977 to physical address re-mapping, Cortex-A8 does not recover from the
978 stale interworking branch prediction. This results in Cortex-A8
979 executing the new code sequence in the incorrect ARM or Thumb state.
980 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
981 and also flushes the branch target cache at every context switch.
982 Note that setting specific bits in the ACTLR register may not be
983 available in non-secure mode.
985 config ARM_ERRATA_458693
986 bool "ARM errata: Processor deadlock when a false hazard is created"
987 depends on CPU_V7
988 depends on !ARCH_MULTIPLATFORM
989 help
990 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
991 erratum. For very specific sequences of memory operations, it is
992 possible for a hazard condition intended for a cache line to instead
993 be incorrectly associated with a different cache line. This false
994 hazard might then cause a processor deadlock. The workaround enables
995 the L1 caching of the NEON accesses and disables the PLD instruction
996 in the ACTLR register. Note that setting specific bits in the ACTLR
997 register may not be available in non-secure mode.
999 config ARM_ERRATA_460075
1000 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1001 depends on CPU_V7
1002 depends on !ARCH_MULTIPLATFORM
1003 help
1004 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1005 erratum. Any asynchronous access to the L2 cache may encounter a
1006 situation in which recent store transactions to the L2 cache are lost
1007 and overwritten with stale memory contents from external memory. The
1008 workaround disables the write-allocate mode for the L2 cache via the
1009 ACTLR register. Note that setting specific bits in the ACTLR register
1010 may not be available in non-secure mode.
1012 config ARM_ERRATA_742230
1013 bool "ARM errata: DMB operation may be faulty"
1014 depends on CPU_V7 && SMP
1015 depends on !ARCH_MULTIPLATFORM
1016 help
1017 This option enables the workaround for the 742230 Cortex-A9
1018 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1019 between two write operations may not ensure the correct visibility
1020 ordering of the two writes. This workaround sets a specific bit in
1021 the diagnostic register of the Cortex-A9 which causes the DMB
1022 instruction to behave as a DSB, ensuring the correct behaviour of
1023 the two writes.
1025 config ARM_ERRATA_742231
1026 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1027 depends on CPU_V7 && SMP
1028 depends on !ARCH_MULTIPLATFORM
1029 help
1030 This option enables the workaround for the 742231 Cortex-A9
1031 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1032 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1033 accessing some data located in the same cache line, may get corrupted
1034 data due to bad handling of the address hazard when the line gets
1035 replaced from one of the CPUs at the same time as another CPU is
1036 accessing it. This workaround sets specific bits in the diagnostic
1037 register of the Cortex-A9 which reduces the linefill issuing
1038 capabilities of the processor.
1040 config ARM_ERRATA_643719
1041 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1042 depends on CPU_V7 && SMP
1043 default y
1044 help
1045 This option enables the workaround for the 643719 Cortex-A9 (prior to
1046 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1047 register returns zero when it should return one. The workaround
1048 corrects this value, ensuring cache maintenance operations which use
1049 it behave as intended and avoiding data corruption.
1051 config ARM_ERRATA_720789
1052 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1053 depends on CPU_V7
1054 help
1055 This option enables the workaround for the 720789 Cortex-A9 (prior to
1056 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1057 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1058 As a consequence of this erratum, some TLB entries which should be
1059 invalidated are not, resulting in an incoherency in the system page
1060 tables. The workaround changes the TLB flushing routines to invalidate
1061 entries regardless of the ASID.
1063 config ARM_ERRATA_743622
1064 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1065 depends on CPU_V7
1066 depends on !ARCH_MULTIPLATFORM
1067 help
1068 This option enables the workaround for the 743622 Cortex-A9
1069 (r2p*) erratum. Under very rare conditions, a faulty
1070 optimisation in the Cortex-A9 Store Buffer may lead to data
1071 corruption. This workaround sets a specific bit in the diagnostic
1072 register of the Cortex-A9 which disables the Store Buffer
1073 optimisation, preventing the defect from occurring. This has no
1074 visible impact on the overall performance or power consumption of the
1075 processor.
1077 config ARM_ERRATA_751472
1078 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1079 depends on CPU_V7
1080 depends on !ARCH_MULTIPLATFORM
1081 help
1082 This option enables the workaround for the 751472 Cortex-A9 (prior
1083 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1084 completion of a following broadcasted operation if the second
1085 operation is received by a CPU before the ICIALLUIS has completed,
1086 potentially leading to corrupted entries in the cache or TLB.
1088 config ARM_ERRATA_754322
1089 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1090 depends on CPU_V7
1091 help
1092 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1093 r3p*) erratum. A speculative memory access may cause a page table walk
1094 which starts prior to an ASID switch but completes afterwards. This
1095 can populate the micro-TLB with a stale entry which may be hit with
1096 the new ASID. This workaround places two dsb instructions in the mm
1097 switching code so that no page table walks can cross the ASID switch.
1099 config ARM_ERRATA_754327
1100 bool "ARM errata: no automatic Store Buffer drain"
1101 depends on CPU_V7 && SMP
1102 help
1103 This option enables the workaround for the 754327 Cortex-A9 (prior to
1104 r2p0) erratum. The Store Buffer does not have any automatic draining
1105 mechanism and therefore a livelock may occur if an external agent
1106 continuously polls a memory location waiting to observe an update.
1107 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1108 written polling loops from denying visibility of updates to memory.
1110 config ARM_ERRATA_364296
1111 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1112 depends on CPU_V6
1113 help
1114 This options enables the workaround for the 364296 ARM1136
1115 r0p2 erratum (possible cache data corruption with
1116 hit-under-miss enabled). It sets the undocumented bit 31 in
1117 the auxiliary control register and the FI bit in the control
1118 register, thus disabling hit-under-miss without putting the
1119 processor into full low interrupt latency mode. ARM11MPCore
1120 is not affected.
1122 config ARM_ERRATA_764369
1123 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1124 depends on CPU_V7 && SMP
1125 help
1126 This option enables the workaround for erratum 764369
1127 affecting Cortex-A9 MPCore with two or more processors (all
1128 current revisions). Under certain timing circumstances, a data
1129 cache line maintenance operation by MVA targeting an Inner
1130 Shareable memory region may fail to proceed up to either the
1131 Point of Coherency or to the Point of Unification of the
1132 system. This workaround adds a DSB instruction before the
1133 relevant cache maintenance functions and sets a specific bit
1134 in the diagnostic control register of the SCU.
1136 config ARM_ERRATA_775420
1137 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1138 depends on CPU_V7
1139 help
1140 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1141 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1142 operation aborts with MMU exception, it might cause the processor
1143 to deadlock. This workaround puts DSB before executing ISB if
1144 an abort may occur on cache maintenance.
1146 config ARM_ERRATA_798181
1147 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1148 depends on CPU_V7 && SMP
1149 help
1150 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1151 adequately shooting down all use of the old entries. This
1152 option enables the Linux kernel workaround for this erratum
1153 which sends an IPI to the CPUs that are running the same ASID
1154 as the one being invalidated.
1156 config ARM_ERRATA_773022
1157 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1158 depends on CPU_V7
1159 help
1160 This option enables the workaround for the 773022 Cortex-A15
1161 (up to r0p4) erratum. In certain rare sequences of code, the
1162 loop buffer may deliver incorrect instructions. This
1163 workaround disables the loop buffer to avoid the erratum.
1165 config ARM_ERRATA_818325_852422
1166 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1167 depends on CPU_V7
1168 help
1169 This option enables the workaround for:
1170 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1171 instruction might deadlock. Fixed in r0p1.
1172 - Cortex-A12 852422: Execution of a sequence of instructions might
1173 lead to either a data corruption or a CPU deadlock. Not fixed in
1174 any Cortex-A12 cores yet.
1175 This workaround for all both errata involves setting bit[12] of the
1176 Feature Register. This bit disables an optimisation applied to a
1177 sequence of 2 instructions that use opposing condition codes.
1179 config ARM_ERRATA_821420
1180 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1181 depends on CPU_V7
1182 help
1183 This option enables the workaround for the 821420 Cortex-A12
1184 (all revs) erratum. In very rare timing conditions, a sequence
1185 of VMOV to Core registers instructions, for which the second
1186 one is in the shadow of a branch or abort, can lead to a
1187 deadlock when the VMOV instructions are issued out-of-order.
1189 config ARM_ERRATA_825619
1190 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1191 depends on CPU_V7
1192 help
1193 This option enables the workaround for the 825619 Cortex-A12
1194 (all revs) erratum. Within rare timing constraints, executing a
1195 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1196 and Device/Strongly-Ordered loads and stores might cause deadlock
1198 config ARM_ERRATA_852421
1199 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1200 depends on CPU_V7
1201 help
1202 This option enables the workaround for the 852421 Cortex-A17
1203 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1204 execution of a DMB ST instruction might fail to properly order
1205 stores from GroupA and stores from GroupB.
1207 config ARM_ERRATA_852423
1208 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1209 depends on CPU_V7
1210 help
1211 This option enables the workaround for:
1212 - Cortex-A17 852423: Execution of a sequence of instructions might
1213 lead to either a data corruption or a CPU deadlock. Not fixed in
1214 any Cortex-A17 cores yet.
1215 This is identical to Cortex-A12 erratum 852422. It is a separate
1216 config option from the A12 erratum due to the way errata are checked
1217 for and handled.
1219 endmenu
1221 source "arch/arm/common/Kconfig"
1223 menu "Bus support"
1225 config ISA
1226 bool
1227 help
1228 Find out whether you have ISA slots on your motherboard. ISA is the
1229 name of a bus system, i.e. the way the CPU talks to the other stuff
1230 inside your box. Other bus systems are PCI, EISA, MicroChannel
1231 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1232 newer boards don't support it. If you have ISA, say Y, otherwise N.
1234 # Select ISA DMA controller support
1235 config ISA_DMA
1236 bool
1237 select ISA_DMA_API
1239 # Select ISA DMA interface
1240 config ISA_DMA_API
1241 bool
1243 config PCI
1244 bool "PCI support" if MIGHT_HAVE_PCI
1245 help
1246 Find out whether you have a PCI motherboard. PCI is the name of a
1247 bus system, i.e. the way the CPU talks to the other stuff inside
1248 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1249 VESA. If you have PCI, say Y, otherwise N.
1251 config PCI_DOMAINS
1252 bool
1253 depends on PCI
1255 config PCI_DOMAINS_GENERIC
1256 def_bool PCI_DOMAINS
1258 config PCI_NANOENGINE
1259 bool "BSE nanoEngine PCI support"
1260 depends on SA1100_NANOENGINE
1261 help
1262 Enable PCI on the BSE nanoEngine board.
1264 config PCI_SYSCALL
1265 def_bool PCI
1267 config PCI_HOST_ITE8152
1268 bool
1269 depends on PCI && MACH_ARMCORE
1270 default y
1271 select DMABOUNCE
1273 source "drivers/pci/Kconfig"
1275 source "drivers/pcmcia/Kconfig"
1277 endmenu
1279 menu "Kernel Features"
1281 config HAVE_SMP
1282 bool
1283 help
1284 This option should be selected by machines which have an SMP-
1285 capable CPU.
1287 The only effect of this option is to make the SMP-related
1288 options available to the user for configuration.
1290 config SMP
1291 bool "Symmetric Multi-Processing"
1292 depends on CPU_V6K || CPU_V7
1293 depends on GENERIC_CLOCKEVENTS
1294 depends on HAVE_SMP
1295 depends on MMU || ARM_MPU
1296 select IRQ_WORK
1297 help
1298 This enables support for systems with more than one CPU. If you have
1299 a system with only one CPU, say N. If you have a system with more
1300 than one CPU, say Y.
1302 If you say N here, the kernel will run on uni- and multiprocessor
1303 machines, but will use only one CPU of a multiprocessor machine. If
1304 you say Y here, the kernel will run on many, but not all,
1305 uniprocessor machines. On a uniprocessor machine, the kernel
1306 will run faster if you say N here.
1308 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1309 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1310 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1312 If you don't know what to do here, say N.
1314 config SMP_ON_UP
1315 bool "Allow booting SMP kernel on uniprocessor systems"
1316 depends on SMP && !XIP_KERNEL && MMU
1317 default y
1318 help
1319 SMP kernels contain instructions which fail on non-SMP processors.
1320 Enabling this option allows the kernel to modify itself to make
1321 these instructions safe. Disabling it allows about 1K of space
1322 savings.
1324 If you don't know what to do here, say Y.
1326 config ARM_CPU_TOPOLOGY
1327 bool "Support cpu topology definition"
1328 depends on SMP && CPU_V7
1329 default y
1330 help
1331 Support ARM cpu topology definition. The MPIDR register defines
1332 affinity between processors which is then used to describe the cpu
1333 topology of an ARM System.
1335 config SCHED_MC
1336 bool "Multi-core scheduler support"
1337 depends on ARM_CPU_TOPOLOGY
1338 help
1339 Multi-core scheduler support improves the CPU scheduler's decision
1340 making when dealing with multi-core CPU chips at a cost of slightly
1341 increased overhead in some places. If unsure say N here.
1343 config SCHED_SMT
1344 bool "SMT scheduler support"
1345 depends on ARM_CPU_TOPOLOGY
1346 help
1347 Improves the CPU scheduler's decision making when dealing with
1348 MultiThreading at a cost of slightly increased overhead in some
1349 places. If unsure say N here.
1351 config HAVE_ARM_SCU
1352 bool
1353 help
1354 This option enables support for the ARM system coherency unit
1356 config HAVE_ARM_ARCH_TIMER
1357 bool "Architected timer support"
1358 depends on CPU_V7
1359 select ARM_ARCH_TIMER
1360 select GENERIC_CLOCKEVENTS
1361 help
1362 This option enables support for the ARM architected timer
1364 config HAVE_ARM_TWD
1365 bool
1366 select TIMER_OF if OF
1367 help
1368 This options enables support for the ARM timer and watchdog unit
1370 config MCPM
1371 bool "Multi-Cluster Power Management"
1372 depends on CPU_V7 && SMP
1373 help
1374 This option provides the common power management infrastructure
1375 for (multi-)cluster based systems, such as big.LITTLE based
1376 systems.
1378 config MCPM_QUAD_CLUSTER
1379 bool
1380 depends on MCPM
1381 help
1382 To avoid wasting resources unnecessarily, MCPM only supports up
1383 to 2 clusters by default.
1384 Platforms with 3 or 4 clusters that use MCPM must select this
1385 option to allow the additional clusters to be managed.
1387 config BIG_LITTLE
1388 bool "big.LITTLE support (Experimental)"
1389 depends on CPU_V7 && SMP
1390 select MCPM
1391 help
1392 This option enables support selections for the big.LITTLE
1393 system architecture.
1395 config BL_SWITCHER
1396 bool "big.LITTLE switcher support"
1397 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1398 select CPU_PM
1399 help
1400 The big.LITTLE "switcher" provides the core functionality to
1401 transparently handle transition between a cluster of A15's
1402 and a cluster of A7's in a big.LITTLE system.
1404 config BL_SWITCHER_DUMMY_IF
1405 tristate "Simple big.LITTLE switcher user interface"
1406 depends on BL_SWITCHER && DEBUG_KERNEL
1407 help
1408 This is a simple and dummy char dev interface to control
1409 the big.LITTLE switcher core code. It is meant for
1410 debugging purposes only.
1412 choice
1413 prompt "Memory split"
1414 depends on MMU
1415 default VMSPLIT_3G
1416 help
1417 Select the desired split between kernel and user memory.
1419 If you are not absolutely sure what you are doing, leave this
1420 option alone!
1422 config VMSPLIT_3G
1423 bool "3G/1G user/kernel split"
1424 config VMSPLIT_3G_OPT
1425 depends on !ARM_LPAE
1426 bool "3G/1G user/kernel split (for full 1G low memory)"
1427 config VMSPLIT_2G
1428 bool "2G/2G user/kernel split"
1429 config VMSPLIT_1G
1430 bool "1G/3G user/kernel split"
1431 endchoice
1433 config PAGE_OFFSET
1434 hex
1435 default PHYS_OFFSET if !MMU
1436 default 0x40000000 if VMSPLIT_1G
1437 default 0x80000000 if VMSPLIT_2G
1438 default 0xB0000000 if VMSPLIT_3G_OPT
1439 default 0xC0000000
1441 config NR_CPUS
1442 int "Maximum number of CPUs (2-32)"
1443 range 2 32
1444 depends on SMP
1445 default "4"
1447 config HOTPLUG_CPU
1448 bool "Support for hot-pluggable CPUs"
1449 depends on SMP
1450 select GENERIC_IRQ_MIGRATION
1451 help
1452 Say Y here to experiment with turning CPUs off and on. CPUs
1453 can be controlled through /sys/devices/system/cpu.
1455 config ARM_PSCI
1456 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1457 depends on HAVE_ARM_SMCCC
1458 select ARM_PSCI_FW
1459 help
1460 Say Y here if you want Linux to communicate with system firmware
1461 implementing the PSCI specification for CPU-centric power
1462 management operations described in ARM document number ARM DEN
1463 0022A ("Power State Coordination Interface System Software on
1464 ARM processors").
1466 # The GPIO number here must be sorted by descending number. In case of
1467 # a multiplatform kernel, we just want the highest value required by the
1468 # selected platforms.
1469 config ARCH_NR_GPIO
1470 int
1471 default 2048 if ARCH_SOCFPGA
1472 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1473 ARCH_ZYNQ
1474 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1475 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1476 default 416 if ARCH_SUNXI
1477 default 392 if ARCH_U8500
1478 default 352 if ARCH_VT8500
1479 default 288 if ARCH_ROCKCHIP
1480 default 264 if MACH_H4700
1481 default 0
1482 help
1483 Maximum number of GPIOs in the system.
1485 If unsure, leave the default value.
1487 source kernel/Kconfig.preempt
1489 config HZ_FIXED
1490 int
1491 default 200 if ARCH_EBSA110
1492 default 128 if SOC_AT91RM9200
1493 default 0
1495 choice
1496 depends on HZ_FIXED = 0
1497 prompt "Timer frequency"
1499 config HZ_100
1500 bool "100 Hz"
1502 config HZ_200
1503 bool "200 Hz"
1505 config HZ_250
1506 bool "250 Hz"
1508 config HZ_300
1509 bool "300 Hz"
1511 config HZ_500
1512 bool "500 Hz"
1514 config HZ_1000
1515 bool "1000 Hz"
1517 endchoice
1519 config HZ
1520 int
1521 default HZ_FIXED if HZ_FIXED != 0
1522 default 100 if HZ_100
1523 default 200 if HZ_200
1524 default 250 if HZ_250
1525 default 300 if HZ_300
1526 default 500 if HZ_500
1527 default 1000
1529 config SCHED_HRTICK
1530 def_bool HIGH_RES_TIMERS
1532 config THUMB2_KERNEL
1533 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1534 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1535 default y if CPU_THUMBONLY
1536 select ARM_ASM_UNIFIED
1537 select ARM_UNWIND
1538 help
1539 By enabling this option, the kernel will be compiled in
1540 Thumb-2 mode. A compiler/assembler that understand the unified
1541 ARM-Thumb syntax is needed.
1543 If unsure, say N.
1545 config THUMB2_AVOID_R_ARM_THM_JUMP11
1546 bool "Work around buggy Thumb-2 short branch relocations in gas"
1547 depends on THUMB2_KERNEL && MODULES
1548 default y
1549 help
1550 Various binutils versions can resolve Thumb-2 branches to
1551 locally-defined, preemptible global symbols as short-range "b.n"
1552 branch instructions.
1554 This is a problem, because there's no guarantee the final
1555 destination of the symbol, or any candidate locations for a
1556 trampoline, are within range of the branch. For this reason, the
1557 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1558 relocation in modules at all, and it makes little sense to add
1559 support.
1561 The symptom is that the kernel fails with an "unsupported
1562 relocation" error when loading some modules.
1564 Until fixed tools are available, passing
1565 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1566 code which hits this problem, at the cost of a bit of extra runtime
1567 stack usage in some cases.
1569 The problem is described in more detail at:
1570 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1572 Only Thumb-2 kernels are affected.
1574 Unless you are sure your tools don't have this problem, say Y.
1576 config ARM_ASM_UNIFIED
1577 bool
1579 config ARM_PATCH_IDIV
1580 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1581 depends on CPU_32v7 && !XIP_KERNEL
1582 default y
1583 help
1584 The ARM compiler inserts calls to __aeabi_idiv() and
1585 __aeabi_uidiv() when it needs to perform division on signed
1586 and unsigned integers. Some v7 CPUs have support for the sdiv
1587 and udiv instructions that can be used to implement those
1588 functions.
1590 Enabling this option allows the kernel to modify itself to
1591 replace the first two instructions of these library functions
1592 with the sdiv or udiv plus "bx lr" instructions when the CPU
1593 it is running on supports them. Typically this will be faster
1594 and less power intensive than running the original library
1595 code to do integer division.
1597 config AEABI
1598 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K
1599 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K
1600 help
1601 This option allows for the kernel to be compiled using the latest
1602 ARM ABI (aka EABI). This is only useful if you are using a user
1603 space environment that is also compiled with EABI.
1605 Since there are major incompatibilities between the legacy ABI and
1606 EABI, especially with regard to structure member alignment, this
1607 option also changes the kernel syscall calling convention to
1608 disambiguate both ABIs and allow for backward compatibility support
1609 (selected with CONFIG_OABI_COMPAT).
1611 To use this you need GCC version 4.0.0 or later.
1613 config OABI_COMPAT
1614 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1615 depends on AEABI && !THUMB2_KERNEL
1616 help
1617 This option preserves the old syscall interface along with the
1618 new (ARM EABI) one. It also provides a compatibility layer to
1619 intercept syscalls that have structure arguments which layout
1620 in memory differs between the legacy ABI and the new ARM EABI
1621 (only for non "thumb" binaries). This option adds a tiny
1622 overhead to all syscalls and produces a slightly larger kernel.
1624 The seccomp filter system will not be available when this is
1625 selected, since there is no way yet to sensibly distinguish
1626 between calling conventions during filtering.
1628 If you know you'll be using only pure EABI user space then you
1629 can say N here. If this option is not selected and you attempt
1630 to execute a legacy ABI binary then the result will be
1631 UNPREDICTABLE (in fact it can be predicted that it won't work
1632 at all). If in doubt say N.
1634 config ARCH_HAS_HOLES_MEMORYMODEL
1635 bool
1637 config ARCH_SPARSEMEM_ENABLE
1638 bool
1640 config ARCH_SPARSEMEM_DEFAULT
1641 def_bool ARCH_SPARSEMEM_ENABLE
1643 config ARCH_SELECT_MEMORY_MODEL
1644 def_bool ARCH_SPARSEMEM_ENABLE
1646 config HAVE_ARCH_PFN_VALID
1647 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1649 config HAVE_GENERIC_GUP
1650 def_bool y
1651 depends on ARM_LPAE
1653 config HIGHMEM
1654 bool "High Memory Support"
1655 depends on MMU
1656 help
1657 The address space of ARM processors is only 4 Gigabytes large
1658 and it has to accommodate user address space, kernel address
1659 space as well as some memory mapped IO. That means that, if you
1660 have a large amount of physical memory and/or IO, not all of the
1661 memory can be "permanently mapped" by the kernel. The physical
1662 memory that is not permanently mapped is called "high memory".
1664 Depending on the selected kernel/user memory split, minimum
1665 vmalloc space and actual amount of RAM, you may not need this
1666 option which should result in a slightly faster kernel.
1668 If unsure, say n.
1670 config HIGHPTE
1671 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1672 depends on HIGHMEM
1673 default y
1674 help
1675 The VM uses one page of physical memory for each page table.
1676 For systems with a lot of processes, this can use a lot of
1677 precious low memory, eventually leading to low memory being
1678 consumed by page tables. Setting this option will allow
1679 user-space 2nd level page tables to reside in high memory.
1681 config CPU_SW_DOMAIN_PAN
1682 bool "Enable use of CPU domains to implement privileged no-access"
1683 depends on MMU && !ARM_LPAE
1684 default y
1685 help
1686 Increase kernel security by ensuring that normal kernel accesses
1687 are unable to access userspace addresses. This can help prevent
1688 use-after-free bugs becoming an exploitable privilege escalation
1689 by ensuring that magic values (such as LIST_POISON) will always
1690 fault when dereferenced.
1692 CPUs with low-vector mappings use a best-efforts implementation.
1693 Their lower 1MB needs to remain accessible for the vectors, but
1694 the remainder of userspace will become appropriately inaccessible.
1696 config HW_PERF_EVENTS
1697 def_bool y
1698 depends on ARM_PMU
1700 config SYS_SUPPORTS_HUGETLBFS
1701 def_bool y
1702 depends on ARM_LPAE
1704 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1705 def_bool y
1706 depends on ARM_LPAE
1708 config ARCH_WANT_GENERAL_HUGETLB
1709 def_bool y
1711 config ARM_MODULE_PLTS
1712 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1713 depends on MODULES
1714 help
1715 Allocate PLTs when loading modules so that jumps and calls whose
1716 targets are too far away for their relative offsets to be encoded
1717 in the instructions themselves can be bounced via veneers in the
1718 module's PLT. This allows modules to be allocated in the generic
1719 vmalloc area after the dedicated module memory area has been
1720 exhausted. The modules will use slightly more memory, but after
1721 rounding up to page size, the actual memory footprint is usually
1722 the same.
1724 Say y if you are getting out of memory errors while loading modules
1726 source "mm/Kconfig"
1728 config FORCE_MAX_ZONEORDER
1729 int "Maximum zone order"
1730 default "12" if SOC_AM33XX
1731 default "9" if SA1111 || ARCH_EFM32
1732 default "11"
1733 help
1734 The kernel memory allocator divides physically contiguous memory
1735 blocks into "zones", where each zone is a power of two number of
1736 pages. This option selects the largest power of two that the kernel
1737 keeps in the memory allocator. If you need to allocate very large
1738 blocks of physically contiguous memory, then you may need to
1739 increase this value.
1741 This config option is actually maximum order plus one. For example,
1742 a value of 11 means that the largest free memory block is 2^10 pages.
1744 config ALIGNMENT_TRAP
1745 bool
1746 depends on CPU_CP15_MMU
1747 default y if !ARCH_EBSA110
1748 select HAVE_PROC_CPU if PROC_FS
1749 help
1750 ARM processors cannot fetch/store information which is not
1751 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1752 address divisible by 4. On 32-bit ARM processors, these non-aligned
1753 fetch/store instructions will be emulated in software if you say
1754 here, which has a severe performance impact. This is necessary for
1755 correct operation of some network protocols. With an IP-only
1756 configuration it is safe to say N, otherwise say Y.
1758 config UACCESS_WITH_MEMCPY
1759 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1760 depends on MMU
1761 default y if CPU_FEROCEON
1762 help
1763 Implement faster copy_to_user and clear_user methods for CPU
1764 cores where a 8-word STM instruction give significantly higher
1765 memory write throughput than a sequence of individual 32bit stores.
1767 A possible side effect is a slight increase in scheduling latency
1768 between threads sharing the same address space if they invoke
1769 such copy operations with large buffers.
1771 However, if the CPU data cache is using a write-allocate mode,
1772 this option is unlikely to provide any performance gain.
1774 config SECCOMP
1775 bool
1776 prompt "Enable seccomp to safely compute untrusted bytecode"
1777 ---help---
1778 This kernel feature is useful for number crunching applications
1779 that may need to compute untrusted bytecode during their
1780 execution. By using pipes or other transports made available to
1781 the process as file descriptors supporting the read/write
1782 syscalls, it's possible to isolate those applications in
1783 their own address space using seccomp. Once seccomp is
1784 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1785 and the task is only allowed to execute a few safe syscalls
1786 defined by each seccomp mode.
1788 config SWIOTLB
1789 def_bool y
1791 config IOMMU_HELPER
1792 def_bool SWIOTLB
1794 config PARAVIRT
1795 bool "Enable paravirtualization code"
1796 help
1797 This changes the kernel so it can modify itself when it is run
1798 under a hypervisor, potentially improving performance significantly
1799 over full virtualization.
1801 config PARAVIRT_TIME_ACCOUNTING
1802 bool "Paravirtual steal time accounting"
1803 select PARAVIRT
1804 default n
1805 help
1806 Select this option to enable fine granularity task steal time
1807 accounting. Time spent executing other tasks in parallel with
1808 the current vCPU is discounted from the vCPU power. To account for
1809 that, there can be a small performance impact.
1811 If in doubt, say N here.
1813 config XEN_DOM0
1814 def_bool y
1815 depends on XEN
1817 config XEN
1818 bool "Xen guest support on ARM"
1819 depends on ARM && AEABI && OF
1820 depends on CPU_V7 && !CPU_V6
1821 depends on !GENERIC_ATOMIC64
1822 depends on MMU
1823 select ARCH_DMA_ADDR_T_64BIT
1824 select ARM_PSCI
1825 select SWIOTLB_XEN
1826 select PARAVIRT
1827 help
1828 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1830 endmenu
1832 menu "Boot options"
1834 config USE_OF
1835 bool "Flattened Device Tree support"
1836 select IRQ_DOMAIN
1837 select OF
1838 help
1839 Include support for flattened device tree machine descriptions.
1841 config ATAGS
1842 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1843 default y
1844 help
1845 This is the traditional way of passing data to the kernel at boot
1846 time. If you are solely relying on the flattened device tree (or
1847 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1848 to remove ATAGS support from your kernel binary. If unsure,
1849 leave this to y.
1851 config DEPRECATED_PARAM_STRUCT
1852 bool "Provide old way to pass kernel parameters"
1853 depends on ATAGS
1854 help
1855 This was deprecated in 2001 and announced to live on for 5 years.
1856 Some old boot loaders still use this way.
1858 # Compressed boot loader in ROM. Yes, we really want to ask about
1859 # TEXT and BSS so we preserve their values in the config files.
1860 config ZBOOT_ROM_TEXT
1861 hex "Compressed ROM boot loader base address"
1862 default "0"
1863 help
1864 The physical address at which the ROM-able zImage is to be
1865 placed in the target. Platforms which normally make use of
1866 ROM-able zImage formats normally set this to a suitable
1867 value in their defconfig file.
1869 If ZBOOT_ROM is not enabled, this has no effect.
1871 config ZBOOT_ROM_BSS
1872 hex "Compressed ROM boot loader BSS address"
1873 default "0"
1874 help
1875 The base address of an area of read/write memory in the target
1876 for the ROM-able zImage which must be available while the
1877 decompressor is running. It must be large enough to hold the
1878 entire decompressed kernel plus an additional 128 KiB.
1879 Platforms which normally make use of ROM-able zImage formats
1880 normally set this to a suitable value in their defconfig file.
1882 If ZBOOT_ROM is not enabled, this has no effect.
1884 config ZBOOT_ROM
1885 bool "Compressed boot loader in ROM/flash"
1886 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1887 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1888 help
1889 Say Y here if you intend to execute your compressed kernel image
1890 (zImage) directly from ROM or flash. If unsure, say N.
1892 config ARM_APPENDED_DTB
1893 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1894 depends on OF
1895 help
1896 With this option, the boot code will look for a device tree binary
1897 (DTB) appended to zImage
1898 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1900 This is meant as a backward compatibility convenience for those
1901 systems with a bootloader that can't be upgraded to accommodate
1902 the documented boot protocol using a device tree.
1904 Beware that there is very little in terms of protection against
1905 this option being confused by leftover garbage in memory that might
1906 look like a DTB header after a reboot if no actual DTB is appended
1907 to zImage. Do not leave this option active in a production kernel
1908 if you don't intend to always append a DTB. Proper passing of the
1909 location into r2 of a bootloader provided DTB is always preferable
1910 to this option.
1912 config ARM_ATAG_DTB_COMPAT
1913 bool "Supplement the appended DTB with traditional ATAG information"
1914 depends on ARM_APPENDED_DTB
1915 help
1916 Some old bootloaders can't be updated to a DTB capable one, yet
1917 they provide ATAGs with memory configuration, the ramdisk address,
1918 the kernel cmdline string, etc. Such information is dynamically
1919 provided by the bootloader and can't always be stored in a static
1920 DTB. To allow a device tree enabled kernel to be used with such
1921 bootloaders, this option allows zImage to extract the information
1922 from the ATAG list and store it at run time into the appended DTB.
1924 choice
1925 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1926 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1928 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1929 bool "Use bootloader kernel arguments if available"
1930 help
1931 Uses the command-line options passed by the boot loader instead of
1932 the device tree bootargs property. If the boot loader doesn't provide
1933 any, the device tree bootargs property will be used.
1935 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1936 bool "Extend with bootloader kernel arguments"
1937 help
1938 The command-line arguments provided by the boot loader will be
1939 appended to the the device tree bootargs property.
1941 endchoice
1943 config CMDLINE
1944 string "Default kernel command string"
1945 default ""
1946 help
1947 On some architectures (EBSA110 and CATS), there is currently no way
1948 for the boot loader to pass arguments to the kernel. For these
1949 architectures, you should supply some command-line options at build
1950 time by entering them here. As a minimum, you should specify the
1951 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1953 choice
1954 prompt "Kernel command line type" if CMDLINE != ""
1955 default CMDLINE_FROM_BOOTLOADER
1956 depends on ATAGS
1958 config CMDLINE_FROM_BOOTLOADER
1959 bool "Use bootloader kernel arguments if available"
1960 help
1961 Uses the command-line options passed by the boot loader. If
1962 the boot loader doesn't provide any, the default kernel command
1963 string provided in CMDLINE will be used.
1965 config CMDLINE_EXTEND
1966 bool "Extend bootloader kernel arguments"
1967 help
1968 The command-line arguments provided by the boot loader will be
1969 appended to the default kernel command string.
1971 config CMDLINE_FORCE
1972 bool "Always use the default kernel command string"
1973 help
1974 Always use the default kernel command string, even if the boot
1975 loader passes other arguments to the kernel.
1976 This is useful if you cannot or don't want to change the
1977 command-line options your boot loader passes to the kernel.
1978 endchoice
1980 config XIP_KERNEL
1981 bool "Kernel Execute-In-Place from ROM"
1982 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1983 help
1984 Execute-In-Place allows the kernel to run from non-volatile storage
1985 directly addressable by the CPU, such as NOR flash. This saves RAM
1986 space since the text section of the kernel is not loaded from flash
1987 to RAM. Read-write sections, such as the data section and stack,
1988 are still copied to RAM. The XIP kernel is not compressed since
1989 it has to run directly from flash, so it will take more space to
1990 store it. The flash address used to link the kernel object files,
1991 and for storing it, is configuration dependent. Therefore, if you
1992 say Y here, you must know the proper physical address where to
1993 store the kernel image depending on your own flash memory usage.
1995 Also note that the make target becomes "make xipImage" rather than
1996 "make zImage" or "make Image". The final kernel binary to put in
1997 ROM memory will be arch/arm/boot/xipImage.
1999 If unsure, say N.
2001 config XIP_PHYS_ADDR
2002 hex "XIP Kernel Physical Location"
2003 depends on XIP_KERNEL
2004 default "0x00080000"
2005 help
2006 This is the physical address in your flash memory the kernel will
2007 be linked for and stored to. This address is dependent on your
2008 own flash usage.
2010 config KEXEC
2011 bool "Kexec system call (EXPERIMENTAL)"
2012 depends on (!SMP || PM_SLEEP_SMP)
2013 depends on !CPU_V7M
2014 select KEXEC_CORE
2015 help
2016 kexec is a system call that implements the ability to shutdown your
2017 current kernel, and to start another kernel. It is like a reboot
2018 but it is independent of the system firmware. And like a reboot
2019 you can start any kernel with it, not just Linux.
2021 It is an ongoing process to be certain the hardware in a machine
2022 is properly shutdown, so do not be surprised if this code does not
2023 initially work for you.
2025 config ATAGS_PROC
2026 bool "Export atags in procfs"
2027 depends on ATAGS && KEXEC
2028 default y
2029 help
2030 Should the atags used to boot the kernel be exported in an "atags"
2031 file in procfs. Useful with kexec.
2033 config CRASH_DUMP
2034 bool "Build kdump crash kernel (EXPERIMENTAL)"
2035 help
2036 Generate crash dump after being started by kexec. This should
2037 be normally only set in special crash dump kernels which are
2038 loaded in the main kernel with kexec-tools into a specially
2039 reserved region and then later executed after a crash by
2040 kdump/kexec. The crash dump kernel must be compiled to a
2041 memory address not used by the main kernel
2043 For more details see Documentation/kdump/kdump.txt
2045 config AUTO_ZRELADDR
2046 bool "Auto calculation of the decompressed kernel image address"
2047 help
2048 ZRELADDR is the physical address where the decompressed kernel
2049 image will be placed. If AUTO_ZRELADDR is selected, the address
2050 will be determined at run-time by masking the current IP with
2051 0xf8000000. This assumes the zImage being placed in the first 128MB
2052 from start of memory.
2054 config EFI_STUB
2055 bool
2057 config EFI
2058 bool "UEFI runtime support"
2059 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2060 select UCS2_STRING
2061 select EFI_PARAMS_FROM_FDT
2062 select EFI_STUB
2063 select EFI_ARMSTUB
2064 select EFI_RUNTIME_WRAPPERS
2065 ---help---
2066 This option provides support for runtime services provided
2067 by UEFI firmware (such as non-volatile variables, realtime
2068 clock, and platform reset). A UEFI stub is also provided to
2069 allow the kernel to be booted as an EFI application. This
2070 is only useful for kernels that may run on systems that have
2071 UEFI firmware.
2073 config DMI
2074 bool "Enable support for SMBIOS (DMI) tables"
2075 depends on EFI
2076 default y
2077 help
2078 This enables SMBIOS/DMI feature for systems.
2080 This option is only useful on systems that have UEFI firmware.
2081 However, even with this option, the resultant kernel should
2082 continue to boot on existing non-UEFI platforms.
2084 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
2085 i.e., the the practice of identifying the platform via DMI to
2086 decide whether certain workarounds for buggy hardware and/or
2087 firmware need to be enabled. This would require the DMI subsystem
2088 to be enabled much earlier than we do on ARM, which is non-trivial.
2090 endmenu
2092 menu "CPU Power Management"
2094 source "drivers/cpufreq/Kconfig"
2096 source "drivers/cpuidle/Kconfig"
2098 endmenu
2100 menu "Floating point emulation"
2102 comment "At least one emulation must be selected"
2104 config FPE_NWFPE
2105 bool "NWFPE math emulation"
2106 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2107 ---help---
2108 Say Y to include the NWFPE floating point emulator in the kernel.
2109 This is necessary to run most binaries. Linux does not currently
2110 support floating point hardware so you need to say Y here even if
2111 your machine has an FPA or floating point co-processor podule.
2113 You may say N here if you are going to load the Acorn FPEmulator
2114 early in the bootup.
2116 config FPE_NWFPE_XP
2117 bool "Support extended precision"
2118 depends on FPE_NWFPE
2119 help
2120 Say Y to include 80-bit support in the kernel floating-point
2121 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2122 Note that gcc does not generate 80-bit operations by default,
2123 so in most cases this option only enlarges the size of the
2124 floating point emulator without any good reason.
2126 You almost surely want to say N here.
2128 config FPE_FASTFPE
2129 bool "FastFPE math emulation (EXPERIMENTAL)"
2130 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2131 ---help---
2132 Say Y here to include the FAST floating point emulator in the kernel.
2133 This is an experimental much faster emulator which now also has full
2134 precision for the mantissa. It does not support any exceptions.
2135 It is very simple, and approximately 3-6 times faster than NWFPE.
2137 It should be sufficient for most programs. It may be not suitable
2138 for scientific calculations, but you have to check this for yourself.
2139 If you do not feel you need a faster FP emulation you should better
2140 choose NWFPE.
2142 config VFP
2143 bool "VFP-format floating point maths"
2144 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2145 help
2146 Say Y to include VFP support code in the kernel. This is needed
2147 if your hardware includes a VFP unit.
2149 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2150 release notes and additional status information.
2152 Say N if your target does not have VFP hardware.
2154 config VFPv3
2155 bool
2156 depends on VFP
2157 default y if CPU_V7
2159 config NEON
2160 bool "Advanced SIMD (NEON) Extension support"
2161 depends on VFPv3 && CPU_V7
2162 help
2163 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2164 Extension.
2166 config KERNEL_MODE_NEON
2167 bool "Support for NEON in kernel mode"
2168 depends on NEON && AEABI
2169 help
2170 Say Y to include support for NEON in kernel mode.
2172 endmenu
2174 menu "Userspace binary formats"
2176 source "fs/Kconfig.binfmt"
2178 endmenu
2180 menu "Power management options"
2182 source "kernel/power/Kconfig"
2184 config ARCH_SUSPEND_POSSIBLE
2185 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2186 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2187 def_bool y
2189 config ARM_CPU_SUSPEND
2190 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2191 depends on ARCH_SUSPEND_POSSIBLE
2193 config ARCH_HIBERNATION_POSSIBLE
2194 bool
2195 depends on MMU
2196 default y if ARCH_SUSPEND_POSSIBLE
2198 endmenu
2200 source "net/Kconfig"
2202 source "drivers/Kconfig"
2204 source "drivers/firmware/Kconfig"
2206 source "fs/Kconfig"
2208 source "arch/arm/Kconfig.debug"
2210 source "security/Kconfig"
2212 source "crypto/Kconfig"
2213 if CRYPTO
2214 source "arch/arm/crypto/Kconfig"
2215 endif
2217 source "lib/Kconfig"
2219 source "arch/arm/kvm/Kconfig"