x86/speculation/mds: Fix documentation typo
[linux/fpc-iii.git] / arch / arm / mach-lpc32xx / serial.c
blob1931229a1eaa6c3ab40de07d4b1a24336f3d7548
1 /*
2 * arch/arm/mach-lpc32xx/serial.c
4 * Author: Kevin Wells <kevin.wells@nxp.com>
6 * Copyright (C) 2010 NXP Semiconductors
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/serial.h>
22 #include <linux/serial_core.h>
23 #include <linux/serial_reg.h>
24 #include <linux/serial_8250.h>
25 #include <linux/clk.h>
26 #include <linux/io.h>
28 #include <mach/hardware.h>
29 #include <mach/platform.h>
30 #include "common.h"
32 #define LPC32XX_SUART_FIFO_SIZE 64
34 struct uartinit {
35 char *uart_ck_name;
36 u32 ck_mode_mask;
37 void __iomem *pdiv_clk_reg;
38 resource_size_t mapbase;
41 static struct uartinit uartinit_data[] __initdata = {
43 .uart_ck_name = "uart5_ck",
44 .ck_mode_mask =
45 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5),
46 .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,
47 .mapbase = LPC32XX_UART5_BASE,
50 .uart_ck_name = "uart3_ck",
51 .ck_mode_mask =
52 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3),
53 .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,
54 .mapbase = LPC32XX_UART3_BASE,
57 .uart_ck_name = "uart4_ck",
58 .ck_mode_mask =
59 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4),
60 .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,
61 .mapbase = LPC32XX_UART4_BASE,
64 .uart_ck_name = "uart6_ck",
65 .ck_mode_mask =
66 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6),
67 .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,
68 .mapbase = LPC32XX_UART6_BASE,
72 void __init lpc32xx_serial_init(void)
74 u32 tmp, clkmodes = 0;
75 struct clk *clk;
76 unsigned int puart;
77 int i, j;
79 for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
80 clk = clk_get(NULL, uartinit_data[i].uart_ck_name);
81 if (!IS_ERR(clk)) {
82 clk_enable(clk);
85 /* Setup UART clock modes for all UARTs, disable autoclock */
86 clkmodes |= uartinit_data[i].ck_mode_mask;
88 /* pre-UART clock divider set to 1 */
89 __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg);
92 * Force a flush of the RX FIFOs to work around a
93 * HW bug
95 puart = uartinit_data[i].mapbase;
96 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
97 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
98 j = LPC32XX_SUART_FIFO_SIZE;
99 while (j--)
100 tmp = __raw_readl(
101 LPC32XX_UART_DLL_FIFO(puart));
102 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
105 /* This needs to be done after all UART clocks are setup */
106 __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
107 for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
108 /* Force a flush of the RX FIFOs to work around a HW bug */
109 puart = uartinit_data[i].mapbase;
110 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
111 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
112 j = LPC32XX_SUART_FIFO_SIZE;
113 while (j--)
114 tmp = __raw_readl(LPC32XX_UART_DLL_FIFO(puart));
115 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
118 /* Disable IrDA pulsing support on UART6 */
119 tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
120 tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
121 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
123 /* Disable UART5->USB transparent mode or USB won't work */
124 tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
125 tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
126 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);