arch/arm/mach-shmobile/platsmp-apmu.c

   1 /*
   2  * SMP support for SoCs with APMU
   3  *
   4  * Copyright (C) 2014  Renesas Electronics Corporation
   5  * Copyright (C) 2013  Magnus Damm
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #include <linux/cpu_pm.h>
  12 #include <linux/delay.h>
  13 #include <linux/init.h>
  14 #include <linux/io.h>
  15 #include <linux/ioport.h>
  16 #include <linux/of_address.h>
  17 #include <linux/smp.h>
  18 #include <linux/suspend.h>
  19 #include <linux/threads.h>
  20 #include <asm/cacheflush.h>
  21 #include <asm/cp15.h>
  22 #include <asm/proc-fns.h>
  23 #include <asm/smp_plat.h>
  24 #include <asm/suspend.h>
  25 #include "common.h"
  26 #include "platsmp-apmu.h"
  27 #include "rcar-gen2.h"
  28
  29 static struct {
  30         void __iomem *iomem;
  31         int bit;
  32 } apmu_cpus[NR_CPUS];
  33
  34 #define WUPCR_OFFS       0x10           /* Wake Up Control Register */
  35 #define PSTR_OFFS        0x40           /* Power Status Register */
  36 #define CPUNCR_OFFS(n)  (0x100 + (0x10 * (n)))
  37                                         /* CPUn Power Status Control Register */
  38 #define DBGRCR_OFFS     0x180           /* Debug Resource Reset Control Reg. */
  39
  40 /* Power Status Register */
  41 #define CPUNST(r, n)    (((r) >> (n * 4)) & 3)  /* CPUn Status Bit */
  42 #define CPUST_RUN       0               /* Run Mode */
  43 #define CPUST_STANDBY   3               /* CoreStandby Mode */
  44
  45 /* Debug Resource Reset Control Register */
  46 #define DBGCPUREN       BIT(24)         /* CPU Other Reset Request Enable */
  47 #define DBGCPUNREN(n)   BIT((n) + 20)   /* CPUn Reset Request Enable */
  48 #define DBGCPUPREN      BIT(19)         /* CPU Peripheral Reset Req. Enable */
  49
  50 static int __maybe_unused apmu_power_on(void __iomem *p, int bit)
  51 {
  52         /* request power on */
  53         writel_relaxed(BIT(bit), p + WUPCR_OFFS);
  54
  55         /* wait for APMU to finish */
  56         while (readl_relaxed(p + WUPCR_OFFS) != 0)
  57                 ;
  58
  59         return 0;
  60 }
  61
  62 static int __maybe_unused apmu_power_off(void __iomem *p, int bit)
  63 {
  64         /* request Core Standby for next WFI */
  65         writel_relaxed(3, p + CPUNCR_OFFS(bit));
  66         return 0;
  67 }
  68
  69 static int __maybe_unused apmu_power_off_poll(void __iomem *p, int bit)
  70 {
  71         int k;
  72
  73         for (k = 0; k < 1000; k++) {
  74                 if (CPUNST(readl_relaxed(p + PSTR_OFFS), bit) == CPUST_STANDBY)
  75                         return 1;
  76
  77                 mdelay(1);
  78         }
  79
  80         return 0;
  81 }
  82
  83 static int __maybe_unused apmu_wrap(int cpu, int (*fn)(void __iomem *p, int cpu))
  84 {
  85         void __iomem *p = apmu_cpus[cpu].iomem;
  86
  87         return p ? fn(p, apmu_cpus[cpu].bit) : -EINVAL;
  88 }
  89
  90 #ifdef CONFIG_SMP
  91 static void apmu_init_cpu(struct resource *res, int cpu, int bit)
  92 {
  93         u32 x;
  94
  95         if ((cpu >= ARRAY_SIZE(apmu_cpus)) || apmu_cpus[cpu].iomem)
  96                 return;
  97
  98         apmu_cpus[cpu].iomem = ioremap_nocache(res->start, resource_size(res));
  99         apmu_cpus[cpu].bit = bit;
 100
 101         pr_debug("apmu ioremap %d %d %pr\n", cpu, bit, res);
 102
 103         /* Setup for debug mode */
 104         x = readl(apmu_cpus[cpu].iomem + DBGRCR_OFFS);
 105         x |= DBGCPUREN | DBGCPUNREN(bit) | DBGCPUPREN;
 106         writel(x, apmu_cpus[cpu].iomem + DBGRCR_OFFS);
 107 }
 108
 109 static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit),
 110                            struct rcar_apmu_config *apmu_config, int num)
 111 {
 112         int id;
 113         int k;
 114         int bit, index;
 115         bool is_allowed;
 116
 117         for (k = 0; k < num; k++) {
 118                 /* only enable the cluster that includes the boot CPU */
 119                 is_allowed = false;
 120                 for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) {
 121                         id = apmu_config[k].cpus[bit];
 122                         if (id >= 0) {
 123                                 if (id == cpu_logical_map(0))
 124                                         is_allowed = true;
 125                         }
 126                 }
 127                 if (!is_allowed)
 128                         continue;
 129
 130                 for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) {
 131                         id = apmu_config[k].cpus[bit];
 132                         if (id >= 0) {
 133                                 index = get_logical_index(id);
 134                                 if (index >= 0)
 135                                         fn(&apmu_config[k].iomem, index, bit);
 136                         }
 137                 }
 138         }
 139 }
 140
 141 static const struct of_device_id apmu_ids[] = {
 142         { .compatible = "renesas,apmu" },
 143         { /*sentinel*/ }
 144 };
 145
 146 static void apmu_parse_dt(void (*fn)(struct resource *res, int cpu, int bit))
 147 {
 148         struct device_node *np_apmu, *np_cpu;
 149         struct resource res;
 150         int bit, index;
 151         u32 id;
 152
 153         for_each_matching_node(np_apmu, apmu_ids) {
 154                 /* only enable the cluster that includes the boot CPU */
 155                 bool is_allowed = false;
 156
 157                 for (bit = 0; bit < CONFIG_NR_CPUS; bit++) {
 158                         np_cpu = of_parse_phandle(np_apmu, "cpus", bit);
 159                         if (np_cpu) {
 160                                 if (!of_property_read_u32(np_cpu, "reg", &id)) {
 161                                         if (id == cpu_logical_map(0)) {
 162                                                 is_allowed = true;
 163                                                 of_node_put(np_cpu);
 164                                                 break;
 165                                         }
 166
 167                                 }
 168                                 of_node_put(np_cpu);
 169                         }
 170                 }
 171                 if (!is_allowed)
 172                         continue;
 173
 174                 for (bit = 0; bit < CONFIG_NR_CPUS; bit++) {
 175                         np_cpu = of_parse_phandle(np_apmu, "cpus", bit);
 176                         if (np_cpu) {
 177                                 if (!of_property_read_u32(np_cpu, "reg", &id)) {
 178                                         index = get_logical_index(id);
 179                                         if ((index >= 0) &&
 180                                             !of_address_to_resource(np_apmu,
 181                                                                     0, &res))
 182                                                 fn(&res, index, bit);
 183                                 }
 184                                 of_node_put(np_cpu);
 185                         }
 186                 }
 187         }
 188 }
 189
 190 static void __init shmobile_smp_apmu_setup_boot(void)
 191 {
 192         /* install boot code shared by all CPUs */
 193         shmobile_boot_fn = __pa_symbol(shmobile_smp_boot);
 194 }
 195
 196 void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
 197                                            struct rcar_apmu_config *apmu_config,
 198                                            int num)
 199 {
 200         shmobile_smp_apmu_setup_boot();
 201         apmu_parse_cfg(apmu_init_cpu, apmu_config, num);
 202 }
 203
 204 int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
 205 {
 206         /* For this particular CPU register boot vector */
 207         shmobile_smp_hook(cpu, __pa_symbol(secondary_startup), 0);
 208
 209         return apmu_wrap(cpu, apmu_power_on);
 210 }
 211
 212 static void __init shmobile_smp_apmu_prepare_cpus_dt(unsigned int max_cpus)
 213 {
 214         shmobile_smp_apmu_setup_boot();
 215         apmu_parse_dt(apmu_init_cpu);
 216         rcar_gen2_pm_init();
 217 }
 218
 219 static struct smp_operations apmu_smp_ops __initdata = {
 220         .smp_prepare_cpus       = shmobile_smp_apmu_prepare_cpus_dt,
 221         .smp_boot_secondary     = shmobile_smp_apmu_boot_secondary,
 222 #ifdef CONFIG_HOTPLUG_CPU
 223         .cpu_can_disable        = shmobile_smp_cpu_can_disable,
 224         .cpu_die                = shmobile_smp_apmu_cpu_die,
 225         .cpu_kill               = shmobile_smp_apmu_cpu_kill,
 226 #endif
 227 };
 228
 229 CPU_METHOD_OF_DECLARE(shmobile_smp_apmu, "renesas,apmu", &apmu_smp_ops);
 230 #endif /* CONFIG_SMP */
 231
 232 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_SUSPEND)
 233 /* nicked from arch/arm/mach-exynos/hotplug.c */
 234 static inline void cpu_enter_lowpower_a15(void)
 235 {
 236         unsigned int v;
 237
 238         asm volatile(
 239         "       mrc     p15, 0, %0, c1, c0, 0\n"
 240         "       bic     %0, %0, %1\n"
 241         "       mcr     p15, 0, %0, c1, c0, 0\n"
 242                 : "=&r" (v)
 243                 : "Ir" (CR_C)
 244                 : "cc");
 245
 246         flush_cache_louis();
 247
 248         asm volatile(
 249         /*
 250          * Turn off coherency
 251          */
 252         "       mrc     p15, 0, %0, c1, c0, 1\n"
 253         "       bic     %0, %0, %1\n"
 254         "       mcr     p15, 0, %0, c1, c0, 1\n"
 255                 : "=&r" (v)
 256                 : "Ir" (0x40)
 257                 : "cc");
 258
 259         isb();
 260         dsb();
 261 }
 262
 263 static void shmobile_smp_apmu_cpu_shutdown(unsigned int cpu)
 264 {
 265
 266         /* Select next sleep mode using the APMU */
 267         apmu_wrap(cpu, apmu_power_off);
 268
 269         /* Do ARM specific CPU shutdown */
 270         cpu_enter_lowpower_a15();
 271 }
 272
 273 static inline void cpu_leave_lowpower(void)
 274 {
 275         unsigned int v;
 276
 277         asm volatile("mrc    p15, 0, %0, c1, c0, 0\n"
 278                      "       orr     %0, %0, %1\n"
 279                      "       mcr     p15, 0, %0, c1, c0, 0\n"
 280                      "       mrc     p15, 0, %0, c1, c0, 1\n"
 281                      "       orr     %0, %0, %2\n"
 282                      "       mcr     p15, 0, %0, c1, c0, 1\n"
 283                      : "=&r" (v)
 284                      : "Ir" (CR_C), "Ir" (0x40)
 285                      : "cc");
 286 }
 287 #endif
 288
 289 #if defined(CONFIG_HOTPLUG_CPU)
 290 void shmobile_smp_apmu_cpu_die(unsigned int cpu)
 291 {
 292         /* For this particular CPU deregister boot vector */
 293         shmobile_smp_hook(cpu, 0, 0);
 294
 295         /* Shutdown CPU core */
 296         shmobile_smp_apmu_cpu_shutdown(cpu);
 297
 298         /* jump to shared mach-shmobile sleep / reset code */
 299         shmobile_smp_sleep();
 300 }
 301
 302 int shmobile_smp_apmu_cpu_kill(unsigned int cpu)
 303 {
 304         return apmu_wrap(cpu, apmu_power_off_poll);
 305 }
 306 #endif
 307
 308 #if defined(CONFIG_SUSPEND)
 309 static int shmobile_smp_apmu_do_suspend(unsigned long cpu)
 310 {
 311         shmobile_smp_hook(cpu, __pa_symbol(cpu_resume), 0);
 312         shmobile_smp_apmu_cpu_shutdown(cpu);
 313         cpu_do_idle(); /* WFI selects Core Standby */
 314         return 1;
 315 }
 316
 317 static int shmobile_smp_apmu_enter_suspend(suspend_state_t state)
 318 {
 319         cpu_suspend(smp_processor_id(), shmobile_smp_apmu_do_suspend);
 320         cpu_leave_lowpower();
 321         return 0;
 322 }
 323
 324 void __init shmobile_smp_apmu_suspend_init(void)
 325 {
 326         shmobile_suspend_ops.enter = shmobile_smp_apmu_enter_suspend;
 327 }
 328 #endif