arch/blackfin/include/asm/bfin_sdh.h

   1 /*
   2  * Blackfin Secure Digital Host (SDH) definitions
   3  *
   4  * Copyright 2008-2010 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #ifndef __BFIN_SDH_H__
  10 #define __BFIN_SDH_H__
  11
  12 /* Platform resources */
  13 struct bfin_sd_host {
  14         int dma_chan;
  15         int irq_int0;
  16         int irq_int1;
  17         u16 pin_req[7];
  18 };
  19
  20 /* SDH_COMMAND bitmasks */
  21 #define CMD_IDX            0x3f        /* Command Index */
  22 #define CMD_RSP            (1 << 6)    /* Response */
  23 #define CMD_L_RSP          (1 << 7)    /* Long Response */
  24 #define CMD_INT_E          (1 << 8)    /* Command Interrupt */
  25 #define CMD_PEND_E         (1 << 9)    /* Command Pending */
  26 #define CMD_E              (1 << 10)   /* Command Enable */
  27 #ifdef RSI_BLKSZ
  28 #define CMD_CRC_CHECK_D    (1 << 11)   /* CRC Check is disabled */
  29 #define CMD_DATA0_BUSY     (1 << 12)   /* Check for Busy State on the DATA0 pin */
  30 #endif
  31
  32 /* SDH_PWR_CTL bitmasks */
  33 #ifndef RSI_BLKSZ
  34 #define PWR_ON             0x3         /* Power On */
  35 #define SD_CMD_OD          (1 << 6)    /* Open Drain Output */
  36 #define ROD_CTL            (1 << 7)    /* Rod Control */
  37 #endif
  38
  39 /* SDH_CLK_CTL bitmasks */
  40 #define CLKDIV             0xff        /* MC_CLK Divisor */
  41 #define CLK_E              (1 << 8)    /* MC_CLK Bus Clock Enable */
  42 #define PWR_SV_E           (1 << 9)    /* Power Save Enable */
  43 #define CLKDIV_BYPASS      (1 << 10)   /* Bypass Divisor */
  44 #define BUS_MODE_MASK      0x1800      /* Bus Mode Mask */
  45 #define STD_BUS_1          0x000       /* Standard Bus 1 bit mode */
  46 #define WIDE_BUS_4         0x800       /* Wide Bus 4 bit mode */
  47 #define BYTE_BUS_8         0x1000      /* Byte Bus 8 bit mode */
  48
  49 /* SDH_RESP_CMD bitmasks */
  50 #define RESP_CMD           0x3f        /* Response Command */
  51
  52 /* SDH_DATA_CTL bitmasks */
  53 #define DTX_E              (1 << 0)    /* Data Transfer Enable */
  54 #define DTX_DIR            (1 << 1)    /* Data Transfer Direction */
  55 #define DTX_MODE           (1 << 2)    /* Data Transfer Mode */
  56 #define DTX_DMA_E          (1 << 3)    /* Data Transfer DMA Enable */
  57 #ifndef RSI_BLKSZ
  58 #define DTX_BLK_LGTH       (0xf << 4)  /* Data Transfer Block Length */
  59 #else
  60
  61 /* Bit masks for SDH_BLK_SIZE */
  62 #define DTX_BLK_LGTH       0x1fff      /* Data Transfer Block Length */
  63 #endif
  64
  65 /* SDH_STATUS bitmasks */
  66 #define CMD_CRC_FAIL       (1 << 0)    /* CMD CRC Fail */
  67 #define DAT_CRC_FAIL       (1 << 1)    /* Data CRC Fail */
  68 #define CMD_TIME_OUT       (1 << 2)    /* CMD Time Out */
  69 #define DAT_TIME_OUT       (1 << 3)    /* Data Time Out */
  70 #define TX_UNDERRUN        (1 << 4)    /* Transmit Underrun */
  71 #define RX_OVERRUN         (1 << 5)    /* Receive Overrun */
  72 #define CMD_RESP_END       (1 << 6)    /* CMD Response End */
  73 #define CMD_SENT           (1 << 7)    /* CMD Sent */
  74 #define DAT_END            (1 << 8)    /* Data End */
  75 #define START_BIT_ERR      (1 << 9)    /* Start Bit Error */
  76 #define DAT_BLK_END        (1 << 10)   /* Data Block End */
  77 #define CMD_ACT            (1 << 11)   /* CMD Active */
  78 #define TX_ACT             (1 << 12)   /* Transmit Active */
  79 #define RX_ACT             (1 << 13)   /* Receive Active */
  80 #define TX_FIFO_STAT       (1 << 14)   /* Transmit FIFO Status */
  81 #define RX_FIFO_STAT       (1 << 15)   /* Receive FIFO Status */
  82 #define TX_FIFO_FULL       (1 << 16)   /* Transmit FIFO Full */
  83 #define RX_FIFO_FULL       (1 << 17)   /* Receive FIFO Full */
  84 #define TX_FIFO_ZERO       (1 << 18)   /* Transmit FIFO Empty */
  85 #define RX_DAT_ZERO        (1 << 19)   /* Receive FIFO Empty */
  86 #define TX_DAT_RDY         (1 << 20)   /* Transmit Data Available */
  87 #define RX_FIFO_RDY        (1 << 21)   /* Receive Data Available */
  88
  89 /* SDH_STATUS_CLR bitmasks */
  90 #define CMD_CRC_FAIL_STAT  (1 << 0)    /* CMD CRC Fail Status */
  91 #define DAT_CRC_FAIL_STAT  (1 << 1)    /* Data CRC Fail Status */
  92 #define CMD_TIMEOUT_STAT   (1 << 2)    /* CMD Time Out Status */
  93 #define DAT_TIMEOUT_STAT   (1 << 3)    /* Data Time Out status */
  94 #define TX_UNDERRUN_STAT   (1 << 4)    /* Transmit Underrun Status */
  95 #define RX_OVERRUN_STAT    (1 << 5)    /* Receive Overrun Status */
  96 #define CMD_RESP_END_STAT  (1 << 6)    /* CMD Response End Status */
  97 #define CMD_SENT_STAT      (1 << 7)    /* CMD Sent Status */
  98 #define DAT_END_STAT       (1 << 8)    /* Data End Status */
  99 #define START_BIT_ERR_STAT (1 << 9)    /* Start Bit Error Status */
 100 #define DAT_BLK_END_STAT   (1 << 10)   /* Data Block End Status */
 101
 102 /* SDH_MASK0 bitmasks */
 103 #define CMD_CRC_FAIL_MASK  (1 << 0)    /* CMD CRC Fail Mask */
 104 #define DAT_CRC_FAIL_MASK  (1 << 1)    /* Data CRC Fail Mask */
 105 #define CMD_TIMEOUT_MASK   (1 << 2)    /* CMD Time Out Mask */
 106 #define DAT_TIMEOUT_MASK   (1 << 3)    /* Data Time Out Mask */
 107 #define TX_UNDERRUN_MASK   (1 << 4)    /* Transmit Underrun Mask */
 108 #define RX_OVERRUN_MASK    (1 << 5)    /* Receive Overrun Mask */
 109 #define CMD_RESP_END_MASK  (1 << 6)    /* CMD Response End Mask */
 110 #define CMD_SENT_MASK      (1 << 7)    /* CMD Sent Mask */
 111 #define DAT_END_MASK       (1 << 8)    /* Data End Mask */
 112 #define START_BIT_ERR_MASK (1 << 9)    /* Start Bit Error Mask */
 113 #define DAT_BLK_END_MASK   (1 << 10)   /* Data Block End Mask */
 114 #define CMD_ACT_MASK       (1 << 11)   /* CMD Active Mask */
 115 #define TX_ACT_MASK        (1 << 12)   /* Transmit Active Mask */
 116 #define RX_ACT_MASK        (1 << 13)   /* Receive Active Mask */
 117 #define TX_FIFO_STAT_MASK  (1 << 14)   /* Transmit FIFO Status Mask */
 118 #define RX_FIFO_STAT_MASK  (1 << 15)   /* Receive FIFO Status Mask */
 119 #define TX_FIFO_FULL_MASK  (1 << 16)   /* Transmit FIFO Full Mask */
 120 #define RX_FIFO_FULL_MASK  (1 << 17)   /* Receive FIFO Full Mask */
 121 #define TX_FIFO_ZERO_MASK  (1 << 18)   /* Transmit FIFO Empty Mask */
 122 #define RX_DAT_ZERO_MASK   (1 << 19)   /* Receive FIFO Empty Mask */
 123 #define TX_DAT_RDY_MASK    (1 << 20)   /* Transmit Data Available Mask */
 124 #define RX_FIFO_RDY_MASK   (1 << 21)   /* Receive Data Available Mask */
 125
 126 /* SDH_FIFO_CNT bitmasks */
 127 #define FIFO_COUNT         0x7fff      /* FIFO Count */
 128
 129 /* SDH_E_STATUS bitmasks */
 130 #define SDIO_INT_DET       (1 << 1)    /* SDIO Int Detected */
 131 #define SD_CARD_DET        (1 << 4)    /* SD Card Detect */
 132 #define SD_CARD_BUSYMODE   (1 << 31)   /* Card is in Busy mode */
 133 #define SD_CARD_SLPMODE    (1 << 30)   /* Card in Sleep Mode */
 134 #define SD_CARD_READY      (1 << 17)   /* Card Ready */
 135
 136 /* SDH_E_MASK bitmasks */
 137 #define SDIO_MSK           (1 << 1)    /* Mask SDIO Int Detected */
 138 #define SCD_MSK            (1 << 4)    /* Mask Card Detect */
 139 #define CARD_READY_MSK     (1 << 16)   /* Mask Card Ready */
 140
 141 /* SDH_CFG bitmasks */
 142 #define CLKS_EN            (1 << 0)    /* Clocks Enable */
 143 #define SD4E               (1 << 2)    /* SDIO 4-Bit Enable */
 144 #define MWE                (1 << 3)    /* Moving Window Enable */
 145 #define SD_RST             (1 << 4)    /* SDMMC Reset */
 146 #define PUP_SDDAT          (1 << 5)    /* Pull-up SD_DAT */
 147 #define PUP_SDDAT3         (1 << 6)    /* Pull-up SD_DAT3 */
 148 #ifndef RSI_BLKSZ
 149 #define PD_SDDAT3          (1 << 7)    /* Pull-down SD_DAT3 */
 150 #else
 151 #define PWR_ON             0x600       /* Power On */
 152 #define SD_CMD_OD          (1 << 11)   /* Open Drain Output */
 153 #define BOOT_EN            (1 << 12)   /* Boot Enable */
 154 #define BOOT_MODE          (1 << 13)   /* Alternate Boot Mode */
 155 #define BOOT_ACK_EN        (1 << 14)   /* Boot ACK is expected */
 156 #endif
 157
 158 /* SDH_RD_WAIT_EN bitmasks */
 159 #define RWR                (1 << 0)    /* Read Wait Request */
 160
 161 #endif