arch/powerpc/crypto/sha1-powerpc-asm.S

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * SHA-1 implementation for PowerPC.
   4  *
   5  * Copyright (C) 2005 Paul Mackerras <paulus@samba.org>
   6  */
   7
   8 #include <asm/ppc_asm.h>
   9 #include <asm/asm-offsets.h>
  10
  11 #ifdef __BIG_ENDIAN__
  12 #define LWZ(rt, d, ra)  \
  13         lwz     rt,d(ra)
  14 #else
  15 #define LWZ(rt, d, ra)  \
  16         li      rt,d;   \
  17         lwbrx   rt,rt,ra
  18 #endif
  19
  20 /*
  21  * We roll the registers for T, A, B, C, D, E around on each
  22  * iteration; T on iteration t is A on iteration t+1, and so on.
  23  * We use registers 7 - 12 for this.
  24  */
  25 #define RT(t)   ((((t)+5)%6)+7)
  26 #define RA(t)   ((((t)+4)%6)+7)
  27 #define RB(t)   ((((t)+3)%6)+7)
  28 #define RC(t)   ((((t)+2)%6)+7)
  29 #define RD(t)   ((((t)+1)%6)+7)
  30 #define RE(t)   ((((t)+0)%6)+7)
  31
  32 /* We use registers 16 - 31 for the W values */
  33 #define W(t)    (((t)%16)+16)
  34
  35 #define LOADW(t)                                \
  36         LWZ(W(t),(t)*4,r4)
  37
  38 #define STEPD0_LOAD(t)                          \
  39         andc    r0,RD(t),RB(t);         \
  40         and     r6,RB(t),RC(t);         \
  41         rotlwi  RT(t),RA(t),5;                  \
  42         or      r6,r6,r0;                       \
  43         add     r0,RE(t),r15;                   \
  44         add     RT(t),RT(t),r6;         \
  45         add     r14,r0,W(t);                    \
  46         LWZ(W((t)+4),((t)+4)*4,r4);     \
  47         rotlwi  RB(t),RB(t),30;                 \
  48         add     RT(t),RT(t),r14
  49
  50 #define STEPD0_UPDATE(t)                        \
  51         and     r6,RB(t),RC(t);         \
  52         andc    r0,RD(t),RB(t);         \
  53         rotlwi  RT(t),RA(t),5;                  \
  54         rotlwi  RB(t),RB(t),30;                 \
  55         or      r6,r6,r0;                       \
  56         add     r0,RE(t),r15;                   \
  57         xor     r5,W((t)+4-3),W((t)+4-8);               \
  58         add     RT(t),RT(t),r6;         \
  59         xor     W((t)+4),W((t)+4-16),W((t)+4-14);       \
  60         add     r0,r0,W(t);                     \
  61         xor     W((t)+4),W((t)+4),r5;                   \
  62         add     RT(t),RT(t),r0;         \
  63         rotlwi  W((t)+4),W((t)+4),1
  64
  65 #define STEPD1(t)                               \
  66         xor     r6,RB(t),RC(t);         \
  67         rotlwi  RT(t),RA(t),5;                  \
  68         rotlwi  RB(t),RB(t),30;                 \
  69         xor     r6,r6,RD(t);                    \
  70         add     r0,RE(t),r15;                   \
  71         add     RT(t),RT(t),r6;         \
  72         add     r0,r0,W(t);                     \
  73         add     RT(t),RT(t),r0
  74
  75 #define STEPD1_UPDATE(t)                                \
  76         xor     r6,RB(t),RC(t);         \
  77         rotlwi  RT(t),RA(t),5;                  \
  78         rotlwi  RB(t),RB(t),30;                 \
  79         xor     r6,r6,RD(t);                    \
  80         add     r0,RE(t),r15;                   \
  81         xor     r5,W((t)+4-3),W((t)+4-8);               \
  82         add     RT(t),RT(t),r6;         \
  83         xor     W((t)+4),W((t)+4-16),W((t)+4-14);       \
  84         add     r0,r0,W(t);                     \
  85         xor     W((t)+4),W((t)+4),r5;                   \
  86         add     RT(t),RT(t),r0;         \
  87         rotlwi  W((t)+4),W((t)+4),1
  88
  89 #define STEPD2_UPDATE(t)                        \
  90         and     r6,RB(t),RC(t);         \
  91         and     r0,RB(t),RD(t);         \
  92         rotlwi  RT(t),RA(t),5;                  \
  93         or      r6,r6,r0;                       \
  94         rotlwi  RB(t),RB(t),30;                 \
  95         and     r0,RC(t),RD(t);         \
  96         xor     r5,W((t)+4-3),W((t)+4-8);       \
  97         or      r6,r6,r0;                       \
  98         xor     W((t)+4),W((t)+4-16),W((t)+4-14);       \
  99         add     r0,RE(t),r15;                   \
 100         add     RT(t),RT(t),r6;         \
 101         add     r0,r0,W(t);                     \
 102         xor     W((t)+4),W((t)+4),r5;           \
 103         add     RT(t),RT(t),r0;         \
 104         rotlwi  W((t)+4),W((t)+4),1
 105
 106 #define STEP0LD4(t)                             \
 107         STEPD0_LOAD(t);                         \
 108         STEPD0_LOAD((t)+1);                     \
 109         STEPD0_LOAD((t)+2);                     \
 110         STEPD0_LOAD((t)+3)
 111
 112 #define STEPUP4(t, fn)                          \
 113         STEP##fn##_UPDATE(t);                   \
 114         STEP##fn##_UPDATE((t)+1);               \
 115         STEP##fn##_UPDATE((t)+2);               \
 116         STEP##fn##_UPDATE((t)+3)
 117
 118 #define STEPUP20(t, fn)                         \
 119         STEPUP4(t, fn);                         \
 120         STEPUP4((t)+4, fn);                     \
 121         STEPUP4((t)+8, fn);                     \
 122         STEPUP4((t)+12, fn);                    \
 123         STEPUP4((t)+16, fn)
 124
 125 _GLOBAL(powerpc_sha_transform)
 126         PPC_STLU r1,-INT_FRAME_SIZE(r1)
 127         SAVE_8GPRS(14, r1)
 128         SAVE_10GPRS(22, r1)
 129
 130         /* Load up A - E */
 131         lwz     RA(0),0(r3)     /* A */
 132         lwz     RB(0),4(r3)     /* B */
 133         lwz     RC(0),8(r3)     /* C */
 134         lwz     RD(0),12(r3)    /* D */
 135         lwz     RE(0),16(r3)    /* E */
 136
 137         LOADW(0)
 138         LOADW(1)
 139         LOADW(2)
 140         LOADW(3)
 141
 142         lis     r15,0x5a82      /* K0-19 */
 143         ori     r15,r15,0x7999
 144         STEP0LD4(0)
 145         STEP0LD4(4)
 146         STEP0LD4(8)
 147         STEPUP4(12, D0)
 148         STEPUP4(16, D0)
 149
 150         lis     r15,0x6ed9      /* K20-39 */
 151         ori     r15,r15,0xeba1
 152         STEPUP20(20, D1)
 153
 154         lis     r15,0x8f1b      /* K40-59 */
 155         ori     r15,r15,0xbcdc
 156         STEPUP20(40, D2)
 157
 158         lis     r15,0xca62      /* K60-79 */
 159         ori     r15,r15,0xc1d6
 160         STEPUP4(60, D1)
 161         STEPUP4(64, D1)
 162         STEPUP4(68, D1)
 163         STEPUP4(72, D1)
 164         lwz     r20,16(r3)
 165         STEPD1(76)
 166         lwz     r19,12(r3)
 167         STEPD1(77)
 168         lwz     r18,8(r3)
 169         STEPD1(78)
 170         lwz     r17,4(r3)
 171         STEPD1(79)
 172
 173         lwz     r16,0(r3)
 174         add     r20,RE(80),r20
 175         add     RD(0),RD(80),r19
 176         add     RC(0),RC(80),r18
 177         add     RB(0),RB(80),r17
 178         add     RA(0),RA(80),r16
 179         mr      RE(0),r20
 180         stw     RA(0),0(r3)
 181         stw     RB(0),4(r3)
 182         stw     RC(0),8(r3)
 183         stw     RD(0),12(r3)
 184         stw     RE(0),16(r3)
 185
 186         REST_8GPRS(14, r1)
 187         REST_10GPRS(22, r1)
 188         addi    r1,r1,INT_FRAME_SIZE
 189         blr