x86/speculation/mds: Fix documentation typo
[linux/fpc-iii.git] / arch / s390 / kernel / perf_cpum_cf_events.c
blob08bfa17ba0a0699937b1bfb725fadd4c94957479
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Perf PMU sysfs events attributes for available CPU-measurement counters
5 */
7 #include <linux/slab.h>
8 #include <linux/perf_event.h>
11 /* BEGIN: CPUM_CF COUNTER DEFINITIONS =================================== */
13 CPUMF_EVENT_ATTR(cf, CPU_CYCLES, 0x0000);
14 CPUMF_EVENT_ATTR(cf, INSTRUCTIONS, 0x0001);
15 CPUMF_EVENT_ATTR(cf, L1I_DIR_WRITES, 0x0002);
16 CPUMF_EVENT_ATTR(cf, L1I_PENALTY_CYCLES, 0x0003);
17 CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_CPU_CYCLES, 0x0020);
18 CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_INSTRUCTIONS, 0x0021);
19 CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_L1I_DIR_WRITES, 0x0022);
20 CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_L1I_PENALTY_CYCLES, 0x0023);
21 CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_L1D_DIR_WRITES, 0x0024);
22 CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_L1D_PENALTY_CYCLES, 0x0025);
23 CPUMF_EVENT_ATTR(cf, L1D_DIR_WRITES, 0x0004);
24 CPUMF_EVENT_ATTR(cf, L1D_PENALTY_CYCLES, 0x0005);
25 CPUMF_EVENT_ATTR(cf, PRNG_FUNCTIONS, 0x0040);
26 CPUMF_EVENT_ATTR(cf, PRNG_CYCLES, 0x0041);
27 CPUMF_EVENT_ATTR(cf, PRNG_BLOCKED_FUNCTIONS, 0x0042);
28 CPUMF_EVENT_ATTR(cf, PRNG_BLOCKED_CYCLES, 0x0043);
29 CPUMF_EVENT_ATTR(cf, SHA_FUNCTIONS, 0x0044);
30 CPUMF_EVENT_ATTR(cf, SHA_CYCLES, 0x0045);
31 CPUMF_EVENT_ATTR(cf, SHA_BLOCKED_FUNCTIONS, 0x0046);
32 CPUMF_EVENT_ATTR(cf, SHA_BLOCKED_CYCLES, 0x0047);
33 CPUMF_EVENT_ATTR(cf, DEA_FUNCTIONS, 0x0048);
34 CPUMF_EVENT_ATTR(cf, DEA_CYCLES, 0x0049);
35 CPUMF_EVENT_ATTR(cf, DEA_BLOCKED_FUNCTIONS, 0x004a);
36 CPUMF_EVENT_ATTR(cf, DEA_BLOCKED_CYCLES, 0x004b);
37 CPUMF_EVENT_ATTR(cf, AES_FUNCTIONS, 0x004c);
38 CPUMF_EVENT_ATTR(cf, AES_CYCLES, 0x004d);
39 CPUMF_EVENT_ATTR(cf, AES_BLOCKED_FUNCTIONS, 0x004e);
40 CPUMF_EVENT_ATTR(cf, AES_BLOCKED_CYCLES, 0x004f);
41 CPUMF_EVENT_ATTR(cf_z10, L1I_L2_SOURCED_WRITES, 0x0080);
42 CPUMF_EVENT_ATTR(cf_z10, L1D_L2_SOURCED_WRITES, 0x0081);
43 CPUMF_EVENT_ATTR(cf_z10, L1I_L3_LOCAL_WRITES, 0x0082);
44 CPUMF_EVENT_ATTR(cf_z10, L1D_L3_LOCAL_WRITES, 0x0083);
45 CPUMF_EVENT_ATTR(cf_z10, L1I_L3_REMOTE_WRITES, 0x0084);
46 CPUMF_EVENT_ATTR(cf_z10, L1D_L3_REMOTE_WRITES, 0x0085);
47 CPUMF_EVENT_ATTR(cf_z10, L1D_LMEM_SOURCED_WRITES, 0x0086);
48 CPUMF_EVENT_ATTR(cf_z10, L1I_LMEM_SOURCED_WRITES, 0x0087);
49 CPUMF_EVENT_ATTR(cf_z10, L1D_RO_EXCL_WRITES, 0x0088);
50 CPUMF_EVENT_ATTR(cf_z10, L1I_CACHELINE_INVALIDATES, 0x0089);
51 CPUMF_EVENT_ATTR(cf_z10, ITLB1_WRITES, 0x008a);
52 CPUMF_EVENT_ATTR(cf_z10, DTLB1_WRITES, 0x008b);
53 CPUMF_EVENT_ATTR(cf_z10, TLB2_PTE_WRITES, 0x008c);
54 CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_WRITES, 0x008d);
55 CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES, 0x008e);
56 CPUMF_EVENT_ATTR(cf_z10, ITLB1_MISSES, 0x0091);
57 CPUMF_EVENT_ATTR(cf_z10, DTLB1_MISSES, 0x0092);
58 CPUMF_EVENT_ATTR(cf_z10, L2C_STORES_SENT, 0x0093);
59 CPUMF_EVENT_ATTR(cf_z196, L1D_L2_SOURCED_WRITES, 0x0080);
60 CPUMF_EVENT_ATTR(cf_z196, L1I_L2_SOURCED_WRITES, 0x0081);
61 CPUMF_EVENT_ATTR(cf_z196, DTLB1_MISSES, 0x0082);
62 CPUMF_EVENT_ATTR(cf_z196, ITLB1_MISSES, 0x0083);
63 CPUMF_EVENT_ATTR(cf_z196, L2C_STORES_SENT, 0x0085);
64 CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0086);
65 CPUMF_EVENT_ATTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0087);
66 CPUMF_EVENT_ATTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES, 0x0088);
67 CPUMF_EVENT_ATTR(cf_z196, L1D_RO_EXCL_WRITES, 0x0089);
68 CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x008a);
69 CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x008b);
70 CPUMF_EVENT_ATTR(cf_z196, DTLB1_HPAGE_WRITES, 0x008c);
71 CPUMF_EVENT_ATTR(cf_z196, L1D_LMEM_SOURCED_WRITES, 0x008d);
72 CPUMF_EVENT_ATTR(cf_z196, L1I_LMEM_SOURCED_WRITES, 0x008e);
73 CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x008f);
74 CPUMF_EVENT_ATTR(cf_z196, DTLB1_WRITES, 0x0090);
75 CPUMF_EVENT_ATTR(cf_z196, ITLB1_WRITES, 0x0091);
76 CPUMF_EVENT_ATTR(cf_z196, TLB2_PTE_WRITES, 0x0092);
77 CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES, 0x0093);
78 CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_WRITES, 0x0094);
79 CPUMF_EVENT_ATTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0096);
80 CPUMF_EVENT_ATTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0098);
81 CPUMF_EVENT_ATTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099);
82 CPUMF_EVENT_ATTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009b);
83 CPUMF_EVENT_ATTR(cf_zec12, DTLB1_MISSES, 0x0080);
84 CPUMF_EVENT_ATTR(cf_zec12, ITLB1_MISSES, 0x0081);
85 CPUMF_EVENT_ATTR(cf_zec12, L1D_L2I_SOURCED_WRITES, 0x0082);
86 CPUMF_EVENT_ATTR(cf_zec12, L1I_L2I_SOURCED_WRITES, 0x0083);
87 CPUMF_EVENT_ATTR(cf_zec12, L1D_L2D_SOURCED_WRITES, 0x0084);
88 CPUMF_EVENT_ATTR(cf_zec12, DTLB1_WRITES, 0x0085);
89 CPUMF_EVENT_ATTR(cf_zec12, L1D_LMEM_SOURCED_WRITES, 0x0087);
90 CPUMF_EVENT_ATTR(cf_zec12, L1I_LMEM_SOURCED_WRITES, 0x0089);
91 CPUMF_EVENT_ATTR(cf_zec12, L1D_RO_EXCL_WRITES, 0x008a);
92 CPUMF_EVENT_ATTR(cf_zec12, DTLB1_HPAGE_WRITES, 0x008b);
93 CPUMF_EVENT_ATTR(cf_zec12, ITLB1_WRITES, 0x008c);
94 CPUMF_EVENT_ATTR(cf_zec12, TLB2_PTE_WRITES, 0x008d);
95 CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES, 0x008e);
96 CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_WRITES, 0x008f);
97 CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
98 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0091);
99 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0092);
100 CPUMF_EVENT_ATTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0093);
101 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x0094);
102 CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TEND, 0x0095);
103 CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0096);
104 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV, 0x0097);
105 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV, 0x0098);
106 CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099);
107 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009a);
108 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x009b);
109 CPUMF_EVENT_ATTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES, 0x009c);
110 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x009d);
111 CPUMF_EVENT_ATTR(cf_zec12, TX_C_TEND, 0x009e);
112 CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x009f);
113 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV, 0x00a0);
114 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV, 0x00a1);
115 CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TABORT, 0x00b1);
116 CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_NO_SPECIAL, 0x00b2);
117 CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_SPECIAL, 0x00b3);
118 CPUMF_EVENT_ATTR(cf_z13, L1D_WRITES_RO_EXCL, 0x0080);
119 CPUMF_EVENT_ATTR(cf_z13, DTLB1_WRITES, 0x0081);
120 CPUMF_EVENT_ATTR(cf_z13, DTLB1_MISSES, 0x0082);
121 CPUMF_EVENT_ATTR(cf_z13, DTLB1_HPAGE_WRITES, 0x0083);
122 CPUMF_EVENT_ATTR(cf_z13, DTLB1_GPAGE_WRITES, 0x0084);
123 CPUMF_EVENT_ATTR(cf_z13, L1D_L2D_SOURCED_WRITES, 0x0085);
124 CPUMF_EVENT_ATTR(cf_z13, ITLB1_WRITES, 0x0086);
125 CPUMF_EVENT_ATTR(cf_z13, ITLB1_MISSES, 0x0087);
126 CPUMF_EVENT_ATTR(cf_z13, L1I_L2I_SOURCED_WRITES, 0x0088);
127 CPUMF_EVENT_ATTR(cf_z13, TLB2_PTE_WRITES, 0x0089);
128 CPUMF_EVENT_ATTR(cf_z13, TLB2_CRSTE_HPAGE_WRITES, 0x008a);
129 CPUMF_EVENT_ATTR(cf_z13, TLB2_CRSTE_WRITES, 0x008b);
130 CPUMF_EVENT_ATTR(cf_z13, TX_C_TEND, 0x008c);
131 CPUMF_EVENT_ATTR(cf_z13, TX_NC_TEND, 0x008d);
132 CPUMF_EVENT_ATTR(cf_z13, L1C_TLB1_MISSES, 0x008f);
133 CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
134 CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0091);
135 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L4_SOURCED_WRITES, 0x0092);
136 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES_IV, 0x0093);
137 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES, 0x0094);
138 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x0095);
139 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES_IV, 0x0096);
140 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES, 0x0097);
141 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES, 0x0098);
142 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV, 0x0099);
143 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES, 0x009a);
144 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES, 0x009b);
145 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV, 0x009c);
146 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES, 0x009d);
147 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_MEM_SOURCED_WRITES, 0x009e);
148 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_MEM_SOURCED_WRITES, 0x009f);
149 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_MEM_SOURCED_WRITES, 0x00a0);
150 CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_MEM_SOURCED_WRITES, 0x00a1);
151 CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
152 CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a3);
153 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L4_SOURCED_WRITES, 0x00a4);
154 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES_IV, 0x00a5);
155 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES, 0x00a6);
156 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00a7);
157 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES_IV, 0x00a8);
158 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES, 0x00a9);
159 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES, 0x00aa);
160 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV, 0x00ab);
161 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES, 0x00ac);
162 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES, 0x00ad);
163 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV, 0x00ae);
164 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES, 0x00af);
165 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_MEM_SOURCED_WRITES, 0x00b0);
166 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_MEM_SOURCED_WRITES, 0x00b1);
167 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_MEM_SOURCED_WRITES, 0x00b2);
168 CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_MEM_SOURCED_WRITES, 0x00b3);
169 CPUMF_EVENT_ATTR(cf_z13, TX_NC_TABORT, 0x00da);
170 CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_NO_SPECIAL, 0x00db);
171 CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_SPECIAL, 0x00dc);
172 CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
173 CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
175 static struct attribute *cpumcf_pmu_event_attr[] __initdata = {
176 CPUMF_EVENT_PTR(cf, CPU_CYCLES),
177 CPUMF_EVENT_PTR(cf, INSTRUCTIONS),
178 CPUMF_EVENT_PTR(cf, L1I_DIR_WRITES),
179 CPUMF_EVENT_PTR(cf, L1I_PENALTY_CYCLES),
180 CPUMF_EVENT_PTR(cf, PROBLEM_STATE_CPU_CYCLES),
181 CPUMF_EVENT_PTR(cf, PROBLEM_STATE_INSTRUCTIONS),
182 CPUMF_EVENT_PTR(cf, PROBLEM_STATE_L1I_DIR_WRITES),
183 CPUMF_EVENT_PTR(cf, PROBLEM_STATE_L1I_PENALTY_CYCLES),
184 CPUMF_EVENT_PTR(cf, PROBLEM_STATE_L1D_DIR_WRITES),
185 CPUMF_EVENT_PTR(cf, PROBLEM_STATE_L1D_PENALTY_CYCLES),
186 CPUMF_EVENT_PTR(cf, L1D_DIR_WRITES),
187 CPUMF_EVENT_PTR(cf, L1D_PENALTY_CYCLES),
188 CPUMF_EVENT_PTR(cf, PRNG_FUNCTIONS),
189 CPUMF_EVENT_PTR(cf, PRNG_CYCLES),
190 CPUMF_EVENT_PTR(cf, PRNG_BLOCKED_FUNCTIONS),
191 CPUMF_EVENT_PTR(cf, PRNG_BLOCKED_CYCLES),
192 CPUMF_EVENT_PTR(cf, SHA_FUNCTIONS),
193 CPUMF_EVENT_PTR(cf, SHA_CYCLES),
194 CPUMF_EVENT_PTR(cf, SHA_BLOCKED_FUNCTIONS),
195 CPUMF_EVENT_PTR(cf, SHA_BLOCKED_CYCLES),
196 CPUMF_EVENT_PTR(cf, DEA_FUNCTIONS),
197 CPUMF_EVENT_PTR(cf, DEA_CYCLES),
198 CPUMF_EVENT_PTR(cf, DEA_BLOCKED_FUNCTIONS),
199 CPUMF_EVENT_PTR(cf, DEA_BLOCKED_CYCLES),
200 CPUMF_EVENT_PTR(cf, AES_FUNCTIONS),
201 CPUMF_EVENT_PTR(cf, AES_CYCLES),
202 CPUMF_EVENT_PTR(cf, AES_BLOCKED_FUNCTIONS),
203 CPUMF_EVENT_PTR(cf, AES_BLOCKED_CYCLES),
204 NULL,
207 static struct attribute *cpumcf_z10_pmu_event_attr[] __initdata = {
208 CPUMF_EVENT_PTR(cf_z10, L1I_L2_SOURCED_WRITES),
209 CPUMF_EVENT_PTR(cf_z10, L1D_L2_SOURCED_WRITES),
210 CPUMF_EVENT_PTR(cf_z10, L1I_L3_LOCAL_WRITES),
211 CPUMF_EVENT_PTR(cf_z10, L1D_L3_LOCAL_WRITES),
212 CPUMF_EVENT_PTR(cf_z10, L1I_L3_REMOTE_WRITES),
213 CPUMF_EVENT_PTR(cf_z10, L1D_L3_REMOTE_WRITES),
214 CPUMF_EVENT_PTR(cf_z10, L1D_LMEM_SOURCED_WRITES),
215 CPUMF_EVENT_PTR(cf_z10, L1I_LMEM_SOURCED_WRITES),
216 CPUMF_EVENT_PTR(cf_z10, L1D_RO_EXCL_WRITES),
217 CPUMF_EVENT_PTR(cf_z10, L1I_CACHELINE_INVALIDATES),
218 CPUMF_EVENT_PTR(cf_z10, ITLB1_WRITES),
219 CPUMF_EVENT_PTR(cf_z10, DTLB1_WRITES),
220 CPUMF_EVENT_PTR(cf_z10, TLB2_PTE_WRITES),
221 CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_WRITES),
222 CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES),
223 CPUMF_EVENT_PTR(cf_z10, ITLB1_MISSES),
224 CPUMF_EVENT_PTR(cf_z10, DTLB1_MISSES),
225 CPUMF_EVENT_PTR(cf_z10, L2C_STORES_SENT),
226 NULL,
229 static struct attribute *cpumcf_z196_pmu_event_attr[] __initdata = {
230 CPUMF_EVENT_PTR(cf_z196, L1D_L2_SOURCED_WRITES),
231 CPUMF_EVENT_PTR(cf_z196, L1I_L2_SOURCED_WRITES),
232 CPUMF_EVENT_PTR(cf_z196, DTLB1_MISSES),
233 CPUMF_EVENT_PTR(cf_z196, ITLB1_MISSES),
234 CPUMF_EVENT_PTR(cf_z196, L2C_STORES_SENT),
235 CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES),
236 CPUMF_EVENT_PTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES),
237 CPUMF_EVENT_PTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES),
238 CPUMF_EVENT_PTR(cf_z196, L1D_RO_EXCL_WRITES),
239 CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES),
240 CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES),
241 CPUMF_EVENT_PTR(cf_z196, DTLB1_HPAGE_WRITES),
242 CPUMF_EVENT_PTR(cf_z196, L1D_LMEM_SOURCED_WRITES),
243 CPUMF_EVENT_PTR(cf_z196, L1I_LMEM_SOURCED_WRITES),
244 CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES),
245 CPUMF_EVENT_PTR(cf_z196, DTLB1_WRITES),
246 CPUMF_EVENT_PTR(cf_z196, ITLB1_WRITES),
247 CPUMF_EVENT_PTR(cf_z196, TLB2_PTE_WRITES),
248 CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES),
249 CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_WRITES),
250 CPUMF_EVENT_PTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES),
251 CPUMF_EVENT_PTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES),
252 CPUMF_EVENT_PTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES),
253 CPUMF_EVENT_PTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES),
254 NULL,
257 static struct attribute *cpumcf_zec12_pmu_event_attr[] __initdata = {
258 CPUMF_EVENT_PTR(cf_zec12, DTLB1_MISSES),
259 CPUMF_EVENT_PTR(cf_zec12, ITLB1_MISSES),
260 CPUMF_EVENT_PTR(cf_zec12, L1D_L2I_SOURCED_WRITES),
261 CPUMF_EVENT_PTR(cf_zec12, L1I_L2I_SOURCED_WRITES),
262 CPUMF_EVENT_PTR(cf_zec12, L1D_L2D_SOURCED_WRITES),
263 CPUMF_EVENT_PTR(cf_zec12, DTLB1_WRITES),
264 CPUMF_EVENT_PTR(cf_zec12, L1D_LMEM_SOURCED_WRITES),
265 CPUMF_EVENT_PTR(cf_zec12, L1I_LMEM_SOURCED_WRITES),
266 CPUMF_EVENT_PTR(cf_zec12, L1D_RO_EXCL_WRITES),
267 CPUMF_EVENT_PTR(cf_zec12, DTLB1_HPAGE_WRITES),
268 CPUMF_EVENT_PTR(cf_zec12, ITLB1_WRITES),
269 CPUMF_EVENT_PTR(cf_zec12, TLB2_PTE_WRITES),
270 CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES),
271 CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_WRITES),
272 CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES),
273 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES),
274 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES),
275 CPUMF_EVENT_PTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES),
276 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES),
277 CPUMF_EVENT_PTR(cf_zec12, TX_NC_TEND),
278 CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
279 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV),
280 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV),
281 CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES),
282 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES),
283 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES),
284 CPUMF_EVENT_PTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES),
285 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES),
286 CPUMF_EVENT_PTR(cf_zec12, TX_C_TEND),
287 CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
288 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV),
289 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV),
290 CPUMF_EVENT_PTR(cf_zec12, TX_NC_TABORT),
291 CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_NO_SPECIAL),
292 CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_SPECIAL),
293 NULL,
296 static struct attribute *cpumcf_z13_pmu_event_attr[] __initdata = {
297 CPUMF_EVENT_PTR(cf_z13, L1D_WRITES_RO_EXCL),
298 CPUMF_EVENT_PTR(cf_z13, DTLB1_WRITES),
299 CPUMF_EVENT_PTR(cf_z13, DTLB1_MISSES),
300 CPUMF_EVENT_PTR(cf_z13, DTLB1_HPAGE_WRITES),
301 CPUMF_EVENT_PTR(cf_z13, DTLB1_GPAGE_WRITES),
302 CPUMF_EVENT_PTR(cf_z13, L1D_L2D_SOURCED_WRITES),
303 CPUMF_EVENT_PTR(cf_z13, ITLB1_WRITES),
304 CPUMF_EVENT_PTR(cf_z13, ITLB1_MISSES),
305 CPUMF_EVENT_PTR(cf_z13, L1I_L2I_SOURCED_WRITES),
306 CPUMF_EVENT_PTR(cf_z13, TLB2_PTE_WRITES),
307 CPUMF_EVENT_PTR(cf_z13, TLB2_CRSTE_HPAGE_WRITES),
308 CPUMF_EVENT_PTR(cf_z13, TLB2_CRSTE_WRITES),
309 CPUMF_EVENT_PTR(cf_z13, TX_C_TEND),
310 CPUMF_EVENT_PTR(cf_z13, TX_NC_TEND),
311 CPUMF_EVENT_PTR(cf_z13, L1C_TLB1_MISSES),
312 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES),
313 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
314 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L4_SOURCED_WRITES),
315 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES_IV),
316 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES),
317 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L4_SOURCED_WRITES),
318 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES_IV),
319 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES),
320 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES),
321 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV),
322 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES),
323 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES),
324 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV),
325 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES),
326 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_MEM_SOURCED_WRITES),
327 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_MEM_SOURCED_WRITES),
328 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_MEM_SOURCED_WRITES),
329 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_MEM_SOURCED_WRITES),
330 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES),
331 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
332 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L4_SOURCED_WRITES),
333 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES_IV),
334 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES),
335 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L4_SOURCED_WRITES),
336 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES_IV),
337 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES),
338 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES),
339 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV),
340 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES),
341 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES),
342 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV),
343 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES),
344 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_MEM_SOURCED_WRITES),
345 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_MEM_SOURCED_WRITES),
346 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_MEM_SOURCED_WRITES),
347 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_MEM_SOURCED_WRITES),
348 CPUMF_EVENT_PTR(cf_z13, TX_NC_TABORT),
349 CPUMF_EVENT_PTR(cf_z13, TX_C_TABORT_NO_SPECIAL),
350 CPUMF_EVENT_PTR(cf_z13, TX_C_TABORT_SPECIAL),
351 CPUMF_EVENT_PTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
352 CPUMF_EVENT_PTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
353 NULL,
356 /* END: CPUM_CF COUNTER DEFINITIONS ===================================== */
358 static struct attribute_group cpumcf_pmu_events_group = {
359 .name = "events",
362 PMU_FORMAT_ATTR(event, "config:0-63");
364 static struct attribute *cpumcf_pmu_format_attr[] = {
365 &format_attr_event.attr,
366 NULL,
369 static struct attribute_group cpumcf_pmu_format_group = {
370 .name = "format",
371 .attrs = cpumcf_pmu_format_attr,
374 static const struct attribute_group *cpumcf_pmu_attr_groups[] = {
375 &cpumcf_pmu_events_group,
376 &cpumcf_pmu_format_group,
377 NULL,
381 static __init struct attribute **merge_attr(struct attribute **a,
382 struct attribute **b)
384 struct attribute **new;
385 int j, i;
387 for (j = 0; a[j]; j++)
389 for (i = 0; b[i]; i++)
390 j++;
391 j++;
393 new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
394 if (!new)
395 return NULL;
396 j = 0;
397 for (i = 0; a[i]; i++)
398 new[j++] = a[i];
399 for (i = 0; b[i]; i++)
400 new[j++] = b[i];
401 new[j] = NULL;
403 return new;
406 __init const struct attribute_group **cpumf_cf_event_group(void)
408 struct attribute **combined, **model;
409 struct attribute *none[] = { NULL };
410 struct cpuid cpu_id;
412 get_cpu_id(&cpu_id);
413 switch (cpu_id.machine) {
414 case 0x2097:
415 case 0x2098:
416 model = cpumcf_z10_pmu_event_attr;
417 break;
418 case 0x2817:
419 case 0x2818:
420 model = cpumcf_z196_pmu_event_attr;
421 break;
422 case 0x2827:
423 case 0x2828:
424 model = cpumcf_zec12_pmu_event_attr;
425 break;
426 case 0x2964:
427 case 0x2965:
428 model = cpumcf_z13_pmu_event_attr;
429 break;
430 default:
431 model = none;
432 break;
435 combined = merge_attr(cpumcf_pmu_event_attr, model);
436 if (combined)
437 cpumcf_pmu_events_group.attrs = combined;
438 return cpumcf_pmu_attr_groups;