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x86/speculation/mds: Fix documentation typo
[linux/fpc-iii.git] / arch / s390 / net / bpf_jit_comp.c
blob6b1474fa99ab3f98f68227fa97fc4d0768445ac3
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * BPF Jit compiler for s390.
4 *
5 * Minimum build requirements:
6 *
7 * - HAVE_MARCH_Z196_FEATURES: laal, laalg
8 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj
9 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf
10 * - PACK_STACK
11 * - 64BIT
12 *
13 * Copyright IBM Corp. 2012,2015
14 *
15 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
16 * Michael Holzheu <holzheu@linux.vnet.ibm.com>
17 */
18
19 #define KMSG_COMPONENT "bpf_jit"
20 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
21
22 #include <linux/netdevice.h>
23 #include <linux/filter.h>
24 #include <linux/init.h>
25 #include <linux/bpf.h>
26 #include <asm/cacheflush.h>
27 #include <asm/dis.h>
28 #include <asm/facility.h>
29 #include <asm/nospec-branch.h>
30 #include <asm/set_memory.h>
31 #include "bpf_jit.h"
32
33 int bpf_jit_enable __read_mostly;
34
35 struct bpf_jit {
36 u32 seen; /* Flags to remember seen eBPF instructions */
37 u32 seen_reg[16]; /* Array to remember which registers are used */
38 u32 *addrs; /* Array with relative instruction addresses */
39 u8 *prg_buf; /* Start of program */
40 int size; /* Size of program and literal pool */
41 int size_prg; /* Size of program */
42 int prg; /* Current position in program */
43 int lit_start; /* Start of literal pool */
44 int lit; /* Current position in literal pool */
45 int base_ip; /* Base address for literal pool */
46 int ret0_ip; /* Address of return 0 */
47 int exit_ip; /* Address of exit */
48 int r1_thunk_ip; /* Address of expoline thunk for 'br %r1' */
49 int r14_thunk_ip; /* Address of expoline thunk for 'br %r14' */
50 int tail_call_start; /* Tail call start offset */
51 int labels[1]; /* Labels for local jumps */
52 };
53
54 #define BPF_SIZE_MAX 0xffff /* Max size for program (16 bit branches) */
55
56 #define SEEN_SKB 1 /* skb access */
57 #define SEEN_MEM 2 /* use mem[] for temporary storage */
58 #define SEEN_RET0 4 /* ret0_ip points to a valid return 0 */
59 #define SEEN_LITERAL 8 /* code uses literals */
60 #define SEEN_FUNC 16 /* calls C functions */
61 #define SEEN_TAIL_CALL 32 /* code uses tail calls */
62 #define SEEN_REG_AX 64 /* code uses constant blinding */
63 #define SEEN_STACK (SEEN_FUNC | SEEN_MEM | SEEN_SKB)
64
65 /*
66 * s390 registers
67 */
68 #define REG_W0 (MAX_BPF_JIT_REG + 0) /* Work register 1 (even) */
69 #define REG_W1 (MAX_BPF_JIT_REG + 1) /* Work register 2 (odd) */
70 #define REG_SKB_DATA (MAX_BPF_JIT_REG + 2) /* SKB data register */
71 #define REG_L (MAX_BPF_JIT_REG + 3) /* Literal pool register */
72 #define REG_15 (MAX_BPF_JIT_REG + 4) /* Register 15 */
73 #define REG_0 REG_W0 /* Register 0 */
74 #define REG_1 REG_W1 /* Register 1 */
75 #define REG_2 BPF_REG_1 /* Register 2 */
76 #define REG_14 BPF_REG_0 /* Register 14 */
77
78 /*
79 * Mapping of BPF registers to s390 registers
80 */
81 static const int reg2hex[] = {
82 /* Return code */
83 [BPF_REG_0] = 14,
84 /* Function parameters */
85 [BPF_REG_1] = 2,
86 [BPF_REG_2] = 3,
87 [BPF_REG_3] = 4,
88 [BPF_REG_4] = 5,
89 [BPF_REG_5] = 6,
90 /* Call saved registers */
91 [BPF_REG_6] = 7,
92 [BPF_REG_7] = 8,
93 [BPF_REG_8] = 9,
94 [BPF_REG_9] = 10,
95 /* BPF stack pointer */
96 [BPF_REG_FP] = 13,
97 /* Register for blinding (shared with REG_SKB_DATA) */
98 [BPF_REG_AX] = 12,
99 /* SKB data pointer */
100 [REG_SKB_DATA] = 12,
101 /* Work registers for s390x backend */
102 [REG_W0] = 0,
103 [REG_W1] = 1,
104 [REG_L] = 11,
105 [REG_15] = 15,
106 };
107
108 static inline u32 reg(u32 dst_reg, u32 src_reg)
109 {
110 return reg2hex[dst_reg] << 4 | reg2hex[src_reg];
111 }
112
113 static inline u32 reg_high(u32 reg)
114 {
115 return reg2hex[reg] << 4;
116 }
117
118 static inline void reg_set_seen(struct bpf_jit *jit, u32 b1)
119 {
120 u32 r1 = reg2hex[b1];
121
122 if (!jit->seen_reg[r1] && r1 >= 6 && r1 <= 15)
123 jit->seen_reg[r1] = 1;
124 }
125
126 #define REG_SET_SEEN(b1) \
127 ({ \
128 reg_set_seen(jit, b1); \
129 })
130
131 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]]
132
133 /*
134 * EMIT macros for code generation
135 */
136
137 #define _EMIT2(op) \
138 ({ \
139 if (jit->prg_buf) \
140 *(u16 *) (jit->prg_buf + jit->prg) = op; \
141 jit->prg += 2; \
142 })
143
144 #define EMIT2(op, b1, b2) \
145 ({ \
146 _EMIT2(op | reg(b1, b2)); \
147 REG_SET_SEEN(b1); \
148 REG_SET_SEEN(b2); \
149 })
150
151 #define _EMIT4(op) \
152 ({ \
153 if (jit->prg_buf) \
154 *(u32 *) (jit->prg_buf + jit->prg) = op; \
155 jit->prg += 4; \
156 })
157
158 #define EMIT4(op, b1, b2) \
159 ({ \
160 _EMIT4(op | reg(b1, b2)); \
161 REG_SET_SEEN(b1); \
162 REG_SET_SEEN(b2); \
163 })
164
165 #define EMIT4_RRF(op, b1, b2, b3) \
166 ({ \
167 _EMIT4(op | reg_high(b3) << 8 | reg(b1, b2)); \
168 REG_SET_SEEN(b1); \
169 REG_SET_SEEN(b2); \
170 REG_SET_SEEN(b3); \
171 })
172
173 #define _EMIT4_DISP(op, disp) \
174 ({ \
175 unsigned int __disp = (disp) & 0xfff; \
176 _EMIT4(op | __disp); \
177 })
178
179 #define EMIT4_DISP(op, b1, b2, disp) \
180 ({ \
181 _EMIT4_DISP(op | reg_high(b1) << 16 | \
182 reg_high(b2) << 8, disp); \
183 REG_SET_SEEN(b1); \
184 REG_SET_SEEN(b2); \
185 })
186
187 #define EMIT4_IMM(op, b1, imm) \
188 ({ \
189 unsigned int __imm = (imm) & 0xffff; \
190 _EMIT4(op | reg_high(b1) << 16 | __imm); \
191 REG_SET_SEEN(b1); \
192 })
193
194 #define EMIT4_PCREL(op, pcrel) \
195 ({ \
196 long __pcrel = ((pcrel) >> 1) & 0xffff; \
197 _EMIT4(op | __pcrel); \
198 })
199
200 #define _EMIT6(op1, op2) \
201 ({ \
202 if (jit->prg_buf) { \
203 *(u32 *) (jit->prg_buf + jit->prg) = op1; \
204 *(u16 *) (jit->prg_buf + jit->prg + 4) = op2; \
205 } \
206 jit->prg += 6; \
207 })
208
209 #define _EMIT6_DISP(op1, op2, disp) \
210 ({ \
211 unsigned int __disp = (disp) & 0xfff; \
212 _EMIT6(op1 | __disp, op2); \
213 })
214
215 #define _EMIT6_DISP_LH(op1, op2, disp) \
216 ({ \
217 u32 _disp = (u32) disp; \
218 unsigned int __disp_h = _disp & 0xff000; \
219 unsigned int __disp_l = _disp & 0x00fff; \
220 _EMIT6(op1 | __disp_l, op2 | __disp_h >> 4); \
221 })
222
223 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \
224 ({ \
225 _EMIT6_DISP_LH(op1 | reg(b1, b2) << 16 | \
226 reg_high(b3) << 8, op2, disp); \
227 REG_SET_SEEN(b1); \
228 REG_SET_SEEN(b2); \
229 REG_SET_SEEN(b3); \
230 })
231
232 #define EMIT6_PCREL_LABEL(op1, op2, b1, b2, label, mask) \
233 ({ \
234 int rel = (jit->labels[label] - jit->prg) >> 1; \
235 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), \
236 op2 | mask << 12); \
237 REG_SET_SEEN(b1); \
238 REG_SET_SEEN(b2); \
239 })
240
241 #define EMIT6_PCREL_IMM_LABEL(op1, op2, b1, imm, label, mask) \
242 ({ \
243 int rel = (jit->labels[label] - jit->prg) >> 1; \
244 _EMIT6(op1 | (reg_high(b1) | mask) << 16 | \
245 (rel & 0xffff), op2 | (imm & 0xff) << 8); \
246 REG_SET_SEEN(b1); \
247 BUILD_BUG_ON(((unsigned long) imm) > 0xff); \
248 })
249
250 #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \
251 ({ \
252 /* Branch instruction needs 6 bytes */ \
253 int rel = (addrs[i + off + 1] - (addrs[i + 1] - 6)) / 2;\
254 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), op2 | mask); \
255 REG_SET_SEEN(b1); \
256 REG_SET_SEEN(b2); \
257 })
258
259 #define EMIT6_PCREL_RILB(op, b, target) \
260 ({ \
261 int rel = (target - jit->prg) / 2; \
262 _EMIT6(op | reg_high(b) << 16 | rel >> 16, rel & 0xffff); \
263 REG_SET_SEEN(b); \
264 })
265
266 #define EMIT6_PCREL_RIL(op, target) \
267 ({ \
268 int rel = (target - jit->prg) / 2; \
269 _EMIT6(op | rel >> 16, rel & 0xffff); \
270 })
271
272 #define _EMIT6_IMM(op, imm) \
273 ({ \
274 unsigned int __imm = (imm); \
275 _EMIT6(op | (__imm >> 16), __imm & 0xffff); \
276 })
277
278 #define EMIT6_IMM(op, b1, imm) \
279 ({ \
280 _EMIT6_IMM(op | reg_high(b1) << 16, imm); \
281 REG_SET_SEEN(b1); \
282 })
283
284 #define EMIT_CONST_U32(val) \
285 ({ \
286 unsigned int ret; \
287 ret = jit->lit - jit->base_ip; \
288 jit->seen |= SEEN_LITERAL; \
289 if (jit->prg_buf) \
290 *(u32 *) (jit->prg_buf + jit->lit) = (u32) val; \
291 jit->lit += 4; \
292 ret; \
293 })
294
295 #define EMIT_CONST_U64(val) \
296 ({ \
297 unsigned int ret; \
298 ret = jit->lit - jit->base_ip; \
299 jit->seen |= SEEN_LITERAL; \
300 if (jit->prg_buf) \
301 *(u64 *) (jit->prg_buf + jit->lit) = (u64) val; \
302 jit->lit += 8; \
303 ret; \
304 })
305
306 #define EMIT_ZERO(b1) \
307 ({ \
308 /* llgfr %dst,%dst (zero extend to 64 bit) */ \
309 EMIT4(0xb9160000, b1, b1); \
310 REG_SET_SEEN(b1); \
311 })
312
313 /*
314 * Fill whole space with illegal instructions
315 */
316 static void jit_fill_hole(void *area, unsigned int size)
317 {
318 memset(area, 0, size);
319 }
320
321 /*
322 * Save registers from "rs" (register start) to "re" (register end) on stack
323 */
324 static void save_regs(struct bpf_jit *jit, u32 rs, u32 re)
325 {
326 u32 off = STK_OFF_R6 + (rs - 6) * 8;
327
328 if (rs == re)
329 /* stg %rs,off(%r15) */
330 _EMIT6(0xe300f000 | rs << 20 | off, 0x0024);
331 else
332 /* stmg %rs,%re,off(%r15) */
333 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0024, off);
334 }
335
336 /*
337 * Restore registers from "rs" (register start) to "re" (register end) on stack
338 */
339 static void restore_regs(struct bpf_jit *jit, u32 rs, u32 re)
340 {
341 u32 off = STK_OFF_R6 + (rs - 6) * 8;
342
343 if (jit->seen & SEEN_STACK)
344 off += STK_OFF;
345
346 if (rs == re)
347 /* lg %rs,off(%r15) */
348 _EMIT6(0xe300f000 | rs << 20 | off, 0x0004);
349 else
350 /* lmg %rs,%re,off(%r15) */
351 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0004, off);
352 }
353
354 /*
355 * Return first seen register (from start)
356 */
357 static int get_start(struct bpf_jit *jit, int start)
358 {
359 int i;
360
361 for (i = start; i <= 15; i++) {
362 if (jit->seen_reg[i])
363 return i;
364 }
365 return 0;
366 }
367
368 /*
369 * Return last seen register (from start) (gap >= 2)
370 */
371 static int get_end(struct bpf_jit *jit, int start)
372 {
373 int i;
374
375 for (i = start; i < 15; i++) {
376 if (!jit->seen_reg[i] && !jit->seen_reg[i + 1])
377 return i - 1;
378 }
379 return jit->seen_reg[15] ? 15 : 14;
380 }
381
382 #define REGS_SAVE 1
383 #define REGS_RESTORE 0
384 /*
385 * Save and restore clobbered registers (6-15) on stack.
386 * We save/restore registers in chunks with gap >= 2 registers.
387 */
388 static void save_restore_regs(struct bpf_jit *jit, int op)
389 {
390
391 int re = 6, rs;
392
393 do {
394 rs = get_start(jit, re);
395 if (!rs)
396 break;
397 re = get_end(jit, rs + 1);
398 if (op == REGS_SAVE)
399 save_regs(jit, rs, re);
400 else
401 restore_regs(jit, rs, re);
402 re++;
403 } while (re <= 15);
404 }
405
406 /*
407 * For SKB access %b1 contains the SKB pointer. For "bpf_jit.S"
408 * we store the SKB header length on the stack and the SKB data
409 * pointer in REG_SKB_DATA if BPF_REG_AX is not used.
410 */
411 static void emit_load_skb_data_hlen(struct bpf_jit *jit)
412 {
413 /* Header length: llgf %w1,<len>(%b1) */
414 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_1,
415 offsetof(struct sk_buff, len));
416 /* s %w1,<data_len>(%b1) */
417 EMIT4_DISP(0x5b000000, REG_W1, BPF_REG_1,
418 offsetof(struct sk_buff, data_len));
419 /* stg %w1,ST_OFF_HLEN(%r0,%r15) */
420 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0, REG_15, STK_OFF_HLEN);
421 if (!(jit->seen & SEEN_REG_AX))
422 /* lg %skb_data,data_off(%b1) */
423 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_SKB_DATA, REG_0,
424 BPF_REG_1, offsetof(struct sk_buff, data));
425 }
426
427 /*
428 * Emit function prologue
429 *
430 * Save registers and create stack frame if necessary.
431 * See stack frame layout desription in "bpf_jit.h"!
432 */
433 static void bpf_jit_prologue(struct bpf_jit *jit)
434 {
435 if (jit->seen & SEEN_TAIL_CALL) {
436 /* xc STK_OFF_TCCNT(4,%r15),STK_OFF_TCCNT(%r15) */
437 _EMIT6(0xd703f000 | STK_OFF_TCCNT, 0xf000 | STK_OFF_TCCNT);
438 } else {
439 /* j tail_call_start: NOP if no tail calls are used */
440 EMIT4_PCREL(0xa7f40000, 6);
441 _EMIT2(0);
442 }
443 /* Tail calls have to skip above initialization */
444 jit->tail_call_start = jit->prg;
445 /* Save registers */
446 save_restore_regs(jit, REGS_SAVE);
447 /* Setup literal pool */
448 if (jit->seen & SEEN_LITERAL) {
449 /* basr %r13,0 */
450 EMIT2(0x0d00, REG_L, REG_0);
451 jit->base_ip = jit->prg;
452 }
453 /* Setup stack and backchain */
454 if (jit->seen & SEEN_STACK) {
455 if (jit->seen & SEEN_FUNC)
456 /* lgr %w1,%r15 (backchain) */
457 EMIT4(0xb9040000, REG_W1, REG_15);
458 /* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */
459 EMIT4_DISP(0x41000000, BPF_REG_FP, REG_15, STK_160_UNUSED);
460 /* aghi %r15,-STK_OFF */
461 EMIT4_IMM(0xa70b0000, REG_15, -STK_OFF);
462 if (jit->seen & SEEN_FUNC)
463 /* stg %w1,152(%r15) (backchain) */
464 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0,
465 REG_15, 152);
466 }
467 if (jit->seen & SEEN_SKB) {
468 emit_load_skb_data_hlen(jit);
469 /* stg %b1,ST_OFF_SKBP(%r0,%r15) */
470 EMIT6_DISP_LH(0xe3000000, 0x0024, BPF_REG_1, REG_0, REG_15,
471 STK_OFF_SKBP);
472 }
473 }
474
475 /*
476 * Function epilogue
477 */
478 static void bpf_jit_epilogue(struct bpf_jit *jit)
479 {
480 /* Return 0 */
481 if (jit->seen & SEEN_RET0) {
482 jit->ret0_ip = jit->prg;
483 /* lghi %b0,0 */
484 EMIT4_IMM(0xa7090000, BPF_REG_0, 0);
485 }
486 jit->exit_ip = jit->prg;
487 /* Load exit code: lgr %r2,%b0 */
488 EMIT4(0xb9040000, REG_2, BPF_REG_0);
489 /* Restore registers */
490 save_restore_regs(jit, REGS_RESTORE);
491 if (IS_ENABLED(CC_USING_EXPOLINE) && !nospec_disable) {
492 jit->r14_thunk_ip = jit->prg;
493 /* Generate __s390_indirect_jump_r14 thunk */
494 if (test_facility(35)) {
495 /* exrl %r0,.+10 */
496 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
497 } else {
498 /* larl %r1,.+14 */
499 EMIT6_PCREL_RILB(0xc0000000, REG_1, jit->prg + 14);
500 /* ex 0,0(%r1) */
501 EMIT4_DISP(0x44000000, REG_0, REG_1, 0);
502 }
503 /* j . */
504 EMIT4_PCREL(0xa7f40000, 0);
505 }
506 /* br %r14 */
507 _EMIT2(0x07fe);
508
509 if (IS_ENABLED(CC_USING_EXPOLINE) && !nospec_disable &&
510 (jit->seen & SEEN_FUNC)) {
511 jit->r1_thunk_ip = jit->prg;
512 /* Generate __s390_indirect_jump_r1 thunk */
513 if (test_facility(35)) {
514 /* exrl %r0,.+10 */
515 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
516 /* j . */
517 EMIT4_PCREL(0xa7f40000, 0);
518 /* br %r1 */
519 _EMIT2(0x07f1);
520 } else {
521 /* ex 0,S390_lowcore.br_r1_tampoline */
522 EMIT4_DISP(0x44000000, REG_0, REG_0,
523 offsetof(struct lowcore, br_r1_trampoline));
524 /* j . */
525 EMIT4_PCREL(0xa7f40000, 0);
526 }
527 }
528 }
529
530 /*
531 * Compile one eBPF instruction into s390x code
532 *
533 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of
534 * stack space for the large switch statement.
535 */
536 static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, int i)
537 {
538 struct bpf_insn *insn = &fp->insnsi[i];
539 int jmp_off, last, insn_count = 1;
540 unsigned int func_addr, mask;
541 u32 dst_reg = insn->dst_reg;
542 u32 src_reg = insn->src_reg;
543 u32 *addrs = jit->addrs;
544 s32 imm = insn->imm;
545 s16 off = insn->off;
546
547 if (dst_reg == BPF_REG_AX || src_reg == BPF_REG_AX)
548 jit->seen |= SEEN_REG_AX;
549 switch (insn->code) {
550 /*
551 * BPF_MOV
552 */
553 case BPF_ALU | BPF_MOV | BPF_X: /* dst = (u32) src */
554 /* llgfr %dst,%src */
555 EMIT4(0xb9160000, dst_reg, src_reg);
556 break;
557 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */
558 /* lgr %dst,%src */
559 EMIT4(0xb9040000, dst_reg, src_reg);
560 break;
561 case BPF_ALU | BPF_MOV | BPF_K: /* dst = (u32) imm */
562 /* llilf %dst,imm */
563 EMIT6_IMM(0xc00f0000, dst_reg, imm);
564 break;
565 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = imm */
566 /* lgfi %dst,imm */
567 EMIT6_IMM(0xc0010000, dst_reg, imm);
568 break;
569 /*
570 * BPF_LD 64
571 */
572 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */
573 {
574 /* 16 byte instruction that uses two 'struct bpf_insn' */
575 u64 imm64;
576
577 imm64 = (u64)(u32) insn[0].imm | ((u64)(u32) insn[1].imm) << 32;
578 /* lg %dst,<d(imm)>(%l) */
579 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, REG_0, REG_L,
580 EMIT_CONST_U64(imm64));
581 insn_count = 2;
582 break;
583 }
584 /*
585 * BPF_ADD
586 */
587 case BPF_ALU | BPF_ADD | BPF_X: /* dst = (u32) dst + (u32) src */
588 /* ar %dst,%src */
589 EMIT2(0x1a00, dst_reg, src_reg);
590 EMIT_ZERO(dst_reg);
591 break;
592 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst = dst + src */
593 /* agr %dst,%src */
594 EMIT4(0xb9080000, dst_reg, src_reg);
595 break;
596 case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */
597 if (!imm)
598 break;
599 /* alfi %dst,imm */
600 EMIT6_IMM(0xc20b0000, dst_reg, imm);
601 EMIT_ZERO(dst_reg);
602 break;
603 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */
604 if (!imm)
605 break;
606 /* agfi %dst,imm */
607 EMIT6_IMM(0xc2080000, dst_reg, imm);
608 break;
609 /*
610 * BPF_SUB
611 */
612 case BPF_ALU | BPF_SUB | BPF_X: /* dst = (u32) dst - (u32) src */
613 /* sr %dst,%src */
614 EMIT2(0x1b00, dst_reg, src_reg);
615 EMIT_ZERO(dst_reg);
616 break;
617 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst = dst - src */
618 /* sgr %dst,%src */
619 EMIT4(0xb9090000, dst_reg, src_reg);
620 break;
621 case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */
622 if (!imm)
623 break;
624 /* alfi %dst,-imm */
625 EMIT6_IMM(0xc20b0000, dst_reg, -imm);
626 EMIT_ZERO(dst_reg);
627 break;
628 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */
629 if (!imm)
630 break;
631 /* agfi %dst,-imm */
632 EMIT6_IMM(0xc2080000, dst_reg, -imm);
633 break;
634 /*
635 * BPF_MUL
636 */
637 case BPF_ALU | BPF_MUL | BPF_X: /* dst = (u32) dst * (u32) src */
638 /* msr %dst,%src */
639 EMIT4(0xb2520000, dst_reg, src_reg);
640 EMIT_ZERO(dst_reg);
641 break;
642 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst = dst * src */
643 /* msgr %dst,%src */
644 EMIT4(0xb90c0000, dst_reg, src_reg);
645 break;
646 case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */
647 if (imm == 1)
648 break;
649 /* msfi %r5,imm */
650 EMIT6_IMM(0xc2010000, dst_reg, imm);
651 EMIT_ZERO(dst_reg);
652 break;
653 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */
654 if (imm == 1)
655 break;
656 /* msgfi %dst,imm */
657 EMIT6_IMM(0xc2000000, dst_reg, imm);
658 break;
659 /*
660 * BPF_DIV / BPF_MOD
661 */
662 case BPF_ALU | BPF_DIV | BPF_X: /* dst = (u32) dst / (u32) src */
663 case BPF_ALU | BPF_MOD | BPF_X: /* dst = (u32) dst % (u32) src */
664 {
665 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
666
667 jit->seen |= SEEN_RET0;
668 /* ltr %src,%src (if src == 0 goto fail) */
669 EMIT2(0x1200, src_reg, src_reg);
670 /* jz <ret0> */
671 EMIT4_PCREL(0xa7840000, jit->ret0_ip - jit->prg);
672 /* lhi %w0,0 */
673 EMIT4_IMM(0xa7080000, REG_W0, 0);
674 /* lr %w1,%dst */
675 EMIT2(0x1800, REG_W1, dst_reg);
676 /* dlr %w0,%src */
677 EMIT4(0xb9970000, REG_W0, src_reg);
678 /* llgfr %dst,%rc */
679 EMIT4(0xb9160000, dst_reg, rc_reg);
680 break;
681 }
682 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst = dst / src */
683 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst = dst % src */
684 {
685 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
686
687 jit->seen |= SEEN_RET0;
688 /* ltgr %src,%src (if src == 0 goto fail) */
689 EMIT4(0xb9020000, src_reg, src_reg);
690 /* jz <ret0> */
691 EMIT4_PCREL(0xa7840000, jit->ret0_ip - jit->prg);
692 /* lghi %w0,0 */
693 EMIT4_IMM(0xa7090000, REG_W0, 0);
694 /* lgr %w1,%dst */
695 EMIT4(0xb9040000, REG_W1, dst_reg);
696 /* dlgr %w0,%dst */
697 EMIT4(0xb9870000, REG_W0, src_reg);
698 /* lgr %dst,%rc */
699 EMIT4(0xb9040000, dst_reg, rc_reg);
700 break;
701 }
702 case BPF_ALU | BPF_DIV | BPF_K: /* dst = (u32) dst / (u32) imm */
703 case BPF_ALU | BPF_MOD | BPF_K: /* dst = (u32) dst % (u32) imm */
704 {
705 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
706
707 if (imm == 1) {
708 if (BPF_OP(insn->code) == BPF_MOD)
709 /* lhgi %dst,0 */
710 EMIT4_IMM(0xa7090000, dst_reg, 0);
711 break;
712 }
713 /* lhi %w0,0 */
714 EMIT4_IMM(0xa7080000, REG_W0, 0);
715 /* lr %w1,%dst */
716 EMIT2(0x1800, REG_W1, dst_reg);
717 /* dl %w0,<d(imm)>(%l) */
718 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L,
719 EMIT_CONST_U32(imm));
720 /* llgfr %dst,%rc */
721 EMIT4(0xb9160000, dst_reg, rc_reg);
722 break;
723 }
724 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst = dst / imm */
725 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst = dst % imm */
726 {
727 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
728
729 if (imm == 1) {
730 if (BPF_OP(insn->code) == BPF_MOD)
731 /* lhgi %dst,0 */
732 EMIT4_IMM(0xa7090000, dst_reg, 0);
733 break;
734 }
735 /* lghi %w0,0 */
736 EMIT4_IMM(0xa7090000, REG_W0, 0);
737 /* lgr %w1,%dst */
738 EMIT4(0xb9040000, REG_W1, dst_reg);
739 /* dlg %w0,<d(imm)>(%l) */
740 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L,
741 EMIT_CONST_U64(imm));
742 /* lgr %dst,%rc */
743 EMIT4(0xb9040000, dst_reg, rc_reg);
744 break;
745 }
746 /*
747 * BPF_AND
748 */
749 case BPF_ALU | BPF_AND | BPF_X: /* dst = (u32) dst & (u32) src */
750 /* nr %dst,%src */
751 EMIT2(0x1400, dst_reg, src_reg);
752 EMIT_ZERO(dst_reg);
753 break;
754 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */
755 /* ngr %dst,%src */
756 EMIT4(0xb9800000, dst_reg, src_reg);
757 break;
758 case BPF_ALU | BPF_AND | BPF_K: /* dst = (u32) dst & (u32) imm */
759 /* nilf %dst,imm */
760 EMIT6_IMM(0xc00b0000, dst_reg, imm);
761 EMIT_ZERO(dst_reg);
762 break;
763 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */
764 /* ng %dst,<d(imm)>(%l) */
765 EMIT6_DISP_LH(0xe3000000, 0x0080, dst_reg, REG_0, REG_L,
766 EMIT_CONST_U64(imm));
767 break;
768 /*
769 * BPF_OR
770 */
771 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */
772 /* or %dst,%src */
773 EMIT2(0x1600, dst_reg, src_reg);
774 EMIT_ZERO(dst_reg);
775 break;
776 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */
777 /* ogr %dst,%src */
778 EMIT4(0xb9810000, dst_reg, src_reg);
779 break;
780 case BPF_ALU | BPF_OR | BPF_K: /* dst = (u32) dst | (u32) imm */
781 /* oilf %dst,imm */
782 EMIT6_IMM(0xc00d0000, dst_reg, imm);
783 EMIT_ZERO(dst_reg);
784 break;
785 case BPF_ALU64 | BPF_OR | BPF_K: /* dst = dst | imm */
786 /* og %dst,<d(imm)>(%l) */
787 EMIT6_DISP_LH(0xe3000000, 0x0081, dst_reg, REG_0, REG_L,
788 EMIT_CONST_U64(imm));
789 break;
790 /*
791 * BPF_XOR
792 */
793 case BPF_ALU | BPF_XOR | BPF_X: /* dst = (u32) dst ^ (u32) src */
794 /* xr %dst,%src */
795 EMIT2(0x1700, dst_reg, src_reg);
796 EMIT_ZERO(dst_reg);
797 break;
798 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst = dst ^ src */
799 /* xgr %dst,%src */
800 EMIT4(0xb9820000, dst_reg, src_reg);
801 break;
802 case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */
803 if (!imm)
804 break;
805 /* xilf %dst,imm */
806 EMIT6_IMM(0xc0070000, dst_reg, imm);
807 EMIT_ZERO(dst_reg);
808 break;
809 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */
810 /* xg %dst,<d(imm)>(%l) */
811 EMIT6_DISP_LH(0xe3000000, 0x0082, dst_reg, REG_0, REG_L,
812 EMIT_CONST_U64(imm));
813 break;
814 /*
815 * BPF_LSH
816 */
817 case BPF_ALU | BPF_LSH | BPF_X: /* dst = (u32) dst << (u32) src */
818 /* sll %dst,0(%src) */
819 EMIT4_DISP(0x89000000, dst_reg, src_reg, 0);
820 EMIT_ZERO(dst_reg);
821 break;
822 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst = dst << src */
823 /* sllg %dst,%dst,0(%src) */
824 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0);
825 break;
826 case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */
827 if (imm == 0)
828 break;
829 /* sll %dst,imm(%r0) */
830 EMIT4_DISP(0x89000000, dst_reg, REG_0, imm);
831 EMIT_ZERO(dst_reg);
832 break;
833 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */
834 if (imm == 0)
835 break;
836 /* sllg %dst,%dst,imm(%r0) */
837 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, REG_0, imm);
838 break;
839 /*
840 * BPF_RSH
841 */
842 case BPF_ALU | BPF_RSH | BPF_X: /* dst = (u32) dst >> (u32) src */
843 /* srl %dst,0(%src) */
844 EMIT4_DISP(0x88000000, dst_reg, src_reg, 0);
845 EMIT_ZERO(dst_reg);
846 break;
847 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst = dst >> src */
848 /* srlg %dst,%dst,0(%src) */
849 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0);
850 break;
851 case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */
852 if (imm == 0)
853 break;
854 /* srl %dst,imm(%r0) */
855 EMIT4_DISP(0x88000000, dst_reg, REG_0, imm);
856 EMIT_ZERO(dst_reg);
857 break;
858 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */
859 if (imm == 0)
860 break;
861 /* srlg %dst,%dst,imm(%r0) */
862 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, REG_0, imm);
863 break;
864 /*
865 * BPF_ARSH
866 */
867 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */
868 /* srag %dst,%dst,0(%src) */
869 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0);
870 break;
871 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */
872 if (imm == 0)
873 break;
874 /* srag %dst,%dst,imm(%r0) */
875 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, REG_0, imm);
876 break;
877 /*
878 * BPF_NEG
879 */
880 case BPF_ALU | BPF_NEG: /* dst = (u32) -dst */
881 /* lcr %dst,%dst */
882 EMIT2(0x1300, dst_reg, dst_reg);
883 EMIT_ZERO(dst_reg);
884 break;
885 case BPF_ALU64 | BPF_NEG: /* dst = -dst */
886 /* lcgr %dst,%dst */
887 EMIT4(0xb9130000, dst_reg, dst_reg);
888 break;
889 /*
890 * BPF_FROM_BE/LE
891 */
892 case BPF_ALU | BPF_END | BPF_FROM_BE:
893 /* s390 is big endian, therefore only clear high order bytes */
894 switch (imm) {
895 case 16: /* dst = (u16) cpu_to_be16(dst) */
896 /* llghr %dst,%dst */
897 EMIT4(0xb9850000, dst_reg, dst_reg);
898 break;
899 case 32: /* dst = (u32) cpu_to_be32(dst) */
900 /* llgfr %dst,%dst */
901 EMIT4(0xb9160000, dst_reg, dst_reg);
902 break;
903 case 64: /* dst = (u64) cpu_to_be64(dst) */
904 break;
905 }
906 break;
907 case BPF_ALU | BPF_END | BPF_FROM_LE:
908 switch (imm) {
909 case 16: /* dst = (u16) cpu_to_le16(dst) */
910 /* lrvr %dst,%dst */
911 EMIT4(0xb91f0000, dst_reg, dst_reg);
912 /* srl %dst,16(%r0) */
913 EMIT4_DISP(0x88000000, dst_reg, REG_0, 16);
914 /* llghr %dst,%dst */
915 EMIT4(0xb9850000, dst_reg, dst_reg);
916 break;
917 case 32: /* dst = (u32) cpu_to_le32(dst) */
918 /* lrvr %dst,%dst */
919 EMIT4(0xb91f0000, dst_reg, dst_reg);
920 /* llgfr %dst,%dst */
921 EMIT4(0xb9160000, dst_reg, dst_reg);
922 break;
923 case 64: /* dst = (u64) cpu_to_le64(dst) */
924 /* lrvgr %dst,%dst */
925 EMIT4(0xb90f0000, dst_reg, dst_reg);
926 break;
927 }
928 break;
929 /*
930 * BPF_ST(X)
931 */
932 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src_reg */
933 /* stcy %src,off(%dst) */
934 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg, dst_reg, REG_0, off);
935 jit->seen |= SEEN_MEM;
936 break;
937 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */
938 /* sthy %src,off(%dst) */
939 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg, dst_reg, REG_0, off);
940 jit->seen |= SEEN_MEM;
941 break;
942 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */
943 /* sty %src,off(%dst) */
944 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg, dst_reg, REG_0, off);
945 jit->seen |= SEEN_MEM;
946 break;
947 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */
948 /* stg %src,off(%dst) */
949 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg, dst_reg, REG_0, off);
950 jit->seen |= SEEN_MEM;
951 break;
952 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */
953 /* lhi %w0,imm */
954 EMIT4_IMM(0xa7080000, REG_W0, (u8) imm);
955 /* stcy %w0,off(dst) */
956 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off);
957 jit->seen |= SEEN_MEM;
958 break;
959 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */
960 /* lhi %w0,imm */
961 EMIT4_IMM(0xa7080000, REG_W0, (u16) imm);
962 /* sthy %w0,off(dst) */
963 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off);
964 jit->seen |= SEEN_MEM;
965 break;
966 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */
967 /* llilf %w0,imm */
968 EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm);
969 /* sty %w0,off(%dst) */
970 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off);
971 jit->seen |= SEEN_MEM;
972 break;
973 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */
974 /* lgfi %w0,imm */
975 EMIT6_IMM(0xc0010000, REG_W0, imm);
976 /* stg %w0,off(%dst) */
977 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off);
978 jit->seen |= SEEN_MEM;
979 break;
980 /*
981 * BPF_STX XADD (atomic_add)
982 */
983 case BPF_STX | BPF_XADD | BPF_W: /* *(u32 *)(dst + off) += src */
984 /* laal %w0,%src,off(%dst) */
985 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0, src_reg,
986 dst_reg, off);
987 jit->seen |= SEEN_MEM;
988 break;
989 case BPF_STX | BPF_XADD | BPF_DW: /* *(u64 *)(dst + off) += src */
990 /* laalg %w0,%src,off(%dst) */
991 EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0, src_reg,
992 dst_reg, off);
993 jit->seen |= SEEN_MEM;
994 break;
995 /*
996 * BPF_LDX
997 */
998 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */
999 /* llgc %dst,0(off,%src) */
1000 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg, src_reg, REG_0, off);
1001 jit->seen |= SEEN_MEM;
1002 break;
1003 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */
1004 /* llgh %dst,0(off,%src) */
1005 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg, src_reg, REG_0, off);
1006 jit->seen |= SEEN_MEM;
1007 break;
1008 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */
1009 /* llgf %dst,off(%src) */
1010 jit->seen |= SEEN_MEM;
1011 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg, src_reg, REG_0, off);
1012 break;
1013 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */
1014 /* lg %dst,0(off,%src) */
1015 jit->seen |= SEEN_MEM;
1016 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, src_reg, REG_0, off);
1017 break;
1018 /*
1019 * BPF_JMP / CALL
1020 */
1021 case BPF_JMP | BPF_CALL:
1022 {
1023 /*
1024 * b0 = (__bpf_call_base + imm)(b1, b2, b3, b4, b5)
1025 */
1026 const u64 func = (u64)__bpf_call_base + imm;
1027
1028 REG_SET_SEEN(BPF_REG_5);
1029 jit->seen |= SEEN_FUNC;
1030 /* lg %w1,<d(imm)>(%l) */
1031 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_W1, REG_0, REG_L,
1032 EMIT_CONST_U64(func));
1033 if (IS_ENABLED(CC_USING_EXPOLINE) && !nospec_disable) {
1034 /* brasl %r14,__s390_indirect_jump_r1 */
1035 EMIT6_PCREL_RILB(0xc0050000, REG_14, jit->r1_thunk_ip);
1036 } else {
1037 /* basr %r14,%w1 */
1038 EMIT2(0x0d00, REG_14, REG_W1);
1039 }
1040 /* lgr %b0,%r2: load return value into %b0 */
1041 EMIT4(0xb9040000, BPF_REG_0, REG_2);
1042 if ((jit->seen & SEEN_SKB) &&
1043 bpf_helper_changes_pkt_data((void *)func)) {
1044 /* lg %b1,ST_OFF_SKBP(%r15) */
1045 EMIT6_DISP_LH(0xe3000000, 0x0004, BPF_REG_1, REG_0,
1046 REG_15, STK_OFF_SKBP);
1047 emit_load_skb_data_hlen(jit);
1048 }
1049 break;
1050 }
1051 case BPF_JMP | BPF_TAIL_CALL:
1052 /*
1053 * Implicit input:
1054 * B1: pointer to ctx
1055 * B2: pointer to bpf_array
1056 * B3: index in bpf_array
1057 */
1058 jit->seen |= SEEN_TAIL_CALL;
1059
1060 /*
1061 * if (index >= array->map.max_entries)
1062 * goto out;
1063 */
1064
1065 /* llgf %w1,map.max_entries(%b2) */
1066 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_2,
1067 offsetof(struct bpf_array, map.max_entries));
1068 /* clgrj %b3,%w1,0xa,label0: if %b3 >= %w1 goto out */
1069 EMIT6_PCREL_LABEL(0xec000000, 0x0065, BPF_REG_3,
1070 REG_W1, 0, 0xa);
1071
1072 /*
1073 * if (tail_call_cnt++ > MAX_TAIL_CALL_CNT)
1074 * goto out;
1075 */
1076
1077 if (jit->seen & SEEN_STACK)
1078 off = STK_OFF_TCCNT + STK_OFF;
1079 else
1080 off = STK_OFF_TCCNT;
1081 /* lhi %w0,1 */
1082 EMIT4_IMM(0xa7080000, REG_W0, 1);
1083 /* laal %w1,%w0,off(%r15) */
1084 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off);
1085 /* clij %w1,MAX_TAIL_CALL_CNT,0x2,label0 */
1086 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007f, REG_W1,
1087 MAX_TAIL_CALL_CNT, 0, 0x2);
1088
1089 /*
1090 * prog = array->ptrs[index];
1091 * if (prog == NULL)
1092 * goto out;
1093 */
1094
1095 /* sllg %r1,%b3,3: %r1 = index * 8 */
1096 EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1, BPF_REG_3, REG_0, 3);
1097 /* lg %r1,prog(%b2,%r1) */
1098 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, BPF_REG_2,
1099 REG_1, offsetof(struct bpf_array, ptrs));
1100 /* clgij %r1,0,0x8,label0 */
1101 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007d, REG_1, 0, 0, 0x8);
1102
1103 /*
1104 * Restore registers before calling function
1105 */
1106 save_restore_regs(jit, REGS_RESTORE);
1107
1108 /*
1109 * goto *(prog->bpf_func + tail_call_start);
1110 */
1111
1112 /* lg %r1,bpf_func(%r1) */
1113 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, REG_1, REG_0,
1114 offsetof(struct bpf_prog, bpf_func));
1115 /* bc 0xf,tail_call_start(%r1) */
1116 _EMIT4(0x47f01000 + jit->tail_call_start);
1117 /* out: */
1118 jit->labels[0] = jit->prg;
1119 break;
1120 case BPF_JMP | BPF_EXIT: /* return b0 */
1121 last = (i == fp->len - 1) ? 1 : 0;
1122 if (last && !(jit->seen & SEEN_RET0))
1123 break;
1124 /* j <exit> */
1125 EMIT4_PCREL(0xa7f40000, jit->exit_ip - jit->prg);
1126 break;
1127 /*
1128 * Branch relative (number of skipped instructions) to offset on
1129 * condition.
1130 *
1131 * Condition code to mask mapping:
1132 *
1133 * CC | Description | Mask
1134 * ------------------------------
1135 * 0 | Operands equal | 8
1136 * 1 | First operand low | 4
1137 * 2 | First operand high | 2
1138 * 3 | Unused | 1
1139 *
1140 * For s390x relative branches: ip = ip + off_bytes
1141 * For BPF relative branches: insn = insn + off_insns + 1
1142 *
1143 * For example for s390x with offset 0 we jump to the branch
1144 * instruction itself (loop) and for BPF with offset 0 we
1145 * branch to the instruction behind the branch.
1146 */
1147 case BPF_JMP | BPF_JA: /* if (true) */
1148 mask = 0xf000; /* j */
1149 goto branch_oc;
1150 case BPF_JMP | BPF_JSGT | BPF_K: /* ((s64) dst > (s64) imm) */
1151 mask = 0x2000; /* jh */
1152 goto branch_ks;
1153 case BPF_JMP | BPF_JSLT | BPF_K: /* ((s64) dst < (s64) imm) */
1154 mask = 0x4000; /* jl */
1155 goto branch_ks;
1156 case BPF_JMP | BPF_JSGE | BPF_K: /* ((s64) dst >= (s64) imm) */
1157 mask = 0xa000; /* jhe */
1158 goto branch_ks;
1159 case BPF_JMP | BPF_JSLE | BPF_K: /* ((s64) dst <= (s64) imm) */
1160 mask = 0xc000; /* jle */
1161 goto branch_ks;
1162 case BPF_JMP | BPF_JGT | BPF_K: /* (dst_reg > imm) */
1163 mask = 0x2000; /* jh */
1164 goto branch_ku;
1165 case BPF_JMP | BPF_JLT | BPF_K: /* (dst_reg < imm) */
1166 mask = 0x4000; /* jl */
1167 goto branch_ku;
1168 case BPF_JMP | BPF_JGE | BPF_K: /* (dst_reg >= imm) */
1169 mask = 0xa000; /* jhe */
1170 goto branch_ku;
1171 case BPF_JMP | BPF_JLE | BPF_K: /* (dst_reg <= imm) */
1172 mask = 0xc000; /* jle */
1173 goto branch_ku;
1174 case BPF_JMP | BPF_JNE | BPF_K: /* (dst_reg != imm) */
1175 mask = 0x7000; /* jne */
1176 goto branch_ku;
1177 case BPF_JMP | BPF_JEQ | BPF_K: /* (dst_reg == imm) */
1178 mask = 0x8000; /* je */
1179 goto branch_ku;
1180 case BPF_JMP | BPF_JSET | BPF_K: /* (dst_reg & imm) */
1181 mask = 0x7000; /* jnz */
1182 /* lgfi %w1,imm (load sign extend imm) */
1183 EMIT6_IMM(0xc0010000, REG_W1, imm);
1184 /* ngr %w1,%dst */
1185 EMIT4(0xb9800000, REG_W1, dst_reg);
1186 goto branch_oc;
1187
1188 case BPF_JMP | BPF_JSGT | BPF_X: /* ((s64) dst > (s64) src) */
1189 mask = 0x2000; /* jh */
1190 goto branch_xs;
1191 case BPF_JMP | BPF_JSLT | BPF_X: /* ((s64) dst < (s64) src) */
1192 mask = 0x4000; /* jl */
1193 goto branch_xs;
1194 case BPF_JMP | BPF_JSGE | BPF_X: /* ((s64) dst >= (s64) src) */
1195 mask = 0xa000; /* jhe */
1196 goto branch_xs;
1197 case BPF_JMP | BPF_JSLE | BPF_X: /* ((s64) dst <= (s64) src) */
1198 mask = 0xc000; /* jle */
1199 goto branch_xs;
1200 case BPF_JMP | BPF_JGT | BPF_X: /* (dst > src) */
1201 mask = 0x2000; /* jh */
1202 goto branch_xu;
1203 case BPF_JMP | BPF_JLT | BPF_X: /* (dst < src) */
1204 mask = 0x4000; /* jl */
1205 goto branch_xu;
1206 case BPF_JMP | BPF_JGE | BPF_X: /* (dst >= src) */
1207 mask = 0xa000; /* jhe */
1208 goto branch_xu;
1209 case BPF_JMP | BPF_JLE | BPF_X: /* (dst <= src) */
1210 mask = 0xc000; /* jle */
1211 goto branch_xu;
1212 case BPF_JMP | BPF_JNE | BPF_X: /* (dst != src) */
1213 mask = 0x7000; /* jne */
1214 goto branch_xu;
1215 case BPF_JMP | BPF_JEQ | BPF_X: /* (dst == src) */
1216 mask = 0x8000; /* je */
1217 goto branch_xu;
1218 case BPF_JMP | BPF_JSET | BPF_X: /* (dst & src) */
1219 mask = 0x7000; /* jnz */
1220 /* ngrk %w1,%dst,%src */
1221 EMIT4_RRF(0xb9e40000, REG_W1, dst_reg, src_reg);
1222 goto branch_oc;
1223 branch_ks:
1224 /* lgfi %w1,imm (load sign extend imm) */
1225 EMIT6_IMM(0xc0010000, REG_W1, imm);
1226 /* cgrj %dst,%w1,mask,off */
1227 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, REG_W1, i, off, mask);
1228 break;
1229 branch_ku:
1230 /* lgfi %w1,imm (load sign extend imm) */
1231 EMIT6_IMM(0xc0010000, REG_W1, imm);
1232 /* clgrj %dst,%w1,mask,off */
1233 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, REG_W1, i, off, mask);
1234 break;
1235 branch_xs:
1236 /* cgrj %dst,%src,mask,off */
1237 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, src_reg, i, off, mask);
1238 break;
1239 branch_xu:
1240 /* clgrj %dst,%src,mask,off */
1241 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, src_reg, i, off, mask);
1242 break;
1243 branch_oc:
1244 /* brc mask,jmp_off (branch instruction needs 4 bytes) */
1245 jmp_off = addrs[i + off + 1] - (addrs[i + 1] - 4);
1246 EMIT4_PCREL(0xa7040000 | mask << 8, jmp_off);
1247 break;
1248 /*
1249 * BPF_LD
1250 */
1251 case BPF_LD | BPF_ABS | BPF_B: /* b0 = *(u8 *) (skb->data+imm) */
1252 case BPF_LD | BPF_IND | BPF_B: /* b0 = *(u8 *) (skb->data+imm+src) */
1253 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1254 func_addr = __pa(sk_load_byte_pos);
1255 else
1256 func_addr = __pa(sk_load_byte);
1257 goto call_fn;
1258 case BPF_LD | BPF_ABS | BPF_H: /* b0 = *(u16 *) (skb->data+imm) */
1259 case BPF_LD | BPF_IND | BPF_H: /* b0 = *(u16 *) (skb->data+imm+src) */
1260 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1261 func_addr = __pa(sk_load_half_pos);
1262 else
1263 func_addr = __pa(sk_load_half);
1264 goto call_fn;
1265 case BPF_LD | BPF_ABS | BPF_W: /* b0 = *(u32 *) (skb->data+imm) */
1266 case BPF_LD | BPF_IND | BPF_W: /* b0 = *(u32 *) (skb->data+imm+src) */
1267 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1268 func_addr = __pa(sk_load_word_pos);
1269 else
1270 func_addr = __pa(sk_load_word);
1271 goto call_fn;
1272 call_fn:
1273 jit->seen |= SEEN_SKB | SEEN_RET0 | SEEN_FUNC;
1274 REG_SET_SEEN(REG_14); /* Return address of possible func call */
1275
1276 /*
1277 * Implicit input:
1278 * BPF_REG_6 (R7) : skb pointer
1279 * REG_SKB_DATA (R12): skb data pointer (if no BPF_REG_AX)
1280 *
1281 * Calculated input:
1282 * BPF_REG_2 (R3) : offset of byte(s) to fetch in skb
1283 * BPF_REG_5 (R6) : return address
1284 *
1285 * Output:
1286 * BPF_REG_0 (R14): data read from skb
1287 *
1288 * Scratch registers (BPF_REG_1-5)
1289 */
1290
1291 /* Call function: llilf %w1,func_addr */
1292 EMIT6_IMM(0xc00f0000, REG_W1, func_addr);
1293
1294 /* Offset: lgfi %b2,imm */
1295 EMIT6_IMM(0xc0010000, BPF_REG_2, imm);
1296 if (BPF_MODE(insn->code) == BPF_IND)
1297 /* agfr %b2,%src (%src is s32 here) */
1298 EMIT4(0xb9180000, BPF_REG_2, src_reg);
1299
1300 /* Reload REG_SKB_DATA if BPF_REG_AX is used */
1301 if (jit->seen & SEEN_REG_AX)
1302 /* lg %skb_data,data_off(%b6) */
1303 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_SKB_DATA, REG_0,
1304 BPF_REG_6, offsetof(struct sk_buff, data));
1305 /* basr %b5,%w1 (%b5 is call saved) */
1306 EMIT2(0x0d00, BPF_REG_5, REG_W1);
1307
1308 /*
1309 * Note: For fast access we jump directly after the
1310 * jnz instruction from bpf_jit.S
1311 */
1312 /* jnz <ret0> */
1313 EMIT4_PCREL(0xa7740000, jit->ret0_ip - jit->prg);
1314 break;
1315 default: /* too complex, give up */
1316 pr_err("Unknown opcode %02x\n", insn->code);
1317 return -1;
1318 }
1319 return insn_count;
1320 }
1321
1322 /*
1323 * Compile eBPF program into s390x code
1324 */
1325 static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp)
1326 {
1327 int i, insn_count;
1328
1329 jit->lit = jit->lit_start;
1330 jit->prg = 0;
1331
1332 bpf_jit_prologue(jit);
1333 for (i = 0; i < fp->len; i += insn_count) {
1334 insn_count = bpf_jit_insn(jit, fp, i);
1335 if (insn_count < 0)
1336 return -1;
1337 /* Next instruction address */
1338 jit->addrs[i + insn_count] = jit->prg;
1339 }
1340 bpf_jit_epilogue(jit);
1341
1342 jit->lit_start = jit->prg;
1343 jit->size = jit->lit;
1344 jit->size_prg = jit->prg;
1345 return 0;
1346 }
1347
1348 /*
1349 * Compile eBPF program "fp"
1350 */
1351 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp)
1352 {
1353 struct bpf_prog *tmp, *orig_fp = fp;
1354 struct bpf_binary_header *header;
1355 bool tmp_blinded = false;
1356 struct bpf_jit jit;
1357 int pass;
1358
1359 if (!bpf_jit_enable)
1360 return orig_fp;
1361
1362 tmp = bpf_jit_blind_constants(fp);
1363 /*
1364 * If blinding was requested and we failed during blinding,
1365 * we must fall back to the interpreter.
1366 */
1367 if (IS_ERR(tmp))
1368 return orig_fp;
1369 if (tmp != fp) {
1370 tmp_blinded = true;
1371 fp = tmp;
1372 }
1373
1374 memset(&jit, 0, sizeof(jit));
1375 jit.addrs = kcalloc(fp->len + 1, sizeof(*jit.addrs), GFP_KERNEL);
1376 if (jit.addrs == NULL) {
1377 fp = orig_fp;
1378 goto out;
1379 }
1380 /*
1381 * Three initial passes:
1382 * - 1/2: Determine clobbered registers
1383 * - 3: Calculate program size and addrs arrray
1384 */
1385 for (pass = 1; pass <= 3; pass++) {
1386 if (bpf_jit_prog(&jit, fp)) {
1387 fp = orig_fp;
1388 goto free_addrs;
1389 }
1390 }
1391 /*
1392 * Final pass: Allocate and generate program
1393 */
1394 if (jit.size >= BPF_SIZE_MAX) {
1395 fp = orig_fp;
1396 goto free_addrs;
1397 }
1398 header = bpf_jit_binary_alloc(jit.size, &jit.prg_buf, 2, jit_fill_hole);
1399 if (!header) {
1400 fp = orig_fp;
1401 goto free_addrs;
1402 }
1403 if (bpf_jit_prog(&jit, fp)) {
1404 bpf_jit_binary_free(header);
1405 fp = orig_fp;
1406 goto free_addrs;
1407 }
1408 if (bpf_jit_enable > 1) {
1409 bpf_jit_dump(fp->len, jit.size, pass, jit.prg_buf);
1410 print_fn_code(jit.prg_buf, jit.size_prg);
1411 }
1412 bpf_jit_binary_lock_ro(header);
1413 fp->bpf_func = (void *) jit.prg_buf;
1414 fp->jited = 1;
1415 fp->jited_len = jit.size;
1416 free_addrs:
1417 kfree(jit.addrs);
1418 out:
1419 if (tmp_blinded)
1420 bpf_jit_prog_release_other(fp, fp == orig_fp ?
1421 tmp : orig_fp);
1422 return fp;
1423 }
Linux with added FPC-III support