arch/s390/pci/pci_insn.c

   1 /*
   2  * s390 specific pci instructions
   3  *
   4  * Copyright IBM Corp. 2013
   5  */
   6
   7 #include <linux/export.h>
   8 #include <linux/errno.h>
   9 #include <linux/delay.h>
  10 #include <asm/facility.h>
  11 #include <asm/pci_insn.h>
  12 #include <asm/pci_debug.h>
  13 #include <asm/processor.h>
  14
  15 #define ZPCI_INSN_BUSY_DELAY    1       /* 1 microsecond */
  16
  17 static inline void zpci_err_insn(u8 cc, u8 status, u64 req, u64 offset)
  18 {
  19         struct {
  20                 u64 req;
  21                 u64 offset;
  22                 u8 cc;
  23                 u8 status;
  24         } __packed data = {req, offset, cc, status};
  25
  26         zpci_err_hex(&data, sizeof(data));
  27 }
  28
  29 /* Modify PCI Function Controls */
  30 static inline u8 __mpcifc(u64 req, struct zpci_fib *fib, u8 *status)
  31 {
  32         u8 cc;
  33
  34         asm volatile (
  35                 "       .insn   rxy,0xe300000000d0,%[req],%[fib]\n"
  36                 "       ipm     %[cc]\n"
  37                 "       srl     %[cc],28\n"
  38                 : [cc] "=d" (cc), [req] "+d" (req), [fib] "+Q" (*fib)
  39                 : : "cc");
  40         *status = req >> 24 & 0xff;
  41         return cc;
  42 }
  43
  44 u8 zpci_mod_fc(u64 req, struct zpci_fib *fib, u8 *status)
  45 {
  46         u8 cc;
  47
  48         do {
  49                 cc = __mpcifc(req, fib, status);
  50                 if (cc == 2)
  51                         msleep(ZPCI_INSN_BUSY_DELAY);
  52         } while (cc == 2);
  53
  54         if (cc)
  55                 zpci_err_insn(cc, *status, req, 0);
  56
  57         return cc;
  58 }
  59
  60 /* Refresh PCI Translations */
  61 static inline u8 __rpcit(u64 fn, u64 addr, u64 range, u8 *status)
  62 {
  63         register u64 __addr asm("2") = addr;
  64         register u64 __range asm("3") = range;
  65         u8 cc;
  66
  67         asm volatile (
  68                 "       .insn   rre,0xb9d30000,%[fn],%[addr]\n"
  69                 "       ipm     %[cc]\n"
  70                 "       srl     %[cc],28\n"
  71                 : [cc] "=d" (cc), [fn] "+d" (fn)
  72                 : [addr] "d" (__addr), "d" (__range)
  73                 : "cc");
  74         *status = fn >> 24 & 0xff;
  75         return cc;
  76 }
  77
  78 int zpci_refresh_trans(u64 fn, u64 addr, u64 range)
  79 {
  80         u8 cc, status;
  81
  82         do {
  83                 cc = __rpcit(fn, addr, range, &status);
  84                 if (cc == 2)
  85                         udelay(ZPCI_INSN_BUSY_DELAY);
  86         } while (cc == 2);
  87
  88         if (cc)
  89                 zpci_err_insn(cc, status, addr, range);
  90
  91         return (cc) ? -EIO : 0;
  92 }
  93
  94 /* Set Interruption Controls */
  95 int zpci_set_irq_ctrl(u16 ctl, char *unused, u8 isc)
  96 {
  97         if (!test_facility(72))
  98                 return -EIO;
  99         asm volatile (
 100                 "       .insn   rsy,0xeb00000000d1,%[ctl],%[isc],%[u]\n"
 101                 : : [ctl] "d" (ctl), [isc] "d" (isc << 27), [u] "Q" (*unused));
 102         return 0;
 103 }
 104
 105 /* PCI Load */
 106 static inline int ____pcilg(u64 *data, u64 req, u64 offset, u8 *status)
 107 {
 108         register u64 __req asm("2") = req;
 109         register u64 __offset asm("3") = offset;
 110         int cc = -ENXIO;
 111         u64 __data;
 112
 113         asm volatile (
 114                 "       .insn   rre,0xb9d20000,%[data],%[req]\n"
 115                 "0:     ipm     %[cc]\n"
 116                 "       srl     %[cc],28\n"
 117                 "1:\n"
 118                 EX_TABLE(0b, 1b)
 119                 : [cc] "+d" (cc), [data] "=d" (__data), [req] "+d" (__req)
 120                 :  "d" (__offset)
 121                 : "cc");
 122         *status = __req >> 24 & 0xff;
 123         *data = __data;
 124         return cc;
 125 }
 126
 127 static inline int __pcilg(u64 *data, u64 req, u64 offset, u8 *status)
 128 {
 129         u64 __data;
 130         int cc;
 131
 132         cc = ____pcilg(&__data, req, offset, status);
 133         if (!cc)
 134                 *data = __data;
 135
 136         return cc;
 137 }
 138
 139 int zpci_load(u64 *data, u64 req, u64 offset)
 140 {
 141         u8 status;
 142         int cc;
 143
 144         do {
 145                 cc = __pcilg(data, req, offset, &status);
 146                 if (cc == 2)
 147                         udelay(ZPCI_INSN_BUSY_DELAY);
 148         } while (cc == 2);
 149
 150         if (cc)
 151                 zpci_err_insn(cc, status, req, offset);
 152
 153         return (cc > 0) ? -EIO : cc;
 154 }
 155 EXPORT_SYMBOL_GPL(zpci_load);
 156
 157 /* PCI Store */
 158 static inline int __pcistg(u64 data, u64 req, u64 offset, u8 *status)
 159 {
 160         register u64 __req asm("2") = req;
 161         register u64 __offset asm("3") = offset;
 162         int cc = -ENXIO;
 163
 164         asm volatile (
 165                 "       .insn   rre,0xb9d00000,%[data],%[req]\n"
 166                 "0:     ipm     %[cc]\n"
 167                 "       srl     %[cc],28\n"
 168                 "1:\n"
 169                 EX_TABLE(0b, 1b)
 170                 : [cc] "+d" (cc), [req] "+d" (__req)
 171                 : "d" (__offset), [data] "d" (data)
 172                 : "cc");
 173         *status = __req >> 24 & 0xff;
 174         return cc;
 175 }
 176
 177 int zpci_store(u64 data, u64 req, u64 offset)
 178 {
 179         u8 status;
 180         int cc;
 181
 182         do {
 183                 cc = __pcistg(data, req, offset, &status);
 184                 if (cc == 2)
 185                         udelay(ZPCI_INSN_BUSY_DELAY);
 186         } while (cc == 2);
 187
 188         if (cc)
 189                 zpci_err_insn(cc, status, req, offset);
 190
 191         return (cc > 0) ? -EIO : cc;
 192 }
 193 EXPORT_SYMBOL_GPL(zpci_store);
 194
 195 /* PCI Store Block */
 196 static inline int __pcistb(const u64 *data, u64 req, u64 offset, u8 *status)
 197 {
 198         int cc = -ENXIO;
 199
 200         asm volatile (
 201                 "       .insn   rsy,0xeb00000000d0,%[req],%[offset],%[data]\n"
 202                 "0:     ipm     %[cc]\n"
 203                 "       srl     %[cc],28\n"
 204                 "1:\n"
 205                 EX_TABLE(0b, 1b)
 206                 : [cc] "+d" (cc), [req] "+d" (req)
 207                 : [offset] "d" (offset), [data] "Q" (*data)
 208                 : "cc");
 209         *status = req >> 24 & 0xff;
 210         return cc;
 211 }
 212
 213 int zpci_store_block(const u64 *data, u64 req, u64 offset)
 214 {
 215         u8 status;
 216         int cc;
 217
 218         do {
 219                 cc = __pcistb(data, req, offset, &status);
 220                 if (cc == 2)
 221                         udelay(ZPCI_INSN_BUSY_DELAY);
 222         } while (cc == 2);
 223
 224         if (cc)
 225                 zpci_err_insn(cc, status, req, offset);
 226
 227         return (cc > 0) ? -EIO : cc;
 228 }
 229 EXPORT_SYMBOL_GPL(zpci_store_block);