arch/x86/events/amd/uncore.c

   1 /*
   2  * Copyright (C) 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Author: Jacob Shin <jacob.shin@amd.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/perf_event.h>
  12 #include <linux/percpu.h>
  13 #include <linux/types.h>
  14 #include <linux/slab.h>
  15 #include <linux/init.h>
  16 #include <linux/cpu.h>
  17 #include <linux/cpumask.h>
  18
  19 #include <asm/cpufeature.h>
  20 #include <asm/perf_event.h>
  21 #include <asm/msr.h>
  22
  23 #define NUM_COUNTERS_NB         4
  24 #define NUM_COUNTERS_L2         4
  25 #define NUM_COUNTERS_L3         6
  26 #define MAX_COUNTERS            6
  27
  28 #define RDPMC_BASE_NB           6
  29 #define RDPMC_BASE_LLC          10
  30
  31 #define COUNTER_SHIFT           16
  32
  33 #undef pr_fmt
  34 #define pr_fmt(fmt)     "amd_uncore: " fmt
  35
  36 static int num_counters_llc;
  37 static int num_counters_nb;
  38 static bool l3_mask;
  39
  40 static HLIST_HEAD(uncore_unused_list);
  41
  42 struct amd_uncore {
  43         int id;
  44         int refcnt;
  45         int cpu;
  46         int num_counters;
  47         int rdpmc_base;
  48         u32 msr_base;
  49         cpumask_t *active_mask;
  50         struct pmu *pmu;
  51         struct perf_event *events[MAX_COUNTERS];
  52         struct hlist_node node;
  53 };
  54
  55 static struct amd_uncore * __percpu *amd_uncore_nb;
  56 static struct amd_uncore * __percpu *amd_uncore_llc;
  57
  58 static struct pmu amd_nb_pmu;
  59 static struct pmu amd_llc_pmu;
  60
  61 static cpumask_t amd_nb_active_mask;
  62 static cpumask_t amd_llc_active_mask;
  63
  64 static bool is_nb_event(struct perf_event *event)
  65 {
  66         return event->pmu->type == amd_nb_pmu.type;
  67 }
  68
  69 static bool is_llc_event(struct perf_event *event)
  70 {
  71         return event->pmu->type == amd_llc_pmu.type;
  72 }
  73
  74 static struct amd_uncore *event_to_amd_uncore(struct perf_event *event)
  75 {
  76         if (is_nb_event(event) && amd_uncore_nb)
  77                 return *per_cpu_ptr(amd_uncore_nb, event->cpu);
  78         else if (is_llc_event(event) && amd_uncore_llc)
  79                 return *per_cpu_ptr(amd_uncore_llc, event->cpu);
  80
  81         return NULL;
  82 }
  83
  84 static void amd_uncore_read(struct perf_event *event)
  85 {
  86         struct hw_perf_event *hwc = &event->hw;
  87         u64 prev, new;
  88         s64 delta;
  89
  90         /*
  91          * since we do not enable counter overflow interrupts,
  92          * we do not have to worry about prev_count changing on us
  93          */
  94
  95         prev = local64_read(&hwc->prev_count);
  96         rdpmcl(hwc->event_base_rdpmc, new);
  97         local64_set(&hwc->prev_count, new);
  98         delta = (new << COUNTER_SHIFT) - (prev << COUNTER_SHIFT);
  99         delta >>= COUNTER_SHIFT;
 100         local64_add(delta, &event->count);
 101 }
 102
 103 static void amd_uncore_start(struct perf_event *event, int flags)
 104 {
 105         struct hw_perf_event *hwc = &event->hw;
 106
 107         if (flags & PERF_EF_RELOAD)
 108                 wrmsrl(hwc->event_base, (u64)local64_read(&hwc->prev_count));
 109
 110         hwc->state = 0;
 111         wrmsrl(hwc->config_base, (hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE));
 112         perf_event_update_userpage(event);
 113 }
 114
 115 static void amd_uncore_stop(struct perf_event *event, int flags)
 116 {
 117         struct hw_perf_event *hwc = &event->hw;
 118
 119         wrmsrl(hwc->config_base, hwc->config);
 120         hwc->state |= PERF_HES_STOPPED;
 121
 122         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
 123                 amd_uncore_read(event);
 124                 hwc->state |= PERF_HES_UPTODATE;
 125         }
 126 }
 127
 128 static int amd_uncore_add(struct perf_event *event, int flags)
 129 {
 130         int i;
 131         struct amd_uncore *uncore = event_to_amd_uncore(event);
 132         struct hw_perf_event *hwc = &event->hw;
 133
 134         /* are we already assigned? */
 135         if (hwc->idx != -1 && uncore->events[hwc->idx] == event)
 136                 goto out;
 137
 138         for (i = 0; i < uncore->num_counters; i++) {
 139                 if (uncore->events[i] == event) {
 140                         hwc->idx = i;
 141                         goto out;
 142                 }
 143         }
 144
 145         /* if not, take the first available counter */
 146         hwc->idx = -1;
 147         for (i = 0; i < uncore->num_counters; i++) {
 148                 if (cmpxchg(&uncore->events[i], NULL, event) == NULL) {
 149                         hwc->idx = i;
 150                         break;
 151                 }
 152         }
 153
 154 out:
 155         if (hwc->idx == -1)
 156                 return -EBUSY;
 157
 158         hwc->config_base = uncore->msr_base + (2 * hwc->idx);
 159         hwc->event_base = uncore->msr_base + 1 + (2 * hwc->idx);
 160         hwc->event_base_rdpmc = uncore->rdpmc_base + hwc->idx;
 161         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
 162
 163         if (flags & PERF_EF_START)
 164                 amd_uncore_start(event, PERF_EF_RELOAD);
 165
 166         return 0;
 167 }
 168
 169 static void amd_uncore_del(struct perf_event *event, int flags)
 170 {
 171         int i;
 172         struct amd_uncore *uncore = event_to_amd_uncore(event);
 173         struct hw_perf_event *hwc = &event->hw;
 174
 175         amd_uncore_stop(event, PERF_EF_UPDATE);
 176
 177         for (i = 0; i < uncore->num_counters; i++) {
 178                 if (cmpxchg(&uncore->events[i], event, NULL) == event)
 179                         break;
 180         }
 181
 182         hwc->idx = -1;
 183 }
 184
 185 static int amd_uncore_event_init(struct perf_event *event)
 186 {
 187         struct amd_uncore *uncore;
 188         struct hw_perf_event *hwc = &event->hw;
 189
 190         if (event->attr.type != event->pmu->type)
 191                 return -ENOENT;
 192
 193         /*
 194          * NB and Last level cache counters (MSRs) are shared across all cores
 195          * that share the same NB / Last level cache. Interrupts can be directed
 196          * to a single target core, however, event counts generated by processes
 197          * running on other cores cannot be masked out. So we do not support
 198          * sampling and per-thread events.
 199          */
 200         if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
 201                 return -EINVAL;
 202
 203         /* NB and Last level cache counters do not have usr/os/guest/host bits */
 204         if (event->attr.exclude_user || event->attr.exclude_kernel ||
 205             event->attr.exclude_host || event->attr.exclude_guest)
 206                 return -EINVAL;
 207
 208         /* and we do not enable counter overflow interrupts */
 209         hwc->config = event->attr.config & AMD64_RAW_EVENT_MASK_NB;
 210         hwc->idx = -1;
 211
 212         /*
 213          * SliceMask and ThreadMask need to be set for certain L3 events in
 214          * Family 17h. For other events, the two fields do not affect the count.
 215          */
 216         if (l3_mask)
 217                 hwc->config |= (AMD64_L3_SLICE_MASK | AMD64_L3_THREAD_MASK);
 218
 219         if (event->cpu < 0)
 220                 return -EINVAL;
 221
 222         uncore = event_to_amd_uncore(event);
 223         if (!uncore)
 224                 return -ENODEV;
 225
 226         /*
 227          * since request can come in to any of the shared cores, we will remap
 228          * to a single common cpu.
 229          */
 230         event->cpu = uncore->cpu;
 231
 232         return 0;
 233 }
 234
 235 static ssize_t amd_uncore_attr_show_cpumask(struct device *dev,
 236                                             struct device_attribute *attr,
 237                                             char *buf)
 238 {
 239         cpumask_t *active_mask;
 240         struct pmu *pmu = dev_get_drvdata(dev);
 241
 242         if (pmu->type == amd_nb_pmu.type)
 243                 active_mask = &amd_nb_active_mask;
 244         else if (pmu->type == amd_llc_pmu.type)
 245                 active_mask = &amd_llc_active_mask;
 246         else
 247                 return 0;
 248
 249         return cpumap_print_to_pagebuf(true, buf, active_mask);
 250 }
 251 static DEVICE_ATTR(cpumask, S_IRUGO, amd_uncore_attr_show_cpumask, NULL);
 252
 253 static struct attribute *amd_uncore_attrs[] = {
 254         &dev_attr_cpumask.attr,
 255         NULL,
 256 };
 257
 258 static struct attribute_group amd_uncore_attr_group = {
 259         .attrs = amd_uncore_attrs,
 260 };
 261
 262 /*
 263  * Similar to PMU_FORMAT_ATTR but allowing for format_attr to be assigned based
 264  * on family
 265  */
 266 #define AMD_FORMAT_ATTR(_dev, _name, _format)                                \
 267 static ssize_t                                                               \
 268 _dev##_show##_name(struct device *dev,                                       \
 269                 struct device_attribute *attr,                               \
 270                 char *page)                                                  \
 271 {                                                                            \
 272         BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE);                          \
 273         return sprintf(page, _format "\n");                                  \
 274 }                                                                            \
 275 static struct device_attribute format_attr_##_dev##_name = __ATTR_RO(_dev);
 276
 277 /* Used for each uncore counter type */
 278 #define AMD_ATTRIBUTE(_name)                                                 \
 279 static struct attribute *amd_uncore_format_attr_##_name[] = {                \
 280         &format_attr_event_##_name.attr,                                     \
 281         &format_attr_umask.attr,                                             \
 282         NULL,                                                                \
 283 };                                                                           \
 284 static struct attribute_group amd_uncore_format_group_##_name = {            \
 285         .name = "format",                                                    \
 286         .attrs = amd_uncore_format_attr_##_name,                             \
 287 };                                                                           \
 288 static const struct attribute_group *amd_uncore_attr_groups_##_name[] = {    \
 289         &amd_uncore_attr_group,                                              \
 290         &amd_uncore_format_group_##_name,                                    \
 291         NULL,                                                                \
 292 };
 293
 294 AMD_FORMAT_ATTR(event, , "config:0-7,32-35");
 295 AMD_FORMAT_ATTR(umask, , "config:8-15");
 296 AMD_FORMAT_ATTR(event, _df, "config:0-7,32-35,59-60");
 297 AMD_FORMAT_ATTR(event, _l3, "config:0-7");
 298 AMD_ATTRIBUTE(df);
 299 AMD_ATTRIBUTE(l3);
 300
 301 static struct pmu amd_nb_pmu = {
 302         .task_ctx_nr    = perf_invalid_context,
 303         .event_init     = amd_uncore_event_init,
 304         .add            = amd_uncore_add,
 305         .del            = amd_uncore_del,
 306         .start          = amd_uncore_start,
 307         .stop           = amd_uncore_stop,
 308         .read           = amd_uncore_read,
 309 };
 310
 311 static struct pmu amd_llc_pmu = {
 312         .task_ctx_nr    = perf_invalid_context,
 313         .event_init     = amd_uncore_event_init,
 314         .add            = amd_uncore_add,
 315         .del            = amd_uncore_del,
 316         .start          = amd_uncore_start,
 317         .stop           = amd_uncore_stop,
 318         .read           = amd_uncore_read,
 319 };
 320
 321 static struct amd_uncore *amd_uncore_alloc(unsigned int cpu)
 322 {
 323         return kzalloc_node(sizeof(struct amd_uncore), GFP_KERNEL,
 324                         cpu_to_node(cpu));
 325 }
 326
 327 static int amd_uncore_cpu_up_prepare(unsigned int cpu)
 328 {
 329         struct amd_uncore *uncore_nb = NULL, *uncore_llc;
 330
 331         if (amd_uncore_nb) {
 332                 uncore_nb = amd_uncore_alloc(cpu);
 333                 if (!uncore_nb)
 334                         goto fail;
 335                 uncore_nb->cpu = cpu;
 336                 uncore_nb->num_counters = num_counters_nb;
 337                 uncore_nb->rdpmc_base = RDPMC_BASE_NB;
 338                 uncore_nb->msr_base = MSR_F15H_NB_PERF_CTL;
 339                 uncore_nb->active_mask = &amd_nb_active_mask;
 340                 uncore_nb->pmu = &amd_nb_pmu;
 341                 uncore_nb->id = -1;
 342                 *per_cpu_ptr(amd_uncore_nb, cpu) = uncore_nb;
 343         }
 344
 345         if (amd_uncore_llc) {
 346                 uncore_llc = amd_uncore_alloc(cpu);
 347                 if (!uncore_llc)
 348                         goto fail;
 349                 uncore_llc->cpu = cpu;
 350                 uncore_llc->num_counters = num_counters_llc;
 351                 uncore_llc->rdpmc_base = RDPMC_BASE_LLC;
 352                 uncore_llc->msr_base = MSR_F16H_L2I_PERF_CTL;
 353                 uncore_llc->active_mask = &amd_llc_active_mask;
 354                 uncore_llc->pmu = &amd_llc_pmu;
 355                 uncore_llc->id = -1;
 356                 *per_cpu_ptr(amd_uncore_llc, cpu) = uncore_llc;
 357         }
 358
 359         return 0;
 360
 361 fail:
 362         if (amd_uncore_nb)
 363                 *per_cpu_ptr(amd_uncore_nb, cpu) = NULL;
 364         kfree(uncore_nb);
 365         return -ENOMEM;
 366 }
 367
 368 static struct amd_uncore *
 369 amd_uncore_find_online_sibling(struct amd_uncore *this,
 370                                struct amd_uncore * __percpu *uncores)
 371 {
 372         unsigned int cpu;
 373         struct amd_uncore *that;
 374
 375         for_each_online_cpu(cpu) {
 376                 that = *per_cpu_ptr(uncores, cpu);
 377
 378                 if (!that)
 379                         continue;
 380
 381                 if (this == that)
 382                         continue;
 383
 384                 if (this->id == that->id) {
 385                         hlist_add_head(&this->node, &uncore_unused_list);
 386                         this = that;
 387                         break;
 388                 }
 389         }
 390
 391         this->refcnt++;
 392         return this;
 393 }
 394
 395 static int amd_uncore_cpu_starting(unsigned int cpu)
 396 {
 397         unsigned int eax, ebx, ecx, edx;
 398         struct amd_uncore *uncore;
 399
 400         if (amd_uncore_nb) {
 401                 uncore = *per_cpu_ptr(amd_uncore_nb, cpu);
 402                 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
 403                 uncore->id = ecx & 0xff;
 404
 405                 uncore = amd_uncore_find_online_sibling(uncore, amd_uncore_nb);
 406                 *per_cpu_ptr(amd_uncore_nb, cpu) = uncore;
 407         }
 408
 409         if (amd_uncore_llc) {
 410                 unsigned int apicid = cpu_data(cpu).apicid;
 411                 unsigned int nshared, subleaf, prev_eax = 0;
 412
 413                 uncore = *per_cpu_ptr(amd_uncore_llc, cpu);
 414                 /*
 415                  * Iterate over Cache Topology Definition leaves until no
 416                  * more cache descriptions are available.
 417                  */
 418                 for (subleaf = 0; subleaf < 5; subleaf++) {
 419                         cpuid_count(0x8000001d, subleaf, &eax, &ebx, &ecx, &edx);
 420
 421                         /* EAX[0:4] gives type of cache */
 422                         if (!(eax & 0x1f))
 423                                 break;
 424
 425                         prev_eax = eax;
 426                 }
 427                 nshared = ((prev_eax >> 14) & 0xfff) + 1;
 428
 429                 uncore->id = apicid - (apicid % nshared);
 430
 431                 uncore = amd_uncore_find_online_sibling(uncore, amd_uncore_llc);
 432                 *per_cpu_ptr(amd_uncore_llc, cpu) = uncore;
 433         }
 434
 435         return 0;
 436 }
 437
 438 static void uncore_clean_online(void)
 439 {
 440         struct amd_uncore *uncore;
 441         struct hlist_node *n;
 442
 443         hlist_for_each_entry_safe(uncore, n, &uncore_unused_list, node) {
 444                 hlist_del(&uncore->node);
 445                 kfree(uncore);
 446         }
 447 }
 448
 449 static void uncore_online(unsigned int cpu,
 450                           struct amd_uncore * __percpu *uncores)
 451 {
 452         struct amd_uncore *uncore = *per_cpu_ptr(uncores, cpu);
 453
 454         uncore_clean_online();
 455
 456         if (cpu == uncore->cpu)
 457                 cpumask_set_cpu(cpu, uncore->active_mask);
 458 }
 459
 460 static int amd_uncore_cpu_online(unsigned int cpu)
 461 {
 462         if (amd_uncore_nb)
 463                 uncore_online(cpu, amd_uncore_nb);
 464
 465         if (amd_uncore_llc)
 466                 uncore_online(cpu, amd_uncore_llc);
 467
 468         return 0;
 469 }
 470
 471 static void uncore_down_prepare(unsigned int cpu,
 472                                 struct amd_uncore * __percpu *uncores)
 473 {
 474         unsigned int i;
 475         struct amd_uncore *this = *per_cpu_ptr(uncores, cpu);
 476
 477         if (this->cpu != cpu)
 478                 return;
 479
 480         /* this cpu is going down, migrate to a shared sibling if possible */
 481         for_each_online_cpu(i) {
 482                 struct amd_uncore *that = *per_cpu_ptr(uncores, i);
 483
 484                 if (cpu == i)
 485                         continue;
 486
 487                 if (this == that) {
 488                         perf_pmu_migrate_context(this->pmu, cpu, i);
 489                         cpumask_clear_cpu(cpu, that->active_mask);
 490                         cpumask_set_cpu(i, that->active_mask);
 491                         that->cpu = i;
 492                         break;
 493                 }
 494         }
 495 }
 496
 497 static int amd_uncore_cpu_down_prepare(unsigned int cpu)
 498 {
 499         if (amd_uncore_nb)
 500                 uncore_down_prepare(cpu, amd_uncore_nb);
 501
 502         if (amd_uncore_llc)
 503                 uncore_down_prepare(cpu, amd_uncore_llc);
 504
 505         return 0;
 506 }
 507
 508 static void uncore_dead(unsigned int cpu, struct amd_uncore * __percpu *uncores)
 509 {
 510         struct amd_uncore *uncore = *per_cpu_ptr(uncores, cpu);
 511
 512         if (cpu == uncore->cpu)
 513                 cpumask_clear_cpu(cpu, uncore->active_mask);
 514
 515         if (!--uncore->refcnt)
 516                 kfree(uncore);
 517         *per_cpu_ptr(uncores, cpu) = NULL;
 518 }
 519
 520 static int amd_uncore_cpu_dead(unsigned int cpu)
 521 {
 522         if (amd_uncore_nb)
 523                 uncore_dead(cpu, amd_uncore_nb);
 524
 525         if (amd_uncore_llc)
 526                 uncore_dead(cpu, amd_uncore_llc);
 527
 528         return 0;
 529 }
 530
 531 static int __init amd_uncore_init(void)
 532 {
 533         int ret = -ENODEV;
 534
 535         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
 536                 return -ENODEV;
 537
 538         if (!boot_cpu_has(X86_FEATURE_TOPOEXT))
 539                 return -ENODEV;
 540
 541         if (boot_cpu_data.x86 == 0x17) {
 542                 /*
 543                  * For F17h, the Northbridge counters are repurposed as Data
 544                  * Fabric counters. Also, L3 counters are supported too. The PMUs
 545                  * are exported based on  family as either L2 or L3 and NB or DF.
 546                  */
 547                 num_counters_nb           = NUM_COUNTERS_NB;
 548                 num_counters_llc          = NUM_COUNTERS_L3;
 549                 amd_nb_pmu.name           = "amd_df";
 550                 amd_llc_pmu.name          = "amd_l3";
 551                 format_attr_event_df.show = &event_show_df;
 552                 format_attr_event_l3.show = &event_show_l3;
 553                 l3_mask                   = true;
 554         } else {
 555                 num_counters_nb           = NUM_COUNTERS_NB;
 556                 num_counters_llc          = NUM_COUNTERS_L2;
 557                 amd_nb_pmu.name           = "amd_nb";
 558                 amd_llc_pmu.name          = "amd_l2";
 559                 format_attr_event_df      = format_attr_event;
 560                 format_attr_event_l3      = format_attr_event;
 561                 l3_mask                   = false;
 562         }
 563
 564         amd_nb_pmu.attr_groups  = amd_uncore_attr_groups_df;
 565         amd_llc_pmu.attr_groups = amd_uncore_attr_groups_l3;
 566
 567         if (boot_cpu_has(X86_FEATURE_PERFCTR_NB)) {
 568                 amd_uncore_nb = alloc_percpu(struct amd_uncore *);
 569                 if (!amd_uncore_nb) {
 570                         ret = -ENOMEM;
 571                         goto fail_nb;
 572                 }
 573                 ret = perf_pmu_register(&amd_nb_pmu, amd_nb_pmu.name, -1);
 574                 if (ret)
 575                         goto fail_nb;
 576
 577                 pr_info("AMD NB counters detected\n");
 578                 ret = 0;
 579         }
 580
 581         if (boot_cpu_has(X86_FEATURE_PERFCTR_LLC)) {
 582                 amd_uncore_llc = alloc_percpu(struct amd_uncore *);
 583                 if (!amd_uncore_llc) {
 584                         ret = -ENOMEM;
 585                         goto fail_llc;
 586                 }
 587                 ret = perf_pmu_register(&amd_llc_pmu, amd_llc_pmu.name, -1);
 588                 if (ret)
 589                         goto fail_llc;
 590
 591                 pr_info("AMD LLC counters detected\n");
 592                 ret = 0;
 593         }
 594
 595         /*
 596          * Install callbacks. Core will call them for each online cpu.
 597          */
 598         if (cpuhp_setup_state(CPUHP_PERF_X86_AMD_UNCORE_PREP,
 599                               "perf/x86/amd/uncore:prepare",
 600                               amd_uncore_cpu_up_prepare, amd_uncore_cpu_dead))
 601                 goto fail_llc;
 602
 603         if (cpuhp_setup_state(CPUHP_AP_PERF_X86_AMD_UNCORE_STARTING,
 604                               "perf/x86/amd/uncore:starting",
 605                               amd_uncore_cpu_starting, NULL))
 606                 goto fail_prep;
 607         if (cpuhp_setup_state(CPUHP_AP_PERF_X86_AMD_UNCORE_ONLINE,
 608                               "perf/x86/amd/uncore:online",
 609                               amd_uncore_cpu_online,
 610                               amd_uncore_cpu_down_prepare))
 611                 goto fail_start;
 612         return 0;
 613
 614 fail_start:
 615         cpuhp_remove_state(CPUHP_AP_PERF_X86_AMD_UNCORE_STARTING);
 616 fail_prep:
 617         cpuhp_remove_state(CPUHP_PERF_X86_AMD_UNCORE_PREP);
 618 fail_llc:
 619         if (boot_cpu_has(X86_FEATURE_PERFCTR_NB))
 620                 perf_pmu_unregister(&amd_nb_pmu);
 621         if (amd_uncore_llc)
 622                 free_percpu(amd_uncore_llc);
 623 fail_nb:
 624         if (amd_uncore_nb)
 625                 free_percpu(amd_uncore_nb);
 626
 627         return ret;
 628 }
 629 device_initcall(amd_uncore_init);