2 * Copyright (C) 1995 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * Gareth Hughes <gareth@valinux.com>, May 2000
9 * This file handles the architecture-dependent parts of process handling..
12 #include <linux/cpu.h>
13 #include <linux/errno.h>
14 #include <linux/sched.h>
15 #include <linux/sched/task.h>
16 #include <linux/sched/task_stack.h>
18 #include <linux/kernel.h>
20 #include <linux/elfcore.h>
21 #include <linux/smp.h>
22 #include <linux/stddef.h>
23 #include <linux/slab.h>
24 #include <linux/vmalloc.h>
25 #include <linux/user.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
28 #include <linux/reboot.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/export.h>
31 #include <linux/kallsyms.h>
32 #include <linux/ptrace.h>
33 #include <linux/personality.h>
34 #include <linux/percpu.h>
35 #include <linux/prctl.h>
36 #include <linux/ftrace.h>
37 #include <linux/uaccess.h>
39 #include <linux/kdebug.h>
40 #include <linux/syscalls.h>
42 #include <asm/pgtable.h>
44 #include <asm/processor.h>
45 #include <asm/fpu/internal.h>
47 #ifdef CONFIG_MATH_EMULATION
48 #include <asm/math_emu.h>
51 #include <linux/err.h>
53 #include <asm/tlbflush.h>
55 #include <asm/syscalls.h>
56 #include <asm/debugreg.h>
57 #include <asm/switch_to.h>
59 #include <asm/intel_rdt_sched.h>
60 #include <asm/proto.h>
64 void __show_regs(struct pt_regs
*regs
, int all
)
66 unsigned long cr0
= 0L, cr2
= 0L, cr3
= 0L, cr4
= 0L;
67 unsigned long d0
, d1
, d2
, d3
, d6
, d7
;
69 unsigned short ss
, gs
;
71 if (user_mode(regs
)) {
74 gs
= get_user_gs(regs
);
76 sp
= kernel_stack_pointer(regs
);
81 printk(KERN_DEFAULT
"EIP: %pS\n", (void *)regs
->ip
);
82 printk(KERN_DEFAULT
"EFLAGS: %08lx CPU: %d\n", regs
->flags
,
83 raw_smp_processor_id());
85 printk(KERN_DEFAULT
"EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
86 regs
->ax
, regs
->bx
, regs
->cx
, regs
->dx
);
87 printk(KERN_DEFAULT
"ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
88 regs
->si
, regs
->di
, regs
->bp
, sp
);
89 printk(KERN_DEFAULT
" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
90 (u16
)regs
->ds
, (u16
)regs
->es
, (u16
)regs
->fs
, gs
, ss
);
99 printk(KERN_DEFAULT
"CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
109 /* Only print out debug registers if they are in their non-default state. */
110 if ((d0
== 0) && (d1
== 0) && (d2
== 0) && (d3
== 0) &&
111 (d6
== DR6_RESERVED
) && (d7
== 0x400))
114 printk(KERN_DEFAULT
"DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
116 printk(KERN_DEFAULT
"DR6: %08lx DR7: %08lx\n",
120 void release_thread(struct task_struct
*dead_task
)
122 BUG_ON(dead_task
->mm
);
123 release_vm86_irqs(dead_task
);
126 int copy_thread_tls(unsigned long clone_flags
, unsigned long sp
,
127 unsigned long arg
, struct task_struct
*p
, unsigned long tls
)
129 struct pt_regs
*childregs
= task_pt_regs(p
);
130 struct fork_frame
*fork_frame
= container_of(childregs
, struct fork_frame
, regs
);
131 struct inactive_task_frame
*frame
= &fork_frame
->frame
;
132 struct task_struct
*tsk
;
136 frame
->ret_addr
= (unsigned long) ret_from_fork
;
137 p
->thread
.sp
= (unsigned long) fork_frame
;
138 p
->thread
.sp0
= (unsigned long) (childregs
+1);
139 memset(p
->thread
.ptrace_bps
, 0, sizeof(p
->thread
.ptrace_bps
));
141 if (unlikely(p
->flags
& PF_KTHREAD
)) {
143 memset(childregs
, 0, sizeof(struct pt_regs
));
144 frame
->bx
= sp
; /* function */
146 p
->thread
.io_bitmap_ptr
= NULL
;
150 *childregs
= *current_pt_regs();
155 task_user_gs(p
) = get_user_gs(current_pt_regs());
157 p
->thread
.io_bitmap_ptr
= NULL
;
161 if (unlikely(test_tsk_thread_flag(tsk
, TIF_IO_BITMAP
))) {
162 p
->thread
.io_bitmap_ptr
= kmemdup(tsk
->thread
.io_bitmap_ptr
,
163 IO_BITMAP_BYTES
, GFP_KERNEL
);
164 if (!p
->thread
.io_bitmap_ptr
) {
165 p
->thread
.io_bitmap_max
= 0;
168 set_tsk_thread_flag(p
, TIF_IO_BITMAP
);
174 * Set a new TLS for the child thread?
176 if (clone_flags
& CLONE_SETTLS
)
177 err
= do_set_thread_area(p
, -1,
178 (struct user_desc __user
*)tls
, 0);
180 if (err
&& p
->thread
.io_bitmap_ptr
) {
181 kfree(p
->thread
.io_bitmap_ptr
);
182 p
->thread
.io_bitmap_max
= 0;
188 start_thread(struct pt_regs
*regs
, unsigned long new_ip
, unsigned long new_sp
)
190 set_user_gs(regs
, 0);
192 regs
->ds
= __USER_DS
;
193 regs
->es
= __USER_DS
;
194 regs
->ss
= __USER_DS
;
195 regs
->cs
= __USER_CS
;
198 regs
->flags
= X86_EFLAGS_IF
;
201 EXPORT_SYMBOL_GPL(start_thread
);
205 * switch_to(x,y) should switch tasks from x to y.
207 * We fsave/fwait so that an exception goes off at the right time
208 * (as a call from the fsave or fwait in effect) rather than to
209 * the wrong process. Lazy FP saving no longer makes any sense
210 * with modern CPU's, and this simplifies a lot of things (SMP
211 * and UP become the same).
213 * NOTE! We used to use the x86 hardware context switching. The
214 * reason for not using it any more becomes apparent when you
215 * try to recover gracefully from saved state that is no longer
216 * valid (stale segment register values in particular). With the
217 * hardware task-switch, there is no way to fix up bad state in
218 * a reasonable manner.
220 * The fact that Intel documents the hardware task-switching to
221 * be slow is a fairly red herring - this code is not noticeably
222 * faster. However, there _is_ some room for improvement here,
223 * so the performance issues may eventually be a valid point.
224 * More important, however, is the fact that this allows us much
227 * The return value (in %ax) will be the "prev" task after
228 * the task-switch, and shows up in ret_from_fork in entry.S,
231 __visible __notrace_funcgraph
struct task_struct
*
232 __switch_to(struct task_struct
*prev_p
, struct task_struct
*next_p
)
234 struct thread_struct
*prev
= &prev_p
->thread
,
235 *next
= &next_p
->thread
;
236 struct fpu
*prev_fpu
= &prev
->fpu
;
237 struct fpu
*next_fpu
= &next
->fpu
;
238 int cpu
= smp_processor_id();
240 /* never put a printk in __switch_to... printk() calls wake_up*() indirectly */
242 switch_fpu_prepare(prev_fpu
, cpu
);
245 * Save away %gs. No need to save %fs, as it was saved on the
246 * stack on entry. No need to save %es and %ds, as those are
247 * always kernel segments while inside the kernel. Doing this
248 * before setting the new TLS descriptors avoids the situation
249 * where we temporarily have non-reloadable segments in %fs
250 * and %gs. This could be an issue if the NMI handler ever
251 * used %fs or %gs (it does not today), or if the kernel is
252 * running inside of a hypervisor layer.
254 lazy_save_gs(prev
->gs
);
257 * Load the per-thread Thread-Local Storage descriptor.
262 * Restore IOPL if needed. In normal use, the flags restore
263 * in the switch assembly will handle this. But if the kernel
264 * is running virtualized at a non-zero CPL, the popf will
265 * not restore flags, so it must be done in a separate step.
267 if (get_kernel_rpl() && unlikely(prev
->iopl
!= next
->iopl
))
268 set_iopl_mask(next
->iopl
);
270 switch_to_extra(prev_p
, next_p
);
273 * Leave lazy mode, flushing any hypercalls made here.
274 * This must be done before restoring TLS segments so
275 * the GDT and LDT are properly updated, and must be
276 * done before fpu__restore(), so the TS bit is up
279 arch_end_context_switch(next_p
);
282 * Reload esp0 and cpu_current_top_of_stack. This changes
283 * current_thread_info(). Refresh the SYSENTER configuration in
284 * case prev or next is vm86.
287 refresh_sysenter_cs(next
);
288 this_cpu_write(cpu_current_top_of_stack
,
289 (unsigned long)task_stack_page(next_p
) +
293 * Restore %gs if needed (which is common)
295 if (prev
->gs
| next
->gs
)
296 lazy_load_gs(next
->gs
);
298 switch_fpu_finish(next_fpu
, cpu
);
300 this_cpu_write(current_task
, next_p
);
302 /* Load the Intel cache allocation PQR MSR. */
303 intel_rdt_sched_in();
308 SYSCALL_DEFINE2(arch_prctl
, int, option
, unsigned long, arg2
)
310 return do_arch_prctl_common(current
, option
, arg2
);