drivers/acpi/acpi_lpss.c

   1 /*
   2  * ACPI support for Intel Lynxpoint LPSS.
   3  *
   4  * Copyright (C) 2013, Intel Corporation
   5  * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
   6  *          Rafael J. Wysocki <rafael.j.wysocki@intel.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/acpi.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/clk-provider.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/mutex.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/platform_data/clk-lpss.h>
  21 #include <linux/platform_data/x86/pmc_atom.h>
  22 #include <linux/pm_domain.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/pwm.h>
  25 #include <linux/delay.h>
  26
  27 #include "internal.h"
  28
  29 ACPI_MODULE_NAME("acpi_lpss");
  30
  31 #ifdef CONFIG_X86_INTEL_LPSS
  32
  33 #include <asm/cpu_device_id.h>
  34 #include <asm/intel-family.h>
  35 #include <asm/iosf_mbi.h>
  36
  37 #define LPSS_ADDR(desc) ((unsigned long)&desc)
  38
  39 #define LPSS_CLK_SIZE   0x04
  40 #define LPSS_LTR_SIZE   0x18
  41
  42 /* Offsets relative to LPSS_PRIVATE_OFFSET */
  43 #define LPSS_CLK_DIVIDER_DEF_MASK       (BIT(1) | BIT(16))
  44 #define LPSS_RESETS                     0x04
  45 #define LPSS_RESETS_RESET_FUNC          BIT(0)
  46 #define LPSS_RESETS_RESET_APB           BIT(1)
  47 #define LPSS_GENERAL                    0x08
  48 #define LPSS_GENERAL_LTR_MODE_SW        BIT(2)
  49 #define LPSS_GENERAL_UART_RTS_OVRD      BIT(3)
  50 #define LPSS_SW_LTR                     0x10
  51 #define LPSS_AUTO_LTR                   0x14
  52 #define LPSS_LTR_SNOOP_REQ              BIT(15)
  53 #define LPSS_LTR_SNOOP_MASK             0x0000FFFF
  54 #define LPSS_LTR_SNOOP_LAT_1US          0x800
  55 #define LPSS_LTR_SNOOP_LAT_32US         0xC00
  56 #define LPSS_LTR_SNOOP_LAT_SHIFT        5
  57 #define LPSS_LTR_SNOOP_LAT_CUTOFF       3000
  58 #define LPSS_LTR_MAX_VAL                0x3FF
  59 #define LPSS_TX_INT                     0x20
  60 #define LPSS_TX_INT_MASK                BIT(1)
  61
  62 #define LPSS_PRV_REG_COUNT              9
  63
  64 /* LPSS Flags */
  65 #define LPSS_CLK                        BIT(0)
  66 #define LPSS_CLK_GATE                   BIT(1)
  67 #define LPSS_CLK_DIVIDER                BIT(2)
  68 #define LPSS_LTR                        BIT(3)
  69 #define LPSS_SAVE_CTX                   BIT(4)
  70 #define LPSS_NO_D3_DELAY                BIT(5)
  71
  72 /* Crystal Cove PMIC shares same ACPI ID between different platforms */
  73 #define BYT_CRC_HRV                     2
  74 #define CHT_CRC_HRV                     3
  75
  76 struct lpss_private_data;
  77
  78 struct lpss_device_desc {
  79         unsigned int flags;
  80         const char *clk_con_id;
  81         unsigned int prv_offset;
  82         size_t prv_size_override;
  83         struct property_entry *properties;
  84         void (*setup)(struct lpss_private_data *pdata);
  85 };
  86
  87 static const struct lpss_device_desc lpss_dma_desc = {
  88         .flags = LPSS_CLK,
  89 };
  90
  91 struct lpss_private_data {
  92         struct acpi_device *adev;
  93         void __iomem *mmio_base;
  94         resource_size_t mmio_size;
  95         unsigned int fixed_clk_rate;
  96         struct clk *clk;
  97         const struct lpss_device_desc *dev_desc;
  98         u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
  99 };
 100
 101 /* LPSS run time quirks */
 102 static unsigned int lpss_quirks;
 103
 104 /*
 105  * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device.
 106  *
 107  * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover
 108  * it can be powered off automatically whenever the last LPSS device goes down.
 109  * In case of no power any access to the DMA controller will hang the system.
 110  * The behaviour is reproduced on some HP laptops based on Intel BayTrail as
 111  * well as on ASuS T100TA transformer.
 112  *
 113  * This quirk overrides power state of entire LPSS island to keep DMA powered
 114  * on whenever we have at least one other device in use.
 115  */
 116 #define LPSS_QUIRK_ALWAYS_POWER_ON      BIT(0)
 117
 118 /* UART Component Parameter Register */
 119 #define LPSS_UART_CPR                   0xF4
 120 #define LPSS_UART_CPR_AFCE              BIT(4)
 121
 122 static void lpss_uart_setup(struct lpss_private_data *pdata)
 123 {
 124         unsigned int offset;
 125         u32 val;
 126
 127         offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
 128         val = readl(pdata->mmio_base + offset);
 129         writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
 130
 131         val = readl(pdata->mmio_base + LPSS_UART_CPR);
 132         if (!(val & LPSS_UART_CPR_AFCE)) {
 133                 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
 134                 val = readl(pdata->mmio_base + offset);
 135                 val |= LPSS_GENERAL_UART_RTS_OVRD;
 136                 writel(val, pdata->mmio_base + offset);
 137         }
 138 }
 139
 140 static void lpss_deassert_reset(struct lpss_private_data *pdata)
 141 {
 142         unsigned int offset;
 143         u32 val;
 144
 145         offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
 146         val = readl(pdata->mmio_base + offset);
 147         val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
 148         writel(val, pdata->mmio_base + offset);
 149 }
 150
 151 /*
 152  * BYT PWM used for backlight control by the i915 driver on systems without
 153  * the Crystal Cove PMIC.
 154  */
 155 static struct pwm_lookup byt_pwm_lookup[] = {
 156         PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0",
 157                                "pwm_backlight", 0, PWM_POLARITY_NORMAL,
 158                                "pwm-lpss-platform"),
 159 };
 160
 161 static void byt_pwm_setup(struct lpss_private_data *pdata)
 162 {
 163         struct acpi_device *adev = pdata->adev;
 164
 165         /* Only call pwm_add_table for the first PWM controller */
 166         if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
 167                 return;
 168
 169         if (!acpi_dev_present("INT33FD", NULL, BYT_CRC_HRV))
 170                 pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));
 171 }
 172
 173 #define LPSS_I2C_ENABLE                 0x6c
 174
 175 static void byt_i2c_setup(struct lpss_private_data *pdata)
 176 {
 177         lpss_deassert_reset(pdata);
 178
 179         if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
 180                 pdata->fixed_clk_rate = 133000000;
 181
 182         writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);
 183 }
 184
 185 /* BSW PWM used for backlight control by the i915 driver */
 186 static struct pwm_lookup bsw_pwm_lookup[] = {
 187         PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0",
 188                                "pwm_backlight", 0, PWM_POLARITY_NORMAL,
 189                                "pwm-lpss-platform"),
 190 };
 191
 192 static void bsw_pwm_setup(struct lpss_private_data *pdata)
 193 {
 194         struct acpi_device *adev = pdata->adev;
 195
 196         /* Only call pwm_add_table for the first PWM controller */
 197         if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
 198                 return;
 199
 200         pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup));
 201 }
 202
 203 static const struct lpss_device_desc lpt_dev_desc = {
 204         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
 205         .prv_offset = 0x800,
 206 };
 207
 208 static const struct lpss_device_desc lpt_i2c_dev_desc = {
 209         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR,
 210         .prv_offset = 0x800,
 211 };
 212
 213 static struct property_entry uart_properties[] = {
 214         PROPERTY_ENTRY_U32("reg-io-width", 4),
 215         PROPERTY_ENTRY_U32("reg-shift", 2),
 216         PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
 217         { },
 218 };
 219
 220 static const struct lpss_device_desc lpt_uart_dev_desc = {
 221         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
 222         .clk_con_id = "baudclk",
 223         .prv_offset = 0x800,
 224         .setup = lpss_uart_setup,
 225         .properties = uart_properties,
 226 };
 227
 228 static const struct lpss_device_desc lpt_sdio_dev_desc = {
 229         .flags = LPSS_LTR,
 230         .prv_offset = 0x1000,
 231         .prv_size_override = 0x1018,
 232 };
 233
 234 static const struct lpss_device_desc byt_pwm_dev_desc = {
 235         .flags = LPSS_SAVE_CTX,
 236         .prv_offset = 0x800,
 237         .setup = byt_pwm_setup,
 238 };
 239
 240 static const struct lpss_device_desc bsw_pwm_dev_desc = {
 241         .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
 242         .prv_offset = 0x800,
 243         .setup = bsw_pwm_setup,
 244 };
 245
 246 static const struct lpss_device_desc byt_uart_dev_desc = {
 247         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
 248         .clk_con_id = "baudclk",
 249         .prv_offset = 0x800,
 250         .setup = lpss_uart_setup,
 251         .properties = uart_properties,
 252 };
 253
 254 static const struct lpss_device_desc bsw_uart_dev_desc = {
 255         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
 256                         | LPSS_NO_D3_DELAY,
 257         .clk_con_id = "baudclk",
 258         .prv_offset = 0x800,
 259         .setup = lpss_uart_setup,
 260         .properties = uart_properties,
 261 };
 262
 263 static const struct lpss_device_desc byt_spi_dev_desc = {
 264         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
 265         .prv_offset = 0x400,
 266 };
 267
 268 static const struct lpss_device_desc byt_sdio_dev_desc = {
 269         .flags = LPSS_CLK,
 270 };
 271
 272 static const struct lpss_device_desc byt_i2c_dev_desc = {
 273         .flags = LPSS_CLK | LPSS_SAVE_CTX,
 274         .prv_offset = 0x800,
 275         .setup = byt_i2c_setup,
 276 };
 277
 278 static const struct lpss_device_desc bsw_i2c_dev_desc = {
 279         .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
 280         .prv_offset = 0x800,
 281         .setup = byt_i2c_setup,
 282 };
 283
 284 static const struct lpss_device_desc bsw_spi_dev_desc = {
 285         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
 286                         | LPSS_NO_D3_DELAY,
 287         .prv_offset = 0x400,
 288         .setup = lpss_deassert_reset,
 289 };
 290
 291 #define ICPU(model)     { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, }
 292
 293 static const struct x86_cpu_id lpss_cpu_ids[] = {
 294         ICPU(INTEL_FAM6_ATOM_SILVERMONT),       /* Valleyview, Bay Trail */
 295         ICPU(INTEL_FAM6_ATOM_AIRMONT),  /* Braswell, Cherry Trail */
 296         {}
 297 };
 298
 299 #else
 300
 301 #define LPSS_ADDR(desc) (0UL)
 302
 303 #endif /* CONFIG_X86_INTEL_LPSS */
 304
 305 static const struct acpi_device_id acpi_lpss_device_ids[] = {
 306         /* Generic LPSS devices */
 307         { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
 308
 309         /* Lynxpoint LPSS devices */
 310         { "INT33C0", LPSS_ADDR(lpt_dev_desc) },
 311         { "INT33C1", LPSS_ADDR(lpt_dev_desc) },
 312         { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
 313         { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
 314         { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
 315         { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
 316         { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
 317         { "INT33C7", },
 318
 319         /* BayTrail LPSS devices */
 320         { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
 321         { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
 322         { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
 323         { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
 324         { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
 325         { "INT33B2", },
 326         { "INT33FC", },
 327
 328         /* Braswell LPSS devices */
 329         { "80862286", LPSS_ADDR(lpss_dma_desc) },
 330         { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
 331         { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) },
 332         { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },
 333         { "808622C0", LPSS_ADDR(lpss_dma_desc) },
 334         { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) },
 335
 336         /* Broadwell LPSS devices */
 337         { "INT3430", LPSS_ADDR(lpt_dev_desc) },
 338         { "INT3431", LPSS_ADDR(lpt_dev_desc) },
 339         { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
 340         { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
 341         { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
 342         { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
 343         { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
 344         { "INT3437", },
 345
 346         /* Wildcat Point LPSS devices */
 347         { "INT3438", LPSS_ADDR(lpt_dev_desc) },
 348
 349         { }
 350 };
 351
 352 #ifdef CONFIG_X86_INTEL_LPSS
 353
 354 static int is_memory(struct acpi_resource *res, void *not_used)
 355 {
 356         struct resource r;
 357         return !acpi_dev_resource_memory(res, &r);
 358 }
 359
 360 /* LPSS main clock device. */
 361 static struct platform_device *lpss_clk_dev;
 362
 363 static inline void lpt_register_clock_device(void)
 364 {
 365         lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0);
 366 }
 367
 368 static int register_device_clock(struct acpi_device *adev,
 369                                  struct lpss_private_data *pdata)
 370 {
 371         const struct lpss_device_desc *dev_desc = pdata->dev_desc;
 372         const char *devname = dev_name(&adev->dev);
 373         struct clk *clk = ERR_PTR(-ENODEV);
 374         struct lpss_clk_data *clk_data;
 375         const char *parent, *clk_name;
 376         void __iomem *prv_base;
 377
 378         if (!lpss_clk_dev)
 379                 lpt_register_clock_device();
 380
 381         clk_data = platform_get_drvdata(lpss_clk_dev);
 382         if (!clk_data)
 383                 return -ENODEV;
 384         clk = clk_data->clk;
 385
 386         if (!pdata->mmio_base
 387             || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
 388                 return -ENODATA;
 389
 390         parent = clk_data->name;
 391         prv_base = pdata->mmio_base + dev_desc->prv_offset;
 392
 393         if (pdata->fixed_clk_rate) {
 394                 clk = clk_register_fixed_rate(NULL, devname, parent, 0,
 395                                               pdata->fixed_clk_rate);
 396                 goto out;
 397         }
 398
 399         if (dev_desc->flags & LPSS_CLK_GATE) {
 400                 clk = clk_register_gate(NULL, devname, parent, 0,
 401                                         prv_base, 0, 0, NULL);
 402                 parent = devname;
 403         }
 404
 405         if (dev_desc->flags & LPSS_CLK_DIVIDER) {
 406                 /* Prevent division by zero */
 407                 if (!readl(prv_base))
 408                         writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
 409
 410                 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
 411                 if (!clk_name)
 412                         return -ENOMEM;
 413                 clk = clk_register_fractional_divider(NULL, clk_name, parent,
 414                                                       0, prv_base,
 415                                                       1, 15, 16, 15, 0, NULL);
 416                 parent = clk_name;
 417
 418                 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
 419                 if (!clk_name) {
 420                         kfree(parent);
 421                         return -ENOMEM;
 422                 }
 423                 clk = clk_register_gate(NULL, clk_name, parent,
 424                                         CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
 425                                         prv_base, 31, 0, NULL);
 426                 kfree(parent);
 427                 kfree(clk_name);
 428         }
 429 out:
 430         if (IS_ERR(clk))
 431                 return PTR_ERR(clk);
 432
 433         pdata->clk = clk;
 434         clk_register_clkdev(clk, dev_desc->clk_con_id, devname);
 435         return 0;
 436 }
 437
 438 static int acpi_lpss_create_device(struct acpi_device *adev,
 439                                    const struct acpi_device_id *id)
 440 {
 441         const struct lpss_device_desc *dev_desc;
 442         struct lpss_private_data *pdata;
 443         struct resource_entry *rentry;
 444         struct list_head resource_list;
 445         struct platform_device *pdev;
 446         int ret;
 447
 448         dev_desc = (const struct lpss_device_desc *)id->driver_data;
 449         if (!dev_desc) {
 450                 pdev = acpi_create_platform_device(adev, NULL);
 451                 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
 452         }
 453         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
 454         if (!pdata)
 455                 return -ENOMEM;
 456
 457         INIT_LIST_HEAD(&resource_list);
 458         ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
 459         if (ret < 0)
 460                 goto err_out;
 461
 462         list_for_each_entry(rentry, &resource_list, node)
 463                 if (resource_type(rentry->res) == IORESOURCE_MEM) {
 464                         if (dev_desc->prv_size_override)
 465                                 pdata->mmio_size = dev_desc->prv_size_override;
 466                         else
 467                                 pdata->mmio_size = resource_size(rentry->res);
 468                         pdata->mmio_base = ioremap(rentry->res->start,
 469                                                    pdata->mmio_size);
 470                         break;
 471                 }
 472
 473         acpi_dev_free_resource_list(&resource_list);
 474
 475         if (!pdata->mmio_base) {
 476                 /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */
 477                 adev->pnp.type.platform_id = 0;
 478                 /* Skip the device, but continue the namespace scan. */
 479                 ret = 0;
 480                 goto err_out;
 481         }
 482
 483         pdata->adev = adev;
 484         pdata->dev_desc = dev_desc;
 485
 486         if (dev_desc->setup)
 487                 dev_desc->setup(pdata);
 488
 489         if (dev_desc->flags & LPSS_CLK) {
 490                 ret = register_device_clock(adev, pdata);
 491                 if (ret) {
 492                         /* Skip the device, but continue the namespace scan. */
 493                         ret = 0;
 494                         goto err_out;
 495                 }
 496         }
 497
 498         /*
 499          * This works around a known issue in ACPI tables where LPSS devices
 500          * have _PS0 and _PS3 without _PSC (and no power resources), so
 501          * acpi_bus_init_power() will assume that the BIOS has put them into D0.
 502          */
 503         ret = acpi_device_fix_up_power(adev);
 504         if (ret) {
 505                 /* Skip the device, but continue the namespace scan. */
 506                 ret = 0;
 507                 goto err_out;
 508         }
 509
 510         adev->driver_data = pdata;
 511         pdev = acpi_create_platform_device(adev, dev_desc->properties);
 512         if (!IS_ERR_OR_NULL(pdev)) {
 513                 return 1;
 514         }
 515
 516         ret = PTR_ERR(pdev);
 517         adev->driver_data = NULL;
 518
 519  err_out:
 520         kfree(pdata);
 521         return ret;
 522 }
 523
 524 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
 525 {
 526         return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
 527 }
 528
 529 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
 530                              unsigned int reg)
 531 {
 532         writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
 533 }
 534
 535 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
 536 {
 537         struct acpi_device *adev;
 538         struct lpss_private_data *pdata;
 539         unsigned long flags;
 540         int ret;
 541
 542         ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
 543         if (WARN_ON(ret))
 544                 return ret;
 545
 546         spin_lock_irqsave(&dev->power.lock, flags);
 547         if (pm_runtime_suspended(dev)) {
 548                 ret = -EAGAIN;
 549                 goto out;
 550         }
 551         pdata = acpi_driver_data(adev);
 552         if (WARN_ON(!pdata || !pdata->mmio_base)) {
 553                 ret = -ENODEV;
 554                 goto out;
 555         }
 556         *val = __lpss_reg_read(pdata, reg);
 557
 558  out:
 559         spin_unlock_irqrestore(&dev->power.lock, flags);
 560         return ret;
 561 }
 562
 563 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
 564                              char *buf)
 565 {
 566         u32 ltr_value = 0;
 567         unsigned int reg;
 568         int ret;
 569
 570         reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
 571         ret = lpss_reg_read(dev, reg, &ltr_value);
 572         if (ret)
 573                 return ret;
 574
 575         return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value);
 576 }
 577
 578 static ssize_t lpss_ltr_mode_show(struct device *dev,
 579                                   struct device_attribute *attr, char *buf)
 580 {
 581         u32 ltr_mode = 0;
 582         char *outstr;
 583         int ret;
 584
 585         ret = lpss_reg_read(dev, LPSS_GENERAL, &ltr_mode);
 586         if (ret)
 587                 return ret;
 588
 589         outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
 590         return sprintf(buf, "%s\n", outstr);
 591 }
 592
 593 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
 594 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
 595 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
 596
 597 static struct attribute *lpss_attrs[] = {
 598         &dev_attr_auto_ltr.attr,
 599         &dev_attr_sw_ltr.attr,
 600         &dev_attr_ltr_mode.attr,
 601         NULL,
 602 };
 603
 604 static const struct attribute_group lpss_attr_group = {
 605         .attrs = lpss_attrs,
 606         .name = "lpss_ltr",
 607 };
 608
 609 static void acpi_lpss_set_ltr(struct device *dev, s32 val)
 610 {
 611         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 612         u32 ltr_mode, ltr_val;
 613
 614         ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
 615         if (val < 0) {
 616                 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
 617                         ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
 618                         __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
 619                 }
 620                 return;
 621         }
 622         ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
 623         if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
 624                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
 625                 val = LPSS_LTR_MAX_VAL;
 626         } else if (val > LPSS_LTR_MAX_VAL) {
 627                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
 628                 val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
 629         } else {
 630                 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
 631         }
 632         ltr_val |= val;
 633         __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
 634         if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
 635                 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
 636                 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
 637         }
 638 }
 639
 640 #ifdef CONFIG_PM
 641 /**
 642  * acpi_lpss_save_ctx() - Save the private registers of LPSS device
 643  * @dev: LPSS device
 644  * @pdata: pointer to the private data of the LPSS device
 645  *
 646  * Most LPSS devices have private registers which may loose their context when
 647  * the device is powered down. acpi_lpss_save_ctx() saves those registers into
 648  * prv_reg_ctx array.
 649  */
 650 static void acpi_lpss_save_ctx(struct device *dev,
 651                                struct lpss_private_data *pdata)
 652 {
 653         unsigned int i;
 654
 655         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
 656                 unsigned long offset = i * sizeof(u32);
 657
 658                 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
 659                 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
 660                         pdata->prv_reg_ctx[i], offset);
 661         }
 662 }
 663
 664 /**
 665  * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
 666  * @dev: LPSS device
 667  * @pdata: pointer to the private data of the LPSS device
 668  *
 669  * Restores the registers that were previously stored with acpi_lpss_save_ctx().
 670  */
 671 static void acpi_lpss_restore_ctx(struct device *dev,
 672                                   struct lpss_private_data *pdata)
 673 {
 674         unsigned int i;
 675
 676         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
 677                 unsigned long offset = i * sizeof(u32);
 678
 679                 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
 680                 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
 681                         pdata->prv_reg_ctx[i], offset);
 682         }
 683 }
 684
 685 static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata)
 686 {
 687         /*
 688          * The following delay is needed or the subsequent write operations may
 689          * fail. The LPSS devices are actually PCI devices and the PCI spec
 690          * expects 10ms delay before the device can be accessed after D3 to D0
 691          * transition. However some platforms like BSW does not need this delay.
 692          */
 693         unsigned int delay = 10;        /* default 10ms delay */
 694
 695         if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY)
 696                 delay = 0;
 697
 698         msleep(delay);
 699 }
 700
 701 static int acpi_lpss_activate(struct device *dev)
 702 {
 703         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 704         int ret;
 705
 706         ret = acpi_dev_runtime_resume(dev);
 707         if (ret)
 708                 return ret;
 709
 710         acpi_lpss_d3_to_d0_delay(pdata);
 711
 712         /*
 713          * This is called only on ->probe() stage where a device is either in
 714          * known state defined by BIOS or most likely powered off. Due to this
 715          * we have to deassert reset line to be sure that ->probe() will
 716          * recognize the device.
 717          */
 718         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 719                 lpss_deassert_reset(pdata);
 720
 721         return 0;
 722 }
 723
 724 static void acpi_lpss_dismiss(struct device *dev)
 725 {
 726         acpi_dev_runtime_suspend(dev);
 727 }
 728
 729 #ifdef CONFIG_PM_SLEEP
 730 static int acpi_lpss_suspend_late(struct device *dev)
 731 {
 732         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 733         int ret;
 734
 735         ret = pm_generic_suspend_late(dev);
 736         if (ret)
 737                 return ret;
 738
 739         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 740                 acpi_lpss_save_ctx(dev, pdata);
 741
 742         return acpi_dev_suspend_late(dev);
 743 }
 744
 745 static int acpi_lpss_resume_early(struct device *dev)
 746 {
 747         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 748         int ret;
 749
 750         ret = acpi_dev_resume_early(dev);
 751         if (ret)
 752                 return ret;
 753
 754         acpi_lpss_d3_to_d0_delay(pdata);
 755
 756         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 757                 acpi_lpss_restore_ctx(dev, pdata);
 758
 759         return pm_generic_resume_early(dev);
 760 }
 761 #endif /* CONFIG_PM_SLEEP */
 762
 763 /* IOSF SB for LPSS island */
 764 #define LPSS_IOSF_UNIT_LPIOEP           0xA0
 765 #define LPSS_IOSF_UNIT_LPIO1            0xAB
 766 #define LPSS_IOSF_UNIT_LPIO2            0xAC
 767
 768 #define LPSS_IOSF_PMCSR                 0x84
 769 #define LPSS_PMCSR_D0                   0
 770 #define LPSS_PMCSR_D3hot                3
 771 #define LPSS_PMCSR_Dx_MASK              GENMASK(1, 0)
 772
 773 #define LPSS_IOSF_GPIODEF0              0x154
 774 #define LPSS_GPIODEF0_DMA1_D3           BIT(2)
 775 #define LPSS_GPIODEF0_DMA2_D3           BIT(3)
 776 #define LPSS_GPIODEF0_DMA_D3_MASK       GENMASK(3, 2)
 777 #define LPSS_GPIODEF0_DMA_LLP           BIT(13)
 778
 779 static DEFINE_MUTEX(lpss_iosf_mutex);
 780
 781 static void lpss_iosf_enter_d3_state(void)
 782 {
 783         u32 value1 = 0;
 784         u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
 785         u32 value2 = LPSS_PMCSR_D3hot;
 786         u32 mask2 = LPSS_PMCSR_Dx_MASK;
 787         /*
 788          * PMC provides an information about actual status of the LPSS devices.
 789          * Here we read the values related to LPSS power island, i.e. LPSS
 790          * devices, excluding both LPSS DMA controllers, along with SCC domain.
 791          */
 792         u32 func_dis, d3_sts_0, pmc_status, pmc_mask = 0xfe000ffe;
 793         int ret;
 794
 795         ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis);
 796         if (ret)
 797                 return;
 798
 799         mutex_lock(&lpss_iosf_mutex);
 800
 801         ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0);
 802         if (ret)
 803                 goto exit;
 804
 805         /*
 806          * Get the status of entire LPSS power island per device basis.
 807          * Shutdown both LPSS DMA controllers if and only if all other devices
 808          * are already in D3hot.
 809          */
 810         pmc_status = (~(d3_sts_0 | func_dis)) & pmc_mask;
 811         if (pmc_status)
 812                 goto exit;
 813
 814         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
 815                         LPSS_IOSF_PMCSR, value2, mask2);
 816
 817         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
 818                         LPSS_IOSF_PMCSR, value2, mask2);
 819
 820         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
 821                         LPSS_IOSF_GPIODEF0, value1, mask1);
 822 exit:
 823         mutex_unlock(&lpss_iosf_mutex);
 824 }
 825
 826 static void lpss_iosf_exit_d3_state(void)
 827 {
 828         u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 |
 829                      LPSS_GPIODEF0_DMA_LLP;
 830         u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
 831         u32 value2 = LPSS_PMCSR_D0;
 832         u32 mask2 = LPSS_PMCSR_Dx_MASK;
 833
 834         mutex_lock(&lpss_iosf_mutex);
 835
 836         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
 837                         LPSS_IOSF_GPIODEF0, value1, mask1);
 838
 839         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
 840                         LPSS_IOSF_PMCSR, value2, mask2);
 841
 842         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
 843                         LPSS_IOSF_PMCSR, value2, mask2);
 844
 845         mutex_unlock(&lpss_iosf_mutex);
 846 }
 847
 848 static int acpi_lpss_runtime_suspend(struct device *dev)
 849 {
 850         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 851         int ret;
 852
 853         ret = pm_generic_runtime_suspend(dev);
 854         if (ret)
 855                 return ret;
 856
 857         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 858                 acpi_lpss_save_ctx(dev, pdata);
 859
 860         ret = acpi_dev_runtime_suspend(dev);
 861
 862         /*
 863          * This call must be last in the sequence, otherwise PMC will return
 864          * wrong status for devices being about to be powered off. See
 865          * lpss_iosf_enter_d3_state() for further information.
 866          */
 867         if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
 868                 lpss_iosf_enter_d3_state();
 869
 870         return ret;
 871 }
 872
 873 static int acpi_lpss_runtime_resume(struct device *dev)
 874 {
 875         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 876         int ret;
 877
 878         /*
 879          * This call is kept first to be in symmetry with
 880          * acpi_lpss_runtime_suspend() one.
 881          */
 882         if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
 883                 lpss_iosf_exit_d3_state();
 884
 885         ret = acpi_dev_runtime_resume(dev);
 886         if (ret)
 887                 return ret;
 888
 889         acpi_lpss_d3_to_d0_delay(pdata);
 890
 891         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 892                 acpi_lpss_restore_ctx(dev, pdata);
 893
 894         return pm_generic_runtime_resume(dev);
 895 }
 896 #endif /* CONFIG_PM */
 897
 898 static struct dev_pm_domain acpi_lpss_pm_domain = {
 899 #ifdef CONFIG_PM
 900         .activate = acpi_lpss_activate,
 901         .dismiss = acpi_lpss_dismiss,
 902 #endif
 903         .ops = {
 904 #ifdef CONFIG_PM
 905 #ifdef CONFIG_PM_SLEEP
 906                 .prepare = acpi_subsys_prepare,
 907                 .complete = pm_complete_with_resume_check,
 908                 .suspend = acpi_subsys_suspend,
 909                 .suspend_late = acpi_lpss_suspend_late,
 910                 .resume_early = acpi_lpss_resume_early,
 911                 .freeze = acpi_subsys_freeze,
 912                 .poweroff = acpi_subsys_suspend,
 913                 .poweroff_late = acpi_lpss_suspend_late,
 914                 .restore_early = acpi_lpss_resume_early,
 915 #endif
 916                 .runtime_suspend = acpi_lpss_runtime_suspend,
 917                 .runtime_resume = acpi_lpss_runtime_resume,
 918 #endif
 919         },
 920 };
 921
 922 static int acpi_lpss_platform_notify(struct notifier_block *nb,
 923                                      unsigned long action, void *data)
 924 {
 925         struct platform_device *pdev = to_platform_device(data);
 926         struct lpss_private_data *pdata;
 927         struct acpi_device *adev;
 928         const struct acpi_device_id *id;
 929
 930         id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
 931         if (!id || !id->driver_data)
 932                 return 0;
 933
 934         if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
 935                 return 0;
 936
 937         pdata = acpi_driver_data(adev);
 938         if (!pdata)
 939                 return 0;
 940
 941         if (pdata->mmio_base &&
 942             pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
 943                 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
 944                 return 0;
 945         }
 946
 947         switch (action) {
 948         case BUS_NOTIFY_BIND_DRIVER:
 949                 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
 950                 break;
 951         case BUS_NOTIFY_DRIVER_NOT_BOUND:
 952         case BUS_NOTIFY_UNBOUND_DRIVER:
 953                 dev_pm_domain_set(&pdev->dev, NULL);
 954                 break;
 955         case BUS_NOTIFY_ADD_DEVICE:
 956                 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
 957                 if (pdata->dev_desc->flags & LPSS_LTR)
 958                         return sysfs_create_group(&pdev->dev.kobj,
 959                                                   &lpss_attr_group);
 960                 break;
 961         case BUS_NOTIFY_DEL_DEVICE:
 962                 if (pdata->dev_desc->flags & LPSS_LTR)
 963                         sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
 964                 dev_pm_domain_set(&pdev->dev, NULL);
 965                 break;
 966         default:
 967                 break;
 968         }
 969
 970         return 0;
 971 }
 972
 973 static struct notifier_block acpi_lpss_nb = {
 974         .notifier_call = acpi_lpss_platform_notify,
 975 };
 976
 977 static void acpi_lpss_bind(struct device *dev)
 978 {
 979         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 980
 981         if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
 982                 return;
 983
 984         if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
 985                 dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
 986         else
 987                 dev_err(dev, "MMIO size insufficient to access LTR\n");
 988 }
 989
 990 static void acpi_lpss_unbind(struct device *dev)
 991 {
 992         dev->power.set_latency_tolerance = NULL;
 993 }
 994
 995 static struct acpi_scan_handler lpss_handler = {
 996         .ids = acpi_lpss_device_ids,
 997         .attach = acpi_lpss_create_device,
 998         .bind = acpi_lpss_bind,
 999         .unbind = acpi_lpss_unbind,
1000 };
1001
1002 void __init acpi_lpss_init(void)
1003 {
1004         const struct x86_cpu_id *id;
1005         int ret;
1006
1007         ret = lpt_clk_init();
1008         if (ret)
1009                 return;
1010
1011         id = x86_match_cpu(lpss_cpu_ids);
1012         if (id)
1013                 lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON;
1014
1015         bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
1016         acpi_scan_add_handler(&lpss_handler);
1017 }
1018
1019 #else
1020
1021 static struct acpi_scan_handler lpss_handler = {
1022         .ids = acpi_lpss_device_ids,
1023 };
1024
1025 void __init acpi_lpss_init(void)
1026 {
1027         acpi_scan_add_handler(&lpss_handler);
1028 }
1029
1030 #endif /* CONFIG_X86_INTEL_LPSS */