drivers/clk/hisilicon/crg-hi3798cv200.c

   1 /*
   2  * Hi3798CV200 Clock and Reset Generator Driver
   3  *
   4  * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program. If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <dt-bindings/clock/histb-clock.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/module.h>
  23 #include <linux/of_device.h>
  24 #include <linux/platform_device.h>
  25 #include "clk.h"
  26 #include "crg.h"
  27 #include "reset.h"
  28
  29 /* hi3798CV200 core CRG */
  30 #define HI3798CV200_INNER_CLK_OFFSET    64
  31 #define HI3798CV200_FIXED_24M   65
  32 #define HI3798CV200_FIXED_25M   66
  33 #define HI3798CV200_FIXED_50M   67
  34 #define HI3798CV200_FIXED_75M   68
  35 #define HI3798CV200_FIXED_100M  69
  36 #define HI3798CV200_FIXED_150M  70
  37 #define HI3798CV200_FIXED_200M  71
  38 #define HI3798CV200_FIXED_250M  72
  39 #define HI3798CV200_FIXED_300M  73
  40 #define HI3798CV200_FIXED_400M  74
  41 #define HI3798CV200_MMC_MUX     75
  42 #define HI3798CV200_ETH_PUB_CLK 76
  43 #define HI3798CV200_ETH_BUS_CLK 77
  44 #define HI3798CV200_ETH_BUS0_CLK        78
  45 #define HI3798CV200_ETH_BUS1_CLK        79
  46 #define HI3798CV200_COMBPHY1_MUX        80
  47 #define HI3798CV200_FIXED_12M   81
  48 #define HI3798CV200_FIXED_48M   82
  49 #define HI3798CV200_FIXED_60M   83
  50
  51 #define HI3798CV200_CRG_NR_CLKS         128
  52
  53 static const struct hisi_fixed_rate_clock hi3798cv200_fixed_rate_clks[] = {
  54         { HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, },
  55         { HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, },
  56         { HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, },
  57         { HI3798CV200_FIXED_12M, "12m", NULL, 0, 12000000, },
  58         { HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, },
  59         { HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, },
  60         { HI3798CV200_FIXED_48M, "48m", NULL, 0, 48000000, },
  61         { HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, },
  62         { HI3798CV200_FIXED_60M, "60m", NULL, 0, 60000000, },
  63         { HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, },
  64         { HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, },
  65         { HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, },
  66         { HI3798CV200_FIXED_200M, "200m", NULL, 0, 200000000, },
  67         { HI3798CV200_FIXED_250M, "250m", NULL, 0, 250000000, },
  68 };
  69
  70 static const char *const mmc_mux_p[] = {
  71                 "100m", "50m", "25m", "200m", "150m" };
  72 static u32 mmc_mux_table[] = {0, 1, 2, 3, 6};
  73
  74 static const char *const comphy1_mux_p[] = {
  75                 "100m", "25m"};
  76 static u32 comphy1_mux_table[] = {2, 3};
  77
  78 static struct hisi_mux_clock hi3798cv200_mux_clks[] = {
  79         { HI3798CV200_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
  80                 CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, },
  81         { HI3798CV200_COMBPHY1_MUX, "combphy1_mux",
  82                 comphy1_mux_p, ARRAY_SIZE(comphy1_mux_p),
  83                 CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy1_mux_table, },
  84 };
  85
  86 static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
  87         /* UART */
  88         { HISTB_UART2_CLK, "clk_uart2", "75m",
  89                 CLK_SET_RATE_PARENT, 0x68, 4, 0, },
  90         /* I2C */
  91         { HISTB_I2C0_CLK, "clk_i2c0", "clk_apb",
  92                 CLK_SET_RATE_PARENT, 0x6C, 4, 0, },
  93         { HISTB_I2C1_CLK, "clk_i2c1", "clk_apb",
  94                 CLK_SET_RATE_PARENT, 0x6C, 8, 0, },
  95         { HISTB_I2C2_CLK, "clk_i2c2", "clk_apb",
  96                 CLK_SET_RATE_PARENT, 0x6C, 12, 0, },
  97         { HISTB_I2C3_CLK, "clk_i2c3", "clk_apb",
  98                 CLK_SET_RATE_PARENT, 0x6C, 16, 0, },
  99         { HISTB_I2C4_CLK, "clk_i2c4", "clk_apb",
 100                 CLK_SET_RATE_PARENT, 0x6C, 20, 0, },
 101         /* SPI */
 102         { HISTB_SPI0_CLK, "clk_spi0", "clk_apb",
 103                 CLK_SET_RATE_PARENT, 0x70, 0, 0, },
 104         /* SDIO */
 105         { HISTB_SDIO0_BIU_CLK, "clk_sdio0_biu", "200m",
 106                         CLK_SET_RATE_PARENT, 0x9c, 0, 0, },
 107         { HISTB_SDIO0_CIU_CLK, "clk_sdio0_ciu", "mmc_mux",
 108                 CLK_SET_RATE_PARENT, 0x9c, 1, 0, },
 109         /* EMMC */
 110         { HISTB_MMC_BIU_CLK, "clk_mmc_biu", "200m",
 111                 CLK_SET_RATE_PARENT, 0xa0, 0, 0, },
 112         { HISTB_MMC_CIU_CLK, "clk_mmc_ciu", "mmc_mux",
 113                 CLK_SET_RATE_PARENT, 0xa0, 1, 0, },
 114         /* PCIE*/
 115         { HISTB_PCIE_BUS_CLK, "clk_pcie_bus", "200m",
 116                 CLK_SET_RATE_PARENT, 0x18c, 0, 0, },
 117         { HISTB_PCIE_SYS_CLK, "clk_pcie_sys", "100m",
 118                 CLK_SET_RATE_PARENT, 0x18c, 1, 0, },
 119         { HISTB_PCIE_PIPE_CLK, "clk_pcie_pipe", "250m",
 120                 CLK_SET_RATE_PARENT, 0x18c, 2, 0, },
 121         { HISTB_PCIE_AUX_CLK, "clk_pcie_aux", "24m",
 122                 CLK_SET_RATE_PARENT, 0x18c, 3, 0, },
 123         /* Ethernet */
 124         { HI3798CV200_ETH_PUB_CLK, "clk_pub", NULL,
 125                 CLK_SET_RATE_PARENT, 0xcc, 5, 0, },
 126         { HI3798CV200_ETH_BUS_CLK, "clk_bus", "clk_pub",
 127                 CLK_SET_RATE_PARENT, 0xcc, 0, 0, },
 128         { HI3798CV200_ETH_BUS0_CLK, "clk_bus_m0", "clk_bus",
 129                 CLK_SET_RATE_PARENT, 0xcc, 1, 0, },
 130         { HI3798CV200_ETH_BUS1_CLK, "clk_bus_m1", "clk_bus",
 131                 CLK_SET_RATE_PARENT, 0xcc, 2, 0, },
 132         { HISTB_ETH0_MAC_CLK, "clk_mac0", "clk_bus_m0",
 133                 CLK_SET_RATE_PARENT, 0xcc, 3, 0, },
 134         { HISTB_ETH0_MACIF_CLK, "clk_macif0", "clk_bus_m0",
 135                 CLK_SET_RATE_PARENT, 0xcc, 24, 0, },
 136         { HISTB_ETH1_MAC_CLK, "clk_mac1", "clk_bus_m1",
 137                 CLK_SET_RATE_PARENT, 0xcc, 4, 0, },
 138         { HISTB_ETH1_MACIF_CLK, "clk_macif1", "clk_bus_m1",
 139                 CLK_SET_RATE_PARENT, 0xcc, 25, 0, },
 140         /* COMBPHY1 */
 141         { HISTB_COMBPHY1_CLK, "clk_combphy1", "combphy1_mux",
 142                 CLK_SET_RATE_PARENT, 0x188, 8, 0, },
 143         /* USB2 */
 144         { HISTB_USB2_BUS_CLK, "clk_u2_bus", "clk_ahb",
 145                 CLK_SET_RATE_PARENT, 0xb8, 0, 0, },
 146         { HISTB_USB2_PHY_CLK, "clk_u2_phy", "60m",
 147                 CLK_SET_RATE_PARENT, 0xb8, 4, 0, },
 148         { HISTB_USB2_12M_CLK, "clk_u2_12m", "12m",
 149                 CLK_SET_RATE_PARENT, 0xb8, 2, 0 },
 150         { HISTB_USB2_48M_CLK, "clk_u2_48m", "48m",
 151                 CLK_SET_RATE_PARENT, 0xb8, 1, 0 },
 152         { HISTB_USB2_UTMI_CLK, "clk_u2_utmi", "60m",
 153                 CLK_SET_RATE_PARENT, 0xb8, 5, 0 },
 154         { HISTB_USB2_PHY1_REF_CLK, "clk_u2_phy1_ref", "24m",
 155                 CLK_SET_RATE_PARENT, 0xbc, 0, 0 },
 156         { HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m",
 157                 CLK_SET_RATE_PARENT, 0xbc, 2, 0 },
 158 };
 159
 160 static struct hisi_clock_data *hi3798cv200_clk_register(
 161                                 struct platform_device *pdev)
 162 {
 163         struct hisi_clock_data *clk_data;
 164         int ret;
 165
 166         clk_data = hisi_clk_alloc(pdev, HI3798CV200_CRG_NR_CLKS);
 167         if (!clk_data)
 168                 return ERR_PTR(-ENOMEM);
 169
 170         ret = hisi_clk_register_fixed_rate(hi3798cv200_fixed_rate_clks,
 171                                      ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
 172                                      clk_data);
 173         if (ret)
 174                 return ERR_PTR(ret);
 175
 176         ret = hisi_clk_register_mux(hi3798cv200_mux_clks,
 177                                 ARRAY_SIZE(hi3798cv200_mux_clks),
 178                                 clk_data);
 179         if (ret)
 180                 goto unregister_fixed_rate;
 181
 182         ret = hisi_clk_register_gate(hi3798cv200_gate_clks,
 183                                 ARRAY_SIZE(hi3798cv200_gate_clks),
 184                                 clk_data);
 185         if (ret)
 186                 goto unregister_mux;
 187
 188         ret = of_clk_add_provider(pdev->dev.of_node,
 189                         of_clk_src_onecell_get, &clk_data->clk_data);
 190         if (ret)
 191                 goto unregister_gate;
 192
 193         return clk_data;
 194
 195 unregister_fixed_rate:
 196         hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks,
 197                                 ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
 198                                 clk_data);
 199
 200 unregister_mux:
 201         hisi_clk_unregister_mux(hi3798cv200_mux_clks,
 202                                 ARRAY_SIZE(hi3798cv200_mux_clks),
 203                                 clk_data);
 204 unregister_gate:
 205         hisi_clk_unregister_gate(hi3798cv200_gate_clks,
 206                                 ARRAY_SIZE(hi3798cv200_gate_clks),
 207                                 clk_data);
 208         return ERR_PTR(ret);
 209 }
 210
 211 static void hi3798cv200_clk_unregister(struct platform_device *pdev)
 212 {
 213         struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
 214
 215         of_clk_del_provider(pdev->dev.of_node);
 216
 217         hisi_clk_unregister_gate(hi3798cv200_gate_clks,
 218                                 ARRAY_SIZE(hi3798cv200_gate_clks),
 219                                 crg->clk_data);
 220         hisi_clk_unregister_mux(hi3798cv200_mux_clks,
 221                                 ARRAY_SIZE(hi3798cv200_mux_clks),
 222                                 crg->clk_data);
 223         hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks,
 224                                 ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
 225                                 crg->clk_data);
 226 }
 227
 228 static const struct hisi_crg_funcs hi3798cv200_crg_funcs = {
 229         .register_clks = hi3798cv200_clk_register,
 230         .unregister_clks = hi3798cv200_clk_unregister,
 231 };
 232
 233 /* hi3798CV200 sysctrl CRG */
 234
 235 #define HI3798CV200_SYSCTRL_NR_CLKS 16
 236
 237 static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = {
 238         { HISTB_IR_CLK, "clk_ir", "100m",
 239                 CLK_SET_RATE_PARENT, 0x48, 4, 0, },
 240         { HISTB_TIMER01_CLK, "clk_timer01", "24m",
 241                 CLK_SET_RATE_PARENT, 0x48, 6, 0, },
 242         { HISTB_UART0_CLK, "clk_uart0", "75m",
 243                 CLK_SET_RATE_PARENT, 0x48, 10, 0, },
 244 };
 245
 246 static struct hisi_clock_data *hi3798cv200_sysctrl_clk_register(
 247                                         struct platform_device *pdev)
 248 {
 249         struct hisi_clock_data *clk_data;
 250         int ret;
 251
 252         clk_data = hisi_clk_alloc(pdev, HI3798CV200_SYSCTRL_NR_CLKS);
 253         if (!clk_data)
 254                 return ERR_PTR(-ENOMEM);
 255
 256         ret = hisi_clk_register_gate(hi3798cv200_sysctrl_gate_clks,
 257                                 ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
 258                                 clk_data);
 259         if (ret)
 260                 return ERR_PTR(ret);
 261
 262         ret = of_clk_add_provider(pdev->dev.of_node,
 263                         of_clk_src_onecell_get, &clk_data->clk_data);
 264         if (ret)
 265                 goto unregister_gate;
 266
 267         return clk_data;
 268
 269 unregister_gate:
 270         hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks,
 271                                 ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
 272                                 clk_data);
 273         return ERR_PTR(ret);
 274 }
 275
 276 static void hi3798cv200_sysctrl_clk_unregister(struct platform_device *pdev)
 277 {
 278         struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
 279
 280         of_clk_del_provider(pdev->dev.of_node);
 281
 282         hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks,
 283                                 ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
 284                                 crg->clk_data);
 285 }
 286
 287 static const struct hisi_crg_funcs hi3798cv200_sysctrl_funcs = {
 288         .register_clks = hi3798cv200_sysctrl_clk_register,
 289         .unregister_clks = hi3798cv200_sysctrl_clk_unregister,
 290 };
 291
 292 static const struct of_device_id hi3798cv200_crg_match_table[] = {
 293         { .compatible = "hisilicon,hi3798cv200-crg",
 294                 .data = &hi3798cv200_crg_funcs },
 295         { .compatible = "hisilicon,hi3798cv200-sysctrl",
 296                 .data = &hi3798cv200_sysctrl_funcs },
 297         { }
 298 };
 299 MODULE_DEVICE_TABLE(of, hi3798cv200_crg_match_table);
 300
 301 static int hi3798cv200_crg_probe(struct platform_device *pdev)
 302 {
 303         struct hisi_crg_dev *crg;
 304
 305         crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
 306         if (!crg)
 307                 return -ENOMEM;
 308
 309         crg->funcs = of_device_get_match_data(&pdev->dev);
 310         if (!crg->funcs)
 311                 return -ENOENT;
 312
 313         crg->rstc = hisi_reset_init(pdev);
 314         if (!crg->rstc)
 315                 return -ENOMEM;
 316
 317         crg->clk_data = crg->funcs->register_clks(pdev);
 318         if (IS_ERR(crg->clk_data)) {
 319                 hisi_reset_exit(crg->rstc);
 320                 return PTR_ERR(crg->clk_data);
 321         }
 322
 323         platform_set_drvdata(pdev, crg);
 324         return 0;
 325 }
 326
 327 static int hi3798cv200_crg_remove(struct platform_device *pdev)
 328 {
 329         struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
 330
 331         hisi_reset_exit(crg->rstc);
 332         crg->funcs->unregister_clks(pdev);
 333         return 0;
 334 }
 335
 336 static struct platform_driver hi3798cv200_crg_driver = {
 337         .probe          = hi3798cv200_crg_probe,
 338         .remove         = hi3798cv200_crg_remove,
 339         .driver         = {
 340                 .name   = "hi3798cv200-crg",
 341                 .of_match_table = hi3798cv200_crg_match_table,
 342         },
 343 };
 344
 345 static int __init hi3798cv200_crg_init(void)
 346 {
 347         return platform_driver_register(&hi3798cv200_crg_driver);
 348 }
 349 core_initcall(hi3798cv200_crg_init);
 350
 351 static void __exit hi3798cv200_crg_exit(void)
 352 {
 353         platform_driver_unregister(&hi3798cv200_crg_driver);
 354 }
 355 module_exit(hi3798cv200_crg_exit);
 356
 357 MODULE_LICENSE("GPL v2");
 358 MODULE_DESCRIPTION("HiSilicon Hi3798CV200 CRG Driver");