drivers/clk/sunxi-ng/ccu_mp.h

   1 /*
   2  * Copyright (c) 2016 Maxime Ripard. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #ifndef _CCU_MP_H_
  15 #define _CCU_MP_H_
  16
  17 #include <linux/bitops.h>
  18 #include <linux/clk-provider.h>
  19
  20 #include "ccu_common.h"
  21 #include "ccu_div.h"
  22 #include "ccu_mult.h"
  23 #include "ccu_mux.h"
  24
  25 /*
  26  * struct ccu_mp - Definition of an M-P clock
  27  *
  28  * Clocks based on the formula parent >> P / M
  29  */
  30 struct ccu_mp {
  31         u32                     enable;
  32
  33         struct ccu_div_internal         m;
  34         struct ccu_div_internal         p;
  35         struct ccu_mux_internal mux;
  36         struct ccu_common       common;
  37 };
  38
  39 #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg,      \
  40                                    _mshift, _mwidth,                    \
  41                                    _pshift, _pwidth,                    \
  42                                    _muxshift, _muxwidth,                \
  43                                    _gate, _flags)                       \
  44         struct ccu_mp _struct = {                                       \
  45                 .enable = _gate,                                        \
  46                 .m      = _SUNXI_CCU_DIV(_mshift, _mwidth),             \
  47                 .p      = _SUNXI_CCU_DIV(_pshift, _pwidth),             \
  48                 .mux    = _SUNXI_CCU_MUX(_muxshift, _muxwidth),         \
  49                 .common = {                                             \
  50                         .reg            = _reg,                         \
  51                         .hw.init        = CLK_HW_INIT_PARENTS(_name,    \
  52                                                               _parents, \
  53                                                               &ccu_mp_ops, \
  54                                                               _flags),  \
  55                 }                                                       \
  56         }
  57
  58 #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg,           \
  59                               _mshift, _mwidth,                         \
  60                               _pshift, _pwidth,                         \
  61                               _muxshift, _muxwidth,                     \
  62                               _flags)                                   \
  63         SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg,      \
  64                                    _mshift, _mwidth,                    \
  65                                    _pshift, _pwidth,                    \
  66                                    _muxshift, _muxwidth,                \
  67                                    0, _flags)
  68
  69 static inline struct ccu_mp *hw_to_ccu_mp(struct clk_hw *hw)
  70 {
  71         struct ccu_common *common = hw_to_ccu_common(hw);
  72
  73         return container_of(common, struct ccu_mp, common);
  74 }
  75
  76 extern const struct clk_ops ccu_mp_ops;
  77
  78 /*
  79  * Special class of M-P clock that supports MMC timing modes
  80  *
  81  * Since the MMC clock registers all follow the same layout, we can
  82  * simplify the macro for this particular case. In addition, as
  83  * switching modes also affects the output clock rate, we need to
  84  * have CLK_GET_RATE_NOCACHE for all these types of clocks.
  85  */
  86
  87 #define SUNXI_CCU_MP_MMC_WITH_MUX_GATE(_struct, _name, _parents, _reg,  \
  88                                        _flags)                          \
  89         struct ccu_mp _struct = {                                       \
  90                 .enable = BIT(31),                                      \
  91                 .m      = _SUNXI_CCU_DIV(0, 4),                         \
  92                 .p      = _SUNXI_CCU_DIV(16, 2),                        \
  93                 .mux    = _SUNXI_CCU_MUX(24, 2),                        \
  94                 .common = {                                             \
  95                         .reg            = _reg,                         \
  96                         .features       = CCU_FEATURE_MMC_TIMING_SWITCH, \
  97                         .hw.init        = CLK_HW_INIT_PARENTS(_name,    \
  98                                                               _parents, \
  99                                                               &ccu_mp_mmc_ops, \
 100                                                               CLK_GET_RATE_NOCACHE | \
 101                                                               _flags),  \
 102                 }                                                       \
 103         }
 104
 105 extern const struct clk_ops ccu_mp_mmc_ops;
 106
 107 #endif /* _CCU_MP_H_ */