| blob | b3b5ea7b7fb3b25fb2adc7fb077f01fabade613e |
1 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
13 #ifndef _CORESIGHT_CORESIGHT_ETM_H
14 #define _CORESIGHT_CORESIGHT_ETM_H
16 #include <asm/local.h>
17 #include <linux/spinlock.h>
20 /*
21 * Device registers:
22 * 0x000 - 0x2FC: Trace registers
23 * 0x300 - 0x314: Management registers
24 * 0x318 - 0xEFC: Trace registers
25 * 0xF00: Management registers
26 * 0xFA0 - 0xFA4: Trace registers
27 * 0xFA8 - 0xFFC: Management registers
28 */
29 /* Trace registers (0x000-0x2FC) */
30 /* Main control and configuration registers */
31 #define TRCPRGCTLR 0x004
32 #define TRCPROCSELR 0x008
33 #define TRCSTATR 0x00C
34 #define TRCCONFIGR 0x010
35 #define TRCAUXCTLR 0x018
36 #define TRCEVENTCTL0R 0x020
37 #define TRCEVENTCTL1R 0x024
38 #define TRCSTALLCTLR 0x02C
39 #define TRCTSCTLR 0x030
40 #define TRCSYNCPR 0x034
41 #define TRCCCCTLR 0x038
42 #define TRCBBCTLR 0x03C
43 #define TRCTRACEIDR 0x040
44 #define TRCQCTLR 0x044
45 /* Filtering control registers */
46 #define TRCVICTLR 0x080
47 #define TRCVIIECTLR 0x084
48 #define TRCVISSCTLR 0x088
49 #define TRCVIPCSSCTLR 0x08C
50 #define TRCVDCTLR 0x0A0
51 #define TRCVDSACCTLR 0x0A4
52 #define TRCVDARCCTLR 0x0A8
53 /* Derived resources registers */
54 #define TRCSEQEVRn(n) (0x100 + (n * 4))
55 #define TRCSEQRSTEVR 0x118
56 #define TRCSEQSTR 0x11C
57 #define TRCEXTINSELR 0x120
58 #define TRCCNTRLDVRn(n) (0x140 + (n * 4))
59 #define TRCCNTCTLRn(n) (0x150 + (n * 4))
60 #define TRCCNTVRn(n) (0x160 + (n * 4))
61 /* ID registers */
62 #define TRCIDR8 0x180
63 #define TRCIDR9 0x184
64 #define TRCIDR10 0x188
65 #define TRCIDR11 0x18C
66 #define TRCIDR12 0x190
67 #define TRCIDR13 0x194
68 #define TRCIMSPEC0 0x1C0
69 #define TRCIMSPECn(n) (0x1C0 + (n * 4))
70 #define TRCIDR0 0x1E0
71 #define TRCIDR1 0x1E4
72 #define TRCIDR2 0x1E8
73 #define TRCIDR3 0x1EC
74 #define TRCIDR4 0x1F0
75 #define TRCIDR5 0x1F4
76 #define TRCIDR6 0x1F8
77 #define TRCIDR7 0x1FC
78 /* Resource selection registers */
79 #define TRCRSCTLRn(n) (0x200 + (n * 4))
80 /* Single-shot comparator registers */
81 #define TRCSSCCRn(n) (0x280 + (n * 4))
82 #define TRCSSCSRn(n) (0x2A0 + (n * 4))
83 #define TRCSSPCICRn(n) (0x2C0 + (n * 4))
84 /* Management registers (0x300-0x314) */
85 #define TRCOSLAR 0x300
86 #define TRCOSLSR 0x304
87 #define TRCPDCR 0x310
88 #define TRCPDSR 0x314
89 /* Trace registers (0x318-0xEFC) */
90 /* Comparator registers */
91 #define TRCACVRn(n) (0x400 + (n * 8))
92 #define TRCACATRn(n) (0x480 + (n * 8))
93 #define TRCDVCVRn(n) (0x500 + (n * 16))
94 #define TRCDVCMRn(n) (0x580 + (n * 16))
95 #define TRCCIDCVRn(n) (0x600 + (n * 8))
96 #define TRCVMIDCVRn(n) (0x640 + (n * 8))
97 #define TRCCIDCCTLR0 0x680
98 #define TRCCIDCCTLR1 0x684
99 #define TRCVMIDCCTLR0 0x688
100 #define TRCVMIDCCTLR1 0x68C
101 /* Management register (0xF00) */
102 /* Integration control registers */
103 #define TRCITCTRL 0xF00
104 /* Trace registers (0xFA0-0xFA4) */
105 /* Claim tag registers */
106 #define TRCCLAIMSET 0xFA0
107 #define TRCCLAIMCLR 0xFA4
108 /* Management registers (0xFA8-0xFFC) */
109 #define TRCDEVAFF0 0xFA8
110 #define TRCDEVAFF1 0xFAC
111 #define TRCLAR 0xFB0
112 #define TRCLSR 0xFB4
113 #define TRCAUTHSTATUS 0xFB8
114 #define TRCDEVARCH 0xFBC
115 #define TRCDEVID 0xFC8
116 #define TRCDEVTYPE 0xFCC
117 #define TRCPIDR4 0xFD0
118 #define TRCPIDR5 0xFD4
119 #define TRCPIDR6 0xFD8
120 #define TRCPIDR7 0xFDC
121 #define TRCPIDR0 0xFE0
122 #define TRCPIDR1 0xFE4
123 #define TRCPIDR2 0xFE8
124 #define TRCPIDR3 0xFEC
125 #define TRCCIDR0 0xFF0
126 #define TRCCIDR1 0xFF4
127 #define TRCCIDR2 0xFF8
128 #define TRCCIDR3 0xFFC
130 /* ETMv4 resources */
131 #define ETM_MAX_NR_PE 8
132 #define ETMv4_MAX_CNTR 4
133 #define ETM_MAX_SEQ_STATES 4
134 #define ETM_MAX_EXT_INP_SEL 4
135 #define ETM_MAX_EXT_INP 256
136 #define ETM_MAX_EXT_OUT 4
137 #define ETM_MAX_SINGLE_ADDR_CMP 16
138 #define ETM_MAX_ADDR_RANGE_CMP (ETM_MAX_SINGLE_ADDR_CMP / 2)
139 #define ETM_MAX_DATA_VAL_CMP 8
140 #define ETMv4_MAX_CTXID_CMP 8
141 #define ETM_MAX_VMID_CMP 8
142 #define ETM_MAX_PE_CMP 8
143 #define ETM_MAX_RES_SEL 16
144 #define ETM_MAX_SS_CMP 8
146 #define ETM_ARCH_V4 0x40
147 #define ETMv4_SYNC_MASK 0x1F
148 #define ETM_CYC_THRESHOLD_MASK 0xFFF
149 #define ETM_CYC_THRESHOLD_DEFAULT 0x100
150 #define ETMv4_EVENT_MASK 0xFF
151 #define ETM_CNTR_MAX_VAL 0xFFFF
152 #define ETM_TRACEID_MASK 0x3f
154 /* ETMv4 programming modes */
155 #define ETM_MODE_EXCLUDE BIT(0)
156 #define ETM_MODE_LOAD BIT(1)
157 #define ETM_MODE_STORE BIT(2)
158 #define ETM_MODE_LOAD_STORE BIT(3)
159 #define ETM_MODE_BB BIT(4)
160 #define ETMv4_MODE_CYCACC BIT(5)
161 #define ETMv4_MODE_CTXID BIT(6)
162 #define ETM_MODE_VMID BIT(7)
163 #define ETM_MODE_COND(val) BMVAL(val, 8, 10)
164 #define ETMv4_MODE_TIMESTAMP BIT(11)
165 #define ETM_MODE_RETURNSTACK BIT(12)
166 #define ETM_MODE_QELEM(val) BMVAL(val, 13, 14)
167 #define ETM_MODE_DATA_TRACE_ADDR BIT(15)
168 #define ETM_MODE_DATA_TRACE_VAL BIT(16)
169 #define ETM_MODE_ISTALL BIT(17)
170 #define ETM_MODE_DSTALL BIT(18)
171 #define ETM_MODE_ATB_TRIGGER BIT(19)
172 #define ETM_MODE_LPOVERRIDE BIT(20)
173 #define ETM_MODE_ISTALL_EN BIT(21)
174 #define ETM_MODE_DSTALL_EN BIT(22)
175 #define ETM_MODE_INSTPRIO BIT(23)
176 #define ETM_MODE_NOOVERFLOW BIT(24)
177 #define ETM_MODE_TRACE_RESET BIT(25)
178 #define ETM_MODE_TRACE_ERR BIT(26)
179 #define ETM_MODE_VIEWINST_STARTSTOP BIT(27)
180 #define ETMv4_MODE_ALL (GENMASK(27, 0) | \
181 ETM_MODE_EXCL_KERN | \
182 ETM_MODE_EXCL_USER)
184 #define TRCSTATR_IDLE_BIT 0
185 #define ETM_DEFAULT_ADDR_COMP 0
187 /* PowerDown Control Register bits */
188 #define TRCPDCR_PU BIT(3)
190 /* secure state access levels */
191 #define ETM_EXLEVEL_S_APP BIT(8)
192 #define ETM_EXLEVEL_S_OS BIT(9)
193 #define ETM_EXLEVEL_S_NA BIT(10)
194 #define ETM_EXLEVEL_S_HYP BIT(11)
195 /* non-secure state access levels */
196 #define ETM_EXLEVEL_NS_APP BIT(12)
197 #define ETM_EXLEVEL_NS_OS BIT(13)
198 #define ETM_EXLEVEL_NS_HYP BIT(14)
199 #define ETM_EXLEVEL_NS_NA BIT(15)
201 /**
202 * struct etmv4_config - configuration information related to an ETMv4
203 * @mode: Controls various modes supported by this ETM.
204 * @pe_sel: Controls which PE to trace.
205 * @cfg: Controls the tracing options.
206 * @eventctrl0: Controls the tracing of arbitrary events.
207 * @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects.
208 * @stallctl: If functionality that prevents trace unit buffer overflows
209 * is available.
210 * @ts_ctrl: Controls the insertion of global timestamps in the
211 * trace streams.
212 * @syncfreq: Controls how often trace synchronization requests occur.
213 * the TRCCCCTLR register.
214 * @ccctlr: Sets the threshold value for cycle counting.
215 * @vinst_ctrl: Controls instruction trace filtering.
216 * @viiectlr: Set or read, the address range comparators.
217 * @vissctlr: Set, or read, the single address comparators that control the
218 * ViewInst start-stop logic.
219 * @vipcssctlr: Set, or read, which PE comparator inputs can control the
220 * ViewInst start-stop logic.
221 * @seq_idx: Sequencor index selector.
222 * @seq_ctrl: Control for the sequencer state transition control register.
223 * @seq_rst: Moves the sequencer to state 0 when a programmed event occurs.
224 * @seq_state: Set, or read the sequencer state.
225 * @cntr_idx: Counter index seletor.
226 * @cntrldvr: Sets or returns the reload count value for a counter.
227 * @cntr_ctrl: Controls the operation of a counter.
228 * @cntr_val: Sets or returns the value for a counter.
229 * @res_idx: Resource index selector.
230 * @res_ctrl: Controls the selection of the resources in the trace unit.
231 * @ss_ctrl: Controls the corresponding single-shot comparator resource.
232 * @ss_status: The status of the corresponding single-shot comparator.
233 * @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control.
234 * @addr_idx: Address comparator index selector.
235 * @addr_val: Value for address comparator.
236 * @addr_acc: Address comparator access type.
237 * @addr_type: Current status of the comparator register.
238 * @ctxid_idx: Context ID index selector.
239 * @ctxid_pid: Value of the context ID comparator.
240 * @ctxid_vpid: Virtual PID seen by users if PID namespace is enabled, otherwise
241 * the same value of ctxid_pid.
242 * @ctxid_mask0:Context ID comparator mask for comparator 0-3.
243 * @ctxid_mask1:Context ID comparator mask for comparator 4-7.
244 * @vmid_idx: VM ID index selector.
245 * @vmid_val: Value of the VM ID comparator.
246 * @vmid_mask0: VM ID comparator mask for comparator 0-3.
247 * @vmid_mask1: VM ID comparator mask for comparator 4-7.
248 * @ext_inp: External input selection.
249 */
251 u32 mode;
252 u32 pe_sel;
253 u32 cfg;
254 u32 eventctrl0;
255 u32 eventctrl1;
256 u32 stall_ctrl;
257 u32 ts_ctrl;
258 u32 syncfreq;
259 u32 ccctlr;
260 u32 bb_ctrl;
261 u32 vinst_ctrl;
262 u32 viiectlr;
263 u32 vissctlr;
264 u32 vipcssctlr;
265 u8 seq_idx;
267 u32 seq_rst;
268 u32 seq_state;
269 u8 cntr_idx;
273 u8 res_idx;
278 u8 addr_idx;
282 u8 ctxid_idx;
285 u32 ctxid_mask0;
286 u32 ctxid_mask1;
287 u8 vmid_idx;
289 u32 vmid_mask0;
290 u32 vmid_mask1;
291 u32 ext_inp;
292 };
294 /**
295 * struct etm4_drvdata - specifics associated to an ETM component
296 * @base: Memory mapped base address for this component.
297 * @dev: The device entity associated to this component.
298 * @csdev: Component vitals needed by the framework.
299 * @spinlock: Only one at a time pls.
300 * @mode: This tracer's mode, i.e sysFS, Perf or disabled.
301 * @cpu: The cpu this component is affined to.
302 * @arch: ETM version number.
303 * @nr_pe: The number of processing entity available for tracing.
304 * @nr_pe_cmp: The number of processing entity comparator inputs that are
305 * available for tracing.
306 * @nr_addr_cmp:Number of pairs of address comparators available
307 * as found in ETMIDR4 0-3.
308 * @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30.
309 * @nr_ext_inp: Number of external input.
310 * @numcidc: Number of contextID comparators.
311 * @numvmidc: Number of VMID comparators.
312 * @nrseqstate: The number of sequencer states that are implemented.
313 * @nr_event: Indicates how many events the trace unit support.
314 * @nr_resource:The number of resource selection pairs available for tracing.
315 * @nr_ss_cmp: Number of single-shot comparator controls that are available.
316 * @trcid: value of the current ID for this component.
317 * @trcid_size: Indicates the trace ID width.
318 * @ts_size: Global timestamp size field.
319 * @ctxid_size: Size of the context ID field to consider.
320 * @vmid_size: Size of the VM ID comparator to consider.
321 * @ccsize: Indicates the size of the cycle counter in bits.
322 * @ccitmin: minimum value that can be programmed in
323 * @s_ex_level: In secure state, indicates whether instruction tracing is
324 * supported for the corresponding Exception level.
325 * @ns_ex_level:In non-secure state, indicates whether instruction tracing is
326 * supported for the corresponding Exception level.
327 * @sticky_enable: true if ETM base configuration has been done.
328 * @boot_enable:True if we should start tracing at boot time.
329 * @os_unlock: True if access to management registers is allowed.
330 * @instrp0: Tracing of load and store instructions
331 * as P0 elements is supported.
332 * @trcbb: Indicates if the trace unit supports branch broadcast tracing.
333 * @trccond: If the trace unit supports conditional
334 * instruction tracing.
335 * @retstack: Indicates if the implementation supports a return stack.
336 * @trccci: Indicates if the trace unit supports cycle counting
337 * for instruction.
338 * @q_support: Q element support characteristics.
339 * @trc_error: Whether a trace unit can trace a system
340 * error exception.
341 * @syncpr: Indicates if an implementation has a fixed
342 * synchronization period.
343 * @stall_ctrl: Enables trace unit functionality that prevents trace
344 * unit buffer overflows.
345 * @sysstall: Does the system support stall control of the PE?
346 * @nooverflow: Indicate if overflow prevention is supported.
347 * @atbtrig: If the implementation can support ATB triggers
348 * @lpoverride: If the implementation can support low-power state over.
349 * @config: structure holding configuration parameters.
350 */
355 spinlock_t spinlock;
356 local_t mode;
358 u8 arch;
359 u8 nr_pe;
360 u8 nr_pe_cmp;
361 u8 nr_addr_cmp;
362 u8 nr_cntr;
363 u8 nr_ext_inp;
364 u8 numcidc;
365 u8 numvmidc;
366 u8 nrseqstate;
367 u8 nr_event;
368 u8 nr_resource;
369 u8 nr_ss_cmp;
370 u8 trcid;
371 u8 trcid_size;
372 u8 ts_size;
373 u8 ctxid_size;
374 u8 vmid_size;
375 u8 ccsize;
376 u8 ccitmin;
377 u8 s_ex_level;
378 u8 ns_ex_level;
379 u8 q_support;
396 };
398 /* Address comparator access types */
400 ETM_INSTR_ADDR,
401 ETM_DATA_LOAD_ADDR,
402 ETM_DATA_STORE_ADDR,
403 ETM_DATA_LOAD_STORE_ADDR,
404 };
406 /* Address comparator context types */
408 ETM_CTX_NONE,
409 ETM_CTX_CTXID,
410 ETM_CTX_VMID,
411 ETM_CTX_CTXID_VMID,
412 };
416 #endif