1 /* Copyright (c) 2012, The Linux Foundation. All rights reserved.
3 * Description: CoreSight Trace Memory Controller driver
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/types.h>
18 #include <linux/device.h>
20 #include <linux/err.h>
22 #include <linux/miscdevice.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/spinlock.h>
27 #include <linux/pm_runtime.h>
29 #include <linux/coresight.h>
30 #include <linux/amba/bus.h>
32 #include "coresight-priv.h"
33 #include "coresight-tmc.h"
35 void tmc_wait_for_tmcready(struct tmc_drvdata
*drvdata
)
37 /* Ensure formatter, unformatter and hardware fifo are empty */
38 if (coresight_timeout(drvdata
->base
,
39 TMC_STS
, TMC_STS_TMCREADY_BIT
, 1)) {
41 "timeout while waiting for TMC to be Ready\n");
45 void tmc_flush_and_stop(struct tmc_drvdata
*drvdata
)
49 ffcr
= readl_relaxed(drvdata
->base
+ TMC_FFCR
);
50 ffcr
|= TMC_FFCR_STOP_ON_FLUSH
;
51 writel_relaxed(ffcr
, drvdata
->base
+ TMC_FFCR
);
52 ffcr
|= BIT(TMC_FFCR_FLUSHMAN_BIT
);
53 writel_relaxed(ffcr
, drvdata
->base
+ TMC_FFCR
);
54 /* Ensure flush completes */
55 if (coresight_timeout(drvdata
->base
,
56 TMC_FFCR
, TMC_FFCR_FLUSHMAN_BIT
, 0)) {
58 "timeout while waiting for completion of Manual Flush\n");
61 tmc_wait_for_tmcready(drvdata
);
64 void tmc_enable_hw(struct tmc_drvdata
*drvdata
)
66 writel_relaxed(TMC_CTL_CAPT_EN
, drvdata
->base
+ TMC_CTL
);
69 void tmc_disable_hw(struct tmc_drvdata
*drvdata
)
71 writel_relaxed(0x0, drvdata
->base
+ TMC_CTL
);
74 static int tmc_read_prepare(struct tmc_drvdata
*drvdata
)
78 switch (drvdata
->config_type
) {
79 case TMC_CONFIG_TYPE_ETB
:
80 case TMC_CONFIG_TYPE_ETF
:
81 ret
= tmc_read_prepare_etb(drvdata
);
83 case TMC_CONFIG_TYPE_ETR
:
84 ret
= tmc_read_prepare_etr(drvdata
);
91 dev_info(drvdata
->dev
, "TMC read start\n");
96 static int tmc_read_unprepare(struct tmc_drvdata
*drvdata
)
100 switch (drvdata
->config_type
) {
101 case TMC_CONFIG_TYPE_ETB
:
102 case TMC_CONFIG_TYPE_ETF
:
103 ret
= tmc_read_unprepare_etb(drvdata
);
105 case TMC_CONFIG_TYPE_ETR
:
106 ret
= tmc_read_unprepare_etr(drvdata
);
113 dev_info(drvdata
->dev
, "TMC read end\n");
118 static int tmc_open(struct inode
*inode
, struct file
*file
)
121 struct tmc_drvdata
*drvdata
= container_of(file
->private_data
,
122 struct tmc_drvdata
, miscdev
);
124 ret
= tmc_read_prepare(drvdata
);
128 nonseekable_open(inode
, file
);
130 dev_dbg(drvdata
->dev
, "%s: successfully opened\n", __func__
);
134 static ssize_t
tmc_read(struct file
*file
, char __user
*data
, size_t len
,
137 struct tmc_drvdata
*drvdata
= container_of(file
->private_data
,
138 struct tmc_drvdata
, miscdev
);
139 char *bufp
= drvdata
->buf
+ *ppos
;
141 if (*ppos
+ len
> drvdata
->len
)
142 len
= drvdata
->len
- *ppos
;
144 if (drvdata
->config_type
== TMC_CONFIG_TYPE_ETR
) {
145 if (bufp
== (char *)(drvdata
->vaddr
+ drvdata
->size
))
146 bufp
= drvdata
->vaddr
;
147 else if (bufp
> (char *)(drvdata
->vaddr
+ drvdata
->size
))
148 bufp
-= drvdata
->size
;
149 if ((bufp
+ len
) > (char *)(drvdata
->vaddr
+ drvdata
->size
))
150 len
= (char *)(drvdata
->vaddr
+ drvdata
->size
) - bufp
;
153 if (copy_to_user(data
, bufp
, len
)) {
154 dev_dbg(drvdata
->dev
, "%s: copy_to_user failed\n", __func__
);
160 dev_dbg(drvdata
->dev
, "%s: %zu bytes copied, %d bytes left\n",
161 __func__
, len
, (int)(drvdata
->len
- *ppos
));
165 static int tmc_release(struct inode
*inode
, struct file
*file
)
168 struct tmc_drvdata
*drvdata
= container_of(file
->private_data
,
169 struct tmc_drvdata
, miscdev
);
171 ret
= tmc_read_unprepare(drvdata
);
175 dev_dbg(drvdata
->dev
, "%s: released\n", __func__
);
179 static const struct file_operations tmc_fops
= {
180 .owner
= THIS_MODULE
,
183 .release
= tmc_release
,
187 static enum tmc_mem_intf_width
tmc_get_memwidth(u32 devid
)
189 enum tmc_mem_intf_width memwidth
;
192 * Excerpt from the TRM:
194 * DEVID::MEMWIDTH[10:8]
195 * 0x2 Memory interface databus is 32 bits wide.
196 * 0x3 Memory interface databus is 64 bits wide.
197 * 0x4 Memory interface databus is 128 bits wide.
198 * 0x5 Memory interface databus is 256 bits wide.
200 switch (BMVAL(devid
, 8, 10)) {
202 memwidth
= TMC_MEM_INTF_WIDTH_32BITS
;
205 memwidth
= TMC_MEM_INTF_WIDTH_64BITS
;
208 memwidth
= TMC_MEM_INTF_WIDTH_128BITS
;
211 memwidth
= TMC_MEM_INTF_WIDTH_256BITS
;
220 #define coresight_tmc_reg(name, offset) \
221 coresight_simple_reg32(struct tmc_drvdata, name, offset)
222 #define coresight_tmc_reg64(name, lo_off, hi_off) \
223 coresight_simple_reg64(struct tmc_drvdata, name, lo_off, hi_off)
225 coresight_tmc_reg(rsz
, TMC_RSZ
);
226 coresight_tmc_reg(sts
, TMC_STS
);
227 coresight_tmc_reg(trg
, TMC_TRG
);
228 coresight_tmc_reg(ctl
, TMC_CTL
);
229 coresight_tmc_reg(ffsr
, TMC_FFSR
);
230 coresight_tmc_reg(ffcr
, TMC_FFCR
);
231 coresight_tmc_reg(mode
, TMC_MODE
);
232 coresight_tmc_reg(pscr
, TMC_PSCR
);
233 coresight_tmc_reg(axictl
, TMC_AXICTL
);
234 coresight_tmc_reg(devid
, CORESIGHT_DEVID
);
235 coresight_tmc_reg64(rrp
, TMC_RRP
, TMC_RRPHI
);
236 coresight_tmc_reg64(rwp
, TMC_RWP
, TMC_RWPHI
);
237 coresight_tmc_reg64(dba
, TMC_DBALO
, TMC_DBAHI
);
239 static struct attribute
*coresight_tmc_mgmt_attrs
[] = {
250 &dev_attr_devid
.attr
,
252 &dev_attr_axictl
.attr
,
256 static ssize_t
trigger_cntr_show(struct device
*dev
,
257 struct device_attribute
*attr
, char *buf
)
259 struct tmc_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
260 unsigned long val
= drvdata
->trigger_cntr
;
262 return sprintf(buf
, "%#lx\n", val
);
265 static ssize_t
trigger_cntr_store(struct device
*dev
,
266 struct device_attribute
*attr
,
267 const char *buf
, size_t size
)
271 struct tmc_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
273 ret
= kstrtoul(buf
, 16, &val
);
277 drvdata
->trigger_cntr
= val
;
280 static DEVICE_ATTR_RW(trigger_cntr
);
282 static struct attribute
*coresight_tmc_attrs
[] = {
283 &dev_attr_trigger_cntr
.attr
,
287 static const struct attribute_group coresight_tmc_group
= {
288 .attrs
= coresight_tmc_attrs
,
291 static const struct attribute_group coresight_tmc_mgmt_group
= {
292 .attrs
= coresight_tmc_mgmt_attrs
,
296 const struct attribute_group
*coresight_tmc_groups
[] = {
297 &coresight_tmc_group
,
298 &coresight_tmc_mgmt_group
,
302 /* Detect and initialise the capabilities of a TMC ETR */
303 static int tmc_etr_setup_caps(struct tmc_drvdata
*drvdata
,
304 u32 devid
, void *dev_caps
)
308 /* Set the unadvertised capabilities */
309 tmc_etr_init_caps(drvdata
, (u32
)(unsigned long)dev_caps
);
311 if (!(devid
& TMC_DEVID_NOSCAT
))
312 tmc_etr_set_cap(drvdata
, TMC_ETR_SG
);
314 /* Check if the AXI address width is available */
315 if (devid
& TMC_DEVID_AXIAW_VALID
)
316 dma_mask
= ((devid
>> TMC_DEVID_AXIAW_SHIFT
) &
317 TMC_DEVID_AXIAW_MASK
);
320 * Unless specified in the device configuration, ETR uses a 40-bit
321 * AXI master in place of the embedded SRAM of ETB/ETF.
329 dev_info(drvdata
->dev
, "Detected dma mask %dbits\n", dma_mask
);
335 return dma_set_mask_and_coherent(drvdata
->dev
, DMA_BIT_MASK(dma_mask
));
338 static int tmc_probe(struct amba_device
*adev
, const struct amba_id
*id
)
343 struct device
*dev
= &adev
->dev
;
344 struct coresight_platform_data
*pdata
= NULL
;
345 struct tmc_drvdata
*drvdata
;
346 struct resource
*res
= &adev
->res
;
347 struct coresight_desc desc
= { 0 };
348 struct device_node
*np
= adev
->dev
.of_node
;
351 pdata
= of_get_coresight_platform_data(dev
, np
);
353 ret
= PTR_ERR(pdata
);
356 adev
->dev
.platform_data
= pdata
;
360 drvdata
= devm_kzalloc(dev
, sizeof(*drvdata
), GFP_KERNEL
);
364 drvdata
->dev
= &adev
->dev
;
365 dev_set_drvdata(dev
, drvdata
);
367 /* Validity for the resource is already checked by the AMBA core */
368 base
= devm_ioremap_resource(dev
, res
);
374 drvdata
->base
= base
;
376 spin_lock_init(&drvdata
->spinlock
);
378 devid
= readl_relaxed(drvdata
->base
+ CORESIGHT_DEVID
);
379 drvdata
->config_type
= BMVAL(devid
, 6, 7);
380 drvdata
->memwidth
= tmc_get_memwidth(devid
);
382 if (drvdata
->config_type
== TMC_CONFIG_TYPE_ETR
) {
384 ret
= of_property_read_u32(np
,
388 drvdata
->size
= SZ_1M
;
390 drvdata
->size
= readl_relaxed(drvdata
->base
+ TMC_RSZ
) * 4;
393 pm_runtime_put(&adev
->dev
);
397 desc
.groups
= coresight_tmc_groups
;
399 switch (drvdata
->config_type
) {
400 case TMC_CONFIG_TYPE_ETB
:
401 desc
.type
= CORESIGHT_DEV_TYPE_SINK
;
402 desc
.subtype
.sink_subtype
= CORESIGHT_DEV_SUBTYPE_SINK_BUFFER
;
403 desc
.ops
= &tmc_etb_cs_ops
;
405 case TMC_CONFIG_TYPE_ETR
:
406 desc
.type
= CORESIGHT_DEV_TYPE_SINK
;
407 desc
.subtype
.sink_subtype
= CORESIGHT_DEV_SUBTYPE_SINK_BUFFER
;
408 desc
.ops
= &tmc_etr_cs_ops
;
409 ret
= tmc_etr_setup_caps(drvdata
, devid
, id
->data
);
413 case TMC_CONFIG_TYPE_ETF
:
414 desc
.type
= CORESIGHT_DEV_TYPE_LINKSINK
;
415 desc
.subtype
.link_subtype
= CORESIGHT_DEV_SUBTYPE_LINK_FIFO
;
416 desc
.ops
= &tmc_etf_cs_ops
;
419 pr_err("%s: Unsupported TMC config\n", pdata
->name
);
424 drvdata
->csdev
= coresight_register(&desc
);
425 if (IS_ERR(drvdata
->csdev
)) {
426 ret
= PTR_ERR(drvdata
->csdev
);
430 drvdata
->miscdev
.name
= pdata
->name
;
431 drvdata
->miscdev
.minor
= MISC_DYNAMIC_MINOR
;
432 drvdata
->miscdev
.fops
= &tmc_fops
;
433 ret
= misc_register(&drvdata
->miscdev
);
435 coresight_unregister(drvdata
->csdev
);
440 static const struct amba_id tmc_ids
[] = {
446 /* Coresight SoC 600 TMC-ETR/ETS */
449 .data
= (void *)(unsigned long)CORESIGHT_SOC_600_ETR_CAPS
,
452 /* Coresight SoC 600 TMC-ETB */
457 /* Coresight SoC 600 TMC-ETF */
464 static struct amba_driver tmc_driver
= {
466 .name
= "coresight-tmc",
467 .owner
= THIS_MODULE
,
468 .suppress_bind_attrs
= true,
473 builtin_amba_driver(tmc_driver
);