drivers/hwtracing/coresight/coresight-tmc.h

   1 /*
   2  * Copyright(C) 2015 Linaro Limited. All rights reserved.
   3  * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef _CORESIGHT_TMC_H
  19 #define _CORESIGHT_TMC_H
  20
  21 #include <linux/miscdevice.h>
  22
  23 #define TMC_RSZ                 0x004
  24 #define TMC_STS                 0x00c
  25 #define TMC_RRD                 0x010
  26 #define TMC_RRP                 0x014
  27 #define TMC_RWP                 0x018
  28 #define TMC_TRG                 0x01c
  29 #define TMC_CTL                 0x020
  30 #define TMC_RWD                 0x024
  31 #define TMC_MODE                0x028
  32 #define TMC_LBUFLEVEL           0x02c
  33 #define TMC_CBUFLEVEL           0x030
  34 #define TMC_BUFWM               0x034
  35 #define TMC_RRPHI               0x038
  36 #define TMC_RWPHI               0x03c
  37 #define TMC_AXICTL              0x110
  38 #define TMC_DBALO               0x118
  39 #define TMC_DBAHI               0x11c
  40 #define TMC_FFSR                0x300
  41 #define TMC_FFCR                0x304
  42 #define TMC_PSCR                0x308
  43 #define TMC_ITMISCOP0           0xee0
  44 #define TMC_ITTRFLIN            0xee8
  45 #define TMC_ITATBDATA0          0xeec
  46 #define TMC_ITATBCTR2           0xef0
  47 #define TMC_ITATBCTR1           0xef4
  48 #define TMC_ITATBCTR0           0xef8
  49
  50 /* register description */
  51 /* TMC_CTL - 0x020 */
  52 #define TMC_CTL_CAPT_EN         BIT(0)
  53 /* TMC_STS - 0x00C */
  54 #define TMC_STS_TMCREADY_BIT    2
  55 #define TMC_STS_FULL            BIT(0)
  56 #define TMC_STS_TRIGGERED       BIT(1)
  57 /*
  58  * TMC_AXICTL - 0x110
  59  *
  60  * TMC AXICTL format for SoC-400
  61  *      Bits [0-1]      : ProtCtrlBit0-1
  62  *      Bits [2-5]      : CacheCtrlBits 0-3 (AXCACHE)
  63  *      Bit  6          : Reserved
  64  *      Bit  7          : ScatterGatherMode
  65  *      Bits [8-11]     : WrBurstLen
  66  *      Bits [12-31]    : Reserved.
  67  * TMC AXICTL format for SoC-600, as above except:
  68  *      Bits [2-5]      : AXI WCACHE
  69  *      Bits [16-19]    : AXI RCACHE
  70  *      Bits [20-31]    : Reserved
  71  */
  72 #define TMC_AXICTL_CLEAR_MASK 0xfbf
  73 #define TMC_AXICTL_ARCACHE_MASK (0xf << 16)
  74
  75 #define TMC_AXICTL_PROT_CTL_B0  BIT(0)
  76 #define TMC_AXICTL_PROT_CTL_B1  BIT(1)
  77 #define TMC_AXICTL_SCT_GAT_MODE BIT(7)
  78 #define TMC_AXICTL_WR_BURST_16  0xF00
  79 /* Write-back Read and Write-allocate */
  80 #define TMC_AXICTL_AXCACHE_OS   (0xf << 2)
  81 #define TMC_AXICTL_ARCACHE_OS   (0xf << 16)
  82
  83 /* TMC_FFCR - 0x304 */
  84 #define TMC_FFCR_FLUSHMAN_BIT   6
  85 #define TMC_FFCR_EN_FMT         BIT(0)
  86 #define TMC_FFCR_EN_TI          BIT(1)
  87 #define TMC_FFCR_FON_FLIN       BIT(4)
  88 #define TMC_FFCR_FON_TRIG_EVT   BIT(5)
  89 #define TMC_FFCR_TRIGON_TRIGIN  BIT(8)
  90 #define TMC_FFCR_STOP_ON_FLUSH  BIT(12)
  91
  92
  93 #define TMC_DEVID_NOSCAT        BIT(24)
  94
  95 #define TMC_DEVID_AXIAW_VALID   BIT(16)
  96 #define TMC_DEVID_AXIAW_SHIFT   17
  97 #define TMC_DEVID_AXIAW_MASK    0x7f
  98
  99 enum tmc_config_type {
 100         TMC_CONFIG_TYPE_ETB,
 101         TMC_CONFIG_TYPE_ETR,
 102         TMC_CONFIG_TYPE_ETF,
 103 };
 104
 105 enum tmc_mode {
 106         TMC_MODE_CIRCULAR_BUFFER,
 107         TMC_MODE_SOFTWARE_FIFO,
 108         TMC_MODE_HARDWARE_FIFO,
 109 };
 110
 111 enum tmc_mem_intf_width {
 112         TMC_MEM_INTF_WIDTH_32BITS       = 1,
 113         TMC_MEM_INTF_WIDTH_64BITS       = 2,
 114         TMC_MEM_INTF_WIDTH_128BITS      = 4,
 115         TMC_MEM_INTF_WIDTH_256BITS      = 8,
 116 };
 117
 118 /* TMC ETR Capability bit definitions */
 119 #define TMC_ETR_SG                      (0x1U << 0)
 120 /* ETR has separate read/write cache encodings */
 121 #define TMC_ETR_AXI_ARCACHE             (0x1U << 1)
 122 /*
 123  * TMC_ETR_SAVE_RESTORE - Values of RRP/RWP/STS.Full are
 124  * retained when TMC leaves Disabled state, allowing us to continue
 125  * the tracing from a point where we stopped. This also implies that
 126  * the RRP/RWP/STS.Full should always be programmed to the correct
 127  * value. Unfortunately this is not advertised by the hardware,
 128  * so we have to rely on PID of the IP to detect the functionality.
 129  */
 130 #define TMC_ETR_SAVE_RESTORE            (0x1U << 2)
 131
 132 /* Coresight SoC-600 TMC-ETR unadvertised capabilities */
 133 #define CORESIGHT_SOC_600_ETR_CAPS      \
 134         (TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE)
 135
 136 /**
 137  * struct tmc_drvdata - specifics associated to an TMC component
 138  * @base:       memory mapped base address for this component.
 139  * @dev:        the device entity associated to this component.
 140  * @csdev:      component vitals needed by the framework.
 141  * @miscdev:    specifics to handle "/dev/xyz.tmc" entry.
 142  * @spinlock:   only one at a time pls.
 143  * @buf:        area of memory where trace data get sent.
 144  * @paddr:      DMA start location in RAM.
 145  * @vaddr:      virtual representation of @paddr.
 146  * @size:       trace buffer size.
 147  * @len:        size of the available trace.
 148  * @mode:       how this TMC is being used.
 149  * @config_type: TMC variant, must be of type @tmc_config_type.
 150  * @memwidth:   width of the memory interface databus, in bytes.
 151  * @trigger_cntr: amount of words to store after a trigger.
 152  * @etr_caps:   Bitmask of capabilities of the TMC ETR, inferred from the
 153  *              device configuration register (DEVID)
 154  */
 155 struct tmc_drvdata {
 156         void __iomem            *base;
 157         struct device           *dev;
 158         struct coresight_device *csdev;
 159         struct miscdevice       miscdev;
 160         spinlock_t              spinlock;
 161         bool                    reading;
 162         char                    *buf;
 163         dma_addr_t              paddr;
 164         void __iomem            *vaddr;
 165         u32                     size;
 166         u32                     len;
 167         u32                     mode;
 168         enum tmc_config_type    config_type;
 169         enum tmc_mem_intf_width memwidth;
 170         u32                     trigger_cntr;
 171         u32                     etr_caps;
 172 };
 173
 174 /* Generic functions */
 175 void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata);
 176 void tmc_flush_and_stop(struct tmc_drvdata *drvdata);
 177 void tmc_enable_hw(struct tmc_drvdata *drvdata);
 178 void tmc_disable_hw(struct tmc_drvdata *drvdata);
 179
 180 /* ETB/ETF functions */
 181 int tmc_read_prepare_etb(struct tmc_drvdata *drvdata);
 182 int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata);
 183 extern const struct coresight_ops tmc_etb_cs_ops;
 184 extern const struct coresight_ops tmc_etf_cs_ops;
 185
 186 /* ETR functions */
 187 int tmc_read_prepare_etr(struct tmc_drvdata *drvdata);
 188 int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata);
 189 extern const struct coresight_ops tmc_etr_cs_ops;
 190
 191
 192 #define TMC_REG_PAIR(name, lo_off, hi_off)                              \
 193 static inline u64                                                       \
 194 tmc_read_##name(struct tmc_drvdata *drvdata)                            \
 195 {                                                                       \
 196         return coresight_read_reg_pair(drvdata->base, lo_off, hi_off);  \
 197 }                                                                       \
 198 static inline void                                                      \
 199 tmc_write_##name(struct tmc_drvdata *drvdata, u64 val)                  \
 200 {                                                                       \
 201         coresight_write_reg_pair(drvdata->base, val, lo_off, hi_off);   \
 202 }
 203
 204 TMC_REG_PAIR(rrp, TMC_RRP, TMC_RRPHI)
 205 TMC_REG_PAIR(rwp, TMC_RWP, TMC_RWPHI)
 206 TMC_REG_PAIR(dba, TMC_DBALO, TMC_DBAHI)
 207
 208 /* Initialise the caps from unadvertised static capabilities of the device */
 209 static inline void tmc_etr_init_caps(struct tmc_drvdata *drvdata, u32 dev_caps)
 210 {
 211         WARN_ON(drvdata->etr_caps);
 212         drvdata->etr_caps = dev_caps;
 213 }
 214
 215 static inline void tmc_etr_set_cap(struct tmc_drvdata *drvdata, u32 cap)
 216 {
 217         drvdata->etr_caps |= cap;
 218 }
 219
 220 static inline bool tmc_etr_has_cap(struct tmc_drvdata *drvdata, u32 cap)
 221 {
 222         return !!(drvdata->etr_caps & cap);
 223 }
 224
 225 #endif