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x86/speculation/mds: Fix documentation typo
[linux/fpc-iii.git] / drivers / iio / accel / bmc150-accel-core.c
blob807299dd45ebf0663fbc97b3831bd8f92148ec20
1 /*
2 * 3-axis accelerometer driver supporting following Bosch-Sensortec chips:
3 * - BMC150
4 * - BMI055
5 * - BMA255
6 * - BMA250E
7 * - BMA222E
8 * - BMA280
9 *
10 * Copyright (c) 2014, Intel Corporation.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms and conditions of the GNU General Public License,
14 * version 2, as published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 */
21
22 #include <linux/module.h>
23 #include <linux/i2c.h>
24 #include <linux/interrupt.h>
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/acpi.h>
28 #include <linux/pm.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/iio/iio.h>
31 #include <linux/iio/sysfs.h>
32 #include <linux/iio/buffer.h>
33 #include <linux/iio/events.h>
34 #include <linux/iio/trigger.h>
35 #include <linux/iio/trigger_consumer.h>
36 #include <linux/iio/triggered_buffer.h>
37 #include <linux/regmap.h>
38
39 #include "bmc150-accel.h"
40
41 #define BMC150_ACCEL_DRV_NAME "bmc150_accel"
42 #define BMC150_ACCEL_IRQ_NAME "bmc150_accel_event"
43
44 #define BMC150_ACCEL_REG_CHIP_ID 0x00
45
46 #define BMC150_ACCEL_REG_INT_STATUS_2 0x0B
47 #define BMC150_ACCEL_ANY_MOTION_MASK 0x07
48 #define BMC150_ACCEL_ANY_MOTION_BIT_X BIT(0)
49 #define BMC150_ACCEL_ANY_MOTION_BIT_Y BIT(1)
50 #define BMC150_ACCEL_ANY_MOTION_BIT_Z BIT(2)
51 #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN BIT(3)
52
53 #define BMC150_ACCEL_REG_PMU_LPW 0x11
54 #define BMC150_ACCEL_PMU_MODE_MASK 0xE0
55 #define BMC150_ACCEL_PMU_MODE_SHIFT 5
56 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK 0x17
57 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT 1
58
59 #define BMC150_ACCEL_REG_PMU_RANGE 0x0F
60
61 #define BMC150_ACCEL_DEF_RANGE_2G 0x03
62 #define BMC150_ACCEL_DEF_RANGE_4G 0x05
63 #define BMC150_ACCEL_DEF_RANGE_8G 0x08
64 #define BMC150_ACCEL_DEF_RANGE_16G 0x0C
65
66 /* Default BW: 125Hz */
67 #define BMC150_ACCEL_REG_PMU_BW 0x10
68 #define BMC150_ACCEL_DEF_BW 125
69
70 #define BMC150_ACCEL_REG_RESET 0x14
71 #define BMC150_ACCEL_RESET_VAL 0xB6
72
73 #define BMC150_ACCEL_REG_INT_MAP_0 0x19
74 #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE BIT(2)
75
76 #define BMC150_ACCEL_REG_INT_MAP_1 0x1A
77 #define BMC150_ACCEL_INT_MAP_1_BIT_DATA BIT(0)
78 #define BMC150_ACCEL_INT_MAP_1_BIT_FWM BIT(1)
79 #define BMC150_ACCEL_INT_MAP_1_BIT_FFULL BIT(2)
80
81 #define BMC150_ACCEL_REG_INT_RST_LATCH 0x21
82 #define BMC150_ACCEL_INT_MODE_LATCH_RESET 0x80
83 #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F
84 #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT 0x00
85
86 #define BMC150_ACCEL_REG_INT_EN_0 0x16
87 #define BMC150_ACCEL_INT_EN_BIT_SLP_X BIT(0)
88 #define BMC150_ACCEL_INT_EN_BIT_SLP_Y BIT(1)
89 #define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2)
90
91 #define BMC150_ACCEL_REG_INT_EN_1 0x17
92 #define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4)
93 #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN BIT(5)
94 #define BMC150_ACCEL_INT_EN_BIT_FWM_EN BIT(6)
95
96 #define BMC150_ACCEL_REG_INT_OUT_CTRL 0x20
97 #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0)
98
99 #define BMC150_ACCEL_REG_INT_5 0x27
100 #define BMC150_ACCEL_SLOPE_DUR_MASK 0x03
101
102 #define BMC150_ACCEL_REG_INT_6 0x28
103 #define BMC150_ACCEL_SLOPE_THRES_MASK 0xFF
104
105 /* Slope duration in terms of number of samples */
106 #define BMC150_ACCEL_DEF_SLOPE_DURATION 1
107 /* in terms of multiples of g's/LSB, based on range */
108 #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD 1
109
110 #define BMC150_ACCEL_REG_XOUT_L 0x02
111
112 #define BMC150_ACCEL_MAX_STARTUP_TIME_MS 100
113
114 /* Sleep Duration values */
115 #define BMC150_ACCEL_SLEEP_500_MICRO 0x05
116 #define BMC150_ACCEL_SLEEP_1_MS 0x06
117 #define BMC150_ACCEL_SLEEP_2_MS 0x07
118 #define BMC150_ACCEL_SLEEP_4_MS 0x08
119 #define BMC150_ACCEL_SLEEP_6_MS 0x09
120 #define BMC150_ACCEL_SLEEP_10_MS 0x0A
121 #define BMC150_ACCEL_SLEEP_25_MS 0x0B
122 #define BMC150_ACCEL_SLEEP_50_MS 0x0C
123 #define BMC150_ACCEL_SLEEP_100_MS 0x0D
124 #define BMC150_ACCEL_SLEEP_500_MS 0x0E
125 #define BMC150_ACCEL_SLEEP_1_SEC 0x0F
126
127 #define BMC150_ACCEL_REG_TEMP 0x08
128 #define BMC150_ACCEL_TEMP_CENTER_VAL 24
129
130 #define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2))
131 #define BMC150_AUTO_SUSPEND_DELAY_MS 2000
132
133 #define BMC150_ACCEL_REG_FIFO_STATUS 0x0E
134 #define BMC150_ACCEL_REG_FIFO_CONFIG0 0x30
135 #define BMC150_ACCEL_REG_FIFO_CONFIG1 0x3E
136 #define BMC150_ACCEL_REG_FIFO_DATA 0x3F
137 #define BMC150_ACCEL_FIFO_LENGTH 32
138
139 enum bmc150_accel_axis {
140 AXIS_X,
141 AXIS_Y,
142 AXIS_Z,
143 AXIS_MAX,
144 };
145
146 enum bmc150_power_modes {
147 BMC150_ACCEL_SLEEP_MODE_NORMAL,
148 BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND,
149 BMC150_ACCEL_SLEEP_MODE_LPM,
150 BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04,
151 };
152
153 struct bmc150_scale_info {
154 int scale;
155 u8 reg_range;
156 };
157
158 struct bmc150_accel_chip_info {
159 const char *name;
160 u8 chip_id;
161 const struct iio_chan_spec *channels;
162 int num_channels;
163 const struct bmc150_scale_info scale_table[4];
164 };
165
166 struct bmc150_accel_interrupt {
167 const struct bmc150_accel_interrupt_info *info;
168 atomic_t users;
169 };
170
171 struct bmc150_accel_trigger {
172 struct bmc150_accel_data *data;
173 struct iio_trigger *indio_trig;
174 int (*setup)(struct bmc150_accel_trigger *t, bool state);
175 int intr;
176 bool enabled;
177 };
178
179 enum bmc150_accel_interrupt_id {
180 BMC150_ACCEL_INT_DATA_READY,
181 BMC150_ACCEL_INT_ANY_MOTION,
182 BMC150_ACCEL_INT_WATERMARK,
183 BMC150_ACCEL_INTERRUPTS,
184 };
185
186 enum bmc150_accel_trigger_id {
187 BMC150_ACCEL_TRIGGER_DATA_READY,
188 BMC150_ACCEL_TRIGGER_ANY_MOTION,
189 BMC150_ACCEL_TRIGGERS,
190 };
191
192 struct bmc150_accel_data {
193 struct regmap *regmap;
194 int irq;
195 struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS];
196 struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS];
197 struct mutex mutex;
198 u8 fifo_mode, watermark;
199 s16 buffer[8];
200 u8 bw_bits;
201 u32 slope_dur;
202 u32 slope_thres;
203 u32 range;
204 int ev_enable_state;
205 int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */
206 const struct bmc150_accel_chip_info *chip_info;
207 };
208
209 static const struct {
210 int val;
211 int val2;
212 u8 bw_bits;
213 } bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08},
214 {31, 260000, 0x09},
215 {62, 500000, 0x0A},
216 {125, 0, 0x0B},
217 {250, 0, 0x0C},
218 {500, 0, 0x0D},
219 {1000, 0, 0x0E},
220 {2000, 0, 0x0F} };
221
222 static const struct {
223 int bw_bits;
224 int msec;
225 } bmc150_accel_sample_upd_time[] = { {0x08, 64},
226 {0x09, 32},
227 {0x0A, 16},
228 {0x0B, 8},
229 {0x0C, 4},
230 {0x0D, 2},
231 {0x0E, 1},
232 {0x0F, 1} };
233
234 static const struct {
235 int sleep_dur;
236 u8 reg_value;
237 } bmc150_accel_sleep_value_table[] = { {0, 0},
238 {500, BMC150_ACCEL_SLEEP_500_MICRO},
239 {1000, BMC150_ACCEL_SLEEP_1_MS},
240 {2000, BMC150_ACCEL_SLEEP_2_MS},
241 {4000, BMC150_ACCEL_SLEEP_4_MS},
242 {6000, BMC150_ACCEL_SLEEP_6_MS},
243 {10000, BMC150_ACCEL_SLEEP_10_MS},
244 {25000, BMC150_ACCEL_SLEEP_25_MS},
245 {50000, BMC150_ACCEL_SLEEP_50_MS},
246 {100000, BMC150_ACCEL_SLEEP_100_MS},
247 {500000, BMC150_ACCEL_SLEEP_500_MS},
248 {1000000, BMC150_ACCEL_SLEEP_1_SEC} };
249
250 const struct regmap_config bmc150_regmap_conf = {
251 .reg_bits = 8,
252 .val_bits = 8,
253 .max_register = 0x3f,
254 };
255 EXPORT_SYMBOL_GPL(bmc150_regmap_conf);
256
257 static int bmc150_accel_set_mode(struct bmc150_accel_data *data,
258 enum bmc150_power_modes mode,
259 int dur_us)
260 {
261 struct device *dev = regmap_get_device(data->regmap);
262 int i;
263 int ret;
264 u8 lpw_bits;
265 int dur_val = -1;
266
267 if (dur_us > 0) {
268 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table);
269 ++i) {
270 if (bmc150_accel_sleep_value_table[i].sleep_dur ==
271 dur_us)
272 dur_val =
273 bmc150_accel_sleep_value_table[i].reg_value;
274 }
275 } else {
276 dur_val = 0;
277 }
278
279 if (dur_val < 0)
280 return -EINVAL;
281
282 lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT;
283 lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT);
284
285 dev_dbg(dev, "Set Mode bits %x\n", lpw_bits);
286
287 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_LPW, lpw_bits);
288 if (ret < 0) {
289 dev_err(dev, "Error writing reg_pmu_lpw\n");
290 return ret;
291 }
292
293 return 0;
294 }
295
296 static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val,
297 int val2)
298 {
299 int i;
300 int ret;
301
302 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
303 if (bmc150_accel_samp_freq_table[i].val == val &&
304 bmc150_accel_samp_freq_table[i].val2 == val2) {
305 ret = regmap_write(data->regmap,
306 BMC150_ACCEL_REG_PMU_BW,
307 bmc150_accel_samp_freq_table[i].bw_bits);
308 if (ret < 0)
309 return ret;
310
311 data->bw_bits =
312 bmc150_accel_samp_freq_table[i].bw_bits;
313 return 0;
314 }
315 }
316
317 return -EINVAL;
318 }
319
320 static int bmc150_accel_update_slope(struct bmc150_accel_data *data)
321 {
322 struct device *dev = regmap_get_device(data->regmap);
323 int ret;
324
325 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_6,
326 data->slope_thres);
327 if (ret < 0) {
328 dev_err(dev, "Error writing reg_int_6\n");
329 return ret;
330 }
331
332 ret = regmap_update_bits(data->regmap, BMC150_ACCEL_REG_INT_5,
333 BMC150_ACCEL_SLOPE_DUR_MASK, data->slope_dur);
334 if (ret < 0) {
335 dev_err(dev, "Error updating reg_int_5\n");
336 return ret;
337 }
338
339 dev_dbg(dev, "%s: %x %x\n", __func__, data->slope_thres,
340 data->slope_dur);
341
342 return ret;
343 }
344
345 static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t,
346 bool state)
347 {
348 if (state)
349 return bmc150_accel_update_slope(t->data);
350
351 return 0;
352 }
353
354 static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val,
355 int *val2)
356 {
357 int i;
358
359 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
360 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) {
361 *val = bmc150_accel_samp_freq_table[i].val;
362 *val2 = bmc150_accel_samp_freq_table[i].val2;
363 return IIO_VAL_INT_PLUS_MICRO;
364 }
365 }
366
367 return -EINVAL;
368 }
369
370 #ifdef CONFIG_PM
371 static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data)
372 {
373 int i;
374
375 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) {
376 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits)
377 return bmc150_accel_sample_upd_time[i].msec;
378 }
379
380 return BMC150_ACCEL_MAX_STARTUP_TIME_MS;
381 }
382
383 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
384 {
385 struct device *dev = regmap_get_device(data->regmap);
386 int ret;
387
388 if (on) {
389 ret = pm_runtime_get_sync(dev);
390 } else {
391 pm_runtime_mark_last_busy(dev);
392 ret = pm_runtime_put_autosuspend(dev);
393 }
394
395 if (ret < 0) {
396 dev_err(dev,
397 "Failed: bmc150_accel_set_power_state for %d\n", on);
398 if (on)
399 pm_runtime_put_noidle(dev);
400
401 return ret;
402 }
403
404 return 0;
405 }
406 #else
407 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
408 {
409 return 0;
410 }
411 #endif
412
413 static const struct bmc150_accel_interrupt_info {
414 u8 map_reg;
415 u8 map_bitmask;
416 u8 en_reg;
417 u8 en_bitmask;
418 } bmc150_accel_interrupts[BMC150_ACCEL_INTERRUPTS] = {
419 { /* data ready interrupt */
420 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
421 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_DATA,
422 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
423 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN,
424 },
425 { /* motion interrupt */
426 .map_reg = BMC150_ACCEL_REG_INT_MAP_0,
427 .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_SLOPE,
428 .en_reg = BMC150_ACCEL_REG_INT_EN_0,
429 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_SLP_X |
430 BMC150_ACCEL_INT_EN_BIT_SLP_Y |
431 BMC150_ACCEL_INT_EN_BIT_SLP_Z
432 },
433 { /* fifo watermark interrupt */
434 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
435 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_FWM,
436 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
437 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN,
438 },
439 };
440
441 static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev,
442 struct bmc150_accel_data *data)
443 {
444 int i;
445
446 for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++)
447 data->interrupts[i].info = &bmc150_accel_interrupts[i];
448 }
449
450 static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i,
451 bool state)
452 {
453 struct device *dev = regmap_get_device(data->regmap);
454 struct bmc150_accel_interrupt *intr = &data->interrupts[i];
455 const struct bmc150_accel_interrupt_info *info = intr->info;
456 int ret;
457
458 if (state) {
459 if (atomic_inc_return(&intr->users) > 1)
460 return 0;
461 } else {
462 if (atomic_dec_return(&intr->users) > 0)
463 return 0;
464 }
465
466 /*
467 * We will expect the enable and disable to do operation in reverse
468 * order. This will happen here anyway, as our resume operation uses
469 * sync mode runtime pm calls. The suspend operation will be delayed
470 * by autosuspend delay.
471 * So the disable operation will still happen in reverse order of
472 * enable operation. When runtime pm is disabled the mode is always on,
473 * so sequence doesn't matter.
474 */
475 ret = bmc150_accel_set_power_state(data, state);
476 if (ret < 0)
477 return ret;
478
479 /* map the interrupt to the appropriate pins */
480 ret = regmap_update_bits(data->regmap, info->map_reg, info->map_bitmask,
481 (state ? info->map_bitmask : 0));
482 if (ret < 0) {
483 dev_err(dev, "Error updating reg_int_map\n");
484 goto out_fix_power_state;
485 }
486
487 /* enable/disable the interrupt */
488 ret = regmap_update_bits(data->regmap, info->en_reg, info->en_bitmask,
489 (state ? info->en_bitmask : 0));
490 if (ret < 0) {
491 dev_err(dev, "Error updating reg_int_en\n");
492 goto out_fix_power_state;
493 }
494
495 return 0;
496
497 out_fix_power_state:
498 bmc150_accel_set_power_state(data, false);
499 return ret;
500 }
501
502 static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val)
503 {
504 struct device *dev = regmap_get_device(data->regmap);
505 int ret, i;
506
507 for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) {
508 if (data->chip_info->scale_table[i].scale == val) {
509 ret = regmap_write(data->regmap,
510 BMC150_ACCEL_REG_PMU_RANGE,
511 data->chip_info->scale_table[i].reg_range);
512 if (ret < 0) {
513 dev_err(dev, "Error writing pmu_range\n");
514 return ret;
515 }
516
517 data->range = data->chip_info->scale_table[i].reg_range;
518 return 0;
519 }
520 }
521
522 return -EINVAL;
523 }
524
525 static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val)
526 {
527 struct device *dev = regmap_get_device(data->regmap);
528 int ret;
529 unsigned int value;
530
531 mutex_lock(&data->mutex);
532
533 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_TEMP, &value);
534 if (ret < 0) {
535 dev_err(dev, "Error reading reg_temp\n");
536 mutex_unlock(&data->mutex);
537 return ret;
538 }
539 *val = sign_extend32(value, 7);
540
541 mutex_unlock(&data->mutex);
542
543 return IIO_VAL_INT;
544 }
545
546 static int bmc150_accel_get_axis(struct bmc150_accel_data *data,
547 struct iio_chan_spec const *chan,
548 int *val)
549 {
550 struct device *dev = regmap_get_device(data->regmap);
551 int ret;
552 int axis = chan->scan_index;
553 __le16 raw_val;
554
555 mutex_lock(&data->mutex);
556 ret = bmc150_accel_set_power_state(data, true);
557 if (ret < 0) {
558 mutex_unlock(&data->mutex);
559 return ret;
560 }
561
562 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_AXIS_TO_REG(axis),
563 &raw_val, sizeof(raw_val));
564 if (ret < 0) {
565 dev_err(dev, "Error reading axis %d\n", axis);
566 bmc150_accel_set_power_state(data, false);
567 mutex_unlock(&data->mutex);
568 return ret;
569 }
570 *val = sign_extend32(le16_to_cpu(raw_val) >> chan->scan_type.shift,
571 chan->scan_type.realbits - 1);
572 ret = bmc150_accel_set_power_state(data, false);
573 mutex_unlock(&data->mutex);
574 if (ret < 0)
575 return ret;
576
577 return IIO_VAL_INT;
578 }
579
580 static int bmc150_accel_read_raw(struct iio_dev *indio_dev,
581 struct iio_chan_spec const *chan,
582 int *val, int *val2, long mask)
583 {
584 struct bmc150_accel_data *data = iio_priv(indio_dev);
585 int ret;
586
587 switch (mask) {
588 case IIO_CHAN_INFO_RAW:
589 switch (chan->type) {
590 case IIO_TEMP:
591 return bmc150_accel_get_temp(data, val);
592 case IIO_ACCEL:
593 if (iio_buffer_enabled(indio_dev))
594 return -EBUSY;
595 else
596 return bmc150_accel_get_axis(data, chan, val);
597 default:
598 return -EINVAL;
599 }
600 case IIO_CHAN_INFO_OFFSET:
601 if (chan->type == IIO_TEMP) {
602 *val = BMC150_ACCEL_TEMP_CENTER_VAL;
603 return IIO_VAL_INT;
604 } else {
605 return -EINVAL;
606 }
607 case IIO_CHAN_INFO_SCALE:
608 *val = 0;
609 switch (chan->type) {
610 case IIO_TEMP:
611 *val2 = 500000;
612 return IIO_VAL_INT_PLUS_MICRO;
613 case IIO_ACCEL:
614 {
615 int i;
616 const struct bmc150_scale_info *si;
617 int st_size = ARRAY_SIZE(data->chip_info->scale_table);
618
619 for (i = 0; i < st_size; ++i) {
620 si = &data->chip_info->scale_table[i];
621 if (si->reg_range == data->range) {
622 *val2 = si->scale;
623 return IIO_VAL_INT_PLUS_MICRO;
624 }
625 }
626 return -EINVAL;
627 }
628 default:
629 return -EINVAL;
630 }
631 case IIO_CHAN_INFO_SAMP_FREQ:
632 mutex_lock(&data->mutex);
633 ret = bmc150_accel_get_bw(data, val, val2);
634 mutex_unlock(&data->mutex);
635 return ret;
636 default:
637 return -EINVAL;
638 }
639 }
640
641 static int bmc150_accel_write_raw(struct iio_dev *indio_dev,
642 struct iio_chan_spec const *chan,
643 int val, int val2, long mask)
644 {
645 struct bmc150_accel_data *data = iio_priv(indio_dev);
646 int ret;
647
648 switch (mask) {
649 case IIO_CHAN_INFO_SAMP_FREQ:
650 mutex_lock(&data->mutex);
651 ret = bmc150_accel_set_bw(data, val, val2);
652 mutex_unlock(&data->mutex);
653 break;
654 case IIO_CHAN_INFO_SCALE:
655 if (val)
656 return -EINVAL;
657
658 mutex_lock(&data->mutex);
659 ret = bmc150_accel_set_scale(data, val2);
660 mutex_unlock(&data->mutex);
661 return ret;
662 default:
663 ret = -EINVAL;
664 }
665
666 return ret;
667 }
668
669 static int bmc150_accel_read_event(struct iio_dev *indio_dev,
670 const struct iio_chan_spec *chan,
671 enum iio_event_type type,
672 enum iio_event_direction dir,
673 enum iio_event_info info,
674 int *val, int *val2)
675 {
676 struct bmc150_accel_data *data = iio_priv(indio_dev);
677
678 *val2 = 0;
679 switch (info) {
680 case IIO_EV_INFO_VALUE:
681 *val = data->slope_thres;
682 break;
683 case IIO_EV_INFO_PERIOD:
684 *val = data->slope_dur;
685 break;
686 default:
687 return -EINVAL;
688 }
689
690 return IIO_VAL_INT;
691 }
692
693 static int bmc150_accel_write_event(struct iio_dev *indio_dev,
694 const struct iio_chan_spec *chan,
695 enum iio_event_type type,
696 enum iio_event_direction dir,
697 enum iio_event_info info,
698 int val, int val2)
699 {
700 struct bmc150_accel_data *data = iio_priv(indio_dev);
701
702 if (data->ev_enable_state)
703 return -EBUSY;
704
705 switch (info) {
706 case IIO_EV_INFO_VALUE:
707 data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK;
708 break;
709 case IIO_EV_INFO_PERIOD:
710 data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK;
711 break;
712 default:
713 return -EINVAL;
714 }
715
716 return 0;
717 }
718
719 static int bmc150_accel_read_event_config(struct iio_dev *indio_dev,
720 const struct iio_chan_spec *chan,
721 enum iio_event_type type,
722 enum iio_event_direction dir)
723 {
724 struct bmc150_accel_data *data = iio_priv(indio_dev);
725
726 return data->ev_enable_state;
727 }
728
729 static int bmc150_accel_write_event_config(struct iio_dev *indio_dev,
730 const struct iio_chan_spec *chan,
731 enum iio_event_type type,
732 enum iio_event_direction dir,
733 int state)
734 {
735 struct bmc150_accel_data *data = iio_priv(indio_dev);
736 int ret;
737
738 if (state == data->ev_enable_state)
739 return 0;
740
741 mutex_lock(&data->mutex);
742
743 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION,
744 state);
745 if (ret < 0) {
746 mutex_unlock(&data->mutex);
747 return ret;
748 }
749
750 data->ev_enable_state = state;
751 mutex_unlock(&data->mutex);
752
753 return 0;
754 }
755
756 static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev,
757 struct iio_trigger *trig)
758 {
759 struct bmc150_accel_data *data = iio_priv(indio_dev);
760 int i;
761
762 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
763 if (data->triggers[i].indio_trig == trig)
764 return 0;
765 }
766
767 return -EINVAL;
768 }
769
770 static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev,
771 struct device_attribute *attr,
772 char *buf)
773 {
774 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
775 struct bmc150_accel_data *data = iio_priv(indio_dev);
776 int wm;
777
778 mutex_lock(&data->mutex);
779 wm = data->watermark;
780 mutex_unlock(&data->mutex);
781
782 return sprintf(buf, "%d\n", wm);
783 }
784
785 static ssize_t bmc150_accel_get_fifo_state(struct device *dev,
786 struct device_attribute *attr,
787 char *buf)
788 {
789 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
790 struct bmc150_accel_data *data = iio_priv(indio_dev);
791 bool state;
792
793 mutex_lock(&data->mutex);
794 state = data->fifo_mode;
795 mutex_unlock(&data->mutex);
796
797 return sprintf(buf, "%d\n", state);
798 }
799
800 static IIO_CONST_ATTR(hwfifo_watermark_min, "1");
801 static IIO_CONST_ATTR(hwfifo_watermark_max,
802 __stringify(BMC150_ACCEL_FIFO_LENGTH));
803 static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO,
804 bmc150_accel_get_fifo_state, NULL, 0);
805 static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO,
806 bmc150_accel_get_fifo_watermark, NULL, 0);
807
808 static const struct attribute *bmc150_accel_fifo_attributes[] = {
809 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
810 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
811 &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
812 &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
813 NULL,
814 };
815
816 static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val)
817 {
818 struct bmc150_accel_data *data = iio_priv(indio_dev);
819
820 if (val > BMC150_ACCEL_FIFO_LENGTH)
821 val = BMC150_ACCEL_FIFO_LENGTH;
822
823 mutex_lock(&data->mutex);
824 data->watermark = val;
825 mutex_unlock(&data->mutex);
826
827 return 0;
828 }
829
830 /*
831 * We must read at least one full frame in one burst, otherwise the rest of the
832 * frame data is discarded.
833 */
834 static int bmc150_accel_fifo_transfer(struct bmc150_accel_data *data,
835 char *buffer, int samples)
836 {
837 struct device *dev = regmap_get_device(data->regmap);
838 int sample_length = 3 * 2;
839 int ret;
840 int total_length = samples * sample_length;
841 int i;
842 size_t step = regmap_get_raw_read_max(data->regmap);
843
844 if (!step || step > total_length)
845 step = total_length;
846 else if (step < total_length)
847 step = sample_length;
848
849 /*
850 * Seems we have a bus with size limitation so we have to execute
851 * multiple reads
852 */
853 for (i = 0; i < total_length; i += step) {
854 ret = regmap_raw_read(data->regmap, BMC150_ACCEL_REG_FIFO_DATA,
855 &buffer[i], step);
856 if (ret)
857 break;
858 }
859
860 if (ret)
861 dev_err(dev,
862 "Error transferring data from fifo in single steps of %zu\n",
863 step);
864
865 return ret;
866 }
867
868 static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev,
869 unsigned samples, bool irq)
870 {
871 struct bmc150_accel_data *data = iio_priv(indio_dev);
872 struct device *dev = regmap_get_device(data->regmap);
873 int ret, i;
874 u8 count;
875 u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3];
876 int64_t tstamp;
877 uint64_t sample_period;
878 unsigned int val;
879
880 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_FIFO_STATUS, &val);
881 if (ret < 0) {
882 dev_err(dev, "Error reading reg_fifo_status\n");
883 return ret;
884 }
885
886 count = val & 0x7F;
887
888 if (!count)
889 return 0;
890
891 /*
892 * If we getting called from IRQ handler we know the stored timestamp is
893 * fairly accurate for the last stored sample. Otherwise, if we are
894 * called as a result of a read operation from userspace and hence
895 * before the watermark interrupt was triggered, take a timestamp
896 * now. We can fall anywhere in between two samples so the error in this
897 * case is at most one sample period.
898 */
899 if (!irq) {
900 data->old_timestamp = data->timestamp;
901 data->timestamp = iio_get_time_ns(indio_dev);
902 }
903
904 /*
905 * Approximate timestamps for each of the sample based on the sampling
906 * frequency, timestamp for last sample and number of samples.
907 *
908 * Note that we can't use the current bandwidth settings to compute the
909 * sample period because the sample rate varies with the device
910 * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That
911 * small variation adds when we store a large number of samples and
912 * creates significant jitter between the last and first samples in
913 * different batches (e.g. 32ms vs 21ms).
914 *
915 * To avoid this issue we compute the actual sample period ourselves
916 * based on the timestamp delta between the last two flush operations.
917 */
918 sample_period = (data->timestamp - data->old_timestamp);
919 do_div(sample_period, count);
920 tstamp = data->timestamp - (count - 1) * sample_period;
921
922 if (samples && count > samples)
923 count = samples;
924
925 ret = bmc150_accel_fifo_transfer(data, (u8 *)buffer, count);
926 if (ret)
927 return ret;
928
929 /*
930 * Ideally we want the IIO core to handle the demux when running in fifo
931 * mode but not when running in triggered buffer mode. Unfortunately
932 * this does not seem to be possible, so stick with driver demux for
933 * now.
934 */
935 for (i = 0; i < count; i++) {
936 u16 sample[8];
937 int j, bit;
938
939 j = 0;
940 for_each_set_bit(bit, indio_dev->active_scan_mask,
941 indio_dev->masklength)
942 memcpy(&sample[j++], &buffer[i * 3 + bit], 2);
943
944 iio_push_to_buffers_with_timestamp(indio_dev, sample, tstamp);
945
946 tstamp += sample_period;
947 }
948
949 return count;
950 }
951
952 static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples)
953 {
954 struct bmc150_accel_data *data = iio_priv(indio_dev);
955 int ret;
956
957 mutex_lock(&data->mutex);
958 ret = __bmc150_accel_fifo_flush(indio_dev, samples, false);
959 mutex_unlock(&data->mutex);
960
961 return ret;
962 }
963
964 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
965 "15.620000 31.260000 62.50000 125 250 500 1000 2000");
966
967 static struct attribute *bmc150_accel_attributes[] = {
968 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
969 NULL,
970 };
971
972 static const struct attribute_group bmc150_accel_attrs_group = {
973 .attrs = bmc150_accel_attributes,
974 };
975
976 static const struct iio_event_spec bmc150_accel_event = {
977 .type = IIO_EV_TYPE_ROC,
978 .dir = IIO_EV_DIR_EITHER,
979 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
980 BIT(IIO_EV_INFO_ENABLE) |
981 BIT(IIO_EV_INFO_PERIOD)
982 };
983
984 #define BMC150_ACCEL_CHANNEL(_axis, bits) { \
985 .type = IIO_ACCEL, \
986 .modified = 1, \
987 .channel2 = IIO_MOD_##_axis, \
988 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
989 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
990 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
991 .scan_index = AXIS_##_axis, \
992 .scan_type = { \
993 .sign = 's', \
994 .realbits = (bits), \
995 .storagebits = 16, \
996 .shift = 16 - (bits), \
997 .endianness = IIO_LE, \
998 }, \
999 .event_spec = &bmc150_accel_event, \
1000 .num_event_specs = 1 \
1001 }
1002
1003 #define BMC150_ACCEL_CHANNELS(bits) { \
1004 { \
1005 .type = IIO_TEMP, \
1006 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1007 BIT(IIO_CHAN_INFO_SCALE) | \
1008 BIT(IIO_CHAN_INFO_OFFSET), \
1009 .scan_index = -1, \
1010 }, \
1011 BMC150_ACCEL_CHANNEL(X, bits), \
1012 BMC150_ACCEL_CHANNEL(Y, bits), \
1013 BMC150_ACCEL_CHANNEL(Z, bits), \
1014 IIO_CHAN_SOFT_TIMESTAMP(3), \
1015 }
1016
1017 static const struct iio_chan_spec bma222e_accel_channels[] =
1018 BMC150_ACCEL_CHANNELS(8);
1019 static const struct iio_chan_spec bma250e_accel_channels[] =
1020 BMC150_ACCEL_CHANNELS(10);
1021 static const struct iio_chan_spec bmc150_accel_channels[] =
1022 BMC150_ACCEL_CHANNELS(12);
1023 static const struct iio_chan_spec bma280_accel_channels[] =
1024 BMC150_ACCEL_CHANNELS(14);
1025
1026 static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = {
1027 [bmc150] = {
1028 .name = "BMC150A",
1029 .chip_id = 0xFA,
1030 .channels = bmc150_accel_channels,
1031 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1032 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1033 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1034 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1035 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1036 },
1037 [bmi055] = {
1038 .name = "BMI055A",
1039 .chip_id = 0xFA,
1040 .channels = bmc150_accel_channels,
1041 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1042 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1043 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1044 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1045 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1046 },
1047 [bma255] = {
1048 .name = "BMA0255",
1049 .chip_id = 0xFA,
1050 .channels = bmc150_accel_channels,
1051 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1052 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1053 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1054 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1055 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1056 },
1057 [bma250e] = {
1058 .name = "BMA250E",
1059 .chip_id = 0xF9,
1060 .channels = bma250e_accel_channels,
1061 .num_channels = ARRAY_SIZE(bma250e_accel_channels),
1062 .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G},
1063 {76590, BMC150_ACCEL_DEF_RANGE_4G},
1064 {153277, BMC150_ACCEL_DEF_RANGE_8G},
1065 {306457, BMC150_ACCEL_DEF_RANGE_16G} },
1066 },
1067 [bma222e] = {
1068 .name = "BMA222E",
1069 .chip_id = 0xF8,
1070 .channels = bma222e_accel_channels,
1071 .num_channels = ARRAY_SIZE(bma222e_accel_channels),
1072 .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G},
1073 {306457, BMC150_ACCEL_DEF_RANGE_4G},
1074 {612915, BMC150_ACCEL_DEF_RANGE_8G},
1075 {1225831, BMC150_ACCEL_DEF_RANGE_16G} },
1076 },
1077 [bma280] = {
1078 .name = "BMA0280",
1079 .chip_id = 0xFB,
1080 .channels = bma280_accel_channels,
1081 .num_channels = ARRAY_SIZE(bma280_accel_channels),
1082 .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G},
1083 {4785, BMC150_ACCEL_DEF_RANGE_4G},
1084 {9581, BMC150_ACCEL_DEF_RANGE_8G},
1085 {19152, BMC150_ACCEL_DEF_RANGE_16G} },
1086 },
1087 };
1088
1089 static const struct iio_info bmc150_accel_info = {
1090 .attrs = &bmc150_accel_attrs_group,
1091 .read_raw = bmc150_accel_read_raw,
1092 .write_raw = bmc150_accel_write_raw,
1093 .read_event_value = bmc150_accel_read_event,
1094 .write_event_value = bmc150_accel_write_event,
1095 .write_event_config = bmc150_accel_write_event_config,
1096 .read_event_config = bmc150_accel_read_event_config,
1097 .driver_module = THIS_MODULE,
1098 };
1099
1100 static const struct iio_info bmc150_accel_info_fifo = {
1101 .attrs = &bmc150_accel_attrs_group,
1102 .read_raw = bmc150_accel_read_raw,
1103 .write_raw = bmc150_accel_write_raw,
1104 .read_event_value = bmc150_accel_read_event,
1105 .write_event_value = bmc150_accel_write_event,
1106 .write_event_config = bmc150_accel_write_event_config,
1107 .read_event_config = bmc150_accel_read_event_config,
1108 .validate_trigger = bmc150_accel_validate_trigger,
1109 .hwfifo_set_watermark = bmc150_accel_set_watermark,
1110 .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush,
1111 .driver_module = THIS_MODULE,
1112 };
1113
1114 static const unsigned long bmc150_accel_scan_masks[] = {
1115 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
1116 0};
1117
1118 static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p)
1119 {
1120 struct iio_poll_func *pf = p;
1121 struct iio_dev *indio_dev = pf->indio_dev;
1122 struct bmc150_accel_data *data = iio_priv(indio_dev);
1123 int ret;
1124
1125 mutex_lock(&data->mutex);
1126 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_REG_XOUT_L,
1127 data->buffer, AXIS_MAX * 2);
1128 mutex_unlock(&data->mutex);
1129 if (ret < 0)
1130 goto err_read;
1131
1132 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
1133 pf->timestamp);
1134 err_read:
1135 iio_trigger_notify_done(indio_dev->trig);
1136
1137 return IRQ_HANDLED;
1138 }
1139
1140 static int bmc150_accel_trig_try_reen(struct iio_trigger *trig)
1141 {
1142 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1143 struct bmc150_accel_data *data = t->data;
1144 struct device *dev = regmap_get_device(data->regmap);
1145 int ret;
1146
1147 /* new data interrupts don't need ack */
1148 if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY])
1149 return 0;
1150
1151 mutex_lock(&data->mutex);
1152 /* clear any latched interrupt */
1153 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1154 BMC150_ACCEL_INT_MODE_LATCH_INT |
1155 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1156 mutex_unlock(&data->mutex);
1157 if (ret < 0) {
1158 dev_err(dev, "Error writing reg_int_rst_latch\n");
1159 return ret;
1160 }
1161
1162 return 0;
1163 }
1164
1165 static int bmc150_accel_trigger_set_state(struct iio_trigger *trig,
1166 bool state)
1167 {
1168 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1169 struct bmc150_accel_data *data = t->data;
1170 int ret;
1171
1172 mutex_lock(&data->mutex);
1173
1174 if (t->enabled == state) {
1175 mutex_unlock(&data->mutex);
1176 return 0;
1177 }
1178
1179 if (t->setup) {
1180 ret = t->setup(t, state);
1181 if (ret < 0) {
1182 mutex_unlock(&data->mutex);
1183 return ret;
1184 }
1185 }
1186
1187 ret = bmc150_accel_set_interrupt(data, t->intr, state);
1188 if (ret < 0) {
1189 mutex_unlock(&data->mutex);
1190 return ret;
1191 }
1192
1193 t->enabled = state;
1194
1195 mutex_unlock(&data->mutex);
1196
1197 return ret;
1198 }
1199
1200 static const struct iio_trigger_ops bmc150_accel_trigger_ops = {
1201 .set_trigger_state = bmc150_accel_trigger_set_state,
1202 .try_reenable = bmc150_accel_trig_try_reen,
1203 .owner = THIS_MODULE,
1204 };
1205
1206 static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev)
1207 {
1208 struct bmc150_accel_data *data = iio_priv(indio_dev);
1209 struct device *dev = regmap_get_device(data->regmap);
1210 int dir;
1211 int ret;
1212 unsigned int val;
1213
1214 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_INT_STATUS_2, &val);
1215 if (ret < 0) {
1216 dev_err(dev, "Error reading reg_int_status_2\n");
1217 return ret;
1218 }
1219
1220 if (val & BMC150_ACCEL_ANY_MOTION_BIT_SIGN)
1221 dir = IIO_EV_DIR_FALLING;
1222 else
1223 dir = IIO_EV_DIR_RISING;
1224
1225 if (val & BMC150_ACCEL_ANY_MOTION_BIT_X)
1226 iio_push_event(indio_dev,
1227 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1228 0,
1229 IIO_MOD_X,
1230 IIO_EV_TYPE_ROC,
1231 dir),
1232 data->timestamp);
1233
1234 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Y)
1235 iio_push_event(indio_dev,
1236 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1237 0,
1238 IIO_MOD_Y,
1239 IIO_EV_TYPE_ROC,
1240 dir),
1241 data->timestamp);
1242
1243 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Z)
1244 iio_push_event(indio_dev,
1245 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1246 0,
1247 IIO_MOD_Z,
1248 IIO_EV_TYPE_ROC,
1249 dir),
1250 data->timestamp);
1251
1252 return ret;
1253 }
1254
1255 static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private)
1256 {
1257 struct iio_dev *indio_dev = private;
1258 struct bmc150_accel_data *data = iio_priv(indio_dev);
1259 struct device *dev = regmap_get_device(data->regmap);
1260 bool ack = false;
1261 int ret;
1262
1263 mutex_lock(&data->mutex);
1264
1265 if (data->fifo_mode) {
1266 ret = __bmc150_accel_fifo_flush(indio_dev,
1267 BMC150_ACCEL_FIFO_LENGTH, true);
1268 if (ret > 0)
1269 ack = true;
1270 }
1271
1272 if (data->ev_enable_state) {
1273 ret = bmc150_accel_handle_roc_event(indio_dev);
1274 if (ret > 0)
1275 ack = true;
1276 }
1277
1278 if (ack) {
1279 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1280 BMC150_ACCEL_INT_MODE_LATCH_INT |
1281 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1282 if (ret)
1283 dev_err(dev, "Error writing reg_int_rst_latch\n");
1284
1285 ret = IRQ_HANDLED;
1286 } else {
1287 ret = IRQ_NONE;
1288 }
1289
1290 mutex_unlock(&data->mutex);
1291
1292 return ret;
1293 }
1294
1295 static irqreturn_t bmc150_accel_irq_handler(int irq, void *private)
1296 {
1297 struct iio_dev *indio_dev = private;
1298 struct bmc150_accel_data *data = iio_priv(indio_dev);
1299 bool ack = false;
1300 int i;
1301
1302 data->old_timestamp = data->timestamp;
1303 data->timestamp = iio_get_time_ns(indio_dev);
1304
1305 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1306 if (data->triggers[i].enabled) {
1307 iio_trigger_poll(data->triggers[i].indio_trig);
1308 ack = true;
1309 break;
1310 }
1311 }
1312
1313 if (data->ev_enable_state || data->fifo_mode)
1314 return IRQ_WAKE_THREAD;
1315
1316 if (ack)
1317 return IRQ_HANDLED;
1318
1319 return IRQ_NONE;
1320 }
1321
1322 static const struct {
1323 int intr;
1324 const char *name;
1325 int (*setup)(struct bmc150_accel_trigger *t, bool state);
1326 } bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = {
1327 {
1328 .intr = 0,
1329 .name = "%s-dev%d",
1330 },
1331 {
1332 .intr = 1,
1333 .name = "%s-any-motion-dev%d",
1334 .setup = bmc150_accel_any_motion_setup,
1335 },
1336 };
1337
1338 static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data,
1339 int from)
1340 {
1341 int i;
1342
1343 for (i = from; i >= 0; i--) {
1344 if (data->triggers[i].indio_trig) {
1345 iio_trigger_unregister(data->triggers[i].indio_trig);
1346 data->triggers[i].indio_trig = NULL;
1347 }
1348 }
1349 }
1350
1351 static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev,
1352 struct bmc150_accel_data *data)
1353 {
1354 struct device *dev = regmap_get_device(data->regmap);
1355 int i, ret;
1356
1357 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1358 struct bmc150_accel_trigger *t = &data->triggers[i];
1359
1360 t->indio_trig = devm_iio_trigger_alloc(dev,
1361 bmc150_accel_triggers[i].name,
1362 indio_dev->name,
1363 indio_dev->id);
1364 if (!t->indio_trig) {
1365 ret = -ENOMEM;
1366 break;
1367 }
1368
1369 t->indio_trig->dev.parent = dev;
1370 t->indio_trig->ops = &bmc150_accel_trigger_ops;
1371 t->intr = bmc150_accel_triggers[i].intr;
1372 t->data = data;
1373 t->setup = bmc150_accel_triggers[i].setup;
1374 iio_trigger_set_drvdata(t->indio_trig, t);
1375
1376 ret = iio_trigger_register(t->indio_trig);
1377 if (ret)
1378 break;
1379 }
1380
1381 if (ret)
1382 bmc150_accel_unregister_triggers(data, i - 1);
1383
1384 return ret;
1385 }
1386
1387 #define BMC150_ACCEL_FIFO_MODE_STREAM 0x80
1388 #define BMC150_ACCEL_FIFO_MODE_FIFO 0x40
1389 #define BMC150_ACCEL_FIFO_MODE_BYPASS 0x00
1390
1391 static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data)
1392 {
1393 struct device *dev = regmap_get_device(data->regmap);
1394 u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1;
1395 int ret;
1396
1397 ret = regmap_write(data->regmap, reg, data->fifo_mode);
1398 if (ret < 0) {
1399 dev_err(dev, "Error writing reg_fifo_config1\n");
1400 return ret;
1401 }
1402
1403 if (!data->fifo_mode)
1404 return 0;
1405
1406 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_FIFO_CONFIG0,
1407 data->watermark);
1408 if (ret < 0)
1409 dev_err(dev, "Error writing reg_fifo_config0\n");
1410
1411 return ret;
1412 }
1413
1414 static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev)
1415 {
1416 struct bmc150_accel_data *data = iio_priv(indio_dev);
1417
1418 return bmc150_accel_set_power_state(data, true);
1419 }
1420
1421 static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev)
1422 {
1423 struct bmc150_accel_data *data = iio_priv(indio_dev);
1424 int ret = 0;
1425
1426 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1427 return iio_triggered_buffer_postenable(indio_dev);
1428
1429 mutex_lock(&data->mutex);
1430
1431 if (!data->watermark)
1432 goto out;
1433
1434 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1435 true);
1436 if (ret)
1437 goto out;
1438
1439 data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO;
1440
1441 ret = bmc150_accel_fifo_set_mode(data);
1442 if (ret) {
1443 data->fifo_mode = 0;
1444 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1445 false);
1446 }
1447
1448 out:
1449 mutex_unlock(&data->mutex);
1450
1451 return ret;
1452 }
1453
1454 static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev)
1455 {
1456 struct bmc150_accel_data *data = iio_priv(indio_dev);
1457
1458 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1459 return iio_triggered_buffer_predisable(indio_dev);
1460
1461 mutex_lock(&data->mutex);
1462
1463 if (!data->fifo_mode)
1464 goto out;
1465
1466 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false);
1467 __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false);
1468 data->fifo_mode = 0;
1469 bmc150_accel_fifo_set_mode(data);
1470
1471 out:
1472 mutex_unlock(&data->mutex);
1473
1474 return 0;
1475 }
1476
1477 static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev)
1478 {
1479 struct bmc150_accel_data *data = iio_priv(indio_dev);
1480
1481 return bmc150_accel_set_power_state(data, false);
1482 }
1483
1484 static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = {
1485 .preenable = bmc150_accel_buffer_preenable,
1486 .postenable = bmc150_accel_buffer_postenable,
1487 .predisable = bmc150_accel_buffer_predisable,
1488 .postdisable = bmc150_accel_buffer_postdisable,
1489 };
1490
1491 static int bmc150_accel_chip_init(struct bmc150_accel_data *data)
1492 {
1493 struct device *dev = regmap_get_device(data->regmap);
1494 int ret, i;
1495 unsigned int val;
1496
1497 /*
1498 * Reset chip to get it in a known good state. A delay of 1.8ms after
1499 * reset is required according to the data sheets of supported chips.
1500 */
1501 regmap_write(data->regmap, BMC150_ACCEL_REG_RESET,
1502 BMC150_ACCEL_RESET_VAL);
1503 usleep_range(1800, 2500);
1504
1505 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_CHIP_ID, &val);
1506 if (ret < 0) {
1507 dev_err(dev, "Error: Reading chip id\n");
1508 return ret;
1509 }
1510
1511 dev_dbg(dev, "Chip Id %x\n", val);
1512 for (i = 0; i < ARRAY_SIZE(bmc150_accel_chip_info_tbl); i++) {
1513 if (bmc150_accel_chip_info_tbl[i].chip_id == val) {
1514 data->chip_info = &bmc150_accel_chip_info_tbl[i];
1515 break;
1516 }
1517 }
1518
1519 if (!data->chip_info) {
1520 dev_err(dev, "Invalid chip %x\n", val);
1521 return -ENODEV;
1522 }
1523
1524 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1525 if (ret < 0)
1526 return ret;
1527
1528 /* Set Bandwidth */
1529 ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0);
1530 if (ret < 0)
1531 return ret;
1532
1533 /* Set Default Range */
1534 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_RANGE,
1535 BMC150_ACCEL_DEF_RANGE_4G);
1536 if (ret < 0) {
1537 dev_err(dev, "Error writing reg_pmu_range\n");
1538 return ret;
1539 }
1540
1541 data->range = BMC150_ACCEL_DEF_RANGE_4G;
1542
1543 /* Set default slope duration and thresholds */
1544 data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD;
1545 data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION;
1546 ret = bmc150_accel_update_slope(data);
1547 if (ret < 0)
1548 return ret;
1549
1550 /* Set default as latched interrupts */
1551 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1552 BMC150_ACCEL_INT_MODE_LATCH_INT |
1553 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1554 if (ret < 0) {
1555 dev_err(dev, "Error writing reg_int_rst_latch\n");
1556 return ret;
1557 }
1558
1559 return 0;
1560 }
1561
1562 int bmc150_accel_core_probe(struct device *dev, struct regmap *regmap, int irq,
1563 const char *name, bool block_supported)
1564 {
1565 struct bmc150_accel_data *data;
1566 struct iio_dev *indio_dev;
1567 int ret;
1568
1569 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1570 if (!indio_dev)
1571 return -ENOMEM;
1572
1573 data = iio_priv(indio_dev);
1574 dev_set_drvdata(dev, indio_dev);
1575 data->irq = irq;
1576
1577 data->regmap = regmap;
1578
1579 ret = bmc150_accel_chip_init(data);
1580 if (ret < 0)
1581 return ret;
1582
1583 mutex_init(&data->mutex);
1584
1585 indio_dev->dev.parent = dev;
1586 indio_dev->channels = data->chip_info->channels;
1587 indio_dev->num_channels = data->chip_info->num_channels;
1588 indio_dev->name = name ? name : data->chip_info->name;
1589 indio_dev->available_scan_masks = bmc150_accel_scan_masks;
1590 indio_dev->modes = INDIO_DIRECT_MODE;
1591 indio_dev->info = &bmc150_accel_info;
1592
1593 ret = iio_triggered_buffer_setup(indio_dev,
1594 &iio_pollfunc_store_time,
1595 bmc150_accel_trigger_handler,
1596 &bmc150_accel_buffer_ops);
1597 if (ret < 0) {
1598 dev_err(dev, "Failed: iio triggered buffer setup\n");
1599 return ret;
1600 }
1601
1602 if (data->irq > 0) {
1603 ret = devm_request_threaded_irq(
1604 dev, data->irq,
1605 bmc150_accel_irq_handler,
1606 bmc150_accel_irq_thread_handler,
1607 IRQF_TRIGGER_RISING,
1608 BMC150_ACCEL_IRQ_NAME,
1609 indio_dev);
1610 if (ret)
1611 goto err_buffer_cleanup;
1612
1613 /*
1614 * Set latched mode interrupt. While certain interrupts are
1615 * non-latched regardless of this settings (e.g. new data) we
1616 * want to use latch mode when we can to prevent interrupt
1617 * flooding.
1618 */
1619 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1620 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1621 if (ret < 0) {
1622 dev_err(dev, "Error writing reg_int_rst_latch\n");
1623 goto err_buffer_cleanup;
1624 }
1625
1626 bmc150_accel_interrupts_setup(indio_dev, data);
1627
1628 ret = bmc150_accel_triggers_setup(indio_dev, data);
1629 if (ret)
1630 goto err_buffer_cleanup;
1631
1632 if (block_supported) {
1633 indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1634 indio_dev->info = &bmc150_accel_info_fifo;
1635 iio_buffer_set_attrs(indio_dev->buffer,
1636 bmc150_accel_fifo_attributes);
1637 }
1638 }
1639
1640 ret = pm_runtime_set_active(dev);
1641 if (ret)
1642 goto err_trigger_unregister;
1643
1644 pm_runtime_enable(dev);
1645 pm_runtime_set_autosuspend_delay(dev, BMC150_AUTO_SUSPEND_DELAY_MS);
1646 pm_runtime_use_autosuspend(dev);
1647
1648 ret = iio_device_register(indio_dev);
1649 if (ret < 0) {
1650 dev_err(dev, "Unable to register iio device\n");
1651 goto err_trigger_unregister;
1652 }
1653
1654 return 0;
1655
1656 err_trigger_unregister:
1657 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1658 err_buffer_cleanup:
1659 iio_triggered_buffer_cleanup(indio_dev);
1660
1661 return ret;
1662 }
1663 EXPORT_SYMBOL_GPL(bmc150_accel_core_probe);
1664
1665 int bmc150_accel_core_remove(struct device *dev)
1666 {
1667 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1668 struct bmc150_accel_data *data = iio_priv(indio_dev);
1669
1670 iio_device_unregister(indio_dev);
1671
1672 pm_runtime_disable(dev);
1673 pm_runtime_set_suspended(dev);
1674 pm_runtime_put_noidle(dev);
1675
1676 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1677
1678 iio_triggered_buffer_cleanup(indio_dev);
1679
1680 mutex_lock(&data->mutex);
1681 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0);
1682 mutex_unlock(&data->mutex);
1683
1684 return 0;
1685 }
1686 EXPORT_SYMBOL_GPL(bmc150_accel_core_remove);
1687
1688 #ifdef CONFIG_PM_SLEEP
1689 static int bmc150_accel_suspend(struct device *dev)
1690 {
1691 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1692 struct bmc150_accel_data *data = iio_priv(indio_dev);
1693
1694 mutex_lock(&data->mutex);
1695 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1696 mutex_unlock(&data->mutex);
1697
1698 return 0;
1699 }
1700
1701 static int bmc150_accel_resume(struct device *dev)
1702 {
1703 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1704 struct bmc150_accel_data *data = iio_priv(indio_dev);
1705
1706 mutex_lock(&data->mutex);
1707 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1708 bmc150_accel_fifo_set_mode(data);
1709 mutex_unlock(&data->mutex);
1710
1711 return 0;
1712 }
1713 #endif
1714
1715 #ifdef CONFIG_PM
1716 static int bmc150_accel_runtime_suspend(struct device *dev)
1717 {
1718 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1719 struct bmc150_accel_data *data = iio_priv(indio_dev);
1720 int ret;
1721
1722 dev_dbg(dev, __func__);
1723 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1724 if (ret < 0)
1725 return -EAGAIN;
1726
1727 return 0;
1728 }
1729
1730 static int bmc150_accel_runtime_resume(struct device *dev)
1731 {
1732 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1733 struct bmc150_accel_data *data = iio_priv(indio_dev);
1734 int ret;
1735 int sleep_val;
1736
1737 dev_dbg(dev, __func__);
1738
1739 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1740 if (ret < 0)
1741 return ret;
1742 ret = bmc150_accel_fifo_set_mode(data);
1743 if (ret < 0)
1744 return ret;
1745
1746 sleep_val = bmc150_accel_get_startup_times(data);
1747 if (sleep_val < 20)
1748 usleep_range(sleep_val * 1000, 20000);
1749 else
1750 msleep_interruptible(sleep_val);
1751
1752 return 0;
1753 }
1754 #endif
1755
1756 const struct dev_pm_ops bmc150_accel_pm_ops = {
1757 SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume)
1758 SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend,
1759 bmc150_accel_runtime_resume, NULL)
1760 };
1761 EXPORT_SYMBOL_GPL(bmc150_accel_pm_ops);
1762
1763 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1764 MODULE_LICENSE("GPL v2");
1765 MODULE_DESCRIPTION("BMC150 accelerometer driver");
Linux with added FPC-III support